if_fxp_pci.c revision 1.22.4.8
1 /* $NetBSD: if_fxp_pci.c,v 1.22.4.8 2005/10/26 22:23:52 jmc Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * PCI bus front-end for the Intel i82557 fast Ethernet controller 42 * driver. Works with Intel Etherexpress Pro 10+, 100B, 100+ cards. 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: if_fxp_pci.c,v 1.22.4.8 2005/10/26 22:23:52 jmc Exp $"); 47 48 #include "rnd.h" 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/mbuf.h> 53 #include <sys/malloc.h> 54 #include <sys/kernel.h> 55 #include <sys/socket.h> 56 #include <sys/ioctl.h> 57 #include <sys/errno.h> 58 #include <sys/device.h> 59 60 #if NRND > 0 61 #include <sys/rnd.h> 62 #endif 63 64 #include <machine/endian.h> 65 66 #include <net/if.h> 67 #include <net/if_dl.h> 68 #include <net/if_media.h> 69 #include <net/if_ether.h> 70 71 #include <machine/bus.h> 72 #include <machine/intr.h> 73 74 #include <dev/mii/miivar.h> 75 76 #include <dev/ic/i82557reg.h> 77 #include <dev/ic/i82557var.h> 78 79 #include <dev/pci/pcivar.h> 80 #include <dev/pci/pcireg.h> 81 #include <dev/pci/pcidevs.h> 82 83 struct fxp_pci_softc { 84 struct fxp_softc psc_fxp; 85 86 pci_chipset_tag_t psc_pc; /* pci chipset tag */ 87 pcireg_t psc_regs[0x20>>2]; /* saved PCI config regs (sparse) */ 88 pcitag_t psc_tag; /* pci register tag */ 89 void *psc_powerhook; /* power hook */ 90 91 int psc_pwrmgmt_csr_reg; /* ACPI power management register */ 92 pcireg_t psc_pwrmgmt_csr; /* ...and the contents at D0 */ 93 }; 94 95 int fxp_pci_match __P((struct device *, struct cfdata *, void *)); 96 void fxp_pci_attach __P((struct device *, struct device *, void *)); 97 98 int fxp_pci_enable __P((struct fxp_softc *)); 99 void fxp_pci_disable __P((struct fxp_softc *)); 100 101 static void fxp_pci_confreg_restore __P((struct fxp_pci_softc *psc)); 102 static void fxp_pci_power __P((int why, void *arg)); 103 104 struct cfattach fxp_pci_ca = { 105 sizeof(struct fxp_pci_softc), fxp_pci_match, fxp_pci_attach 106 }; 107 108 const struct fxp_pci_product { 109 u_int32_t fpp_prodid; /* PCI product ID */ 110 const char *fpp_name; /* device name */ 111 } fxp_pci_products[] = { 112 { PCI_PRODUCT_INTEL_82557, 113 "Intel i82557 Ethernet" }, 114 { PCI_PRODUCT_INTEL_82559ER, 115 "Intel i82559ER Ethernet" }, 116 { PCI_PRODUCT_INTEL_IN_BUSINESS, 117 "Intel InBusiness Ethernet" }, 118 { PCI_PRODUCT_INTEL_82801BA_LAN, 119 "Intel i82562 Ethernet" }, 120 { PCI_PRODUCT_INTEL_82801E_LAN_1, 121 "Intel i82559 Ethernet" }, 122 { PCI_PRODUCT_INTEL_82801E_LAN_2, 123 "Intel i82559 Ethernet" }, 124 { PCI_PRODUCT_INTEL_PRO_100_VE_0, 125 "Intel PRO/100 VE Network Controller" }, 126 { PCI_PRODUCT_INTEL_PRO_100_VE_1, 127 "Intel PRO/100 VE Network Controller" }, 128 { PCI_PRODUCT_INTEL_PRO_100_VE_2, 129 "Intel PRO/100 VE Network Controller with 82562ET/EZ PHY" }, 130 { PCI_PRODUCT_INTEL_PRO_100_VE_3, 131 "Intel PRO/100 VE Network Controller with 82562ET/EZ (CNR) PHY" }, 132 { PCI_PRODUCT_INTEL_PRO_100_VE_4, 133 "Intel PRO/100 VE (MOB) Network Controller" }, 134 { PCI_PRODUCT_INTEL_PRO_100_VM_0, 135 "Intel PRO/100 VM Network Controller" }, 136 { PCI_PRODUCT_INTEL_PRO_100_VM_1, 137 "Intel PRO/100 VM Network Controller" }, 138 { PCI_PRODUCT_INTEL_PRO_100_VM_2, 139 "Intel PRO/100 VM Network Controller" }, 140 { PCI_PRODUCT_INTEL_PRO_100_VM_3, 141 "Intel PRO/100 VM Network Controller with 82562EM/EX PHY" }, 142 { PCI_PRODUCT_INTEL_PRO_100_VM_4, 143 "Intel PRO/100 VM Network Controller with 82562EM/EX (CNR) PHY" }, 144 { PCI_PRODUCT_INTEL_PRO_100_VM_6, 145 "Intel PRO/100 VM Network Controller with 82562ET PHY" }, 146 { PCI_PRODUCT_INTEL_PRO_100_M, 147 "Intel PRO/100 M Network Controller" }, 148 { PCI_PRODUCT_INTEL_82801EB_LAN, 149 "Intel 82801EB/ER (ICH5) Network Controller" }, 150 { PCI_PRODUCT_INTEL_82801FB_LAN, 151 "Intel 82562EZ (ICH6)" }, 152 { 0, 153 NULL }, 154 }; 155 156 static const struct fxp_pci_product * 157 fxp_pci_lookup(const struct pci_attach_args *pa) 158 { 159 const struct fxp_pci_product *fpp; 160 161 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 162 return (NULL); 163 164 for (fpp = fxp_pci_products; fpp->fpp_name != NULL; fpp++) 165 if (PCI_PRODUCT(pa->pa_id) == fpp->fpp_prodid) 166 return (fpp); 167 168 return (NULL); 169 } 170 171 int 172 fxp_pci_match(parent, match, aux) 173 struct device *parent; 174 struct cfdata *match; 175 void *aux; 176 { 177 struct pci_attach_args *pa = aux; 178 179 if (fxp_pci_lookup(pa) != NULL) 180 return (1); 181 182 return (0); 183 } 184 185 /* 186 * Restore PCI configuration registers that may have been clobbered. 187 * This is necessary due to bugs on the Sony VAIO Z505-series on-board 188 * ethernet, after an APM suspend/resume, as well as after an ACPI 189 * D3->D0 transition. We call this function from a power hook after 190 * APM resume events, as well as after the ACPI D3->D0 transition. 191 */ 192 static void 193 fxp_pci_confreg_restore(psc) 194 struct fxp_pci_softc *psc; 195 { 196 pcireg_t reg; 197 198 #if 0 199 /* 200 * Check to see if the command register is blank -- if so, then 201 * we'll assume that all the clobberable-registers have been 202 * clobbered. 203 */ 204 205 /* 206 * In general, the above metric is accurate. Unfortunately, 207 * it is inaccurate across a hibernation. Ideally APM/ACPI 208 * code should take note of hibernation events and execute 209 * a hibernation wakeup hook, but at present a hibernation wake 210 * is indistinguishable from a suspend wake. 211 */ 212 213 if (((reg = pci_conf_read(psc->psc_pc, psc->psc_tag, 214 PCI_COMMAND_STATUS_REG)) & 0xffff) != 0) 215 return; 216 #else 217 reg = pci_conf_read(psc->psc_pc, psc->psc_tag, PCI_COMMAND_STATUS_REG); 218 #endif 219 220 pci_conf_write(psc->psc_pc, psc->psc_tag, 221 PCI_COMMAND_STATUS_REG, 222 (reg & 0xffff0000) | 223 (psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] & 0xffff)); 224 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_BHLC_REG, 225 psc->psc_regs[PCI_BHLC_REG>>2]); 226 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x0, 227 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2]); 228 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x4, 229 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2]); 230 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x8, 231 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2]); 232 } 233 234 235 /* 236 * Power handler routine. Called when the system is transitioning into/out 237 * of power save modes. We restore the (bashed) PCI configuration registers 238 * on a resume. 239 */ 240 static void 241 fxp_pci_power(why, arg) 242 int why; 243 void *arg; 244 { 245 struct fxp_pci_softc *psc = arg; 246 247 if (why == PWR_RESUME) 248 fxp_pci_confreg_restore(psc); 249 } 250 251 void 252 fxp_pci_attach(parent, self, aux) 253 struct device *parent, *self; 254 void *aux; 255 { 256 struct fxp_pci_softc *psc = (struct fxp_pci_softc *)self; 257 struct fxp_softc *sc = (struct fxp_softc *)self; 258 struct pci_attach_args *pa = aux; 259 pci_chipset_tag_t pc = pa->pa_pc; 260 pci_intr_handle_t ih; 261 const struct fxp_pci_product *fpp; 262 const char *intrstr = NULL; 263 bus_space_tag_t iot, memt; 264 bus_space_handle_t ioh, memh; 265 int ioh_valid, memh_valid; 266 bus_addr_t addr; 267 bus_size_t size; 268 int flags; 269 int pci_pwrmgmt_cap_reg; 270 271 /* 272 * Map control/status registers. 273 */ 274 ioh_valid = (pci_mapreg_map(pa, FXP_PCI_IOBA, 275 PCI_MAPREG_TYPE_IO, 0, 276 &iot, &ioh, NULL, NULL) == 0); 277 278 /* 279 * Version 2.1 of the PCI spec, page 196, "Address Maps": 280 * 281 * Prefetchable 282 * 283 * Set to one if there are no side effects on reads, the 284 * device returns all bytes regardless of the byte enables, 285 * and host bridges can merge processor writes into this 286 * range without causing errors. Bit must be set to zero 287 * otherwise. 288 * 289 * The 82557 incorrectly sets the "prefetchable" bit, resulting 290 * in errors on systems which will do merged reads and writes. 291 * These errors manifest themselves as all-bits-set when reading 292 * from the EEPROM or other < 4 byte registers. 293 * 294 * We must work around this problem by always forcing the mapping 295 * for memory space to be uncacheable. On systems which cannot 296 * create an uncacheable mapping (because the firmware mapped it 297 * into only cacheable/prefetchable space due to the "prefetchable" 298 * bit), we can fall back onto i/o mapped access. 299 */ 300 memh_valid = 0; 301 memt = pa->pa_memt; 302 if (((pa->pa_flags & PCI_FLAGS_MEM_ENABLED) != 0) && 303 pci_mapreg_info(pa->pa_pc, pa->pa_tag, FXP_PCI_MMBA, 304 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 305 &addr, &size, &flags) == 0) { 306 flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 307 if (bus_space_map(memt, addr, size, flags, &memh) == 0) 308 memh_valid = 1; 309 } 310 311 if (memh_valid) { 312 sc->sc_st = memt; 313 sc->sc_sh = memh; 314 } else if (ioh_valid) { 315 sc->sc_st = iot; 316 sc->sc_sh = ioh; 317 } else { 318 printf(": unable to map device registers\n"); 319 return; 320 } 321 322 sc->sc_dmat = pa->pa_dmat; 323 324 fpp = fxp_pci_lookup(pa); 325 if (fpp == NULL) { 326 printf("\n"); 327 panic("fxp_pci_attach: impossible"); 328 } 329 330 sc->sc_rev = PCI_REVISION(pa->pa_class); 331 332 switch (fpp->fpp_prodid) { 333 case PCI_PRODUCT_INTEL_82557: 334 case PCI_PRODUCT_INTEL_82559ER: 335 case PCI_PRODUCT_INTEL_IN_BUSINESS: 336 { 337 const char *chipname = NULL; 338 339 if (sc->sc_rev >= FXP_REV_82558_A4) { 340 chipname = "i82558 Ethernet"; 341 /* 342 * Enable the MWI command for memory writes. 343 */ 344 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 345 sc->sc_flags |= FXPF_MWI; 346 } 347 if (sc->sc_rev >= FXP_REV_82559_A0) 348 chipname = "i82559 Ethernet"; 349 if (sc->sc_rev >= FXP_REV_82559S_A) 350 chipname = "i82559S Ethernet"; 351 if (sc->sc_rev >= FXP_REV_82550) 352 chipname = "i82550 Ethernet"; 353 354 /* 355 * Mark all i82559 and i82550 revisions as having 356 * the "resume bug". See i82557.c for details. 357 */ 358 if (sc->sc_rev >= FXP_REV_82559_A0) 359 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 360 361 printf(": %s, rev %d\n", chipname != NULL ? chipname : 362 fpp->fpp_name, sc->sc_rev); 363 break; 364 } 365 366 case PCI_PRODUCT_INTEL_82801BA_LAN: 367 printf(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 368 369 /* 370 * The 82801BA Ethernet has a bug which requires us to send a 371 * NOP before a CU_RESUME if we're in 10baseT mode. 372 */ 373 if (fpp->fpp_prodid == PCI_PRODUCT_INTEL_82801BA_LAN) 374 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 375 break; 376 377 case PCI_PRODUCT_INTEL_PRO_100_VE_0: 378 case PCI_PRODUCT_INTEL_PRO_100_VE_1: 379 case PCI_PRODUCT_INTEL_PRO_100_VM_0: 380 case PCI_PRODUCT_INTEL_PRO_100_VM_1: 381 case PCI_PRODUCT_INTEL_82562EH_HPNA_0: 382 case PCI_PRODUCT_INTEL_82562EH_HPNA_1: 383 case PCI_PRODUCT_INTEL_82562EH_HPNA_2: 384 case PCI_PRODUCT_INTEL_PRO_100_VM_2: 385 case PCI_PRODUCT_INTEL_PRO_100_VM_3: 386 case PCI_PRODUCT_INTEL_PRO_100_VM_4: 387 case PCI_PRODUCT_INTEL_PRO_100_VM_6: 388 case PCI_PRODUCT_INTEL_82801EB_LAN: 389 case PCI_PRODUCT_INTEL_82801FB_LAN: 390 printf(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 391 392 /* 393 * ICH3 chips apparently have problems with the enhanced 394 * features, so just treat them as an i82557. It also 395 * has the resume bug that the ICH2 has. 396 */ 397 sc->sc_rev = 1; 398 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 399 break; 400 case PCI_PRODUCT_INTEL_82801E_LAN_1: 401 case PCI_PRODUCT_INTEL_82801E_LAN_2: 402 printf(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 403 404 /* 405 * XXX We have to read the C-ICH's developer's manual 406 * in detail 407 */ 408 break; 409 } 410 411 /* Make sure bus-mastering is enabled. */ 412 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 413 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 414 PCI_COMMAND_MASTER_ENABLE); 415 416 /* 417 * Under some circumstances (such as APM suspend/resume 418 * cycles, and across ACPI power state changes), the 419 * i82257-family can lose the contents of critical PCI 420 * configuration registers, causing the card to be 421 * non-responsive and useless. This occurs on the Sony VAIO 422 * Z505-series, among others. Preserve them here so they can 423 * be later restored (by fxp_pci_confreg_restore()). 424 */ 425 psc->psc_pc = pc; 426 psc->psc_tag = pa->pa_tag; 427 psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] = 428 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 429 psc->psc_regs[PCI_BHLC_REG>>2] = 430 pci_conf_read(pc, pa->pa_tag, PCI_BHLC_REG); 431 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2] = 432 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x0); 433 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2] = 434 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x4); 435 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2] = 436 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x8); 437 438 /* 439 * Work around BIOS ACPI bugs where the chip is inadvertantly 440 * left in ACPI D3 (lowest power state). First confirm the device 441 * supports ACPI power management, then move it to the D0 (fully 442 * functional) state if it is not already there. 443 */ 444 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 445 &pci_pwrmgmt_cap_reg, 0)) { 446 pcireg_t reg; 447 448 sc->sc_enable = fxp_pci_enable; 449 sc->sc_disable = fxp_pci_disable; 450 451 psc->psc_pwrmgmt_csr_reg = pci_pwrmgmt_cap_reg + 4; 452 reg = pci_conf_read(pc, pa->pa_tag, psc->psc_pwrmgmt_csr_reg); 453 psc->psc_pwrmgmt_csr = (reg & ~PCI_PMCSR_STATE_MASK) | 454 PCI_PMCSR_STATE_D0; 455 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0) 456 pci_conf_write(pc, pa->pa_tag, psc->psc_pwrmgmt_csr_reg, 457 psc->psc_pwrmgmt_csr); 458 } 459 /* Restore PCI configuration registers. */ 460 fxp_pci_confreg_restore(psc); 461 462 sc->sc_enabled = 1; 463 464 /* 465 * Map and establish our interrupt. 466 */ 467 if (pci_intr_map(pa, &ih)) { 468 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 469 return; 470 } 471 intrstr = pci_intr_string(pc, ih); 472 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, fxp_intr, sc); 473 if (sc->sc_ih == NULL) { 474 printf("%s: couldn't establish interrupt", 475 sc->sc_dev.dv_xname); 476 if (intrstr != NULL) 477 printf(" at %s", intrstr); 478 printf("\n"); 479 return; 480 } 481 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 482 483 /* Finish off the attach. */ 484 fxp_attach(sc); 485 if (sc->sc_disable != NULL) 486 fxp_disable(sc); 487 488 /* Add a suspend hook to restore PCI config state */ 489 psc->psc_powerhook = powerhook_establish(fxp_pci_power, psc); 490 if (psc->psc_powerhook == NULL) 491 printf ("%s: WARNING: unable to establish pci power hook\n", 492 sc->sc_dev.dv_xname); 493 } 494 495 int 496 fxp_pci_enable(struct fxp_softc *sc) 497 { 498 struct fxp_pci_softc *psc = (void *) sc; 499 500 #if 0 501 printf("%s: going to power state D0\n", sc->sc_dev.dv_xname); 502 #endif 503 504 /* Bring the device into D0 power state. */ 505 pci_conf_write(psc->psc_pc, psc->psc_tag, 506 psc->psc_pwrmgmt_csr_reg, psc->psc_pwrmgmt_csr); 507 508 /* Now restore the configuration registers. */ 509 fxp_pci_confreg_restore(psc); 510 511 return (0); 512 } 513 514 void 515 fxp_pci_disable(struct fxp_softc *sc) 516 { 517 struct fxp_pci_softc *psc = (void *) sc; 518 519 /* 520 * for some 82558_A4 and 82558_B0, entering D3 state makes 521 * media detection disordered. 522 */ 523 if (sc->sc_rev <= FXP_REV_82558_B0) 524 return; 525 526 #if 0 527 printf("%s: going to power state D3\n", sc->sc_dev.dv_xname); 528 #endif 529 530 /* Put the device into D3 state. */ 531 pci_conf_write(psc->psc_pc, psc->psc_tag, 532 psc->psc_pwrmgmt_csr_reg, (psc->psc_pwrmgmt_csr & 533 ~PCI_PMCSR_STATE_MASK) | PCI_PMCSR_STATE_D3); 534 } 535
Indexes created Thu Oct 02 01:09:59 GMT 2025