if_fxp_pci.c revision 1.35
1 /* $NetBSD: if_fxp_pci.c,v 1.35 2003/08/14 07:59:39 nonaka Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * PCI bus front-end for the Intel i82557 fast Ethernet controller 42 * driver. Works with Intel Etherexpress Pro 10+, 100B, 100+ cards. 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: if_fxp_pci.c,v 1.35 2003/08/14 07:59:39 nonaka Exp $"); 47 48 #include "rnd.h" 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/mbuf.h> 53 #include <sys/malloc.h> 54 #include <sys/kernel.h> 55 #include <sys/socket.h> 56 #include <sys/ioctl.h> 57 #include <sys/errno.h> 58 #include <sys/device.h> 59 60 #if NRND > 0 61 #include <sys/rnd.h> 62 #endif 63 64 #include <machine/endian.h> 65 66 #include <net/if.h> 67 #include <net/if_dl.h> 68 #include <net/if_media.h> 69 #include <net/if_ether.h> 70 71 #include <machine/bus.h> 72 #include <machine/intr.h> 73 74 #include <dev/mii/miivar.h> 75 76 #include <dev/ic/i82557reg.h> 77 #include <dev/ic/i82557var.h> 78 79 #include <dev/pci/pcivar.h> 80 #include <dev/pci/pcireg.h> 81 #include <dev/pci/pcidevs.h> 82 83 struct fxp_pci_softc { 84 struct fxp_softc psc_fxp; 85 86 pci_chipset_tag_t psc_pc; /* pci chipset tag */ 87 pcireg_t psc_regs[0x20>>2]; /* saved PCI config regs (sparse) */ 88 pcitag_t psc_tag; /* pci register tag */ 89 void *psc_powerhook; /* power hook */ 90 91 int psc_pwrmgmt_csr_reg; /* ACPI power management register */ 92 pcireg_t psc_pwrmgmt_csr; /* ...and the contents at D0 */ 93 }; 94 95 int fxp_pci_match __P((struct device *, struct cfdata *, void *)); 96 void fxp_pci_attach __P((struct device *, struct device *, void *)); 97 98 int fxp_pci_enable __P((struct fxp_softc *)); 99 void fxp_pci_disable __P((struct fxp_softc *)); 100 101 static void fxp_pci_confreg_restore __P((struct fxp_pci_softc *psc)); 102 static void fxp_pci_power __P((int why, void *arg)); 103 104 CFATTACH_DECL(fxp_pci, sizeof(struct fxp_pci_softc), 105 fxp_pci_match, fxp_pci_attach, NULL, NULL); 106 107 const struct fxp_pci_product { 108 u_int32_t fpp_prodid; /* PCI product ID */ 109 const char *fpp_name; /* device name */ 110 } fxp_pci_products[] = { 111 { PCI_PRODUCT_INTEL_82557, 112 "Intel i82557 Ethernet" }, 113 { PCI_PRODUCT_INTEL_82559ER, 114 "Intel i82559ER Ethernet" }, 115 { PCI_PRODUCT_INTEL_IN_BUSINESS, 116 "Intel InBusiness Ethernet" }, 117 { PCI_PRODUCT_INTEL_82801BA_LAN, 118 "Intel i82562 Ethernet" }, 119 { PCI_PRODUCT_INTEL_82801E_LAN_1, 120 "Intel i82559 Ethernet" }, 121 { PCI_PRODUCT_INTEL_82801E_LAN_2, 122 "Intel i82559 Ethernet" }, 123 { PCI_PRODUCT_INTEL_PRO_100_VE_0, 124 "Intel PRO/100 VE Network Controller" }, 125 { PCI_PRODUCT_INTEL_PRO_100_VE_1, 126 "Intel PRO/100 VE Network Controller" }, 127 { PCI_PRODUCT_INTEL_PRO_100_VE_2, 128 "Intel PRO/100 VE Network Controller with 82562ET/EZ PHY" }, 129 { PCI_PRODUCT_INTEL_PRO_100_VE_3, 130 "Intel PRO/100 VE Network Controller with 82562ET/EZ (CNR) PHY" }, 131 { PCI_PRODUCT_INTEL_PRO_100_VE_4, 132 "Intel PRO/100 VE (MOB) Network Controller" }, 133 { PCI_PRODUCT_INTEL_PRO_100_VM_0, 134 "Intel PRO/100 VM Network Controller" }, 135 { PCI_PRODUCT_INTEL_PRO_100_VM_1, 136 "Intel PRO/100 VM Network Controller" }, 137 { PCI_PRODUCT_INTEL_PRO_100_VM_2, 138 "Intel PRO/100 VM Network Controller" }, 139 { PCI_PRODUCT_INTEL_PRO_100_VM_3, 140 "Intel PRO/100 VM Network Controller with 82562EM/EX PHY" }, 141 { PCI_PRODUCT_INTEL_PRO_100_VM_4, 142 "Intel PRO/100 VM Network Controller with 82562EM/EX (CNR) PHY" }, 143 { PCI_PRODUCT_INTEL_PRO_100_VM_5, 144 "Intel PRO/100 VM (MOB) Network Controller" }, 145 { PCI_PRODUCT_INTEL_PRO_100_VM_6, 146 "Intel PRO/100 VM Network Controller with 82562ET PHY" }, 147 { PCI_PRODUCT_INTEL_PRO_100_M, 148 "Intel PRO/100 M Network Controller" }, 149 { 0, 150 NULL }, 151 }; 152 153 static const struct fxp_pci_product * 154 fxp_pci_lookup(const struct pci_attach_args *pa) 155 { 156 const struct fxp_pci_product *fpp; 157 158 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 159 return (NULL); 160 161 for (fpp = fxp_pci_products; fpp->fpp_name != NULL; fpp++) 162 if (PCI_PRODUCT(pa->pa_id) == fpp->fpp_prodid) 163 return (fpp); 164 165 return (NULL); 166 } 167 168 int 169 fxp_pci_match(parent, match, aux) 170 struct device *parent; 171 struct cfdata *match; 172 void *aux; 173 { 174 struct pci_attach_args *pa = aux; 175 176 if (fxp_pci_lookup(pa) != NULL) 177 return (1); 178 179 return (0); 180 } 181 182 /* 183 * Restore PCI configuration registers that may have been clobbered. 184 * This is necessary due to bugs on the Sony VAIO Z505-series on-board 185 * ethernet, after an APM suspend/resume, as well as after an ACPI 186 * D3->D0 transition. We call this function from a power hook after 187 * APM resume events, as well as after the ACPI D3->D0 transition. 188 */ 189 static void 190 fxp_pci_confreg_restore(psc) 191 struct fxp_pci_softc *psc; 192 { 193 pcireg_t reg; 194 195 #if 0 196 /* 197 * Check to see if the command register is blank -- if so, then 198 * we'll assume that all the clobberable-registers have been 199 * clobbered. 200 */ 201 202 /* 203 * In general, the above metric is accurate. Unfortunately, 204 * it is inaccurate across a hibernation. Ideally APM/ACPI 205 * code should take note of hibernation events and execute 206 * a hibernation wakeup hook, but at present a hibernation wake 207 * is indistinguishable from a suspend wake. 208 */ 209 210 if (((reg = pci_conf_read(psc->psc_pc, psc->psc_tag, 211 PCI_COMMAND_STATUS_REG)) & 0xffff) != 0) 212 return; 213 #else 214 reg = pci_conf_read(psc->psc_pc, psc->psc_tag, PCI_COMMAND_STATUS_REG); 215 #endif 216 217 pci_conf_write(psc->psc_pc, psc->psc_tag, 218 PCI_COMMAND_STATUS_REG, 219 (reg & 0xffff0000) | 220 (psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] & 0xffff)); 221 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_BHLC_REG, 222 psc->psc_regs[PCI_BHLC_REG>>2]); 223 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x0, 224 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2]); 225 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x4, 226 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2]); 227 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x8, 228 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2]); 229 } 230 231 232 /* 233 * Power handler routine. Called when the system is transitioning into/out 234 * of power save modes. We restore the (bashed) PCI configuration registers 235 * on a resume. 236 */ 237 static void 238 fxp_pci_power(why, arg) 239 int why; 240 void *arg; 241 { 242 struct fxp_pci_softc *psc = arg; 243 244 if (why == PWR_RESUME) 245 fxp_pci_confreg_restore(psc); 246 } 247 248 void 249 fxp_pci_attach(parent, self, aux) 250 struct device *parent, *self; 251 void *aux; 252 { 253 struct fxp_pci_softc *psc = (struct fxp_pci_softc *)self; 254 struct fxp_softc *sc = (struct fxp_softc *)self; 255 struct pci_attach_args *pa = aux; 256 pci_chipset_tag_t pc = pa->pa_pc; 257 pci_intr_handle_t ih; 258 const struct fxp_pci_product *fpp; 259 const char *intrstr = NULL; 260 bus_space_tag_t iot, memt; 261 bus_space_handle_t ioh, memh; 262 int ioh_valid, memh_valid; 263 bus_addr_t addr; 264 bus_size_t size; 265 int flags; 266 int pci_pwrmgmt_cap_reg; 267 268 aprint_naive(": Ethernet controller\n"); 269 270 /* 271 * Map control/status registers. 272 */ 273 ioh_valid = (pci_mapreg_map(pa, FXP_PCI_IOBA, 274 PCI_MAPREG_TYPE_IO, 0, 275 &iot, &ioh, NULL, NULL) == 0); 276 277 /* 278 * Version 2.1 of the PCI spec, page 196, "Address Maps": 279 * 280 * Prefetchable 281 * 282 * Set to one if there are no side effects on reads, the 283 * device returns all bytes regardless of the byte enables, 284 * and host bridges can merge processor writes into this 285 * range without causing errors. Bit must be set to zero 286 * otherwise. 287 * 288 * The 82557 incorrectly sets the "prefetchable" bit, resulting 289 * in errors on systems which will do merged reads and writes. 290 * These errors manifest themselves as all-bits-set when reading 291 * from the EEPROM or other < 4 byte registers. 292 * 293 * We must work around this problem by always forcing the mapping 294 * for memory space to be uncacheable. On systems which cannot 295 * create an uncacheable mapping (because the firmware mapped it 296 * into only cacheable/prefetchable space due to the "prefetchable" 297 * bit), we can fall back onto i/o mapped access. 298 */ 299 memh_valid = 0; 300 memt = pa->pa_memt; 301 if (((pa->pa_flags & PCI_FLAGS_MEM_ENABLED) != 0) && 302 pci_mapreg_info(pa->pa_pc, pa->pa_tag, FXP_PCI_MMBA, 303 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 304 &addr, &size, &flags) == 0) { 305 flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 306 if (bus_space_map(memt, addr, size, flags, &memh) == 0) 307 memh_valid = 1; 308 } 309 310 if (memh_valid) { 311 sc->sc_st = memt; 312 sc->sc_sh = memh; 313 } else if (ioh_valid) { 314 sc->sc_st = iot; 315 sc->sc_sh = ioh; 316 } else { 317 aprint_error(": unable to map device registers\n"); 318 return; 319 } 320 321 sc->sc_dmat = pa->pa_dmat; 322 323 fpp = fxp_pci_lookup(pa); 324 if (fpp == NULL) { 325 printf("\n"); 326 panic("fxp_pci_attach: impossible"); 327 } 328 329 sc->sc_rev = PCI_REVISION(pa->pa_class); 330 331 switch (fpp->fpp_prodid) { 332 case PCI_PRODUCT_INTEL_82557: 333 case PCI_PRODUCT_INTEL_82559ER: 334 case PCI_PRODUCT_INTEL_IN_BUSINESS: 335 { 336 const char *chipname = NULL; 337 338 if (sc->sc_rev >= FXP_REV_82558_A4) { 339 chipname = "i82558 Ethernet"; 340 /* 341 * Enable the MWI command for memory writes. 342 */ 343 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 344 sc->sc_flags |= FXPF_MWI; 345 } 346 if (sc->sc_rev >= FXP_REV_82559_A0) 347 chipname = "i82559 Ethernet"; 348 if (sc->sc_rev >= FXP_REV_82559S_A) 349 chipname = "i82559S Ethernet"; 350 if (sc->sc_rev >= FXP_REV_82550) 351 chipname = "i82550 Ethernet"; 352 353 /* 354 * Mark all i82559 and i82550 revisions as having 355 * the "resume bug". See i82557.c for details. 356 */ 357 if (sc->sc_rev >= FXP_REV_82559_A0) 358 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 359 360 aprint_normal(": %s, rev %d\n", chipname != NULL ? chipname : 361 fpp->fpp_name, sc->sc_rev); 362 break; 363 } 364 365 case PCI_PRODUCT_INTEL_82801BA_LAN: 366 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 367 368 /* 369 * The 82801BA Ethernet has a bug which requires us to send a 370 * NOP before a CU_RESUME if we're in 10baseT mode. 371 */ 372 if (fpp->fpp_prodid == PCI_PRODUCT_INTEL_82801BA_LAN) 373 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 374 break; 375 376 case PCI_PRODUCT_INTEL_PRO_100_VE_0: 377 case PCI_PRODUCT_INTEL_PRO_100_VE_1: 378 case PCI_PRODUCT_INTEL_PRO_100_VM_0: 379 case PCI_PRODUCT_INTEL_PRO_100_VM_1: 380 case PCI_PRODUCT_INTEL_82562EH_HPNA_0: 381 case PCI_PRODUCT_INTEL_82562EH_HPNA_1: 382 case PCI_PRODUCT_INTEL_82562EH_HPNA_2: 383 case PCI_PRODUCT_INTEL_PRO_100_VM_2: 384 case PCI_PRODUCT_INTEL_PRO_100_VM_3: 385 case PCI_PRODUCT_INTEL_PRO_100_VM_4: 386 case PCI_PRODUCT_INTEL_PRO_100_VM_5: 387 case PCI_PRODUCT_INTEL_PRO_100_VM_6: 388 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 389 390 /* 391 * ICH3 chips apparently have problems with the enhanced 392 * features, so just treat them as an i82557. It also 393 * has the resume bug that the ICH2 has. 394 */ 395 sc->sc_rev = 1; 396 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 397 break; 398 case PCI_PRODUCT_INTEL_82801E_LAN_1: 399 case PCI_PRODUCT_INTEL_82801E_LAN_2: 400 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 401 402 /* 403 * XXX We have to read the C-ICH's developer's manual 404 * in detail 405 */ 406 break; 407 } 408 409 /* Make sure bus-mastering is enabled. */ 410 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 411 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 412 PCI_COMMAND_MASTER_ENABLE); 413 414 /* 415 * Under some circumstances (such as APM suspend/resume 416 * cycles, and across ACPI power state changes), the 417 * i82257-family can lose the contents of critical PCI 418 * configuration registers, causing the card to be 419 * non-responsive and useless. This occurs on the Sony VAIO 420 * Z505-series, among others. Preserve them here so they can 421 * be later restored (by fxp_pci_confreg_restore()). 422 */ 423 psc->psc_pc = pc; 424 psc->psc_tag = pa->pa_tag; 425 psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] = 426 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 427 psc->psc_regs[PCI_BHLC_REG>>2] = 428 pci_conf_read(pc, pa->pa_tag, PCI_BHLC_REG); 429 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2] = 430 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x0); 431 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2] = 432 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x4); 433 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2] = 434 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x8); 435 436 /* 437 * Work around BIOS ACPI bugs where the chip is inadvertantly 438 * left in ACPI D3 (lowest power state). First confirm the device 439 * supports ACPI power management, then move it to the D0 (fully 440 * functional) state if it is not already there. 441 */ 442 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 443 &pci_pwrmgmt_cap_reg, 0)) { 444 pcireg_t reg; 445 446 sc->sc_enable = fxp_pci_enable; 447 sc->sc_disable = fxp_pci_disable; 448 449 psc->psc_pwrmgmt_csr_reg = pci_pwrmgmt_cap_reg + PCI_PMCSR; 450 reg = pci_conf_read(pc, pa->pa_tag, psc->psc_pwrmgmt_csr_reg); 451 psc->psc_pwrmgmt_csr = (reg & ~PCI_PMCSR_STATE_MASK) | 452 PCI_PMCSR_STATE_D0; 453 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0) 454 pci_conf_write(pc, pa->pa_tag, psc->psc_pwrmgmt_csr_reg, 455 psc->psc_pwrmgmt_csr); 456 } 457 /* Restore PCI configuration registers. */ 458 fxp_pci_confreg_restore(psc); 459 460 sc->sc_enabled = 1; 461 462 /* 463 * Map and establish our interrupt. 464 */ 465 if (pci_intr_map(pa, &ih)) { 466 aprint_error("%s: couldn't map interrupt\n", 467 sc->sc_dev.dv_xname); 468 return; 469 } 470 intrstr = pci_intr_string(pc, ih); 471 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, fxp_intr, sc); 472 if (sc->sc_ih == NULL) { 473 aprint_error("%s: couldn't establish interrupt", 474 sc->sc_dev.dv_xname); 475 if (intrstr != NULL) 476 aprint_normal(" at %s", intrstr); 477 aprint_normal("\n"); 478 return; 479 } 480 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 481 482 /* Finish off the attach. */ 483 fxp_attach(sc); 484 if (sc->sc_disable != NULL) 485 fxp_disable(sc); 486 487 /* Add a suspend hook to restore PCI config state */ 488 psc->psc_powerhook = powerhook_establish(fxp_pci_power, psc); 489 if (psc->psc_powerhook == NULL) 490 aprint_error( 491 "%s: WARNING: unable to establish pci power hook\n", 492 sc->sc_dev.dv_xname); 493 } 494 495 int 496 fxp_pci_enable(struct fxp_softc *sc) 497 { 498 struct fxp_pci_softc *psc = (void *) sc; 499 500 #if 0 501 printf("%s: going to power state D0\n", sc->sc_dev.dv_xname); 502 #endif 503 504 /* Bring the device into D0 power state. */ 505 pci_conf_write(psc->psc_pc, psc->psc_tag, 506 psc->psc_pwrmgmt_csr_reg, psc->psc_pwrmgmt_csr); 507 508 /* Now restore the configuration registers. */ 509 fxp_pci_confreg_restore(psc); 510 511 return (0); 512 } 513 514 void 515 fxp_pci_disable(struct fxp_softc *sc) 516 { 517 struct fxp_pci_softc *psc = (void *) sc; 518 519 /* 520 * for some 82558_A4 and 82558_B0, entering D3 state makes 521 * media detection disordered. 522 */ 523 if (sc->sc_rev <= FXP_REV_82558_B0) 524 return; 525 526 #if 0 527 printf("%s: going to power state D3\n", sc->sc_dev.dv_xname); 528 #endif 529 530 /* Put the device into D3 state. */ 531 pci_conf_write(psc->psc_pc, psc->psc_tag, 532 psc->psc_pwrmgmt_csr_reg, (psc->psc_pwrmgmt_csr & 533 ~PCI_PMCSR_STATE_MASK) | PCI_PMCSR_STATE_D3); 534 } 535
Indexes created Thu Oct 02 01:09:59 GMT 2025