if_fxp_pci.c revision 1.40
1 /* $NetBSD: if_fxp_pci.c,v 1.40 2005/02/27 00:27:33 perry Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * PCI bus front-end for the Intel i82557 fast Ethernet controller 42 * driver. Works with Intel Etherexpress Pro 10+, 100B, 100+ cards. 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: if_fxp_pci.c,v 1.40 2005/02/27 00:27:33 perry Exp $"); 47 48 #include "rnd.h" 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/mbuf.h> 53 #include <sys/malloc.h> 54 #include <sys/kernel.h> 55 #include <sys/socket.h> 56 #include <sys/ioctl.h> 57 #include <sys/errno.h> 58 #include <sys/device.h> 59 60 #if NRND > 0 61 #include <sys/rnd.h> 62 #endif 63 64 #include <machine/endian.h> 65 66 #include <net/if.h> 67 #include <net/if_dl.h> 68 #include <net/if_media.h> 69 #include <net/if_ether.h> 70 71 #include <machine/bus.h> 72 #include <machine/intr.h> 73 74 #include <dev/mii/miivar.h> 75 76 #include <dev/ic/i82557reg.h> 77 #include <dev/ic/i82557var.h> 78 79 #include <dev/pci/pcivar.h> 80 #include <dev/pci/pcireg.h> 81 #include <dev/pci/pcidevs.h> 82 83 struct fxp_pci_softc { 84 struct fxp_softc psc_fxp; 85 86 pci_chipset_tag_t psc_pc; /* pci chipset tag */ 87 pcireg_t psc_regs[0x20>>2]; /* saved PCI config regs (sparse) */ 88 pcitag_t psc_tag; /* pci register tag */ 89 void *psc_powerhook; /* power hook */ 90 91 int psc_pwrmgmt_csr_reg; /* ACPI power management register */ 92 pcireg_t psc_pwrmgmt_csr; /* ...and the contents at D0 */ 93 }; 94 95 static int fxp_pci_match(struct device *, struct cfdata *, void *); 96 static void fxp_pci_attach(struct device *, struct device *, void *); 97 98 static int fxp_pci_enable(struct fxp_softc *); 99 static void fxp_pci_disable(struct fxp_softc *); 100 101 static void fxp_pci_confreg_restore(struct fxp_pci_softc *psc); 102 static void fxp_pci_power(int why, void *arg); 103 104 CFATTACH_DECL(fxp_pci, sizeof(struct fxp_pci_softc), 105 fxp_pci_match, fxp_pci_attach, NULL, NULL); 106 107 static const struct fxp_pci_product { 108 u_int32_t fpp_prodid; /* PCI product ID */ 109 const char *fpp_name; /* device name */ 110 } fxp_pci_products[] = { 111 { PCI_PRODUCT_INTEL_82557, 112 "Intel i82557 Ethernet" }, 113 { PCI_PRODUCT_INTEL_82559ER, 114 "Intel i82559ER Ethernet" }, 115 { PCI_PRODUCT_INTEL_IN_BUSINESS, 116 "Intel InBusiness Ethernet" }, 117 { PCI_PRODUCT_INTEL_82801BA_LAN, 118 "Intel i82562 Ethernet" }, 119 { PCI_PRODUCT_INTEL_82801E_LAN_1, 120 "Intel i82559 Ethernet" }, 121 { PCI_PRODUCT_INTEL_82801E_LAN_2, 122 "Intel i82559 Ethernet" }, 123 { PCI_PRODUCT_INTEL_PRO_100_VE_0, 124 "Intel PRO/100 VE Network Controller" }, 125 { PCI_PRODUCT_INTEL_PRO_100_VE_1, 126 "Intel PRO/100 VE Network Controller" }, 127 { PCI_PRODUCT_INTEL_PRO_100_VE_2, 128 "Intel PRO/100 VE Network Controller with 82562ET/EZ PHY" }, 129 { PCI_PRODUCT_INTEL_PRO_100_VE_3, 130 "Intel PRO/100 VE Network Controller with 82562ET/EZ (CNR) PHY" }, 131 { PCI_PRODUCT_INTEL_PRO_100_VE_4, 132 "Intel PRO/100 VE (MOB) Network Controller" }, 133 { PCI_PRODUCT_INTEL_PRO_100_VM_0, 134 "Intel PRO/100 VM Network Controller" }, 135 { PCI_PRODUCT_INTEL_PRO_100_VM_1, 136 "Intel PRO/100 VM Network Controller" }, 137 { PCI_PRODUCT_INTEL_PRO_100_VM_2, 138 "Intel PRO/100 VM Network Controller" }, 139 { PCI_PRODUCT_INTEL_PRO_100_VM_3, 140 "Intel PRO/100 VM Network Controller with 82562EM/EX PHY" }, 141 { PCI_PRODUCT_INTEL_PRO_100_VM_4, 142 "Intel PRO/100 VM Network Controller with 82562EM/EX (CNR) PHY" }, 143 { PCI_PRODUCT_INTEL_PRO_100_VM_5, 144 "Intel PRO/100 VM (MOB) Network Controller" }, 145 { PCI_PRODUCT_INTEL_PRO_100_VM_6, 146 "Intel PRO/100 VM Network Controller with 82562ET/EZ PHY" }, 147 { PCI_PRODUCT_INTEL_PRO_100_M, 148 "Intel PRO/100 M Network Controller" }, 149 { PCI_PRODUCT_INTEL_82801EB_LAN, 150 "Intel 82801EB/ER (ICH5) Network Controller" }, 151 { 0, 152 NULL }, 153 }; 154 155 static const struct fxp_pci_product * 156 fxp_pci_lookup(const struct pci_attach_args *pa) 157 { 158 const struct fxp_pci_product *fpp; 159 160 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 161 return (NULL); 162 163 for (fpp = fxp_pci_products; fpp->fpp_name != NULL; fpp++) 164 if (PCI_PRODUCT(pa->pa_id) == fpp->fpp_prodid) 165 return (fpp); 166 167 return (NULL); 168 } 169 170 static int 171 fxp_pci_match(struct device *parent, struct cfdata *match, void *aux) 172 { 173 struct pci_attach_args *pa = aux; 174 175 if (fxp_pci_lookup(pa) != NULL) 176 return (1); 177 178 return (0); 179 } 180 181 /* 182 * Restore PCI configuration registers that may have been clobbered. 183 * This is necessary due to bugs on the Sony VAIO Z505-series on-board 184 * ethernet, after an APM suspend/resume, as well as after an ACPI 185 * D3->D0 transition. We call this function from a power hook after 186 * APM resume events, as well as after the ACPI D3->D0 transition. 187 */ 188 static void 189 fxp_pci_confreg_restore(struct fxp_pci_softc *psc) 190 { 191 pcireg_t reg; 192 193 #if 0 194 /* 195 * Check to see if the command register is blank -- if so, then 196 * we'll assume that all the clobberable-registers have been 197 * clobbered. 198 */ 199 200 /* 201 * In general, the above metric is accurate. Unfortunately, 202 * it is inaccurate across a hibernation. Ideally APM/ACPI 203 * code should take note of hibernation events and execute 204 * a hibernation wakeup hook, but at present a hibernation wake 205 * is indistinguishable from a suspend wake. 206 */ 207 208 if (((reg = pci_conf_read(psc->psc_pc, psc->psc_tag, 209 PCI_COMMAND_STATUS_REG)) & 0xffff) != 0) 210 return; 211 #else 212 reg = pci_conf_read(psc->psc_pc, psc->psc_tag, PCI_COMMAND_STATUS_REG); 213 #endif 214 215 pci_conf_write(psc->psc_pc, psc->psc_tag, 216 PCI_COMMAND_STATUS_REG, 217 (reg & 0xffff0000) | 218 (psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] & 0xffff)); 219 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_BHLC_REG, 220 psc->psc_regs[PCI_BHLC_REG>>2]); 221 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x0, 222 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2]); 223 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x4, 224 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2]); 225 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x8, 226 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2]); 227 } 228 229 230 /* 231 * Power handler routine. Called when the system is transitioning into/out 232 * of power save modes. We restore the (bashed) PCI configuration registers 233 * on a resume. 234 */ 235 static void 236 fxp_pci_power(int why, void *arg) 237 { 238 struct fxp_pci_softc *psc = arg; 239 240 if (why == PWR_RESUME) 241 fxp_pci_confreg_restore(psc); 242 } 243 244 static void 245 fxp_pci_attach(struct device *parent, struct device *self, void *aux) 246 { 247 struct fxp_pci_softc *psc = (struct fxp_pci_softc *)self; 248 struct fxp_softc *sc = (struct fxp_softc *)self; 249 struct pci_attach_args *pa = aux; 250 pci_chipset_tag_t pc = pa->pa_pc; 251 pci_intr_handle_t ih; 252 const struct fxp_pci_product *fpp; 253 const char *intrstr = NULL; 254 bus_space_tag_t iot, memt; 255 bus_space_handle_t ioh, memh; 256 int ioh_valid, memh_valid; 257 bus_addr_t addr; 258 bus_size_t size; 259 int flags; 260 int pci_pwrmgmt_cap_reg; 261 262 aprint_naive(": Ethernet controller\n"); 263 264 /* 265 * Map control/status registers. 266 */ 267 ioh_valid = (pci_mapreg_map(pa, FXP_PCI_IOBA, 268 PCI_MAPREG_TYPE_IO, 0, 269 &iot, &ioh, NULL, NULL) == 0); 270 271 /* 272 * Version 2.1 of the PCI spec, page 196, "Address Maps": 273 * 274 * Prefetchable 275 * 276 * Set to one if there are no side effects on reads, the 277 * device returns all bytes regardless of the byte enables, 278 * and host bridges can merge processor writes into this 279 * range without causing errors. Bit must be set to zero 280 * otherwise. 281 * 282 * The 82557 incorrectly sets the "prefetchable" bit, resulting 283 * in errors on systems which will do merged reads and writes. 284 * These errors manifest themselves as all-bits-set when reading 285 * from the EEPROM or other < 4 byte registers. 286 * 287 * We must work around this problem by always forcing the mapping 288 * for memory space to be uncacheable. On systems which cannot 289 * create an uncacheable mapping (because the firmware mapped it 290 * into only cacheable/prefetchable space due to the "prefetchable" 291 * bit), we can fall back onto i/o mapped access. 292 */ 293 memh_valid = 0; 294 memt = pa->pa_memt; 295 if (((pa->pa_flags & PCI_FLAGS_MEM_ENABLED) != 0) && 296 pci_mapreg_info(pa->pa_pc, pa->pa_tag, FXP_PCI_MMBA, 297 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 298 &addr, &size, &flags) == 0) { 299 flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 300 if (bus_space_map(memt, addr, size, flags, &memh) == 0) 301 memh_valid = 1; 302 } 303 304 if (memh_valid) { 305 sc->sc_st = memt; 306 sc->sc_sh = memh; 307 } else if (ioh_valid) { 308 sc->sc_st = iot; 309 sc->sc_sh = ioh; 310 } else { 311 aprint_error(": unable to map device registers\n"); 312 return; 313 } 314 315 sc->sc_dmat = pa->pa_dmat; 316 317 fpp = fxp_pci_lookup(pa); 318 if (fpp == NULL) { 319 printf("\n"); 320 panic("fxp_pci_attach: impossible"); 321 } 322 323 sc->sc_rev = PCI_REVISION(pa->pa_class); 324 325 switch (fpp->fpp_prodid) { 326 case PCI_PRODUCT_INTEL_82557: 327 case PCI_PRODUCT_INTEL_82559ER: 328 case PCI_PRODUCT_INTEL_IN_BUSINESS: 329 { 330 const char *chipname = NULL; 331 332 if (sc->sc_rev >= FXP_REV_82558_A4) { 333 chipname = "i82558 Ethernet"; 334 /* 335 * Enable the MWI command for memory writes. 336 */ 337 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 338 sc->sc_flags |= FXPF_MWI; 339 } 340 if (sc->sc_rev >= FXP_REV_82559_A0) 341 chipname = "i82559 Ethernet"; 342 if (sc->sc_rev >= FXP_REV_82559S_A) 343 chipname = "i82559S Ethernet"; 344 if (sc->sc_rev >= FXP_REV_82550) 345 chipname = "i82550 Ethernet"; 346 347 /* 348 * Mark all i82559 and i82550 revisions as having 349 * the "resume bug". See i82557.c for details. 350 */ 351 if (sc->sc_rev >= FXP_REV_82559_A0) 352 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 353 354 aprint_normal(": %s, rev %d\n", chipname != NULL ? chipname : 355 fpp->fpp_name, sc->sc_rev); 356 break; 357 } 358 359 case PCI_PRODUCT_INTEL_82801BA_LAN: 360 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 361 362 /* 363 * The 82801BA Ethernet has a bug which requires us to send a 364 * NOP before a CU_RESUME if we're in 10baseT mode. 365 */ 366 if (fpp->fpp_prodid == PCI_PRODUCT_INTEL_82801BA_LAN) 367 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 368 break; 369 370 case PCI_PRODUCT_INTEL_PRO_100_VE_0: 371 case PCI_PRODUCT_INTEL_PRO_100_VE_1: 372 case PCI_PRODUCT_INTEL_PRO_100_VM_0: 373 case PCI_PRODUCT_INTEL_PRO_100_VM_1: 374 case PCI_PRODUCT_INTEL_82562EH_HPNA_0: 375 case PCI_PRODUCT_INTEL_82562EH_HPNA_1: 376 case PCI_PRODUCT_INTEL_82562EH_HPNA_2: 377 case PCI_PRODUCT_INTEL_PRO_100_VM_2: 378 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 379 380 /* 381 * ICH3 chips apparently have problems with the enhanced 382 * features, so just treat them as an i82557. It also 383 * has the resume bug that the ICH2 has. 384 */ 385 sc->sc_rev = 1; 386 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 387 break; 388 case PCI_PRODUCT_INTEL_82801E_LAN_1: 389 case PCI_PRODUCT_INTEL_82801E_LAN_2: 390 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 391 392 /* 393 * XXX We have to read the C-ICH's developer's manual 394 * in detail 395 */ 396 break; 397 case PCI_PRODUCT_INTEL_PRO_100_VE_2: 398 case PCI_PRODUCT_INTEL_PRO_100_VE_3: 399 case PCI_PRODUCT_INTEL_PRO_100_VE_4: 400 case PCI_PRODUCT_INTEL_PRO_100_VM_3: 401 case PCI_PRODUCT_INTEL_PRO_100_VM_4: 402 case PCI_PRODUCT_INTEL_PRO_100_VM_5: 403 case PCI_PRODUCT_INTEL_PRO_100_VM_6: 404 case PCI_PRODUCT_INTEL_82801EB_LAN: 405 default: 406 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 407 408 /* 409 * No particular quirks. 410 */ 411 break; 412 } 413 414 /* Make sure bus-mastering is enabled. */ 415 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 416 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 417 PCI_COMMAND_MASTER_ENABLE); 418 419 /* 420 * Under some circumstances (such as APM suspend/resume 421 * cycles, and across ACPI power state changes), the 422 * i82257-family can lose the contents of critical PCI 423 * configuration registers, causing the card to be 424 * non-responsive and useless. This occurs on the Sony VAIO 425 * Z505-series, among others. Preserve them here so they can 426 * be later restored (by fxp_pci_confreg_restore()). 427 */ 428 psc->psc_pc = pc; 429 psc->psc_tag = pa->pa_tag; 430 psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] = 431 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 432 psc->psc_regs[PCI_BHLC_REG>>2] = 433 pci_conf_read(pc, pa->pa_tag, PCI_BHLC_REG); 434 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2] = 435 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x0); 436 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2] = 437 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x4); 438 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2] = 439 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x8); 440 441 /* 442 * Work around BIOS ACPI bugs where the chip is inadvertantly 443 * left in ACPI D3 (lowest power state). First confirm the device 444 * supports ACPI power management, then move it to the D0 (fully 445 * functional) state if it is not already there. 446 */ 447 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 448 &pci_pwrmgmt_cap_reg, 0)) { 449 pcireg_t reg; 450 451 sc->sc_enable = fxp_pci_enable; 452 sc->sc_disable = fxp_pci_disable; 453 454 psc->psc_pwrmgmt_csr_reg = pci_pwrmgmt_cap_reg + PCI_PMCSR; 455 reg = pci_conf_read(pc, pa->pa_tag, psc->psc_pwrmgmt_csr_reg); 456 psc->psc_pwrmgmt_csr = (reg & ~PCI_PMCSR_STATE_MASK) | 457 PCI_PMCSR_STATE_D0; 458 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0) 459 pci_conf_write(pc, pa->pa_tag, psc->psc_pwrmgmt_csr_reg, 460 psc->psc_pwrmgmt_csr); 461 } 462 /* Restore PCI configuration registers. */ 463 fxp_pci_confreg_restore(psc); 464 465 sc->sc_enabled = 1; 466 467 /* 468 * Map and establish our interrupt. 469 */ 470 if (pci_intr_map(pa, &ih)) { 471 aprint_error("%s: couldn't map interrupt\n", 472 sc->sc_dev.dv_xname); 473 return; 474 } 475 intrstr = pci_intr_string(pc, ih); 476 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, fxp_intr, sc); 477 if (sc->sc_ih == NULL) { 478 aprint_error("%s: couldn't establish interrupt", 479 sc->sc_dev.dv_xname); 480 if (intrstr != NULL) 481 aprint_normal(" at %s", intrstr); 482 aprint_normal("\n"); 483 return; 484 } 485 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 486 487 /* Finish off the attach. */ 488 fxp_attach(sc); 489 if (sc->sc_disable != NULL) 490 fxp_disable(sc); 491 492 /* Add a suspend hook to restore PCI config state */ 493 psc->psc_powerhook = powerhook_establish(fxp_pci_power, psc); 494 if (psc->psc_powerhook == NULL) 495 aprint_error( 496 "%s: WARNING: unable to establish pci power hook\n", 497 sc->sc_dev.dv_xname); 498 } 499 500 static int 501 fxp_pci_enable(struct fxp_softc *sc) 502 { 503 struct fxp_pci_softc *psc = (void *) sc; 504 505 #if 0 506 printf("%s: going to power state D0\n", sc->sc_dev.dv_xname); 507 #endif 508 509 /* Bring the device into D0 power state. */ 510 pci_conf_write(psc->psc_pc, psc->psc_tag, 511 psc->psc_pwrmgmt_csr_reg, psc->psc_pwrmgmt_csr); 512 513 /* Now restore the configuration registers. */ 514 fxp_pci_confreg_restore(psc); 515 516 return (0); 517 } 518 519 static void 520 fxp_pci_disable(struct fxp_softc *sc) 521 { 522 struct fxp_pci_softc *psc = (void *) sc; 523 524 /* 525 * for some 82558_A4 and 82558_B0, entering D3 state makes 526 * media detection disordered. 527 */ 528 if (sc->sc_rev <= FXP_REV_82558_B0) 529 return; 530 531 #if 0 532 printf("%s: going to power state D3\n", sc->sc_dev.dv_xname); 533 #endif 534 535 /* Put the device into D3 state. */ 536 pci_conf_write(psc->psc_pc, psc->psc_tag, 537 psc->psc_pwrmgmt_csr_reg, (psc->psc_pwrmgmt_csr & 538 ~PCI_PMCSR_STATE_MASK) | PCI_PMCSR_STATE_D3); 539 } 540
Indexes created Wed Sep 24 05:09:52 GMT 2025