if_fxp_pci.c revision 1.41
1 /* $NetBSD: if_fxp_pci.c,v 1.41 2005/05/18 20:33:46 riz Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * PCI bus front-end for the Intel i82557 fast Ethernet controller 42 * driver. Works with Intel Etherexpress Pro 10+, 100B, 100+ cards. 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: if_fxp_pci.c,v 1.41 2005/05/18 20:33:46 riz Exp $"); 47 48 #include "rnd.h" 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/mbuf.h> 53 #include <sys/malloc.h> 54 #include <sys/kernel.h> 55 #include <sys/socket.h> 56 #include <sys/ioctl.h> 57 #include <sys/errno.h> 58 #include <sys/device.h> 59 60 #if NRND > 0 61 #include <sys/rnd.h> 62 #endif 63 64 #include <machine/endian.h> 65 66 #include <net/if.h> 67 #include <net/if_dl.h> 68 #include <net/if_media.h> 69 #include <net/if_ether.h> 70 71 #include <machine/bus.h> 72 #include <machine/intr.h> 73 74 #include <dev/mii/miivar.h> 75 76 #include <dev/ic/i82557reg.h> 77 #include <dev/ic/i82557var.h> 78 79 #include <dev/pci/pcivar.h> 80 #include <dev/pci/pcireg.h> 81 #include <dev/pci/pcidevs.h> 82 83 struct fxp_pci_softc { 84 struct fxp_softc psc_fxp; 85 86 pci_chipset_tag_t psc_pc; /* pci chipset tag */ 87 pcireg_t psc_regs[0x20>>2]; /* saved PCI config regs (sparse) */ 88 pcitag_t psc_tag; /* pci register tag */ 89 void *psc_powerhook; /* power hook */ 90 91 int psc_pwrmgmt_csr_reg; /* ACPI power management register */ 92 pcireg_t psc_pwrmgmt_csr; /* ...and the contents at D0 */ 93 }; 94 95 static int fxp_pci_match(struct device *, struct cfdata *, void *); 96 static void fxp_pci_attach(struct device *, struct device *, void *); 97 98 static int fxp_pci_enable(struct fxp_softc *); 99 static void fxp_pci_disable(struct fxp_softc *); 100 101 static void fxp_pci_confreg_restore(struct fxp_pci_softc *psc); 102 static void fxp_pci_power(int why, void *arg); 103 104 CFATTACH_DECL(fxp_pci, sizeof(struct fxp_pci_softc), 105 fxp_pci_match, fxp_pci_attach, NULL, NULL); 106 107 static const struct fxp_pci_product { 108 u_int32_t fpp_prodid; /* PCI product ID */ 109 const char *fpp_name; /* device name */ 110 } fxp_pci_products[] = { 111 { PCI_PRODUCT_INTEL_82557, 112 "Intel i82557 Ethernet" }, 113 { PCI_PRODUCT_INTEL_82559ER, 114 "Intel i82559ER Ethernet" }, 115 { PCI_PRODUCT_INTEL_IN_BUSINESS, 116 "Intel InBusiness Ethernet" }, 117 { PCI_PRODUCT_INTEL_82801BA_LAN, 118 "Intel i82562 Ethernet" }, 119 { PCI_PRODUCT_INTEL_82801E_LAN_1, 120 "Intel i82559 Ethernet" }, 121 { PCI_PRODUCT_INTEL_82801E_LAN_2, 122 "Intel i82559 Ethernet" }, 123 { PCI_PRODUCT_INTEL_PRO_100_VE_0, 124 "Intel PRO/100 VE Network Controller" }, 125 { PCI_PRODUCT_INTEL_PRO_100_VE_1, 126 "Intel PRO/100 VE Network Controller" }, 127 { PCI_PRODUCT_INTEL_PRO_100_VE_2, 128 "Intel PRO/100 VE Network Controller with 82562ET/EZ PHY" }, 129 { PCI_PRODUCT_INTEL_PRO_100_VE_3, 130 "Intel PRO/100 VE Network Controller with 82562ET/EZ (CNR) PHY" }, 131 { PCI_PRODUCT_INTEL_PRO_100_VE_4, 132 "Intel PRO/100 VE (MOB) Network Controller" }, 133 { PCI_PRODUCT_INTEL_PRO_100_VM_0, 134 "Intel PRO/100 VM Network Controller" }, 135 { PCI_PRODUCT_INTEL_PRO_100_VM_1, 136 "Intel PRO/100 VM Network Controller" }, 137 { PCI_PRODUCT_INTEL_PRO_100_VM_2, 138 "Intel PRO/100 VM Network Controller" }, 139 { PCI_PRODUCT_INTEL_PRO_100_VM_3, 140 "Intel PRO/100 VM Network Controller with 82562EM/EX PHY" }, 141 { PCI_PRODUCT_INTEL_PRO_100_VM_4, 142 "Intel PRO/100 VM Network Controller with 82562EM/EX (CNR) PHY" }, 143 { PCI_PRODUCT_INTEL_PRO_100_VM_5, 144 "Intel PRO/100 VM (MOB) Network Controller" }, 145 { PCI_PRODUCT_INTEL_PRO_100_VM_6, 146 "Intel PRO/100 VM Network Controller with 82562ET/EZ PHY" }, 147 { PCI_PRODUCT_INTEL_PRO_100_M, 148 "Intel PRO/100 M Network Controller" }, 149 { PCI_PRODUCT_INTEL_82801EB_LAN, 150 "Intel 82801EB/ER (ICH5) Network Controller" }, 151 { PCI_PRODUCT_INTEL_82801FB_LAN, 152 "Intel 82562EZ (ICH6)" }, 153 { 0, 154 NULL }, 155 }; 156 157 static const struct fxp_pci_product * 158 fxp_pci_lookup(const struct pci_attach_args *pa) 159 { 160 const struct fxp_pci_product *fpp; 161 162 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 163 return (NULL); 164 165 for (fpp = fxp_pci_products; fpp->fpp_name != NULL; fpp++) 166 if (PCI_PRODUCT(pa->pa_id) == fpp->fpp_prodid) 167 return (fpp); 168 169 return (NULL); 170 } 171 172 static int 173 fxp_pci_match(struct device *parent, struct cfdata *match, void *aux) 174 { 175 struct pci_attach_args *pa = aux; 176 177 if (fxp_pci_lookup(pa) != NULL) 178 return (1); 179 180 return (0); 181 } 182 183 /* 184 * Restore PCI configuration registers that may have been clobbered. 185 * This is necessary due to bugs on the Sony VAIO Z505-series on-board 186 * ethernet, after an APM suspend/resume, as well as after an ACPI 187 * D3->D0 transition. We call this function from a power hook after 188 * APM resume events, as well as after the ACPI D3->D0 transition. 189 */ 190 static void 191 fxp_pci_confreg_restore(struct fxp_pci_softc *psc) 192 { 193 pcireg_t reg; 194 195 #if 0 196 /* 197 * Check to see if the command register is blank -- if so, then 198 * we'll assume that all the clobberable-registers have been 199 * clobbered. 200 */ 201 202 /* 203 * In general, the above metric is accurate. Unfortunately, 204 * it is inaccurate across a hibernation. Ideally APM/ACPI 205 * code should take note of hibernation events and execute 206 * a hibernation wakeup hook, but at present a hibernation wake 207 * is indistinguishable from a suspend wake. 208 */ 209 210 if (((reg = pci_conf_read(psc->psc_pc, psc->psc_tag, 211 PCI_COMMAND_STATUS_REG)) & 0xffff) != 0) 212 return; 213 #else 214 reg = pci_conf_read(psc->psc_pc, psc->psc_tag, PCI_COMMAND_STATUS_REG); 215 #endif 216 217 pci_conf_write(psc->psc_pc, psc->psc_tag, 218 PCI_COMMAND_STATUS_REG, 219 (reg & 0xffff0000) | 220 (psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] & 0xffff)); 221 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_BHLC_REG, 222 psc->psc_regs[PCI_BHLC_REG>>2]); 223 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x0, 224 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2]); 225 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x4, 226 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2]); 227 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x8, 228 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2]); 229 } 230 231 232 /* 233 * Power handler routine. Called when the system is transitioning into/out 234 * of power save modes. We restore the (bashed) PCI configuration registers 235 * on a resume. 236 */ 237 static void 238 fxp_pci_power(int why, void *arg) 239 { 240 struct fxp_pci_softc *psc = arg; 241 242 if (why == PWR_RESUME) 243 fxp_pci_confreg_restore(psc); 244 } 245 246 static void 247 fxp_pci_attach(struct device *parent, struct device *self, void *aux) 248 { 249 struct fxp_pci_softc *psc = (struct fxp_pci_softc *)self; 250 struct fxp_softc *sc = (struct fxp_softc *)self; 251 struct pci_attach_args *pa = aux; 252 pci_chipset_tag_t pc = pa->pa_pc; 253 pci_intr_handle_t ih; 254 const struct fxp_pci_product *fpp; 255 const char *intrstr = NULL; 256 bus_space_tag_t iot, memt; 257 bus_space_handle_t ioh, memh; 258 int ioh_valid, memh_valid; 259 bus_addr_t addr; 260 bus_size_t size; 261 int flags; 262 int pci_pwrmgmt_cap_reg; 263 264 aprint_naive(": Ethernet controller\n"); 265 266 /* 267 * Map control/status registers. 268 */ 269 ioh_valid = (pci_mapreg_map(pa, FXP_PCI_IOBA, 270 PCI_MAPREG_TYPE_IO, 0, 271 &iot, &ioh, NULL, NULL) == 0); 272 273 /* 274 * Version 2.1 of the PCI spec, page 196, "Address Maps": 275 * 276 * Prefetchable 277 * 278 * Set to one if there are no side effects on reads, the 279 * device returns all bytes regardless of the byte enables, 280 * and host bridges can merge processor writes into this 281 * range without causing errors. Bit must be set to zero 282 * otherwise. 283 * 284 * The 82557 incorrectly sets the "prefetchable" bit, resulting 285 * in errors on systems which will do merged reads and writes. 286 * These errors manifest themselves as all-bits-set when reading 287 * from the EEPROM or other < 4 byte registers. 288 * 289 * We must work around this problem by always forcing the mapping 290 * for memory space to be uncacheable. On systems which cannot 291 * create an uncacheable mapping (because the firmware mapped it 292 * into only cacheable/prefetchable space due to the "prefetchable" 293 * bit), we can fall back onto i/o mapped access. 294 */ 295 memh_valid = 0; 296 memt = pa->pa_memt; 297 if (((pa->pa_flags & PCI_FLAGS_MEM_ENABLED) != 0) && 298 pci_mapreg_info(pa->pa_pc, pa->pa_tag, FXP_PCI_MMBA, 299 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 300 &addr, &size, &flags) == 0) { 301 flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 302 if (bus_space_map(memt, addr, size, flags, &memh) == 0) 303 memh_valid = 1; 304 } 305 306 if (memh_valid) { 307 sc->sc_st = memt; 308 sc->sc_sh = memh; 309 } else if (ioh_valid) { 310 sc->sc_st = iot; 311 sc->sc_sh = ioh; 312 } else { 313 aprint_error(": unable to map device registers\n"); 314 return; 315 } 316 317 sc->sc_dmat = pa->pa_dmat; 318 319 fpp = fxp_pci_lookup(pa); 320 if (fpp == NULL) { 321 printf("\n"); 322 panic("fxp_pci_attach: impossible"); 323 } 324 325 sc->sc_rev = PCI_REVISION(pa->pa_class); 326 327 switch (fpp->fpp_prodid) { 328 case PCI_PRODUCT_INTEL_82557: 329 case PCI_PRODUCT_INTEL_82559ER: 330 case PCI_PRODUCT_INTEL_IN_BUSINESS: 331 { 332 const char *chipname = NULL; 333 334 if (sc->sc_rev >= FXP_REV_82558_A4) { 335 chipname = "i82558 Ethernet"; 336 /* 337 * Enable the MWI command for memory writes. 338 */ 339 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 340 sc->sc_flags |= FXPF_MWI; 341 } 342 if (sc->sc_rev >= FXP_REV_82559_A0) 343 chipname = "i82559 Ethernet"; 344 if (sc->sc_rev >= FXP_REV_82559S_A) 345 chipname = "i82559S Ethernet"; 346 if (sc->sc_rev >= FXP_REV_82550) 347 chipname = "i82550 Ethernet"; 348 349 /* 350 * Mark all i82559 and i82550 revisions as having 351 * the "resume bug". See i82557.c for details. 352 */ 353 if (sc->sc_rev >= FXP_REV_82559_A0) 354 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 355 356 aprint_normal(": %s, rev %d\n", chipname != NULL ? chipname : 357 fpp->fpp_name, sc->sc_rev); 358 break; 359 } 360 361 case PCI_PRODUCT_INTEL_82801BA_LAN: 362 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 363 364 /* 365 * The 82801BA Ethernet has a bug which requires us to send a 366 * NOP before a CU_RESUME if we're in 10baseT mode. 367 */ 368 if (fpp->fpp_prodid == PCI_PRODUCT_INTEL_82801BA_LAN) 369 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 370 break; 371 372 case PCI_PRODUCT_INTEL_PRO_100_VE_0: 373 case PCI_PRODUCT_INTEL_PRO_100_VE_1: 374 case PCI_PRODUCT_INTEL_PRO_100_VM_0: 375 case PCI_PRODUCT_INTEL_PRO_100_VM_1: 376 case PCI_PRODUCT_INTEL_82562EH_HPNA_0: 377 case PCI_PRODUCT_INTEL_82562EH_HPNA_1: 378 case PCI_PRODUCT_INTEL_82562EH_HPNA_2: 379 case PCI_PRODUCT_INTEL_PRO_100_VM_2: 380 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 381 382 /* 383 * ICH3 chips apparently have problems with the enhanced 384 * features, so just treat them as an i82557. It also 385 * has the resume bug that the ICH2 has. 386 */ 387 sc->sc_rev = 1; 388 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 389 break; 390 case PCI_PRODUCT_INTEL_82801E_LAN_1: 391 case PCI_PRODUCT_INTEL_82801E_LAN_2: 392 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 393 394 /* 395 * XXX We have to read the C-ICH's developer's manual 396 * in detail 397 */ 398 break; 399 case PCI_PRODUCT_INTEL_PRO_100_VE_2: 400 case PCI_PRODUCT_INTEL_PRO_100_VE_3: 401 case PCI_PRODUCT_INTEL_PRO_100_VE_4: 402 case PCI_PRODUCT_INTEL_PRO_100_VM_3: 403 case PCI_PRODUCT_INTEL_PRO_100_VM_4: 404 case PCI_PRODUCT_INTEL_PRO_100_VM_5: 405 case PCI_PRODUCT_INTEL_PRO_100_VM_6: 406 case PCI_PRODUCT_INTEL_82801EB_LAN: 407 case PCI_PRODUCT_INTEL_82801FB_LAN: 408 default: 409 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 410 411 /* 412 * No particular quirks. 413 */ 414 break; 415 } 416 417 /* Make sure bus-mastering is enabled. */ 418 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 419 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 420 PCI_COMMAND_MASTER_ENABLE); 421 422 /* 423 * Under some circumstances (such as APM suspend/resume 424 * cycles, and across ACPI power state changes), the 425 * i82257-family can lose the contents of critical PCI 426 * configuration registers, causing the card to be 427 * non-responsive and useless. This occurs on the Sony VAIO 428 * Z505-series, among others. Preserve them here so they can 429 * be later restored (by fxp_pci_confreg_restore()). 430 */ 431 psc->psc_pc = pc; 432 psc->psc_tag = pa->pa_tag; 433 psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] = 434 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 435 psc->psc_regs[PCI_BHLC_REG>>2] = 436 pci_conf_read(pc, pa->pa_tag, PCI_BHLC_REG); 437 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2] = 438 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x0); 439 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2] = 440 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x4); 441 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2] = 442 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x8); 443 444 /* 445 * Work around BIOS ACPI bugs where the chip is inadvertantly 446 * left in ACPI D3 (lowest power state). First confirm the device 447 * supports ACPI power management, then move it to the D0 (fully 448 * functional) state if it is not already there. 449 */ 450 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 451 &pci_pwrmgmt_cap_reg, 0)) { 452 pcireg_t reg; 453 454 sc->sc_enable = fxp_pci_enable; 455 sc->sc_disable = fxp_pci_disable; 456 457 psc->psc_pwrmgmt_csr_reg = pci_pwrmgmt_cap_reg + PCI_PMCSR; 458 reg = pci_conf_read(pc, pa->pa_tag, psc->psc_pwrmgmt_csr_reg); 459 psc->psc_pwrmgmt_csr = (reg & ~PCI_PMCSR_STATE_MASK) | 460 PCI_PMCSR_STATE_D0; 461 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0) 462 pci_conf_write(pc, pa->pa_tag, psc->psc_pwrmgmt_csr_reg, 463 psc->psc_pwrmgmt_csr); 464 } 465 /* Restore PCI configuration registers. */ 466 fxp_pci_confreg_restore(psc); 467 468 sc->sc_enabled = 1; 469 470 /* 471 * Map and establish our interrupt. 472 */ 473 if (pci_intr_map(pa, &ih)) { 474 aprint_error("%s: couldn't map interrupt\n", 475 sc->sc_dev.dv_xname); 476 return; 477 } 478 intrstr = pci_intr_string(pc, ih); 479 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, fxp_intr, sc); 480 if (sc->sc_ih == NULL) { 481 aprint_error("%s: couldn't establish interrupt", 482 sc->sc_dev.dv_xname); 483 if (intrstr != NULL) 484 aprint_normal(" at %s", intrstr); 485 aprint_normal("\n"); 486 return; 487 } 488 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 489 490 /* Finish off the attach. */ 491 fxp_attach(sc); 492 if (sc->sc_disable != NULL) 493 fxp_disable(sc); 494 495 /* Add a suspend hook to restore PCI config state */ 496 psc->psc_powerhook = powerhook_establish(fxp_pci_power, psc); 497 if (psc->psc_powerhook == NULL) 498 aprint_error( 499 "%s: WARNING: unable to establish pci power hook\n", 500 sc->sc_dev.dv_xname); 501 } 502 503 static int 504 fxp_pci_enable(struct fxp_softc *sc) 505 { 506 struct fxp_pci_softc *psc = (void *) sc; 507 508 #if 0 509 printf("%s: going to power state D0\n", sc->sc_dev.dv_xname); 510 #endif 511 512 /* Bring the device into D0 power state. */ 513 pci_conf_write(psc->psc_pc, psc->psc_tag, 514 psc->psc_pwrmgmt_csr_reg, psc->psc_pwrmgmt_csr); 515 516 /* Now restore the configuration registers. */ 517 fxp_pci_confreg_restore(psc); 518 519 return (0); 520 } 521 522 static void 523 fxp_pci_disable(struct fxp_softc *sc) 524 { 525 struct fxp_pci_softc *psc = (void *) sc; 526 527 /* 528 * for some 82558_A4 and 82558_B0, entering D3 state makes 529 * media detection disordered. 530 */ 531 if (sc->sc_rev <= FXP_REV_82558_B0) 532 return; 533 534 #if 0 535 printf("%s: going to power state D3\n", sc->sc_dev.dv_xname); 536 #endif 537 538 /* Put the device into D3 state. */ 539 pci_conf_write(psc->psc_pc, psc->psc_tag, 540 psc->psc_pwrmgmt_csr_reg, (psc->psc_pwrmgmt_csr & 541 ~PCI_PMCSR_STATE_MASK) | PCI_PMCSR_STATE_D3); 542 } 543
Indexes created Fri Sep 26 08:10:20 GMT 2025