if_fxp_pci.c revision 1.44
1 /* $NetBSD: if_fxp_pci.c,v 1.44 2006/01/10 20:31:36 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * PCI bus front-end for the Intel i82557 fast Ethernet controller 42 * driver. Works with Intel Etherexpress Pro 10+, 100B, 100+ cards. 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: if_fxp_pci.c,v 1.44 2006/01/10 20:31:36 christos Exp $"); 47 48 #include "rnd.h" 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/mbuf.h> 53 #include <sys/malloc.h> 54 #include <sys/kernel.h> 55 #include <sys/socket.h> 56 #include <sys/ioctl.h> 57 #include <sys/errno.h> 58 #include <sys/device.h> 59 60 #if NRND > 0 61 #include <sys/rnd.h> 62 #endif 63 64 #include <machine/endian.h> 65 66 #include <net/if.h> 67 #include <net/if_dl.h> 68 #include <net/if_media.h> 69 #include <net/if_ether.h> 70 71 #include <machine/bus.h> 72 #include <machine/intr.h> 73 74 #include <dev/mii/miivar.h> 75 76 #include <dev/ic/i82557reg.h> 77 #include <dev/ic/i82557var.h> 78 79 #include <dev/pci/pcivar.h> 80 #include <dev/pci/pcireg.h> 81 #include <dev/pci/pcidevs.h> 82 83 struct fxp_pci_softc { 84 struct fxp_softc psc_fxp; 85 86 pci_chipset_tag_t psc_pc; /* pci chipset tag */ 87 pcireg_t psc_regs[0x20>>2]; /* saved PCI config regs (sparse) */ 88 pcitag_t psc_tag; /* pci register tag */ 89 void *psc_powerhook; /* power hook */ 90 91 int psc_pwrmgmt_csr_reg; /* ACPI power management register */ 92 pcireg_t psc_pwrmgmt_csr; /* ...and the contents at D0 */ 93 }; 94 95 static int fxp_pci_match(struct device *, struct cfdata *, void *); 96 static void fxp_pci_attach(struct device *, struct device *, void *); 97 98 static int fxp_pci_enable(struct fxp_softc *); 99 static void fxp_pci_disable(struct fxp_softc *); 100 101 static void fxp_pci_confreg_restore(struct fxp_pci_softc *psc); 102 static void fxp_pci_power(int why, void *arg); 103 104 CFATTACH_DECL(fxp_pci, sizeof(struct fxp_pci_softc), 105 fxp_pci_match, fxp_pci_attach, NULL, NULL); 106 107 static const struct fxp_pci_product { 108 u_int32_t fpp_prodid; /* PCI product ID */ 109 const char *fpp_name; /* device name */ 110 } fxp_pci_products[] = { 111 { PCI_PRODUCT_INTEL_82557, 112 "Intel i82557 Ethernet" }, 113 { PCI_PRODUCT_INTEL_82559ER, 114 "Intel i82559ER Ethernet" }, 115 { PCI_PRODUCT_INTEL_IN_BUSINESS, 116 "Intel InBusiness Ethernet" }, 117 { PCI_PRODUCT_INTEL_82801BA_LAN, 118 "Intel i82562 Ethernet" }, 119 { PCI_PRODUCT_INTEL_82801E_LAN_1, 120 "Intel i82559 Ethernet" }, 121 { PCI_PRODUCT_INTEL_82801E_LAN_2, 122 "Intel i82559 Ethernet" }, 123 { PCI_PRODUCT_INTEL_PRO_100_VE_0, 124 "Intel PRO/100 VE Network Controller" }, 125 { PCI_PRODUCT_INTEL_PRO_100_VE_1, 126 "Intel PRO/100 VE Network Controller" }, 127 { PCI_PRODUCT_INTEL_PRO_100_VE_2, 128 "Intel PRO/100 VE Network Controller with 82562ET/EZ PHY" }, 129 { PCI_PRODUCT_INTEL_PRO_100_VE_3, 130 "Intel PRO/100 VE Network Controller with 82562ET/EZ (CNR) PHY" }, 131 { PCI_PRODUCT_INTEL_PRO_100_VE_4, 132 "Intel PRO/100 VE (MOB) Network Controller" }, 133 { PCI_PRODUCT_INTEL_PRO_100_VE_5, 134 "Intel PRO/100 VE (LOM) Network Controller" }, 135 { PCI_PRODUCT_INTEL_PRO_100_VM_0, 136 "Intel PRO/100 VM Network Controller" }, 137 { PCI_PRODUCT_INTEL_PRO_100_VM_1, 138 "Intel PRO/100 VM Network Controller" }, 139 { PCI_PRODUCT_INTEL_PRO_100_VM_2, 140 "Intel PRO/100 VM Network Controller" }, 141 { PCI_PRODUCT_INTEL_PRO_100_VM_3, 142 "Intel PRO/100 VM Network Controller with 82562EM/EX PHY" }, 143 { PCI_PRODUCT_INTEL_PRO_100_VM_4, 144 "Intel PRO/100 VM Network Controller with 82562EM/EX (CNR) PHY" }, 145 { PCI_PRODUCT_INTEL_PRO_100_VM_5, 146 "Intel PRO/100 VM (MOB) Network Controller" }, 147 { PCI_PRODUCT_INTEL_PRO_100_VM_6, 148 "Intel PRO/100 VM Network Controller with 82562ET/EZ PHY" }, 149 { PCI_PRODUCT_INTEL_PRO_100_M, 150 "Intel PRO/100 M Network Controller" }, 151 { PCI_PRODUCT_INTEL_82801EB_LAN, 152 "Intel 82801EB/ER (ICH5) Network Controller" }, 153 { PCI_PRODUCT_INTEL_82801FB_LAN, 154 "Intel 82562EZ (ICH6)" }, 155 { PCI_PRODUCT_INTEL_82801G_LAN, 156 "Intel 82801GB/GR (ICH7) Network Controller" }, 157 { 0, 158 NULL }, 159 }; 160 161 static const struct fxp_pci_product * 162 fxp_pci_lookup(const struct pci_attach_args *pa) 163 { 164 const struct fxp_pci_product *fpp; 165 166 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 167 return (NULL); 168 169 for (fpp = fxp_pci_products; fpp->fpp_name != NULL; fpp++) 170 if (PCI_PRODUCT(pa->pa_id) == fpp->fpp_prodid) 171 return (fpp); 172 173 return (NULL); 174 } 175 176 static int 177 fxp_pci_match(struct device *parent, struct cfdata *match, void *aux) 178 { 179 struct pci_attach_args *pa = aux; 180 181 if (fxp_pci_lookup(pa) != NULL) 182 return (1); 183 184 return (0); 185 } 186 187 /* 188 * Restore PCI configuration registers that may have been clobbered. 189 * This is necessary due to bugs on the Sony VAIO Z505-series on-board 190 * ethernet, after an APM suspend/resume, as well as after an ACPI 191 * D3->D0 transition. We call this function from a power hook after 192 * APM resume events, as well as after the ACPI D3->D0 transition. 193 */ 194 static void 195 fxp_pci_confreg_restore(struct fxp_pci_softc *psc) 196 { 197 pcireg_t reg; 198 199 #if 0 200 /* 201 * Check to see if the command register is blank -- if so, then 202 * we'll assume that all the clobberable-registers have been 203 * clobbered. 204 */ 205 206 /* 207 * In general, the above metric is accurate. Unfortunately, 208 * it is inaccurate across a hibernation. Ideally APM/ACPI 209 * code should take note of hibernation events and execute 210 * a hibernation wakeup hook, but at present a hibernation wake 211 * is indistinguishable from a suspend wake. 212 */ 213 214 if (((reg = pci_conf_read(psc->psc_pc, psc->psc_tag, 215 PCI_COMMAND_STATUS_REG)) & 0xffff) != 0) 216 return; 217 #else 218 reg = pci_conf_read(psc->psc_pc, psc->psc_tag, PCI_COMMAND_STATUS_REG); 219 #endif 220 221 pci_conf_write(psc->psc_pc, psc->psc_tag, 222 PCI_COMMAND_STATUS_REG, 223 (reg & 0xffff0000) | 224 (psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] & 0xffff)); 225 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_BHLC_REG, 226 psc->psc_regs[PCI_BHLC_REG>>2]); 227 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x0, 228 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2]); 229 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x4, 230 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2]); 231 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x8, 232 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2]); 233 } 234 235 236 /* 237 * Power handler routine. Called when the system is transitioning into/out 238 * of power save modes. We restore the (bashed) PCI configuration registers 239 * on a resume. 240 */ 241 static void 242 fxp_pci_power(int why, void *arg) 243 { 244 struct fxp_pci_softc *psc = arg; 245 246 if (why == PWR_RESUME) 247 fxp_pci_confreg_restore(psc); 248 } 249 250 static void 251 fxp_pci_attach(struct device *parent, struct device *self, void *aux) 252 { 253 struct fxp_pci_softc *psc = (struct fxp_pci_softc *)self; 254 struct fxp_softc *sc = (struct fxp_softc *)self; 255 struct pci_attach_args *pa = aux; 256 pci_chipset_tag_t pc = pa->pa_pc; 257 pci_intr_handle_t ih; 258 const struct fxp_pci_product *fpp; 259 const char *intrstr = NULL; 260 bus_space_tag_t iot, memt; 261 bus_space_handle_t ioh, memh; 262 int ioh_valid, memh_valid; 263 bus_addr_t addr; 264 bus_size_t size; 265 int flags; 266 int pci_pwrmgmt_cap_reg; 267 268 aprint_naive(": Ethernet controller\n"); 269 270 /* 271 * Map control/status registers. 272 */ 273 ioh_valid = (pci_mapreg_map(pa, FXP_PCI_IOBA, 274 PCI_MAPREG_TYPE_IO, 0, 275 &iot, &ioh, NULL, NULL) == 0); 276 277 /* 278 * Version 2.1 of the PCI spec, page 196, "Address Maps": 279 * 280 * Prefetchable 281 * 282 * Set to one if there are no side effects on reads, the 283 * device returns all bytes regardless of the byte enables, 284 * and host bridges can merge processor writes into this 285 * range without causing errors. Bit must be set to zero 286 * otherwise. 287 * 288 * The 82557 incorrectly sets the "prefetchable" bit, resulting 289 * in errors on systems which will do merged reads and writes. 290 * These errors manifest themselves as all-bits-set when reading 291 * from the EEPROM or other < 4 byte registers. 292 * 293 * We must work around this problem by always forcing the mapping 294 * for memory space to be uncacheable. On systems which cannot 295 * create an uncacheable mapping (because the firmware mapped it 296 * into only cacheable/prefetchable space due to the "prefetchable" 297 * bit), we can fall back onto i/o mapped access. 298 */ 299 memh_valid = 0; 300 memt = pa->pa_memt; 301 if (((pa->pa_flags & PCI_FLAGS_MEM_ENABLED) != 0) && 302 pci_mapreg_info(pa->pa_pc, pa->pa_tag, FXP_PCI_MMBA, 303 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 304 &addr, &size, &flags) == 0) { 305 flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 306 if (bus_space_map(memt, addr, size, flags, &memh) == 0) 307 memh_valid = 1; 308 } 309 310 if (memh_valid) { 311 sc->sc_st = memt; 312 sc->sc_sh = memh; 313 } else if (ioh_valid) { 314 sc->sc_st = iot; 315 sc->sc_sh = ioh; 316 } else { 317 aprint_error(": unable to map device registers\n"); 318 return; 319 } 320 321 sc->sc_dmat = pa->pa_dmat; 322 323 fpp = fxp_pci_lookup(pa); 324 if (fpp == NULL) { 325 printf("\n"); 326 panic("fxp_pci_attach: impossible"); 327 } 328 329 sc->sc_rev = PCI_REVISION(pa->pa_class); 330 331 switch (fpp->fpp_prodid) { 332 case PCI_PRODUCT_INTEL_82557: 333 case PCI_PRODUCT_INTEL_82559ER: 334 case PCI_PRODUCT_INTEL_IN_BUSINESS: 335 { 336 const char *chipname = NULL; 337 338 if (sc->sc_rev >= FXP_REV_82558_A4) { 339 chipname = "i82558 Ethernet"; 340 /* 341 * Enable the MWI command for memory writes. 342 */ 343 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 344 sc->sc_flags |= FXPF_MWI; 345 } 346 if (sc->sc_rev >= FXP_REV_82559_A0) 347 chipname = "i82559 Ethernet"; 348 if (sc->sc_rev >= FXP_REV_82559S_A) 349 chipname = "i82559S Ethernet"; 350 if (sc->sc_rev >= FXP_REV_82550) 351 chipname = "i82550 Ethernet"; 352 353 /* 354 * Mark all i82559 and i82550 revisions as having 355 * the "resume bug". See i82557.c for details. 356 */ 357 if (sc->sc_rev >= FXP_REV_82559_A0) 358 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 359 360 aprint_normal(": %s, rev %d\n", chipname != NULL ? chipname : 361 fpp->fpp_name, sc->sc_rev); 362 break; 363 } 364 365 case PCI_PRODUCT_INTEL_82801BA_LAN: 366 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 367 368 /* 369 * The 82801BA Ethernet has a bug which requires us to send a 370 * NOP before a CU_RESUME if we're in 10baseT mode. 371 */ 372 if (fpp->fpp_prodid == PCI_PRODUCT_INTEL_82801BA_LAN) 373 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 374 break; 375 376 case PCI_PRODUCT_INTEL_PRO_100_VE_0: 377 case PCI_PRODUCT_INTEL_PRO_100_VE_1: 378 case PCI_PRODUCT_INTEL_PRO_100_VM_0: 379 case PCI_PRODUCT_INTEL_PRO_100_VM_1: 380 case PCI_PRODUCT_INTEL_82562EH_HPNA_0: 381 case PCI_PRODUCT_INTEL_82562EH_HPNA_1: 382 case PCI_PRODUCT_INTEL_82562EH_HPNA_2: 383 case PCI_PRODUCT_INTEL_PRO_100_VM_2: 384 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 385 386 /* 387 * ICH3 chips apparently have problems with the enhanced 388 * features, so just treat them as an i82557. It also 389 * has the resume bug that the ICH2 has. 390 */ 391 sc->sc_rev = 1; 392 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 393 break; 394 case PCI_PRODUCT_INTEL_82801E_LAN_1: 395 case PCI_PRODUCT_INTEL_82801E_LAN_2: 396 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 397 398 /* 399 * XXX We have to read the C-ICH's developer's manual 400 * in detail 401 */ 402 break; 403 case PCI_PRODUCT_INTEL_PRO_100_VE_2: 404 case PCI_PRODUCT_INTEL_PRO_100_VE_3: 405 case PCI_PRODUCT_INTEL_PRO_100_VE_4: 406 case PCI_PRODUCT_INTEL_PRO_100_VE_5: 407 case PCI_PRODUCT_INTEL_PRO_100_VM_3: 408 case PCI_PRODUCT_INTEL_PRO_100_VM_4: 409 case PCI_PRODUCT_INTEL_PRO_100_VM_5: 410 case PCI_PRODUCT_INTEL_PRO_100_VM_6: 411 case PCI_PRODUCT_INTEL_82801EB_LAN: 412 case PCI_PRODUCT_INTEL_82801FB_LAN: 413 case PCI_PRODUCT_INTEL_82801G_LAN: 414 default: 415 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 416 417 /* 418 * No particular quirks. 419 */ 420 break; 421 } 422 423 /* Make sure bus-mastering is enabled. */ 424 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 425 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 426 PCI_COMMAND_MASTER_ENABLE); 427 428 /* 429 * Under some circumstances (such as APM suspend/resume 430 * cycles, and across ACPI power state changes), the 431 * i82257-family can lose the contents of critical PCI 432 * configuration registers, causing the card to be 433 * non-responsive and useless. This occurs on the Sony VAIO 434 * Z505-series, among others. Preserve them here so they can 435 * be later restored (by fxp_pci_confreg_restore()). 436 */ 437 psc->psc_pc = pc; 438 psc->psc_tag = pa->pa_tag; 439 psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] = 440 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 441 psc->psc_regs[PCI_BHLC_REG>>2] = 442 pci_conf_read(pc, pa->pa_tag, PCI_BHLC_REG); 443 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2] = 444 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x0); 445 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2] = 446 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x4); 447 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2] = 448 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x8); 449 450 /* 451 * Work around BIOS ACPI bugs where the chip is inadvertantly 452 * left in ACPI D3 (lowest power state). First confirm the device 453 * supports ACPI power management, then move it to the D0 (fully 454 * functional) state if it is not already there. 455 */ 456 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 457 &pci_pwrmgmt_cap_reg, 0)) { 458 pcireg_t reg; 459 460 sc->sc_enable = fxp_pci_enable; 461 sc->sc_disable = fxp_pci_disable; 462 463 psc->psc_pwrmgmt_csr_reg = pci_pwrmgmt_cap_reg + PCI_PMCSR; 464 reg = pci_conf_read(pc, pa->pa_tag, psc->psc_pwrmgmt_csr_reg); 465 psc->psc_pwrmgmt_csr = (reg & ~PCI_PMCSR_STATE_MASK) | 466 PCI_PMCSR_STATE_D0; 467 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0) 468 pci_conf_write(pc, pa->pa_tag, psc->psc_pwrmgmt_csr_reg, 469 psc->psc_pwrmgmt_csr); 470 } 471 /* Restore PCI configuration registers. */ 472 fxp_pci_confreg_restore(psc); 473 474 sc->sc_enabled = 1; 475 476 /* 477 * Map and establish our interrupt. 478 */ 479 if (pci_intr_map(pa, &ih)) { 480 aprint_error("%s: couldn't map interrupt\n", 481 sc->sc_dev.dv_xname); 482 return; 483 } 484 intrstr = pci_intr_string(pc, ih); 485 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, fxp_intr, sc); 486 if (sc->sc_ih == NULL) { 487 aprint_error("%s: couldn't establish interrupt", 488 sc->sc_dev.dv_xname); 489 if (intrstr != NULL) 490 aprint_normal(" at %s", intrstr); 491 aprint_normal("\n"); 492 return; 493 } 494 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 495 496 /* Finish off the attach. */ 497 fxp_attach(sc); 498 if (sc->sc_disable != NULL) 499 fxp_disable(sc); 500 501 /* Add a suspend hook to restore PCI config state */ 502 psc->psc_powerhook = powerhook_establish(fxp_pci_power, psc); 503 if (psc->psc_powerhook == NULL) 504 aprint_error( 505 "%s: WARNING: unable to establish pci power hook\n", 506 sc->sc_dev.dv_xname); 507 } 508 509 static int 510 fxp_pci_enable(struct fxp_softc *sc) 511 { 512 struct fxp_pci_softc *psc = (void *) sc; 513 514 #if 0 515 printf("%s: going to power state D0\n", sc->sc_dev.dv_xname); 516 #endif 517 518 /* Bring the device into D0 power state. */ 519 pci_conf_write(psc->psc_pc, psc->psc_tag, 520 psc->psc_pwrmgmt_csr_reg, psc->psc_pwrmgmt_csr); 521 522 /* Now restore the configuration registers. */ 523 fxp_pci_confreg_restore(psc); 524 525 return (0); 526 } 527 528 static void 529 fxp_pci_disable(struct fxp_softc *sc) 530 { 531 struct fxp_pci_softc *psc = (void *) sc; 532 533 /* 534 * for some 82558_A4 and 82558_B0, entering D3 state makes 535 * media detection disordered. 536 */ 537 if (sc->sc_rev <= FXP_REV_82558_B0) 538 return; 539 540 #if 0 541 printf("%s: going to power state D3\n", sc->sc_dev.dv_xname); 542 #endif 543 544 /* Put the device into D3 state. */ 545 pci_conf_write(psc->psc_pc, psc->psc_tag, 546 psc->psc_pwrmgmt_csr_reg, (psc->psc_pwrmgmt_csr & 547 ~PCI_PMCSR_STATE_MASK) | PCI_PMCSR_STATE_D3); 548 } 549
Indexes created Wed Sep 24 05:09:52 GMT 2025