if_fxp_pci.c revision 1.44.14.1
1 /* $NetBSD: if_fxp_pci.c,v 1.44.14.1 2006/07/13 17:49:27 gdamore Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * PCI bus front-end for the Intel i82557 fast Ethernet controller 42 * driver. Works with Intel Etherexpress Pro 10+, 100B, 100+ cards. 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: if_fxp_pci.c,v 1.44.14.1 2006/07/13 17:49:27 gdamore Exp $"); 47 48 #include "rnd.h" 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/mbuf.h> 53 #include <sys/malloc.h> 54 #include <sys/kernel.h> 55 #include <sys/socket.h> 56 #include <sys/ioctl.h> 57 #include <sys/errno.h> 58 #include <sys/device.h> 59 60 #if NRND > 0 61 #include <sys/rnd.h> 62 #endif 63 64 #include <machine/endian.h> 65 66 #include <net/if.h> 67 #include <net/if_dl.h> 68 #include <net/if_media.h> 69 #include <net/if_ether.h> 70 71 #include <machine/bus.h> 72 #include <machine/intr.h> 73 74 #include <dev/mii/miivar.h> 75 76 #include <dev/ic/i82557reg.h> 77 #include <dev/ic/i82557var.h> 78 79 #include <dev/pci/pcivar.h> 80 #include <dev/pci/pcireg.h> 81 #include <dev/pci/pcidevs.h> 82 83 struct fxp_pci_softc { 84 struct fxp_softc psc_fxp; 85 86 pci_chipset_tag_t psc_pc; /* pci chipset tag */ 87 pcireg_t psc_regs[0x20>>2]; /* saved PCI config regs (sparse) */ 88 pcitag_t psc_tag; /* pci register tag */ 89 void *psc_powerhook; /* power hook */ 90 91 int psc_pwrmgmt_csr_reg; /* ACPI power management register */ 92 pcireg_t psc_pwrmgmt_csr; /* ...and the contents at D0 */ 93 struct pci_conf_state psc_pciconf; /* standard PCI configuration regs */ 94 }; 95 96 static int fxp_pci_match(struct device *, struct cfdata *, void *); 97 static void fxp_pci_attach(struct device *, struct device *, void *); 98 99 static int fxp_pci_enable(struct fxp_softc *); 100 static void fxp_pci_disable(struct fxp_softc *); 101 102 static void fxp_pci_confreg_restore(struct fxp_pci_softc *psc); 103 static void fxp_pci_powerhook(int why, void *arg); 104 105 CFATTACH_DECL(fxp_pci, sizeof(struct fxp_pci_softc), 106 fxp_pci_match, fxp_pci_attach, NULL, NULL); 107 108 static const struct fxp_pci_product { 109 u_int32_t fpp_prodid; /* PCI product ID */ 110 const char *fpp_name; /* device name */ 111 } fxp_pci_products[] = { 112 { PCI_PRODUCT_INTEL_82557, 113 "Intel i82557 Ethernet" }, 114 { PCI_PRODUCT_INTEL_82559ER, 115 "Intel i82559ER Ethernet" }, 116 { PCI_PRODUCT_INTEL_IN_BUSINESS, 117 "Intel InBusiness Ethernet" }, 118 { PCI_PRODUCT_INTEL_82801BA_LAN, 119 "Intel i82562 Ethernet" }, 120 { PCI_PRODUCT_INTEL_82801E_LAN_1, 121 "Intel i82559 Ethernet" }, 122 { PCI_PRODUCT_INTEL_82801E_LAN_2, 123 "Intel i82559 Ethernet" }, 124 { PCI_PRODUCT_INTEL_PRO_100_VE_0, 125 "Intel PRO/100 VE Network Controller" }, 126 { PCI_PRODUCT_INTEL_PRO_100_VE_1, 127 "Intel PRO/100 VE Network Controller" }, 128 { PCI_PRODUCT_INTEL_PRO_100_VE_2, 129 "Intel PRO/100 VE Network Controller with 82562ET/EZ PHY" }, 130 { PCI_PRODUCT_INTEL_PRO_100_VE_3, 131 "Intel PRO/100 VE Network Controller with 82562ET/EZ (CNR) PHY" }, 132 { PCI_PRODUCT_INTEL_PRO_100_VE_4, 133 "Intel PRO/100 VE (MOB) Network Controller" }, 134 { PCI_PRODUCT_INTEL_PRO_100_VE_5, 135 "Intel PRO/100 VE (LOM) Network Controller" }, 136 { PCI_PRODUCT_INTEL_PRO_100_VM_0, 137 "Intel PRO/100 VM Network Controller" }, 138 { PCI_PRODUCT_INTEL_PRO_100_VM_1, 139 "Intel PRO/100 VM Network Controller" }, 140 { PCI_PRODUCT_INTEL_PRO_100_VM_2, 141 "Intel PRO/100 VM Network Controller" }, 142 { PCI_PRODUCT_INTEL_PRO_100_VM_3, 143 "Intel PRO/100 VM Network Controller with 82562EM/EX PHY" }, 144 { PCI_PRODUCT_INTEL_PRO_100_VM_4, 145 "Intel PRO/100 VM Network Controller with 82562EM/EX (CNR) PHY" }, 146 { PCI_PRODUCT_INTEL_PRO_100_VM_5, 147 "Intel PRO/100 VM (MOB) Network Controller" }, 148 { PCI_PRODUCT_INTEL_PRO_100_VM_6, 149 "Intel PRO/100 VM Network Controller with 82562ET/EZ PHY" }, 150 { PCI_PRODUCT_INTEL_PRO_100_M, 151 "Intel PRO/100 M Network Controller" }, 152 { PCI_PRODUCT_INTEL_82801EB_LAN, 153 "Intel 82801EB/ER (ICH5) Network Controller" }, 154 { PCI_PRODUCT_INTEL_82801FB_LAN, 155 "Intel 82562EZ (ICH6)" }, 156 { PCI_PRODUCT_INTEL_82801G_LAN, 157 "Intel 82801GB/GR (ICH7) Network Controller" }, 158 { 0, 159 NULL }, 160 }; 161 162 static const struct fxp_pci_product * 163 fxp_pci_lookup(const struct pci_attach_args *pa) 164 { 165 const struct fxp_pci_product *fpp; 166 167 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 168 return (NULL); 169 170 for (fpp = fxp_pci_products; fpp->fpp_name != NULL; fpp++) 171 if (PCI_PRODUCT(pa->pa_id) == fpp->fpp_prodid) 172 return (fpp); 173 174 return (NULL); 175 } 176 177 static int 178 fxp_pci_match(struct device *parent, struct cfdata *match, void *aux) 179 { 180 struct pci_attach_args *pa = aux; 181 182 if (fxp_pci_lookup(pa) != NULL) 183 return (1); 184 185 return (0); 186 } 187 188 /* 189 * Restore PCI configuration registers that may have been clobbered. 190 * This is necessary due to bugs on the Sony VAIO Z505-series on-board 191 * ethernet, after an APM suspend/resume, as well as after an ACPI 192 * D3->D0 transition. We call this function from a power hook after 193 * APM resume events, as well as after the ACPI D3->D0 transition. 194 */ 195 static void 196 fxp_pci_confreg_restore(struct fxp_pci_softc *psc) 197 { 198 pcireg_t reg; 199 200 #if 0 201 /* 202 * Check to see if the command register is blank -- if so, then 203 * we'll assume that all the clobberable-registers have been 204 * clobbered. 205 */ 206 207 /* 208 * In general, the above metric is accurate. Unfortunately, 209 * it is inaccurate across a hibernation. Ideally APM/ACPI 210 * code should take note of hibernation events and execute 211 * a hibernation wakeup hook, but at present a hibernation wake 212 * is indistinguishable from a suspend wake. 213 */ 214 215 if (((reg = pci_conf_read(psc->psc_pc, psc->psc_tag, 216 PCI_COMMAND_STATUS_REG)) & 0xffff) != 0) 217 return; 218 #else 219 reg = pci_conf_read(psc->psc_pc, psc->psc_tag, PCI_COMMAND_STATUS_REG); 220 #endif 221 222 pci_conf_write(psc->psc_pc, psc->psc_tag, 223 PCI_COMMAND_STATUS_REG, 224 (reg & 0xffff0000) | 225 (psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] & 0xffff)); 226 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_BHLC_REG, 227 psc->psc_regs[PCI_BHLC_REG>>2]); 228 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x0, 229 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2]); 230 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x4, 231 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2]); 232 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x8, 233 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2]); 234 } 235 236 237 /* 238 * Power handler routine. Called when the system is transitioning into/out 239 * of power save modes. We restore the (bashed) PCI configuration registers 240 * on a resume. 241 */ 242 static void 243 fxp_pci_powerhook(int why, void *arg) 244 { 245 struct fxp_pci_softc *psc = arg; 246 247 switch (why) { 248 case PWR_SUSPEND: 249 pci_conf_capture(psc->psc_pc, psc->psc_tag, &psc->psc_pciconf); 250 break; 251 case PWR_RESUME: 252 pci_conf_restore(psc->psc_pc, psc->psc_tag, &psc->psc_pciconf); 253 fxp_pci_confreg_restore(psc); 254 break; 255 } 256 257 return; 258 } 259 260 static void 261 fxp_pci_attach(struct device *parent, struct device *self, void *aux) 262 { 263 struct fxp_pci_softc *psc = (struct fxp_pci_softc *)self; 264 struct fxp_softc *sc = (struct fxp_softc *)self; 265 struct pci_attach_args *pa = aux; 266 pci_chipset_tag_t pc = pa->pa_pc; 267 pci_intr_handle_t ih; 268 const struct fxp_pci_product *fpp; 269 const char *intrstr = NULL; 270 bus_space_tag_t iot, memt; 271 bus_space_handle_t ioh, memh; 272 int ioh_valid, memh_valid; 273 bus_addr_t addr; 274 bus_size_t size; 275 int flags; 276 int error; 277 278 aprint_naive(": Ethernet controller\n"); 279 280 /* 281 * Map control/status registers. 282 */ 283 ioh_valid = (pci_mapreg_map(pa, FXP_PCI_IOBA, 284 PCI_MAPREG_TYPE_IO, 0, 285 &iot, &ioh, NULL, NULL) == 0); 286 287 /* 288 * Version 2.1 of the PCI spec, page 196, "Address Maps": 289 * 290 * Prefetchable 291 * 292 * Set to one if there are no side effects on reads, the 293 * device returns all bytes regardless of the byte enables, 294 * and host bridges can merge processor writes into this 295 * range without causing errors. Bit must be set to zero 296 * otherwise. 297 * 298 * The 82557 incorrectly sets the "prefetchable" bit, resulting 299 * in errors on systems which will do merged reads and writes. 300 * These errors manifest themselves as all-bits-set when reading 301 * from the EEPROM or other < 4 byte registers. 302 * 303 * We must work around this problem by always forcing the mapping 304 * for memory space to be uncacheable. On systems which cannot 305 * create an uncacheable mapping (because the firmware mapped it 306 * into only cacheable/prefetchable space due to the "prefetchable" 307 * bit), we can fall back onto i/o mapped access. 308 */ 309 memh_valid = 0; 310 memt = pa->pa_memt; 311 if (((pa->pa_flags & PCI_FLAGS_MEM_ENABLED) != 0) && 312 pci_mapreg_info(pa->pa_pc, pa->pa_tag, FXP_PCI_MMBA, 313 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 314 &addr, &size, &flags) == 0) { 315 flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 316 if (bus_space_map(memt, addr, size, flags, &memh) == 0) 317 memh_valid = 1; 318 } 319 320 if (memh_valid) { 321 sc->sc_st = memt; 322 sc->sc_sh = memh; 323 } else if (ioh_valid) { 324 sc->sc_st = iot; 325 sc->sc_sh = ioh; 326 } else { 327 aprint_error(": unable to map device registers\n"); 328 return; 329 } 330 331 sc->sc_dmat = pa->pa_dmat; 332 333 fpp = fxp_pci_lookup(pa); 334 if (fpp == NULL) { 335 printf("\n"); 336 panic("fxp_pci_attach: impossible"); 337 } 338 339 sc->sc_rev = PCI_REVISION(pa->pa_class); 340 341 switch (fpp->fpp_prodid) { 342 case PCI_PRODUCT_INTEL_82557: 343 case PCI_PRODUCT_INTEL_82559ER: 344 case PCI_PRODUCT_INTEL_IN_BUSINESS: 345 { 346 const char *chipname = NULL; 347 348 if (sc->sc_rev >= FXP_REV_82558_A4) { 349 chipname = "i82558 Ethernet"; 350 /* 351 * Enable the MWI command for memory writes. 352 */ 353 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 354 sc->sc_flags |= FXPF_MWI; 355 } 356 if (sc->sc_rev >= FXP_REV_82559_A0) 357 chipname = "i82559 Ethernet"; 358 if (sc->sc_rev >= FXP_REV_82559S_A) 359 chipname = "i82559S Ethernet"; 360 if (sc->sc_rev >= FXP_REV_82550) 361 chipname = "i82550 Ethernet"; 362 363 /* 364 * Mark all i82559 and i82550 revisions as having 365 * the "resume bug". See i82557.c for details. 366 */ 367 if (sc->sc_rev >= FXP_REV_82559_A0) 368 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 369 370 aprint_normal(": %s, rev %d\n", chipname != NULL ? chipname : 371 fpp->fpp_name, sc->sc_rev); 372 break; 373 } 374 375 case PCI_PRODUCT_INTEL_82801BA_LAN: 376 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 377 378 /* 379 * The 82801BA Ethernet has a bug which requires us to send a 380 * NOP before a CU_RESUME if we're in 10baseT mode. 381 */ 382 if (fpp->fpp_prodid == PCI_PRODUCT_INTEL_82801BA_LAN) 383 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 384 break; 385 386 case PCI_PRODUCT_INTEL_PRO_100_VE_0: 387 case PCI_PRODUCT_INTEL_PRO_100_VE_1: 388 case PCI_PRODUCT_INTEL_PRO_100_VM_0: 389 case PCI_PRODUCT_INTEL_PRO_100_VM_1: 390 case PCI_PRODUCT_INTEL_82562EH_HPNA_0: 391 case PCI_PRODUCT_INTEL_82562EH_HPNA_1: 392 case PCI_PRODUCT_INTEL_82562EH_HPNA_2: 393 case PCI_PRODUCT_INTEL_PRO_100_VM_2: 394 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 395 396 /* 397 * ICH3 chips apparently have problems with the enhanced 398 * features, so just treat them as an i82557. It also 399 * has the resume bug that the ICH2 has. 400 */ 401 sc->sc_rev = 1; 402 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 403 break; 404 case PCI_PRODUCT_INTEL_82801E_LAN_1: 405 case PCI_PRODUCT_INTEL_82801E_LAN_2: 406 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 407 408 /* 409 * XXX We have to read the C-ICH's developer's manual 410 * in detail 411 */ 412 break; 413 case PCI_PRODUCT_INTEL_PRO_100_VE_2: 414 case PCI_PRODUCT_INTEL_PRO_100_VE_3: 415 case PCI_PRODUCT_INTEL_PRO_100_VE_4: 416 case PCI_PRODUCT_INTEL_PRO_100_VE_5: 417 case PCI_PRODUCT_INTEL_PRO_100_VM_3: 418 case PCI_PRODUCT_INTEL_PRO_100_VM_4: 419 case PCI_PRODUCT_INTEL_PRO_100_VM_5: 420 case PCI_PRODUCT_INTEL_PRO_100_VM_6: 421 case PCI_PRODUCT_INTEL_82801EB_LAN: 422 case PCI_PRODUCT_INTEL_82801FB_LAN: 423 case PCI_PRODUCT_INTEL_82801G_LAN: 424 default: 425 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 426 427 /* 428 * No particular quirks. 429 */ 430 break; 431 } 432 433 /* Make sure bus-mastering is enabled. */ 434 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 435 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 436 PCI_COMMAND_MASTER_ENABLE); 437 438 /* 439 * Under some circumstances (such as APM suspend/resume 440 * cycles, and across ACPI power state changes), the 441 * i82257-family can lose the contents of critical PCI 442 * configuration registers, causing the card to be 443 * non-responsive and useless. This occurs on the Sony VAIO 444 * Z505-series, among others. Preserve them here so they can 445 * be later restored (by fxp_pci_confreg_restore()). 446 */ 447 psc->psc_pc = pc; 448 psc->psc_tag = pa->pa_tag; 449 psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] = 450 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 451 psc->psc_regs[PCI_BHLC_REG>>2] = 452 pci_conf_read(pc, pa->pa_tag, PCI_BHLC_REG); 453 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2] = 454 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x0); 455 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2] = 456 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x4); 457 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2] = 458 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x8); 459 460 /* power up chip */ 461 switch ((error = pci_activate(pa->pa_pc, pa->pa_tag, sc, 462 pci_activate_null))) { 463 case EOPNOTSUPP: 464 break; 465 case 0: 466 sc->sc_enable = fxp_pci_enable; 467 sc->sc_disable = fxp_pci_disable; 468 break; 469 default: 470 aprint_error("%s: cannot activate %d\n", sc->sc_dev.dv_xname, 471 error); 472 return; 473 } 474 475 /* Restore PCI configuration registers. */ 476 fxp_pci_confreg_restore(psc); 477 478 sc->sc_enabled = 1; 479 480 /* 481 * Map and establish our interrupt. 482 */ 483 if (pci_intr_map(pa, &ih)) { 484 aprint_error("%s: couldn't map interrupt\n", 485 sc->sc_dev.dv_xname); 486 return; 487 } 488 intrstr = pci_intr_string(pc, ih); 489 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, fxp_intr, sc); 490 if (sc->sc_ih == NULL) { 491 aprint_error("%s: couldn't establish interrupt", 492 sc->sc_dev.dv_xname); 493 if (intrstr != NULL) 494 aprint_normal(" at %s", intrstr); 495 aprint_normal("\n"); 496 return; 497 } 498 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 499 500 /* Finish off the attach. */ 501 fxp_attach(sc); 502 if (sc->sc_disable != NULL) 503 fxp_disable(sc); 504 505 /* Add a suspend hook to restore PCI config state */ 506 psc->psc_powerhook = powerhook_establish(fxp_pci_powerhook, psc); 507 if (psc->psc_powerhook == NULL) 508 aprint_error( 509 "%s: WARNING: unable to establish pci power hook\n", 510 sc->sc_dev.dv_xname); 511 } 512 513 static int 514 fxp_pci_enable(struct fxp_softc *sc) 515 { 516 struct fxp_pci_softc *psc = (void *) sc; 517 518 #if 0 519 printf("%s: going to power state D0\n", sc->sc_dev.dv_xname); 520 #endif 521 522 /* Bring the device into D0 power state. */ 523 pci_conf_write(psc->psc_pc, psc->psc_tag, 524 psc->psc_pwrmgmt_csr_reg, psc->psc_pwrmgmt_csr); 525 526 /* Now restore the configuration registers. */ 527 fxp_pci_confreg_restore(psc); 528 529 return (0); 530 } 531 532 static void 533 fxp_pci_disable(struct fxp_softc *sc) 534 { 535 struct fxp_pci_softc *psc = (void *) sc; 536 537 /* 538 * for some 82558_A4 and 82558_B0, entering D3 state makes 539 * media detection disordered. 540 */ 541 if (sc->sc_rev <= FXP_REV_82558_B0) 542 return; 543 544 #if 0 545 printf("%s: going to power state D3\n", sc->sc_dev.dv_xname); 546 #endif 547 548 /* Put the device into D3 state. */ 549 pci_conf_write(psc->psc_pc, psc->psc_tag, 550 psc->psc_pwrmgmt_csr_reg, (psc->psc_pwrmgmt_csr & 551 ~PCI_PMCSR_STATE_MASK) | PCI_PMCSR_STATE_D3); 552 } 553
Indexes created Thu Oct 02 01:09:59 GMT 2025