if_fxp_pci.c revision 1.47
1 /* $NetBSD: if_fxp_pci.c,v 1.47 2006/07/30 21:09:00 oster Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * PCI bus front-end for the Intel i82557 fast Ethernet controller 42 * driver. Works with Intel Etherexpress Pro 10+, 100B, 100+ cards. 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: if_fxp_pci.c,v 1.47 2006/07/30 21:09:00 oster Exp $"); 47 48 #include "rnd.h" 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/mbuf.h> 53 #include <sys/malloc.h> 54 #include <sys/kernel.h> 55 #include <sys/socket.h> 56 #include <sys/ioctl.h> 57 #include <sys/errno.h> 58 #include <sys/device.h> 59 60 #if NRND > 0 61 #include <sys/rnd.h> 62 #endif 63 64 #include <machine/endian.h> 65 66 #include <net/if.h> 67 #include <net/if_dl.h> 68 #include <net/if_media.h> 69 #include <net/if_ether.h> 70 71 #include <machine/bus.h> 72 #include <machine/intr.h> 73 74 #include <dev/mii/miivar.h> 75 76 #include <dev/ic/i82557reg.h> 77 #include <dev/ic/i82557var.h> 78 79 #include <dev/pci/pcivar.h> 80 #include <dev/pci/pcireg.h> 81 #include <dev/pci/pcidevs.h> 82 83 struct fxp_pci_softc { 84 struct fxp_softc psc_fxp; 85 86 pci_chipset_tag_t psc_pc; /* pci chipset tag */ 87 pcireg_t psc_regs[0x20>>2]; /* saved PCI config regs (sparse) */ 88 pcitag_t psc_tag; /* pci register tag */ 89 void *psc_powerhook; /* power hook */ 90 91 int psc_pwrmgmt_csr_reg; /* ACPI power management register */ 92 pcireg_t psc_pwrmgmt_csr; /* ...and the contents at D0 */ 93 struct pci_conf_state psc_pciconf; /* standard PCI configuration regs */ 94 }; 95 96 static int fxp_pci_match(struct device *, struct cfdata *, void *); 97 static void fxp_pci_attach(struct device *, struct device *, void *); 98 99 static int fxp_pci_enable(struct fxp_softc *); 100 static void fxp_pci_disable(struct fxp_softc *); 101 102 static void fxp_pci_confreg_restore(struct fxp_pci_softc *psc); 103 static void fxp_pci_powerhook(int why, void *arg); 104 105 CFATTACH_DECL(fxp_pci, sizeof(struct fxp_pci_softc), 106 fxp_pci_match, fxp_pci_attach, NULL, NULL); 107 108 static const struct fxp_pci_product { 109 u_int32_t fpp_prodid; /* PCI product ID */ 110 const char *fpp_name; /* device name */ 111 } fxp_pci_products[] = { 112 { PCI_PRODUCT_INTEL_82557, 113 "Intel i82557 Ethernet" }, 114 { PCI_PRODUCT_INTEL_82559ER, 115 "Intel i82559ER Ethernet" }, 116 { PCI_PRODUCT_INTEL_IN_BUSINESS, 117 "Intel InBusiness Ethernet" }, 118 { PCI_PRODUCT_INTEL_82801BA_LAN, 119 "Intel i82562 Ethernet" }, 120 { PCI_PRODUCT_INTEL_82801E_LAN_1, 121 "Intel i82559 Ethernet" }, 122 { PCI_PRODUCT_INTEL_82801E_LAN_2, 123 "Intel i82559 Ethernet" }, 124 { PCI_PRODUCT_INTEL_PRO_100_VE_0, 125 "Intel PRO/100 VE Network Controller" }, 126 { PCI_PRODUCT_INTEL_PRO_100_VE_1, 127 "Intel PRO/100 VE Network Controller" }, 128 { PCI_PRODUCT_INTEL_PRO_100_VE_2, 129 "Intel PRO/100 VE Network Controller with 82562ET/EZ PHY" }, 130 { PCI_PRODUCT_INTEL_PRO_100_VE_3, 131 "Intel PRO/100 VE Network Controller with 82562ET/EZ (CNR) PHY" }, 132 { PCI_PRODUCT_INTEL_PRO_100_VE_4, 133 "Intel PRO/100 VE (MOB) Network Controller" }, 134 { PCI_PRODUCT_INTEL_PRO_100_VE_5, 135 "Intel PRO/100 VE (LOM) Network Controller" }, 136 { PCI_PRODUCT_INTEL_PRO_100_VE_6, 137 "Intel PRO/100 VE Network Controller" }, 138 { PCI_PRODUCT_INTEL_PRO_100_VM_0, 139 "Intel PRO/100 VM Network Controller" }, 140 { PCI_PRODUCT_INTEL_PRO_100_VM_1, 141 "Intel PRO/100 VM Network Controller" }, 142 { PCI_PRODUCT_INTEL_PRO_100_VM_2, 143 "Intel PRO/100 VM Network Controller" }, 144 { PCI_PRODUCT_INTEL_PRO_100_VM_3, 145 "Intel PRO/100 VM Network Controller with 82562EM/EX PHY" }, 146 { PCI_PRODUCT_INTEL_PRO_100_VM_4, 147 "Intel PRO/100 VM Network Controller with 82562EM/EX (CNR) PHY" }, 148 { PCI_PRODUCT_INTEL_PRO_100_VM_5, 149 "Intel PRO/100 VM (MOB) Network Controller" }, 150 { PCI_PRODUCT_INTEL_PRO_100_VM_6, 151 "Intel PRO/100 VM Network Controller with 82562ET/EZ PHY" }, 152 { PCI_PRODUCT_INTEL_PRO_100_M, 153 "Intel PRO/100 M Network Controller" }, 154 { PCI_PRODUCT_INTEL_82801EB_LAN, 155 "Intel 82801EB/ER (ICH5) Network Controller" }, 156 { PCI_PRODUCT_INTEL_82801FB_LAN, 157 "Intel 82562EZ (ICH6)" }, 158 { PCI_PRODUCT_INTEL_82801G_LAN, 159 "Intel 82801GB/GR (ICH7) Network Controller" }, 160 { 0, 161 NULL }, 162 }; 163 164 static const struct fxp_pci_product * 165 fxp_pci_lookup(const struct pci_attach_args *pa) 166 { 167 const struct fxp_pci_product *fpp; 168 169 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 170 return (NULL); 171 172 for (fpp = fxp_pci_products; fpp->fpp_name != NULL; fpp++) 173 if (PCI_PRODUCT(pa->pa_id) == fpp->fpp_prodid) 174 return (fpp); 175 176 return (NULL); 177 } 178 179 static int 180 fxp_pci_match(struct device *parent, struct cfdata *match, void *aux) 181 { 182 struct pci_attach_args *pa = aux; 183 184 if (fxp_pci_lookup(pa) != NULL) 185 return (1); 186 187 return (0); 188 } 189 190 /* 191 * Restore PCI configuration registers that may have been clobbered. 192 * This is necessary due to bugs on the Sony VAIO Z505-series on-board 193 * ethernet, after an APM suspend/resume, as well as after an ACPI 194 * D3->D0 transition. We call this function from a power hook after 195 * APM resume events, as well as after the ACPI D3->D0 transition. 196 */ 197 static void 198 fxp_pci_confreg_restore(struct fxp_pci_softc *psc) 199 { 200 pcireg_t reg; 201 202 #if 0 203 /* 204 * Check to see if the command register is blank -- if so, then 205 * we'll assume that all the clobberable-registers have been 206 * clobbered. 207 */ 208 209 /* 210 * In general, the above metric is accurate. Unfortunately, 211 * it is inaccurate across a hibernation. Ideally APM/ACPI 212 * code should take note of hibernation events and execute 213 * a hibernation wakeup hook, but at present a hibernation wake 214 * is indistinguishable from a suspend wake. 215 */ 216 217 if (((reg = pci_conf_read(psc->psc_pc, psc->psc_tag, 218 PCI_COMMAND_STATUS_REG)) & 0xffff) != 0) 219 return; 220 #else 221 reg = pci_conf_read(psc->psc_pc, psc->psc_tag, PCI_COMMAND_STATUS_REG); 222 #endif 223 224 pci_conf_write(psc->psc_pc, psc->psc_tag, 225 PCI_COMMAND_STATUS_REG, 226 (reg & 0xffff0000) | 227 (psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] & 0xffff)); 228 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_BHLC_REG, 229 psc->psc_regs[PCI_BHLC_REG>>2]); 230 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x0, 231 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2]); 232 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x4, 233 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2]); 234 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x8, 235 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2]); 236 } 237 238 239 /* 240 * Power handler routine. Called when the system is transitioning into/out 241 * of power save modes. We restore the (bashed) PCI configuration registers 242 * on a resume. 243 */ 244 static void 245 fxp_pci_powerhook(int why, void *arg) 246 { 247 struct fxp_pci_softc *psc = arg; 248 249 switch (why) { 250 case PWR_SUSPEND: 251 pci_conf_capture(psc->psc_pc, psc->psc_tag, &psc->psc_pciconf); 252 break; 253 case PWR_RESUME: 254 pci_conf_restore(psc->psc_pc, psc->psc_tag, &psc->psc_pciconf); 255 fxp_pci_confreg_restore(psc); 256 break; 257 } 258 259 return; 260 } 261 262 static void 263 fxp_pci_attach(struct device *parent, struct device *self, void *aux) 264 { 265 struct fxp_pci_softc *psc = (struct fxp_pci_softc *)self; 266 struct fxp_softc *sc = (struct fxp_softc *)self; 267 struct pci_attach_args *pa = aux; 268 pci_chipset_tag_t pc = pa->pa_pc; 269 pci_intr_handle_t ih; 270 const struct fxp_pci_product *fpp; 271 const char *intrstr = NULL; 272 bus_space_tag_t iot, memt; 273 bus_space_handle_t ioh, memh; 274 int ioh_valid, memh_valid; 275 bus_addr_t addr; 276 bus_size_t size; 277 int flags; 278 int error; 279 280 aprint_naive(": Ethernet controller\n"); 281 282 /* 283 * Map control/status registers. 284 */ 285 ioh_valid = (pci_mapreg_map(pa, FXP_PCI_IOBA, 286 PCI_MAPREG_TYPE_IO, 0, 287 &iot, &ioh, NULL, NULL) == 0); 288 289 /* 290 * Version 2.1 of the PCI spec, page 196, "Address Maps": 291 * 292 * Prefetchable 293 * 294 * Set to one if there are no side effects on reads, the 295 * device returns all bytes regardless of the byte enables, 296 * and host bridges can merge processor writes into this 297 * range without causing errors. Bit must be set to zero 298 * otherwise. 299 * 300 * The 82557 incorrectly sets the "prefetchable" bit, resulting 301 * in errors on systems which will do merged reads and writes. 302 * These errors manifest themselves as all-bits-set when reading 303 * from the EEPROM or other < 4 byte registers. 304 * 305 * We must work around this problem by always forcing the mapping 306 * for memory space to be uncacheable. On systems which cannot 307 * create an uncacheable mapping (because the firmware mapped it 308 * into only cacheable/prefetchable space due to the "prefetchable" 309 * bit), we can fall back onto i/o mapped access. 310 */ 311 memh_valid = 0; 312 memt = pa->pa_memt; 313 if (((pa->pa_flags & PCI_FLAGS_MEM_ENABLED) != 0) && 314 pci_mapreg_info(pa->pa_pc, pa->pa_tag, FXP_PCI_MMBA, 315 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 316 &addr, &size, &flags) == 0) { 317 flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 318 if (bus_space_map(memt, addr, size, flags, &memh) == 0) 319 memh_valid = 1; 320 } 321 322 if (memh_valid) { 323 sc->sc_st = memt; 324 sc->sc_sh = memh; 325 } else if (ioh_valid) { 326 sc->sc_st = iot; 327 sc->sc_sh = ioh; 328 } else { 329 aprint_error(": unable to map device registers\n"); 330 return; 331 } 332 333 sc->sc_dmat = pa->pa_dmat; 334 335 fpp = fxp_pci_lookup(pa); 336 if (fpp == NULL) { 337 printf("\n"); 338 panic("fxp_pci_attach: impossible"); 339 } 340 341 sc->sc_rev = PCI_REVISION(pa->pa_class); 342 343 switch (fpp->fpp_prodid) { 344 case PCI_PRODUCT_INTEL_82557: 345 case PCI_PRODUCT_INTEL_82559ER: 346 case PCI_PRODUCT_INTEL_IN_BUSINESS: 347 { 348 const char *chipname = NULL; 349 350 if (sc->sc_rev >= FXP_REV_82558_A4) { 351 chipname = "i82558 Ethernet"; 352 /* 353 * Enable the MWI command for memory writes. 354 */ 355 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 356 sc->sc_flags |= FXPF_MWI; 357 } 358 if (sc->sc_rev >= FXP_REV_82559_A0) 359 chipname = "i82559 Ethernet"; 360 if (sc->sc_rev >= FXP_REV_82559S_A) 361 chipname = "i82559S Ethernet"; 362 if (sc->sc_rev >= FXP_REV_82550) 363 chipname = "i82550 Ethernet"; 364 365 /* 366 * Mark all i82559 and i82550 revisions as having 367 * the "resume bug". See i82557.c for details. 368 */ 369 if (sc->sc_rev >= FXP_REV_82559_A0) 370 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 371 372 aprint_normal(": %s, rev %d\n", chipname != NULL ? chipname : 373 fpp->fpp_name, sc->sc_rev); 374 break; 375 } 376 377 case PCI_PRODUCT_INTEL_82801BA_LAN: 378 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 379 380 /* 381 * The 82801BA Ethernet has a bug which requires us to send a 382 * NOP before a CU_RESUME if we're in 10baseT mode. 383 */ 384 if (fpp->fpp_prodid == PCI_PRODUCT_INTEL_82801BA_LAN) 385 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 386 break; 387 388 case PCI_PRODUCT_INTEL_PRO_100_VE_0: 389 case PCI_PRODUCT_INTEL_PRO_100_VE_1: 390 case PCI_PRODUCT_INTEL_PRO_100_VM_0: 391 case PCI_PRODUCT_INTEL_PRO_100_VM_1: 392 case PCI_PRODUCT_INTEL_82562EH_HPNA_0: 393 case PCI_PRODUCT_INTEL_82562EH_HPNA_1: 394 case PCI_PRODUCT_INTEL_82562EH_HPNA_2: 395 case PCI_PRODUCT_INTEL_PRO_100_VM_2: 396 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 397 398 /* 399 * ICH3 chips apparently have problems with the enhanced 400 * features, so just treat them as an i82557. It also 401 * has the resume bug that the ICH2 has. 402 */ 403 sc->sc_rev = 1; 404 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 405 break; 406 case PCI_PRODUCT_INTEL_82801E_LAN_1: 407 case PCI_PRODUCT_INTEL_82801E_LAN_2: 408 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 409 410 /* 411 * XXX We have to read the C-ICH's developer's manual 412 * in detail 413 */ 414 break; 415 case PCI_PRODUCT_INTEL_PRO_100_VE_2: 416 case PCI_PRODUCT_INTEL_PRO_100_VE_3: 417 case PCI_PRODUCT_INTEL_PRO_100_VE_4: 418 case PCI_PRODUCT_INTEL_PRO_100_VE_5: 419 case PCI_PRODUCT_INTEL_PRO_100_VM_3: 420 case PCI_PRODUCT_INTEL_PRO_100_VM_4: 421 case PCI_PRODUCT_INTEL_PRO_100_VM_5: 422 case PCI_PRODUCT_INTEL_PRO_100_VM_6: 423 case PCI_PRODUCT_INTEL_82801EB_LAN: 424 case PCI_PRODUCT_INTEL_82801FB_LAN: 425 case PCI_PRODUCT_INTEL_82801G_LAN: 426 default: 427 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 428 429 /* 430 * No particular quirks. 431 */ 432 break; 433 } 434 435 /* Make sure bus-mastering is enabled. */ 436 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 437 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 438 PCI_COMMAND_MASTER_ENABLE); 439 440 /* 441 * Under some circumstances (such as APM suspend/resume 442 * cycles, and across ACPI power state changes), the 443 * i82257-family can lose the contents of critical PCI 444 * configuration registers, causing the card to be 445 * non-responsive and useless. This occurs on the Sony VAIO 446 * Z505-series, among others. Preserve them here so they can 447 * be later restored (by fxp_pci_confreg_restore()). 448 */ 449 psc->psc_pc = pc; 450 psc->psc_tag = pa->pa_tag; 451 psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] = 452 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 453 psc->psc_regs[PCI_BHLC_REG>>2] = 454 pci_conf_read(pc, pa->pa_tag, PCI_BHLC_REG); 455 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2] = 456 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x0); 457 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2] = 458 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x4); 459 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2] = 460 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x8); 461 462 /* power up chip */ 463 switch ((error = pci_activate(pa->pa_pc, pa->pa_tag, sc, 464 pci_activate_null))) { 465 case EOPNOTSUPP: 466 break; 467 case 0: 468 sc->sc_enable = fxp_pci_enable; 469 sc->sc_disable = fxp_pci_disable; 470 break; 471 default: 472 aprint_error("%s: cannot activate %d\n", sc->sc_dev.dv_xname, 473 error); 474 return; 475 } 476 477 /* Restore PCI configuration registers. */ 478 fxp_pci_confreg_restore(psc); 479 480 sc->sc_enabled = 1; 481 482 /* 483 * Map and establish our interrupt. 484 */ 485 if (pci_intr_map(pa, &ih)) { 486 aprint_error("%s: couldn't map interrupt\n", 487 sc->sc_dev.dv_xname); 488 return; 489 } 490 intrstr = pci_intr_string(pc, ih); 491 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, fxp_intr, sc); 492 if (sc->sc_ih == NULL) { 493 aprint_error("%s: couldn't establish interrupt", 494 sc->sc_dev.dv_xname); 495 if (intrstr != NULL) 496 aprint_normal(" at %s", intrstr); 497 aprint_normal("\n"); 498 return; 499 } 500 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 501 502 /* Finish off the attach. */ 503 fxp_attach(sc); 504 if (sc->sc_disable != NULL) 505 fxp_disable(sc); 506 507 /* Add a suspend hook to restore PCI config state */ 508 psc->psc_powerhook = powerhook_establish(fxp_pci_powerhook, psc); 509 if (psc->psc_powerhook == NULL) 510 aprint_error( 511 "%s: WARNING: unable to establish pci power hook\n", 512 sc->sc_dev.dv_xname); 513 } 514 515 static int 516 fxp_pci_enable(struct fxp_softc *sc) 517 { 518 struct fxp_pci_softc *psc = (void *) sc; 519 520 #if 0 521 printf("%s: going to power state D0\n", sc->sc_dev.dv_xname); 522 #endif 523 524 /* Bring the device into D0 power state. */ 525 pci_conf_write(psc->psc_pc, psc->psc_tag, 526 psc->psc_pwrmgmt_csr_reg, psc->psc_pwrmgmt_csr); 527 528 /* Now restore the configuration registers. */ 529 fxp_pci_confreg_restore(psc); 530 531 return (0); 532 } 533 534 static void 535 fxp_pci_disable(struct fxp_softc *sc) 536 { 537 struct fxp_pci_softc *psc = (void *) sc; 538 539 /* 540 * for some 82558_A4 and 82558_B0, entering D3 state makes 541 * media detection disordered. 542 */ 543 if (sc->sc_rev <= FXP_REV_82558_B0) 544 return; 545 546 #if 0 547 printf("%s: going to power state D3\n", sc->sc_dev.dv_xname); 548 #endif 549 550 /* Put the device into D3 state. */ 551 pci_conf_write(psc->psc_pc, psc->psc_tag, 552 psc->psc_pwrmgmt_csr_reg, (psc->psc_pwrmgmt_csr & 553 ~PCI_PMCSR_STATE_MASK) | PCI_PMCSR_STATE_D3); 554 } 555
Indexes created Thu Sep 25 16:09:42 GMT 2025