if_fxp_pci.c revision 1.47.6.2
1 /* $NetBSD: if_fxp_pci.c,v 1.47.6.2 2006/12/10 07:17:43 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * PCI bus front-end for the Intel i82557 fast Ethernet controller 42 * driver. Works with Intel Etherexpress Pro 10+, 100B, 100+ cards. 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: if_fxp_pci.c,v 1.47.6.2 2006/12/10 07:17:43 yamt Exp $"); 47 48 #include "rnd.h" 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/mbuf.h> 53 #include <sys/malloc.h> 54 #include <sys/kernel.h> 55 #include <sys/socket.h> 56 #include <sys/ioctl.h> 57 #include <sys/errno.h> 58 #include <sys/device.h> 59 60 #if NRND > 0 61 #include <sys/rnd.h> 62 #endif 63 64 #include <machine/endian.h> 65 66 #include <net/if.h> 67 #include <net/if_dl.h> 68 #include <net/if_media.h> 69 #include <net/if_ether.h> 70 71 #include <machine/bus.h> 72 #include <machine/intr.h> 73 74 #include <dev/mii/miivar.h> 75 76 #include <dev/ic/i82557reg.h> 77 #include <dev/ic/i82557var.h> 78 79 #include <dev/pci/pcivar.h> 80 #include <dev/pci/pcireg.h> 81 #include <dev/pci/pcidevs.h> 82 83 struct fxp_pci_softc { 84 struct fxp_softc psc_fxp; 85 86 pci_chipset_tag_t psc_pc; /* pci chipset tag */ 87 pcireg_t psc_regs[0x20>>2]; /* saved PCI config regs (sparse) */ 88 pcitag_t psc_tag; /* pci register tag */ 89 void *psc_powerhook; /* power hook */ 90 91 int psc_pwrmgmt_csr_reg; /* ACPI power management register */ 92 pcireg_t psc_pwrmgmt_csr; /* ...and the contents at D0 */ 93 struct pci_conf_state psc_pciconf; /* standard PCI configuration regs */ 94 }; 95 96 static int fxp_pci_match(struct device *, struct cfdata *, void *); 97 static void fxp_pci_attach(struct device *, struct device *, void *); 98 99 static int fxp_pci_enable(struct fxp_softc *); 100 static void fxp_pci_disable(struct fxp_softc *); 101 102 static void fxp_pci_confreg_restore(struct fxp_pci_softc *psc); 103 static void fxp_pci_powerhook(int why, void *arg); 104 105 CFATTACH_DECL(fxp_pci, sizeof(struct fxp_pci_softc), 106 fxp_pci_match, fxp_pci_attach, NULL, NULL); 107 108 static const struct fxp_pci_product { 109 u_int32_t fpp_prodid; /* PCI product ID */ 110 const char *fpp_name; /* device name */ 111 } fxp_pci_products[] = { 112 { PCI_PRODUCT_INTEL_82557, 113 "Intel i82557 Ethernet" }, 114 { PCI_PRODUCT_INTEL_82559ER, 115 "Intel i82559ER Ethernet" }, 116 { PCI_PRODUCT_INTEL_IN_BUSINESS, 117 "Intel InBusiness Ethernet" }, 118 { PCI_PRODUCT_INTEL_82801BA_LAN, 119 "Intel i82562 Ethernet" }, 120 { PCI_PRODUCT_INTEL_82801E_LAN_1, 121 "Intel i82559 Ethernet" }, 122 { PCI_PRODUCT_INTEL_82801E_LAN_2, 123 "Intel i82559 Ethernet" }, 124 { PCI_PRODUCT_INTEL_PRO_100_VE_0, 125 "Intel PRO/100 VE Network Controller" }, 126 { PCI_PRODUCT_INTEL_PRO_100_VE_1, 127 "Intel PRO/100 VE Network Controller" }, 128 { PCI_PRODUCT_INTEL_PRO_100_VE_2, 129 "Intel PRO/100 VE Network Controller with 82562ET/EZ PHY" }, 130 { PCI_PRODUCT_INTEL_PRO_100_VE_3, 131 "Intel PRO/100 VE Network Controller with 82562ET/EZ (CNR) PHY" }, 132 { PCI_PRODUCT_INTEL_PRO_100_VE_4, 133 "Intel PRO/100 VE (MOB) Network Controller" }, 134 { PCI_PRODUCT_INTEL_PRO_100_VE_5, 135 "Intel PRO/100 VE (LOM) Network Controller" }, 136 { PCI_PRODUCT_INTEL_PRO_100_VE_6, 137 "Intel PRO/100 VE Network Controller" }, 138 { PCI_PRODUCT_INTEL_PRO_100_VE_7, 139 "Intel PRO/100 VE Network Controller" }, 140 { PCI_PRODUCT_INTEL_PRO_100_VE_8, 141 "Intel PRO/100 VE Network Controller" }, 142 { PCI_PRODUCT_INTEL_PRO_100_VM_0, 143 "Intel PRO/100 VM Network Controller" }, 144 { PCI_PRODUCT_INTEL_PRO_100_VM_1, 145 "Intel PRO/100 VM Network Controller" }, 146 { PCI_PRODUCT_INTEL_PRO_100_VM_2, 147 "Intel PRO/100 VM Network Controller" }, 148 { PCI_PRODUCT_INTEL_PRO_100_VM_3, 149 "Intel PRO/100 VM Network Controller with 82562EM/EX PHY" }, 150 { PCI_PRODUCT_INTEL_PRO_100_VM_4, 151 "Intel PRO/100 VM Network Controller with 82562EM/EX (CNR) PHY" }, 152 { PCI_PRODUCT_INTEL_PRO_100_VM_5, 153 "Intel PRO/100 VM (MOB) Network Controller" }, 154 { PCI_PRODUCT_INTEL_PRO_100_VM_6, 155 "Intel PRO/100 VM Network Controller with 82562ET/EZ PHY" }, 156 { PCI_PRODUCT_INTEL_PRO_100_M, 157 "Intel PRO/100 M Network Controller" }, 158 { PCI_PRODUCT_INTEL_82801EB_LAN, 159 "Intel 82801EB/ER (ICH5) Network Controller" }, 160 { PCI_PRODUCT_INTEL_82801FB_LAN, 161 "Intel 82562EZ (ICH6)" }, 162 { PCI_PRODUCT_INTEL_82801G_LAN, 163 "Intel 82801GB/GR (ICH7) Network Controller" }, 164 { 0, 165 NULL }, 166 }; 167 168 static const struct fxp_pci_product * 169 fxp_pci_lookup(const struct pci_attach_args *pa) 170 { 171 const struct fxp_pci_product *fpp; 172 173 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 174 return (NULL); 175 176 for (fpp = fxp_pci_products; fpp->fpp_name != NULL; fpp++) 177 if (PCI_PRODUCT(pa->pa_id) == fpp->fpp_prodid) 178 return (fpp); 179 180 return (NULL); 181 } 182 183 static int 184 fxp_pci_match(struct device *parent, struct cfdata *match, 185 void *aux) 186 { 187 struct pci_attach_args *pa = aux; 188 189 if (fxp_pci_lookup(pa) != NULL) 190 return (1); 191 192 return (0); 193 } 194 195 /* 196 * Restore PCI configuration registers that may have been clobbered. 197 * This is necessary due to bugs on the Sony VAIO Z505-series on-board 198 * ethernet, after an APM suspend/resume, as well as after an ACPI 199 * D3->D0 transition. We call this function from a power hook after 200 * APM resume events, as well as after the ACPI D3->D0 transition. 201 */ 202 static void 203 fxp_pci_confreg_restore(struct fxp_pci_softc *psc) 204 { 205 pcireg_t reg; 206 207 #if 0 208 /* 209 * Check to see if the command register is blank -- if so, then 210 * we'll assume that all the clobberable-registers have been 211 * clobbered. 212 */ 213 214 /* 215 * In general, the above metric is accurate. Unfortunately, 216 * it is inaccurate across a hibernation. Ideally APM/ACPI 217 * code should take note of hibernation events and execute 218 * a hibernation wakeup hook, but at present a hibernation wake 219 * is indistinguishable from a suspend wake. 220 */ 221 222 if (((reg = pci_conf_read(psc->psc_pc, psc->psc_tag, 223 PCI_COMMAND_STATUS_REG)) & 0xffff) != 0) 224 return; 225 #else 226 reg = pci_conf_read(psc->psc_pc, psc->psc_tag, PCI_COMMAND_STATUS_REG); 227 #endif 228 229 pci_conf_write(psc->psc_pc, psc->psc_tag, 230 PCI_COMMAND_STATUS_REG, 231 (reg & 0xffff0000) | 232 (psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] & 0xffff)); 233 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_BHLC_REG, 234 psc->psc_regs[PCI_BHLC_REG>>2]); 235 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x0, 236 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2]); 237 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x4, 238 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2]); 239 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x8, 240 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2]); 241 } 242 243 244 /* 245 * Power handler routine. Called when the system is transitioning into/out 246 * of power save modes. We restore the (bashed) PCI configuration registers 247 * on a resume. 248 */ 249 static void 250 fxp_pci_powerhook(int why, void *arg) 251 { 252 struct fxp_pci_softc *psc = arg; 253 254 switch (why) { 255 case PWR_SUSPEND: 256 pci_conf_capture(psc->psc_pc, psc->psc_tag, &psc->psc_pciconf); 257 break; 258 case PWR_RESUME: 259 pci_conf_restore(psc->psc_pc, psc->psc_tag, &psc->psc_pciconf); 260 fxp_pci_confreg_restore(psc); 261 break; 262 } 263 264 return; 265 } 266 267 static void 268 fxp_pci_attach(struct device *parent, struct device *self, void *aux) 269 { 270 struct fxp_pci_softc *psc = (struct fxp_pci_softc *)self; 271 struct fxp_softc *sc = (struct fxp_softc *)self; 272 struct pci_attach_args *pa = aux; 273 pci_chipset_tag_t pc = pa->pa_pc; 274 pci_intr_handle_t ih; 275 const struct fxp_pci_product *fpp; 276 const char *intrstr = NULL; 277 bus_space_tag_t iot, memt; 278 bus_space_handle_t ioh, memh; 279 int ioh_valid, memh_valid; 280 bus_addr_t addr; 281 bus_size_t size; 282 int flags; 283 int error; 284 285 aprint_naive(": Ethernet controller\n"); 286 287 /* 288 * Map control/status registers. 289 */ 290 ioh_valid = (pci_mapreg_map(pa, FXP_PCI_IOBA, 291 PCI_MAPREG_TYPE_IO, 0, 292 &iot, &ioh, NULL, NULL) == 0); 293 294 /* 295 * Version 2.1 of the PCI spec, page 196, "Address Maps": 296 * 297 * Prefetchable 298 * 299 * Set to one if there are no side effects on reads, the 300 * device returns all bytes regardless of the byte enables, 301 * and host bridges can merge processor writes into this 302 * range without causing errors. Bit must be set to zero 303 * otherwise. 304 * 305 * The 82557 incorrectly sets the "prefetchable" bit, resulting 306 * in errors on systems which will do merged reads and writes. 307 * These errors manifest themselves as all-bits-set when reading 308 * from the EEPROM or other < 4 byte registers. 309 * 310 * We must work around this problem by always forcing the mapping 311 * for memory space to be uncacheable. On systems which cannot 312 * create an uncacheable mapping (because the firmware mapped it 313 * into only cacheable/prefetchable space due to the "prefetchable" 314 * bit), we can fall back onto i/o mapped access. 315 */ 316 memh_valid = 0; 317 memt = pa->pa_memt; 318 if (((pa->pa_flags & PCI_FLAGS_MEM_ENABLED) != 0) && 319 pci_mapreg_info(pa->pa_pc, pa->pa_tag, FXP_PCI_MMBA, 320 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 321 &addr, &size, &flags) == 0) { 322 flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 323 if (bus_space_map(memt, addr, size, flags, &memh) == 0) 324 memh_valid = 1; 325 } 326 327 if (memh_valid) { 328 sc->sc_st = memt; 329 sc->sc_sh = memh; 330 } else if (ioh_valid) { 331 sc->sc_st = iot; 332 sc->sc_sh = ioh; 333 } else { 334 aprint_error(": unable to map device registers\n"); 335 return; 336 } 337 338 sc->sc_dmat = pa->pa_dmat; 339 340 fpp = fxp_pci_lookup(pa); 341 if (fpp == NULL) { 342 printf("\n"); 343 panic("fxp_pci_attach: impossible"); 344 } 345 346 sc->sc_rev = PCI_REVISION(pa->pa_class); 347 348 switch (fpp->fpp_prodid) { 349 case PCI_PRODUCT_INTEL_82557: 350 case PCI_PRODUCT_INTEL_82559ER: 351 case PCI_PRODUCT_INTEL_IN_BUSINESS: 352 { 353 const char *chipname = NULL; 354 355 if (sc->sc_rev >= FXP_REV_82558_A4) { 356 chipname = "i82558 Ethernet"; 357 /* 358 * Enable the MWI command for memory writes. 359 */ 360 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 361 sc->sc_flags |= FXPF_MWI; 362 } 363 if (sc->sc_rev >= FXP_REV_82559_A0) 364 chipname = "i82559 Ethernet"; 365 if (sc->sc_rev >= FXP_REV_82559S_A) 366 chipname = "i82559S Ethernet"; 367 if (sc->sc_rev >= FXP_REV_82550) 368 chipname = "i82550 Ethernet"; 369 370 /* 371 * Mark all i82559 and i82550 revisions as having 372 * the "resume bug". See i82557.c for details. 373 */ 374 if (sc->sc_rev >= FXP_REV_82559_A0) 375 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 376 377 aprint_normal(": %s, rev %d\n", chipname != NULL ? chipname : 378 fpp->fpp_name, sc->sc_rev); 379 break; 380 } 381 382 case PCI_PRODUCT_INTEL_82801BA_LAN: 383 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 384 385 /* 386 * The 82801BA Ethernet has a bug which requires us to send a 387 * NOP before a CU_RESUME if we're in 10baseT mode. 388 */ 389 if (fpp->fpp_prodid == PCI_PRODUCT_INTEL_82801BA_LAN) 390 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 391 break; 392 393 case PCI_PRODUCT_INTEL_PRO_100_VE_0: 394 case PCI_PRODUCT_INTEL_PRO_100_VE_1: 395 case PCI_PRODUCT_INTEL_PRO_100_VM_0: 396 case PCI_PRODUCT_INTEL_PRO_100_VM_1: 397 case PCI_PRODUCT_INTEL_82562EH_HPNA_0: 398 case PCI_PRODUCT_INTEL_82562EH_HPNA_1: 399 case PCI_PRODUCT_INTEL_82562EH_HPNA_2: 400 case PCI_PRODUCT_INTEL_PRO_100_VM_2: 401 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 402 403 /* 404 * ICH3 chips apparently have problems with the enhanced 405 * features, so just treat them as an i82557. It also 406 * has the resume bug that the ICH2 has. 407 */ 408 sc->sc_rev = 1; 409 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 410 break; 411 case PCI_PRODUCT_INTEL_82801E_LAN_1: 412 case PCI_PRODUCT_INTEL_82801E_LAN_2: 413 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 414 415 /* 416 * XXX We have to read the C-ICH's developer's manual 417 * in detail 418 */ 419 break; 420 case PCI_PRODUCT_INTEL_PRO_100_VE_2: 421 case PCI_PRODUCT_INTEL_PRO_100_VE_3: 422 case PCI_PRODUCT_INTEL_PRO_100_VE_4: 423 case PCI_PRODUCT_INTEL_PRO_100_VE_5: 424 case PCI_PRODUCT_INTEL_PRO_100_VM_3: 425 case PCI_PRODUCT_INTEL_PRO_100_VM_4: 426 case PCI_PRODUCT_INTEL_PRO_100_VM_5: 427 case PCI_PRODUCT_INTEL_PRO_100_VM_6: 428 case PCI_PRODUCT_INTEL_82801EB_LAN: 429 case PCI_PRODUCT_INTEL_82801FB_LAN: 430 case PCI_PRODUCT_INTEL_82801G_LAN: 431 default: 432 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 433 434 /* 435 * No particular quirks. 436 */ 437 break; 438 } 439 440 /* Make sure bus-mastering is enabled. */ 441 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 442 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 443 PCI_COMMAND_MASTER_ENABLE); 444 445 /* 446 * Under some circumstances (such as APM suspend/resume 447 * cycles, and across ACPI power state changes), the 448 * i82257-family can lose the contents of critical PCI 449 * configuration registers, causing the card to be 450 * non-responsive and useless. This occurs on the Sony VAIO 451 * Z505-series, among others. Preserve them here so they can 452 * be later restored (by fxp_pci_confreg_restore()). 453 */ 454 psc->psc_pc = pc; 455 psc->psc_tag = pa->pa_tag; 456 psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] = 457 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 458 psc->psc_regs[PCI_BHLC_REG>>2] = 459 pci_conf_read(pc, pa->pa_tag, PCI_BHLC_REG); 460 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2] = 461 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x0); 462 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2] = 463 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x4); 464 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2] = 465 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x8); 466 467 /* power up chip */ 468 switch ((error = pci_activate(pa->pa_pc, pa->pa_tag, sc, 469 pci_activate_null))) { 470 case EOPNOTSUPP: 471 break; 472 case 0: 473 sc->sc_enable = fxp_pci_enable; 474 sc->sc_disable = fxp_pci_disable; 475 break; 476 default: 477 aprint_error("%s: cannot activate %d\n", sc->sc_dev.dv_xname, 478 error); 479 return; 480 } 481 482 /* Restore PCI configuration registers. */ 483 fxp_pci_confreg_restore(psc); 484 485 sc->sc_enabled = 1; 486 487 /* 488 * Map and establish our interrupt. 489 */ 490 if (pci_intr_map(pa, &ih)) { 491 aprint_error("%s: couldn't map interrupt\n", 492 sc->sc_dev.dv_xname); 493 return; 494 } 495 intrstr = pci_intr_string(pc, ih); 496 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, fxp_intr, sc); 497 if (sc->sc_ih == NULL) { 498 aprint_error("%s: couldn't establish interrupt", 499 sc->sc_dev.dv_xname); 500 if (intrstr != NULL) 501 aprint_normal(" at %s", intrstr); 502 aprint_normal("\n"); 503 return; 504 } 505 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 506 507 /* Finish off the attach. */ 508 fxp_attach(sc); 509 if (sc->sc_disable != NULL) 510 fxp_disable(sc); 511 512 /* Add a suspend hook to restore PCI config state */ 513 psc->psc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 514 fxp_pci_powerhook, psc); 515 if (psc->psc_powerhook == NULL) 516 aprint_error( 517 "%s: WARNING: unable to establish pci power hook\n", 518 sc->sc_dev.dv_xname); 519 } 520 521 static int 522 fxp_pci_enable(struct fxp_softc *sc) 523 { 524 struct fxp_pci_softc *psc = (void *) sc; 525 526 #if 0 527 printf("%s: going to power state D0\n", sc->sc_dev.dv_xname); 528 #endif 529 530 /* Bring the device into D0 power state. */ 531 pci_conf_write(psc->psc_pc, psc->psc_tag, 532 psc->psc_pwrmgmt_csr_reg, psc->psc_pwrmgmt_csr); 533 534 /* Now restore the configuration registers. */ 535 fxp_pci_confreg_restore(psc); 536 537 return (0); 538 } 539 540 static void 541 fxp_pci_disable(struct fxp_softc *sc) 542 { 543 struct fxp_pci_softc *psc = (void *) sc; 544 545 /* 546 * for some 82558_A4 and 82558_B0, entering D3 state makes 547 * media detection disordered. 548 */ 549 if (sc->sc_rev <= FXP_REV_82558_B0) 550 return; 551 552 #if 0 553 printf("%s: going to power state D3\n", sc->sc_dev.dv_xname); 554 #endif 555 556 /* Put the device into D3 state. */ 557 pci_conf_write(psc->psc_pc, psc->psc_tag, 558 psc->psc_pwrmgmt_csr_reg, (psc->psc_pwrmgmt_csr & 559 ~PCI_PMCSR_STATE_MASK) | PCI_PMCSR_STATE_D3); 560 } 561
Indexes created Thu Oct 02 01:09:59 GMT 2025