if_fxp_pci.c revision 1.54
1 /* $NetBSD: if_fxp_pci.c,v 1.54 2007/12/10 16:15:02 degroote Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * PCI bus front-end for the Intel i82557 fast Ethernet controller 42 * driver. Works with Intel Etherexpress Pro 10+, 100B, 100+ cards. 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: if_fxp_pci.c,v 1.54 2007/12/10 16:15:02 degroote Exp $"); 47 48 #include "rnd.h" 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/mbuf.h> 53 #include <sys/malloc.h> 54 #include <sys/kernel.h> 55 #include <sys/socket.h> 56 #include <sys/ioctl.h> 57 #include <sys/errno.h> 58 #include <sys/device.h> 59 60 #if NRND > 0 61 #include <sys/rnd.h> 62 #endif 63 64 #include <machine/endian.h> 65 66 #include <net/if.h> 67 #include <net/if_dl.h> 68 #include <net/if_media.h> 69 #include <net/if_ether.h> 70 71 #include <sys/bus.h> 72 #include <sys/intr.h> 73 74 #include <dev/mii/miivar.h> 75 76 #include <dev/ic/i82557reg.h> 77 #include <dev/ic/i82557var.h> 78 79 #include <dev/pci/pcivar.h> 80 #include <dev/pci/pcireg.h> 81 #include <dev/pci/pcidevs.h> 82 83 struct fxp_pci_softc { 84 struct fxp_softc psc_fxp; 85 86 pci_chipset_tag_t psc_pc; /* pci chipset tag */ 87 pcireg_t psc_regs[0x20>>2]; /* saved PCI config regs (sparse) */ 88 pcitag_t psc_tag; /* pci register tag */ 89 90 int psc_pwrmgmt_csr_reg; /* ACPI power management register */ 91 pcireg_t psc_pwrmgmt_csr; /* ...and the contents at D0 */ 92 struct pci_conf_state psc_pciconf; /* standard PCI configuration regs */ 93 }; 94 95 static int fxp_pci_match(struct device *, struct cfdata *, void *); 96 static void fxp_pci_attach(struct device *, struct device *, void *); 97 98 static int fxp_pci_enable(struct fxp_softc *); 99 static void fxp_pci_disable(struct fxp_softc *); 100 101 static void fxp_pci_confreg_restore(struct fxp_pci_softc *psc); 102 static bool fxp_pci_resume(device_t dv); 103 104 CFATTACH_DECL(fxp_pci, sizeof(struct fxp_pci_softc), 105 fxp_pci_match, fxp_pci_attach, NULL, NULL); 106 107 static const struct fxp_pci_product { 108 u_int32_t fpp_prodid; /* PCI product ID */ 109 const char *fpp_name; /* device name */ 110 } fxp_pci_products[] = { 111 { PCI_PRODUCT_INTEL_82557, 112 "Intel i82557 Ethernet" }, 113 { PCI_PRODUCT_INTEL_82559ER, 114 "Intel i82559ER Ethernet" }, 115 { PCI_PRODUCT_INTEL_IN_BUSINESS, 116 "Intel InBusiness Ethernet" }, 117 { PCI_PRODUCT_INTEL_82801BA_LAN, 118 "Intel i82562 Ethernet" }, 119 { PCI_PRODUCT_INTEL_82801E_LAN_1, 120 "Intel i82559 Ethernet" }, 121 { PCI_PRODUCT_INTEL_82801E_LAN_2, 122 "Intel i82559 Ethernet" }, 123 { PCI_PRODUCT_INTEL_PRO_100_VE_0, 124 "Intel PRO/100 VE Network Controller" }, 125 { PCI_PRODUCT_INTEL_PRO_100_VE_1, 126 "Intel PRO/100 VE Network Controller" }, 127 { PCI_PRODUCT_INTEL_PRO_100_VE_2, 128 "Intel PRO/100 VE Network Controller with 82562ET/EZ PHY" }, 129 { PCI_PRODUCT_INTEL_PRO_100_VE_3, 130 "Intel PRO/100 VE Network Controller with 82562ET/EZ (CNR) PHY" }, 131 { PCI_PRODUCT_INTEL_PRO_100_VE_4, 132 "Intel PRO/100 VE (MOB) Network Controller" }, 133 { PCI_PRODUCT_INTEL_PRO_100_VE_5, 134 "Intel PRO/100 VE (LOM) Network Controller" }, 135 { PCI_PRODUCT_INTEL_PRO_100_VE_6, 136 "Intel PRO/100 VE Network Controller" }, 137 { PCI_PRODUCT_INTEL_PRO_100_VE_7, 138 "Intel PRO/100 VE Network Controller" }, 139 { PCI_PRODUCT_INTEL_PRO_100_VE_8, 140 "Intel PRO/100 VE Network Controller" }, 141 { PCI_PRODUCT_INTEL_PRO_100_VM_0, 142 "Intel PRO/100 VM Network Controller" }, 143 { PCI_PRODUCT_INTEL_PRO_100_VM_1, 144 "Intel PRO/100 VM Network Controller" }, 145 { PCI_PRODUCT_INTEL_PRO_100_VM_2, 146 "Intel PRO/100 VM Network Controller" }, 147 { PCI_PRODUCT_INTEL_PRO_100_VM_3, 148 "Intel PRO/100 VM Network Controller with 82562EM/EX PHY" }, 149 { PCI_PRODUCT_INTEL_PRO_100_VM_4, 150 "Intel PRO/100 VM Network Controller with 82562EM/EX (CNR) PHY" }, 151 { PCI_PRODUCT_INTEL_PRO_100_VM_5, 152 "Intel PRO/100 VM (MOB) Network Controller" }, 153 { PCI_PRODUCT_INTEL_PRO_100_VM_6, 154 "Intel PRO/100 VM Network Controller with 82562ET/EZ PHY" }, 155 { PCI_PRODUCT_INTEL_PRO_100_M, 156 "Intel PRO/100 M Network Controller" }, 157 { PCI_PRODUCT_INTEL_82801EB_LAN, 158 "Intel 82801EB/ER (ICH5) Network Controller" }, 159 { PCI_PRODUCT_INTEL_82801FB_LAN, 160 "Intel 82562EZ (ICH6)" }, 161 { PCI_PRODUCT_INTEL_82801G_LAN, 162 "Intel 82801GB/GR (ICH7) Network Controller" }, 163 { 0, 164 NULL }, 165 }; 166 167 static const struct fxp_pci_product * 168 fxp_pci_lookup(const struct pci_attach_args *pa) 169 { 170 const struct fxp_pci_product *fpp; 171 172 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 173 return (NULL); 174 175 for (fpp = fxp_pci_products; fpp->fpp_name != NULL; fpp++) 176 if (PCI_PRODUCT(pa->pa_id) == fpp->fpp_prodid) 177 return (fpp); 178 179 return (NULL); 180 } 181 182 static int 183 fxp_pci_match(struct device *parent, struct cfdata *match, 184 void *aux) 185 { 186 struct pci_attach_args *pa = aux; 187 188 if (fxp_pci_lookup(pa) != NULL) 189 return (1); 190 191 return (0); 192 } 193 194 /* 195 * On resume : (XXX it is necessary with new pmf framework ?) 196 * Restore PCI configuration registers that may have been clobbered. 197 * This is necessary due to bugs on the Sony VAIO Z505-series on-board 198 * ethernet, after an APM suspend/resume, as well as after an ACPI 199 * D3->D0 transition. We call this function from a power hook after 200 * APM resume events, as well as after the ACPI D3->D0 transition. 201 */ 202 static void 203 fxp_pci_confreg_restore(struct fxp_pci_softc *psc) 204 { 205 pcireg_t reg; 206 207 #if 0 208 /* 209 * Check to see if the command register is blank -- if so, then 210 * we'll assume that all the clobberable-registers have been 211 * clobbered. 212 */ 213 214 /* 215 * In general, the above metric is accurate. Unfortunately, 216 * it is inaccurate across a hibernation. Ideally APM/ACPI 217 * code should take note of hibernation events and execute 218 * a hibernation wakeup hook, but at present a hibernation wake 219 * is indistinguishable from a suspend wake. 220 */ 221 222 if (((reg = pci_conf_read(psc->psc_pc, psc->psc_tag, 223 PCI_COMMAND_STATUS_REG)) & 0xffff) != 0) 224 return; 225 #else 226 reg = pci_conf_read(psc->psc_pc, psc->psc_tag, PCI_COMMAND_STATUS_REG); 227 #endif 228 229 pci_conf_write(psc->psc_pc, psc->psc_tag, 230 PCI_COMMAND_STATUS_REG, 231 (reg & 0xffff0000) | 232 (psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] & 0xffff)); 233 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_BHLC_REG, 234 psc->psc_regs[PCI_BHLC_REG>>2]); 235 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x0, 236 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2]); 237 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x4, 238 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2]); 239 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x8, 240 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2]); 241 } 242 243 static bool 244 fxp_pci_resume(device_t dv) 245 { 246 struct fxp_pci_softc *psc = device_private(dv); 247 fxp_pci_confreg_restore(psc); 248 249 return true; 250 } 251 252 static void 253 fxp_pci_attach(struct device *parent, struct device *self, void *aux) 254 { 255 struct fxp_pci_softc *psc = (struct fxp_pci_softc *)self; 256 struct fxp_softc *sc = (struct fxp_softc *)self; 257 struct pci_attach_args *pa = aux; 258 pci_chipset_tag_t pc = pa->pa_pc; 259 pci_intr_handle_t ih; 260 const struct fxp_pci_product *fpp; 261 const char *intrstr = NULL; 262 bus_space_tag_t iot, memt; 263 bus_space_handle_t ioh, memh; 264 int ioh_valid, memh_valid; 265 bus_addr_t addr; 266 bus_size_t size; 267 int flags; 268 int error; 269 270 aprint_naive(": Ethernet controller\n"); 271 272 /* 273 * Map control/status registers. 274 */ 275 ioh_valid = (pci_mapreg_map(pa, FXP_PCI_IOBA, 276 PCI_MAPREG_TYPE_IO, 0, 277 &iot, &ioh, NULL, NULL) == 0); 278 279 /* 280 * Version 2.1 of the PCI spec, page 196, "Address Maps": 281 * 282 * Prefetchable 283 * 284 * Set to one if there are no side effects on reads, the 285 * device returns all bytes regardless of the byte enables, 286 * and host bridges can merge processor writes into this 287 * range without causing errors. Bit must be set to zero 288 * otherwise. 289 * 290 * The 82557 incorrectly sets the "prefetchable" bit, resulting 291 * in errors on systems which will do merged reads and writes. 292 * These errors manifest themselves as all-bits-set when reading 293 * from the EEPROM or other < 4 byte registers. 294 * 295 * We must work around this problem by always forcing the mapping 296 * for memory space to be uncacheable. On systems which cannot 297 * create an uncacheable mapping (because the firmware mapped it 298 * into only cacheable/prefetchable space due to the "prefetchable" 299 * bit), we can fall back onto i/o mapped access. 300 */ 301 memh_valid = 0; 302 memt = pa->pa_memt; 303 if (((pa->pa_flags & PCI_FLAGS_MEM_ENABLED) != 0) && 304 pci_mapreg_info(pa->pa_pc, pa->pa_tag, FXP_PCI_MMBA, 305 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 306 &addr, &size, &flags) == 0) { 307 flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 308 if (bus_space_map(memt, addr, size, flags, &memh) == 0) 309 memh_valid = 1; 310 } 311 312 if (memh_valid) { 313 sc->sc_st = memt; 314 sc->sc_sh = memh; 315 } else if (ioh_valid) { 316 sc->sc_st = iot; 317 sc->sc_sh = ioh; 318 } else { 319 aprint_error(": unable to map device registers\n"); 320 return; 321 } 322 323 sc->sc_dmat = pa->pa_dmat; 324 325 fpp = fxp_pci_lookup(pa); 326 if (fpp == NULL) { 327 printf("\n"); 328 panic("fxp_pci_attach: impossible"); 329 } 330 331 sc->sc_rev = PCI_REVISION(pa->pa_class); 332 333 switch (fpp->fpp_prodid) { 334 case PCI_PRODUCT_INTEL_82557: 335 case PCI_PRODUCT_INTEL_82559ER: 336 case PCI_PRODUCT_INTEL_IN_BUSINESS: 337 { 338 const char *chipname = NULL; 339 340 if (sc->sc_rev >= FXP_REV_82558_A4) { 341 chipname = "i82558 Ethernet"; 342 /* 343 * Enable the MWI command for memory writes. 344 */ 345 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 346 sc->sc_flags |= FXPF_MWI; 347 } 348 if (sc->sc_rev >= FXP_REV_82559_A0) 349 chipname = "i82559 Ethernet"; 350 if (sc->sc_rev >= FXP_REV_82559S_A) 351 chipname = "i82559S Ethernet"; 352 if (sc->sc_rev >= FXP_REV_82550) 353 chipname = "i82550 Ethernet"; 354 355 /* 356 * Mark all i82559 and i82550 revisions as having 357 * the "resume bug". See i82557.c for details. 358 */ 359 if (sc->sc_rev >= FXP_REV_82559_A0) 360 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 361 362 aprint_normal(": %s, rev %d\n", chipname != NULL ? chipname : 363 fpp->fpp_name, sc->sc_rev); 364 break; 365 } 366 367 case PCI_PRODUCT_INTEL_82801BA_LAN: 368 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 369 370 /* 371 * The 82801BA Ethernet has a bug which requires us to send a 372 * NOP before a CU_RESUME if we're in 10baseT mode. 373 */ 374 if (fpp->fpp_prodid == PCI_PRODUCT_INTEL_82801BA_LAN) 375 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 376 break; 377 378 case PCI_PRODUCT_INTEL_PRO_100_VE_0: 379 case PCI_PRODUCT_INTEL_PRO_100_VE_1: 380 case PCI_PRODUCT_INTEL_PRO_100_VM_0: 381 case PCI_PRODUCT_INTEL_PRO_100_VM_1: 382 case PCI_PRODUCT_INTEL_82562EH_HPNA_0: 383 case PCI_PRODUCT_INTEL_82562EH_HPNA_1: 384 case PCI_PRODUCT_INTEL_82562EH_HPNA_2: 385 case PCI_PRODUCT_INTEL_PRO_100_VM_2: 386 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 387 388 /* 389 * ICH3 chips apparently have problems with the enhanced 390 * features, so just treat them as an i82557. It also 391 * has the resume bug that the ICH2 has. 392 */ 393 sc->sc_rev = 1; 394 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 395 break; 396 case PCI_PRODUCT_INTEL_82801E_LAN_1: 397 case PCI_PRODUCT_INTEL_82801E_LAN_2: 398 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 399 400 /* 401 * XXX We have to read the C-ICH's developer's manual 402 * in detail 403 */ 404 break; 405 case PCI_PRODUCT_INTEL_PRO_100_VE_2: 406 case PCI_PRODUCT_INTEL_PRO_100_VE_3: 407 case PCI_PRODUCT_INTEL_PRO_100_VE_4: 408 case PCI_PRODUCT_INTEL_PRO_100_VE_5: 409 case PCI_PRODUCT_INTEL_PRO_100_VM_3: 410 case PCI_PRODUCT_INTEL_PRO_100_VM_4: 411 case PCI_PRODUCT_INTEL_PRO_100_VM_5: 412 case PCI_PRODUCT_INTEL_PRO_100_VM_6: 413 case PCI_PRODUCT_INTEL_82801EB_LAN: 414 case PCI_PRODUCT_INTEL_82801FB_LAN: 415 case PCI_PRODUCT_INTEL_82801G_LAN: 416 default: 417 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 418 419 /* 420 * No particular quirks. 421 */ 422 break; 423 } 424 425 /* Make sure bus-mastering is enabled. */ 426 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 427 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 428 PCI_COMMAND_MASTER_ENABLE); 429 430 /* 431 * Under some circumstances (such as APM suspend/resume 432 * cycles, and across ACPI power state changes), the 433 * i82257-family can lose the contents of critical PCI 434 * configuration registers, causing the card to be 435 * non-responsive and useless. This occurs on the Sony VAIO 436 * Z505-series, among others. Preserve them here so they can 437 * be later restored (by fxp_pci_confreg_restore()). 438 */ 439 psc->psc_pc = pc; 440 psc->psc_tag = pa->pa_tag; 441 psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] = 442 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 443 psc->psc_regs[PCI_BHLC_REG>>2] = 444 pci_conf_read(pc, pa->pa_tag, PCI_BHLC_REG); 445 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2] = 446 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x0); 447 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2] = 448 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x4); 449 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2] = 450 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x8); 451 452 /* power up chip */ 453 switch ((error = pci_activate(pa->pa_pc, pa->pa_tag, sc, 454 pci_activate_null))) { 455 case EOPNOTSUPP: 456 break; 457 case 0: 458 sc->sc_enable = fxp_pci_enable; 459 sc->sc_disable = fxp_pci_disable; 460 break; 461 default: 462 aprint_error("%s: cannot activate %d\n", sc->sc_dev.dv_xname, 463 error); 464 return; 465 } 466 467 /* Restore PCI configuration registers. */ 468 fxp_pci_confreg_restore(psc); 469 470 sc->sc_enabled = 1; 471 472 /* 473 * Map and establish our interrupt. 474 */ 475 if (pci_intr_map(pa, &ih)) { 476 aprint_error("%s: couldn't map interrupt\n", 477 sc->sc_dev.dv_xname); 478 return; 479 } 480 intrstr = pci_intr_string(pc, ih); 481 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, fxp_intr, sc); 482 if (sc->sc_ih == NULL) { 483 aprint_error("%s: couldn't establish interrupt", 484 sc->sc_dev.dv_xname); 485 if (intrstr != NULL) 486 aprint_normal(" at %s", intrstr); 487 aprint_normal("\n"); 488 return; 489 } 490 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 491 492 /* Finish off the attach. */ 493 fxp_attach(sc); 494 if (sc->sc_disable != NULL) 495 fxp_disable(sc); 496 497 /* Add a suspend hook to restore PCI config state */ 498 if (!pmf_device_register(self, NULL, fxp_pci_resume)) 499 aprint_error_dev(self, "couldn't establish power handler\n"); 500 else 501 pmf_class_network_register(self, &sc->sc_ethercom.ec_if); 502 } 503 504 static int 505 fxp_pci_enable(struct fxp_softc *sc) 506 { 507 struct fxp_pci_softc *psc = (void *) sc; 508 509 #if 0 510 printf("%s: going to power state D0\n", sc->sc_dev.dv_xname); 511 #endif 512 513 /* Bring the device into D0 power state. */ 514 pci_conf_write(psc->psc_pc, psc->psc_tag, 515 psc->psc_pwrmgmt_csr_reg, psc->psc_pwrmgmt_csr); 516 517 /* Now restore the configuration registers. */ 518 fxp_pci_confreg_restore(psc); 519 520 return (0); 521 } 522 523 static void 524 fxp_pci_disable(struct fxp_softc *sc) 525 { 526 struct fxp_pci_softc *psc = (void *) sc; 527 528 /* 529 * for some 82558_A4 and 82558_B0, entering D3 state makes 530 * media detection disordered. 531 */ 532 if (sc->sc_rev <= FXP_REV_82558_B0) 533 return; 534 535 #if 0 536 printf("%s: going to power state D3\n", sc->sc_dev.dv_xname); 537 #endif 538 539 /* Put the device into D3 state. */ 540 pci_conf_write(psc->psc_pc, psc->psc_tag, 541 psc->psc_pwrmgmt_csr_reg, (psc->psc_pwrmgmt_csr & 542 ~PCI_PMCSR_STATE_MASK) | PCI_PMCSR_STATE_D3); 543 } 544
Indexes created Wed Sep 24 14:09:57 GMT 2025