if_fxp_pci.c revision 1.55.6.2
1 /* $NetBSD: if_fxp_pci.c,v 1.55.6.2 2008/06/02 13:23:39 mjf Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * PCI bus front-end for the Intel i82557 fast Ethernet controller 35 * driver. Works with Intel Etherexpress Pro 10+, 100B, 100+ cards. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: if_fxp_pci.c,v 1.55.6.2 2008/06/02 13:23:39 mjf Exp $"); 40 41 #include "rnd.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/mbuf.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #include <sys/socket.h> 49 #include <sys/ioctl.h> 50 #include <sys/errno.h> 51 #include <sys/device.h> 52 53 #if NRND > 0 54 #include <sys/rnd.h> 55 #endif 56 57 #include <machine/endian.h> 58 59 #include <net/if.h> 60 #include <net/if_dl.h> 61 #include <net/if_media.h> 62 #include <net/if_ether.h> 63 64 #include <sys/bus.h> 65 #include <sys/intr.h> 66 67 #include <dev/mii/miivar.h> 68 69 #include <dev/ic/i82557reg.h> 70 #include <dev/ic/i82557var.h> 71 72 #include <dev/pci/pcivar.h> 73 #include <dev/pci/pcireg.h> 74 #include <dev/pci/pcidevs.h> 75 76 struct fxp_pci_softc { 77 struct fxp_softc psc_fxp; 78 79 pci_chipset_tag_t psc_pc; /* pci chipset tag */ 80 pcireg_t psc_regs[0x20>>2]; /* saved PCI config regs (sparse) */ 81 pcitag_t psc_tag; /* pci register tag */ 82 83 int psc_pwrmgmt_csr_reg; /* ACPI power management register */ 84 pcireg_t psc_pwrmgmt_csr; /* ...and the contents at D0 */ 85 struct pci_conf_state psc_pciconf; /* standard PCI configuration regs */ 86 }; 87 88 static int fxp_pci_match(struct device *, struct cfdata *, void *); 89 static void fxp_pci_attach(struct device *, struct device *, void *); 90 91 static int fxp_pci_enable(struct fxp_softc *); 92 static void fxp_pci_disable(struct fxp_softc *); 93 94 static void fxp_pci_confreg_restore(struct fxp_pci_softc *psc); 95 static bool fxp_pci_resume(device_t dv PMF_FN_PROTO); 96 97 CFATTACH_DECL(fxp_pci, sizeof(struct fxp_pci_softc), 98 fxp_pci_match, fxp_pci_attach, NULL, NULL); 99 100 static const struct fxp_pci_product { 101 u_int32_t fpp_prodid; /* PCI product ID */ 102 const char *fpp_name; /* device name */ 103 } fxp_pci_products[] = { 104 { PCI_PRODUCT_INTEL_82557, 105 "Intel i82557 Ethernet" }, 106 { PCI_PRODUCT_INTEL_82559ER, 107 "Intel i82559ER Ethernet" }, 108 { PCI_PRODUCT_INTEL_IN_BUSINESS, 109 "Intel InBusiness Ethernet" }, 110 { PCI_PRODUCT_INTEL_82801BA_LAN, 111 "Intel i82562 Ethernet" }, 112 { PCI_PRODUCT_INTEL_82801E_LAN_1, 113 "Intel i82559 Ethernet" }, 114 { PCI_PRODUCT_INTEL_82801E_LAN_2, 115 "Intel i82559 Ethernet" }, 116 { PCI_PRODUCT_INTEL_PRO_100_VE_0, 117 "Intel PRO/100 VE Network Controller" }, 118 { PCI_PRODUCT_INTEL_PRO_100_VE_1, 119 "Intel PRO/100 VE Network Controller" }, 120 { PCI_PRODUCT_INTEL_PRO_100_VE_2, 121 "Intel PRO/100 VE Network Controller with 82562ET/EZ PHY" }, 122 { PCI_PRODUCT_INTEL_PRO_100_VE_3, 123 "Intel PRO/100 VE Network Controller with 82562ET/EZ (CNR) PHY" }, 124 { PCI_PRODUCT_INTEL_PRO_100_VE_4, 125 "Intel PRO/100 VE (MOB) Network Controller" }, 126 { PCI_PRODUCT_INTEL_PRO_100_VE_5, 127 "Intel PRO/100 VE (LOM) Network Controller" }, 128 { PCI_PRODUCT_INTEL_PRO_100_VE_6, 129 "Intel PRO/100 VE Network Controller" }, 130 { PCI_PRODUCT_INTEL_PRO_100_VE_7, 131 "Intel PRO/100 VE Network Controller" }, 132 { PCI_PRODUCT_INTEL_PRO_100_VE_8, 133 "Intel PRO/100 VE Network Controller" }, 134 { PCI_PRODUCT_INTEL_PRO_100_VM_0, 135 "Intel PRO/100 VM Network Controller" }, 136 { PCI_PRODUCT_INTEL_PRO_100_VM_1, 137 "Intel PRO/100 VM Network Controller" }, 138 { PCI_PRODUCT_INTEL_PRO_100_VM_2, 139 "Intel PRO/100 VM Network Controller" }, 140 { PCI_PRODUCT_INTEL_PRO_100_VM_3, 141 "Intel PRO/100 VM Network Controller with 82562EM/EX PHY" }, 142 { PCI_PRODUCT_INTEL_PRO_100_VM_4, 143 "Intel PRO/100 VM Network Controller with 82562EM/EX (CNR) PHY" }, 144 { PCI_PRODUCT_INTEL_PRO_100_VM_5, 145 "Intel PRO/100 VM (MOB) Network Controller" }, 146 { PCI_PRODUCT_INTEL_PRO_100_VM_6, 147 "Intel PRO/100 VM Network Controller with 82562ET/EZ PHY" }, 148 { PCI_PRODUCT_INTEL_PRO_100_M, 149 "Intel PRO/100 M Network Controller" }, 150 { PCI_PRODUCT_INTEL_82801EB_LAN, 151 "Intel 82801EB/ER (ICH5) Network Controller" }, 152 { PCI_PRODUCT_INTEL_82801FB_LAN, 153 "Intel 82562EZ (ICH6)" }, 154 { PCI_PRODUCT_INTEL_82801G_LAN, 155 "Intel 82801GB/GR (ICH7) Network Controller" }, 156 { PCI_PRODUCT_INTEL_82801GB_LAN, 157 "Intel 82801GB 10/100 Network Controller" }, 158 { 0, 159 NULL }, 160 }; 161 162 static const struct fxp_pci_product * 163 fxp_pci_lookup(const struct pci_attach_args *pa) 164 { 165 const struct fxp_pci_product *fpp; 166 167 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 168 return (NULL); 169 170 for (fpp = fxp_pci_products; fpp->fpp_name != NULL; fpp++) 171 if (PCI_PRODUCT(pa->pa_id) == fpp->fpp_prodid) 172 return (fpp); 173 174 return (NULL); 175 } 176 177 static int 178 fxp_pci_match(device_t parent, struct cfdata *match, void *aux) 179 { 180 struct pci_attach_args *pa = aux; 181 182 if (fxp_pci_lookup(pa) != NULL) 183 return (1); 184 185 return (0); 186 } 187 188 /* 189 * On resume : (XXX it is necessary with new pmf framework ?) 190 * Restore PCI configuration registers that may have been clobbered. 191 * This is necessary due to bugs on the Sony VAIO Z505-series on-board 192 * ethernet, after an APM suspend/resume, as well as after an ACPI 193 * D3->D0 transition. We call this function from a power hook after 194 * APM resume events, as well as after the ACPI D3->D0 transition. 195 */ 196 static void 197 fxp_pci_confreg_restore(struct fxp_pci_softc *psc) 198 { 199 pcireg_t reg; 200 201 #if 0 202 /* 203 * Check to see if the command register is blank -- if so, then 204 * we'll assume that all the clobberable-registers have been 205 * clobbered. 206 */ 207 208 /* 209 * In general, the above metric is accurate. Unfortunately, 210 * it is inaccurate across a hibernation. Ideally APM/ACPI 211 * code should take note of hibernation events and execute 212 * a hibernation wakeup hook, but at present a hibernation wake 213 * is indistinguishable from a suspend wake. 214 */ 215 216 if (((reg = pci_conf_read(psc->psc_pc, psc->psc_tag, 217 PCI_COMMAND_STATUS_REG)) & 0xffff) != 0) 218 return; 219 #else 220 reg = pci_conf_read(psc->psc_pc, psc->psc_tag, PCI_COMMAND_STATUS_REG); 221 #endif 222 223 pci_conf_write(psc->psc_pc, psc->psc_tag, 224 PCI_COMMAND_STATUS_REG, 225 (reg & 0xffff0000) | 226 (psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] & 0xffff)); 227 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_BHLC_REG, 228 psc->psc_regs[PCI_BHLC_REG>>2]); 229 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x0, 230 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2]); 231 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x4, 232 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2]); 233 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x8, 234 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2]); 235 } 236 237 static bool 238 fxp_pci_resume(device_t dv PMF_FN_ARGS) 239 { 240 struct fxp_pci_softc *psc = device_private(dv); 241 fxp_pci_confreg_restore(psc); 242 243 return true; 244 } 245 246 static void 247 fxp_pci_attach(device_t parent, device_t self, void *aux) 248 { 249 struct fxp_pci_softc *psc = device_private(self); 250 struct fxp_softc *sc = &psc->psc_fxp; 251 struct pci_attach_args *pa = aux; 252 pci_chipset_tag_t pc = pa->pa_pc; 253 pci_intr_handle_t ih; 254 const struct fxp_pci_product *fpp; 255 const char *intrstr = NULL; 256 bus_space_tag_t iot, memt; 257 bus_space_handle_t ioh, memh; 258 int ioh_valid, memh_valid; 259 bus_addr_t addr; 260 bus_size_t size; 261 int flags; 262 int error; 263 264 aprint_naive(": Ethernet controller\n"); 265 266 /* 267 * Map control/status registers. 268 */ 269 ioh_valid = (pci_mapreg_map(pa, FXP_PCI_IOBA, 270 PCI_MAPREG_TYPE_IO, 0, 271 &iot, &ioh, NULL, NULL) == 0); 272 273 /* 274 * Version 2.1 of the PCI spec, page 196, "Address Maps": 275 * 276 * Prefetchable 277 * 278 * Set to one if there are no side effects on reads, the 279 * device returns all bytes regardless of the byte enables, 280 * and host bridges can merge processor writes into this 281 * range without causing errors. Bit must be set to zero 282 * otherwise. 283 * 284 * The 82557 incorrectly sets the "prefetchable" bit, resulting 285 * in errors on systems which will do merged reads and writes. 286 * These errors manifest themselves as all-bits-set when reading 287 * from the EEPROM or other < 4 byte registers. 288 * 289 * We must work around this problem by always forcing the mapping 290 * for memory space to be uncacheable. On systems which cannot 291 * create an uncacheable mapping (because the firmware mapped it 292 * into only cacheable/prefetchable space due to the "prefetchable" 293 * bit), we can fall back onto i/o mapped access. 294 */ 295 memh_valid = 0; 296 memt = pa->pa_memt; 297 if (((pa->pa_flags & PCI_FLAGS_MEM_ENABLED) != 0) && 298 pci_mapreg_info(pa->pa_pc, pa->pa_tag, FXP_PCI_MMBA, 299 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 300 &addr, &size, &flags) == 0) { 301 flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 302 if (bus_space_map(memt, addr, size, flags, &memh) == 0) 303 memh_valid = 1; 304 } 305 306 if (memh_valid) { 307 sc->sc_st = memt; 308 sc->sc_sh = memh; 309 } else if (ioh_valid) { 310 sc->sc_st = iot; 311 sc->sc_sh = ioh; 312 } else { 313 aprint_error(": unable to map device registers\n"); 314 return; 315 } 316 317 sc->sc_dmat = pa->pa_dmat; 318 319 fpp = fxp_pci_lookup(pa); 320 if (fpp == NULL) { 321 printf("\n"); 322 panic("fxp_pci_attach: impossible"); 323 } 324 325 sc->sc_rev = PCI_REVISION(pa->pa_class); 326 327 switch (fpp->fpp_prodid) { 328 case PCI_PRODUCT_INTEL_82557: 329 case PCI_PRODUCT_INTEL_82559ER: 330 case PCI_PRODUCT_INTEL_IN_BUSINESS: 331 { 332 const char *chipname = NULL; 333 334 if (sc->sc_rev >= FXP_REV_82558_A4) { 335 chipname = "i82558 Ethernet"; 336 /* 337 * Enable the MWI command for memory writes. 338 */ 339 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 340 sc->sc_flags |= FXPF_MWI; 341 } 342 if (sc->sc_rev >= FXP_REV_82559_A0) 343 chipname = "i82559 Ethernet"; 344 if (sc->sc_rev >= FXP_REV_82559S_A) 345 chipname = "i82559S Ethernet"; 346 if (sc->sc_rev >= FXP_REV_82550) 347 chipname = "i82550 Ethernet"; 348 349 /* 350 * Mark all i82559 and i82550 revisions as having 351 * the "resume bug". See i82557.c for details. 352 */ 353 if (sc->sc_rev >= FXP_REV_82559_A0) 354 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 355 356 aprint_normal(": %s, rev %d\n", chipname != NULL ? chipname : 357 fpp->fpp_name, sc->sc_rev); 358 break; 359 } 360 361 case PCI_PRODUCT_INTEL_82801BA_LAN: 362 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 363 364 /* 365 * The 82801BA Ethernet has a bug which requires us to send a 366 * NOP before a CU_RESUME if we're in 10baseT mode. 367 */ 368 if (fpp->fpp_prodid == PCI_PRODUCT_INTEL_82801BA_LAN) 369 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 370 break; 371 372 case PCI_PRODUCT_INTEL_PRO_100_VE_0: 373 case PCI_PRODUCT_INTEL_PRO_100_VE_1: 374 case PCI_PRODUCT_INTEL_PRO_100_VM_0: 375 case PCI_PRODUCT_INTEL_PRO_100_VM_1: 376 case PCI_PRODUCT_INTEL_82562EH_HPNA_0: 377 case PCI_PRODUCT_INTEL_82562EH_HPNA_1: 378 case PCI_PRODUCT_INTEL_82562EH_HPNA_2: 379 case PCI_PRODUCT_INTEL_PRO_100_VM_2: 380 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 381 382 /* 383 * ICH3 chips apparently have problems with the enhanced 384 * features, so just treat them as an i82557. It also 385 * has the resume bug that the ICH2 has. 386 */ 387 sc->sc_rev = 1; 388 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 389 break; 390 case PCI_PRODUCT_INTEL_82801E_LAN_1: 391 case PCI_PRODUCT_INTEL_82801E_LAN_2: 392 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 393 394 /* 395 * XXX We have to read the C-ICH's developer's manual 396 * in detail 397 */ 398 break; 399 case PCI_PRODUCT_INTEL_PRO_100_VE_2: 400 case PCI_PRODUCT_INTEL_PRO_100_VE_3: 401 case PCI_PRODUCT_INTEL_PRO_100_VE_4: 402 case PCI_PRODUCT_INTEL_PRO_100_VE_5: 403 case PCI_PRODUCT_INTEL_PRO_100_VM_3: 404 case PCI_PRODUCT_INTEL_PRO_100_VM_4: 405 case PCI_PRODUCT_INTEL_PRO_100_VM_5: 406 case PCI_PRODUCT_INTEL_PRO_100_VM_6: 407 case PCI_PRODUCT_INTEL_82801EB_LAN: 408 case PCI_PRODUCT_INTEL_82801FB_LAN: 409 case PCI_PRODUCT_INTEL_82801G_LAN: 410 default: 411 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 412 413 /* 414 * No particular quirks. 415 */ 416 break; 417 } 418 419 /* Make sure bus-mastering is enabled. */ 420 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 421 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 422 PCI_COMMAND_MASTER_ENABLE); 423 424 /* 425 * Under some circumstances (such as APM suspend/resume 426 * cycles, and across ACPI power state changes), the 427 * i82257-family can lose the contents of critical PCI 428 * configuration registers, causing the card to be 429 * non-responsive and useless. This occurs on the Sony VAIO 430 * Z505-series, among others. Preserve them here so they can 431 * be later restored (by fxp_pci_confreg_restore()). 432 */ 433 psc->psc_pc = pc; 434 psc->psc_tag = pa->pa_tag; 435 psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] = 436 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 437 psc->psc_regs[PCI_BHLC_REG>>2] = 438 pci_conf_read(pc, pa->pa_tag, PCI_BHLC_REG); 439 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2] = 440 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x0); 441 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2] = 442 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x4); 443 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2] = 444 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x8); 445 446 /* power up chip */ 447 switch ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 448 pci_activate_null))) { 449 case EOPNOTSUPP: 450 break; 451 case 0: 452 sc->sc_enable = fxp_pci_enable; 453 sc->sc_disable = fxp_pci_disable; 454 break; 455 default: 456 aprint_error_dev(&sc->sc_dev, "cannot activate %d\n", 457 error); 458 return; 459 } 460 461 /* Restore PCI configuration registers. */ 462 fxp_pci_confreg_restore(psc); 463 464 sc->sc_enabled = 1; 465 466 /* 467 * Map and establish our interrupt. 468 */ 469 if (pci_intr_map(pa, &ih)) { 470 aprint_error_dev(&sc->sc_dev, "couldn't map interrupt\n"); 471 return; 472 } 473 intrstr = pci_intr_string(pc, ih); 474 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, fxp_intr, sc); 475 if (sc->sc_ih == NULL) { 476 aprint_error_dev(&sc->sc_dev, "couldn't establish interrupt"); 477 if (intrstr != NULL) 478 aprint_normal(" at %s", intrstr); 479 aprint_normal("\n"); 480 return; 481 } 482 aprint_normal_dev(&sc->sc_dev, "interrupting at %s\n", intrstr); 483 484 /* Finish off the attach. */ 485 fxp_attach(sc); 486 if (sc->sc_disable != NULL) 487 fxp_disable(sc); 488 489 /* Add a suspend hook to restore PCI config state */ 490 if (!pmf_device_register(self, NULL, fxp_pci_resume)) 491 aprint_error_dev(self, "couldn't establish power handler\n"); 492 else 493 pmf_class_network_register(self, &sc->sc_ethercom.ec_if); 494 } 495 496 static int 497 fxp_pci_enable(struct fxp_softc *sc) 498 { 499 struct fxp_pci_softc *psc = (void *) sc; 500 501 #if 0 502 printf("%s: going to power state D0\n", device_xname(&sc->sc_dev)); 503 #endif 504 505 /* Bring the device into D0 power state. */ 506 pci_conf_write(psc->psc_pc, psc->psc_tag, 507 psc->psc_pwrmgmt_csr_reg, psc->psc_pwrmgmt_csr); 508 509 /* Now restore the configuration registers. */ 510 fxp_pci_confreg_restore(psc); 511 512 return (0); 513 } 514 515 static void 516 fxp_pci_disable(struct fxp_softc *sc) 517 { 518 struct fxp_pci_softc *psc = (void *) sc; 519 520 /* 521 * for some 82558_A4 and 82558_B0, entering D3 state makes 522 * media detection disordered. 523 */ 524 if (sc->sc_rev <= FXP_REV_82558_B0) 525 return; 526 527 #if 0 528 printf("%s: going to power state D3\n", device_xname(&sc->sc_dev)); 529 #endif 530 531 /* Put the device into D3 state. */ 532 pci_conf_write(psc->psc_pc, psc->psc_tag, 533 psc->psc_pwrmgmt_csr_reg, (psc->psc_pwrmgmt_csr & 534 ~PCI_PMCSR_STATE_MASK) | PCI_PMCSR_STATE_D3); 535 } 536
Indexes created Thu Oct 02 01:09:59 GMT 2025