if_fxp_pci.c revision 1.57
1 /* $NetBSD: if_fxp_pci.c,v 1.57 2008/03/21 07:47:43 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * PCI bus front-end for the Intel i82557 fast Ethernet controller 42 * driver. Works with Intel Etherexpress Pro 10+, 100B, 100+ cards. 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: if_fxp_pci.c,v 1.57 2008/03/21 07:47:43 dyoung Exp $"); 47 48 #include "rnd.h" 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/mbuf.h> 53 #include <sys/malloc.h> 54 #include <sys/kernel.h> 55 #include <sys/socket.h> 56 #include <sys/ioctl.h> 57 #include <sys/errno.h> 58 #include <sys/device.h> 59 60 #if NRND > 0 61 #include <sys/rnd.h> 62 #endif 63 64 #include <machine/endian.h> 65 66 #include <net/if.h> 67 #include <net/if_dl.h> 68 #include <net/if_media.h> 69 #include <net/if_ether.h> 70 71 #include <sys/bus.h> 72 #include <sys/intr.h> 73 74 #include <dev/mii/miivar.h> 75 76 #include <dev/ic/i82557reg.h> 77 #include <dev/ic/i82557var.h> 78 79 #include <dev/pci/pcivar.h> 80 #include <dev/pci/pcireg.h> 81 #include <dev/pci/pcidevs.h> 82 83 struct fxp_pci_softc { 84 struct fxp_softc psc_fxp; 85 86 pci_chipset_tag_t psc_pc; /* pci chipset tag */ 87 pcireg_t psc_regs[0x20>>2]; /* saved PCI config regs (sparse) */ 88 pcitag_t psc_tag; /* pci register tag */ 89 90 int psc_pwrmgmt_csr_reg; /* ACPI power management register */ 91 pcireg_t psc_pwrmgmt_csr; /* ...and the contents at D0 */ 92 struct pci_conf_state psc_pciconf; /* standard PCI configuration regs */ 93 }; 94 95 static int fxp_pci_match(struct device *, struct cfdata *, void *); 96 static void fxp_pci_attach(struct device *, struct device *, void *); 97 98 static int fxp_pci_enable(struct fxp_softc *); 99 static void fxp_pci_disable(struct fxp_softc *); 100 101 static void fxp_pci_confreg_restore(struct fxp_pci_softc *psc); 102 static bool fxp_pci_resume(device_t dv PMF_FN_PROTO); 103 104 CFATTACH_DECL(fxp_pci, sizeof(struct fxp_pci_softc), 105 fxp_pci_match, fxp_pci_attach, NULL, NULL); 106 107 static const struct fxp_pci_product { 108 u_int32_t fpp_prodid; /* PCI product ID */ 109 const char *fpp_name; /* device name */ 110 } fxp_pci_products[] = { 111 { PCI_PRODUCT_INTEL_82557, 112 "Intel i82557 Ethernet" }, 113 { PCI_PRODUCT_INTEL_82559ER, 114 "Intel i82559ER Ethernet" }, 115 { PCI_PRODUCT_INTEL_IN_BUSINESS, 116 "Intel InBusiness Ethernet" }, 117 { PCI_PRODUCT_INTEL_82801BA_LAN, 118 "Intel i82562 Ethernet" }, 119 { PCI_PRODUCT_INTEL_82801E_LAN_1, 120 "Intel i82559 Ethernet" }, 121 { PCI_PRODUCT_INTEL_82801E_LAN_2, 122 "Intel i82559 Ethernet" }, 123 { PCI_PRODUCT_INTEL_PRO_100_VE_0, 124 "Intel PRO/100 VE Network Controller" }, 125 { PCI_PRODUCT_INTEL_PRO_100_VE_1, 126 "Intel PRO/100 VE Network Controller" }, 127 { PCI_PRODUCT_INTEL_PRO_100_VE_2, 128 "Intel PRO/100 VE Network Controller with 82562ET/EZ PHY" }, 129 { PCI_PRODUCT_INTEL_PRO_100_VE_3, 130 "Intel PRO/100 VE Network Controller with 82562ET/EZ (CNR) PHY" }, 131 { PCI_PRODUCT_INTEL_PRO_100_VE_4, 132 "Intel PRO/100 VE (MOB) Network Controller" }, 133 { PCI_PRODUCT_INTEL_PRO_100_VE_5, 134 "Intel PRO/100 VE (LOM) Network Controller" }, 135 { PCI_PRODUCT_INTEL_PRO_100_VE_6, 136 "Intel PRO/100 VE Network Controller" }, 137 { PCI_PRODUCT_INTEL_PRO_100_VE_7, 138 "Intel PRO/100 VE Network Controller" }, 139 { PCI_PRODUCT_INTEL_PRO_100_VE_8, 140 "Intel PRO/100 VE Network Controller" }, 141 { PCI_PRODUCT_INTEL_PRO_100_VM_0, 142 "Intel PRO/100 VM Network Controller" }, 143 { PCI_PRODUCT_INTEL_PRO_100_VM_1, 144 "Intel PRO/100 VM Network Controller" }, 145 { PCI_PRODUCT_INTEL_PRO_100_VM_2, 146 "Intel PRO/100 VM Network Controller" }, 147 { PCI_PRODUCT_INTEL_PRO_100_VM_3, 148 "Intel PRO/100 VM Network Controller with 82562EM/EX PHY" }, 149 { PCI_PRODUCT_INTEL_PRO_100_VM_4, 150 "Intel PRO/100 VM Network Controller with 82562EM/EX (CNR) PHY" }, 151 { PCI_PRODUCT_INTEL_PRO_100_VM_5, 152 "Intel PRO/100 VM (MOB) Network Controller" }, 153 { PCI_PRODUCT_INTEL_PRO_100_VM_6, 154 "Intel PRO/100 VM Network Controller with 82562ET/EZ PHY" }, 155 { PCI_PRODUCT_INTEL_PRO_100_M, 156 "Intel PRO/100 M Network Controller" }, 157 { PCI_PRODUCT_INTEL_82801EB_LAN, 158 "Intel 82801EB/ER (ICH5) Network Controller" }, 159 { PCI_PRODUCT_INTEL_82801FB_LAN, 160 "Intel 82562EZ (ICH6)" }, 161 { PCI_PRODUCT_INTEL_82801G_LAN, 162 "Intel 82801GB/GR (ICH7) Network Controller" }, 163 { PCI_PRODUCT_INTEL_82801GB_LAN, 164 "Intel 82801GB 10/100 Network Controller" }, 165 { 0, 166 NULL }, 167 }; 168 169 static const struct fxp_pci_product * 170 fxp_pci_lookup(const struct pci_attach_args *pa) 171 { 172 const struct fxp_pci_product *fpp; 173 174 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 175 return (NULL); 176 177 for (fpp = fxp_pci_products; fpp->fpp_name != NULL; fpp++) 178 if (PCI_PRODUCT(pa->pa_id) == fpp->fpp_prodid) 179 return (fpp); 180 181 return (NULL); 182 } 183 184 static int 185 fxp_pci_match(device_t parent, struct cfdata *match, void *aux) 186 { 187 struct pci_attach_args *pa = aux; 188 189 if (fxp_pci_lookup(pa) != NULL) 190 return (1); 191 192 return (0); 193 } 194 195 /* 196 * On resume : (XXX it is necessary with new pmf framework ?) 197 * Restore PCI configuration registers that may have been clobbered. 198 * This is necessary due to bugs on the Sony VAIO Z505-series on-board 199 * ethernet, after an APM suspend/resume, as well as after an ACPI 200 * D3->D0 transition. We call this function from a power hook after 201 * APM resume events, as well as after the ACPI D3->D0 transition. 202 */ 203 static void 204 fxp_pci_confreg_restore(struct fxp_pci_softc *psc) 205 { 206 pcireg_t reg; 207 208 #if 0 209 /* 210 * Check to see if the command register is blank -- if so, then 211 * we'll assume that all the clobberable-registers have been 212 * clobbered. 213 */ 214 215 /* 216 * In general, the above metric is accurate. Unfortunately, 217 * it is inaccurate across a hibernation. Ideally APM/ACPI 218 * code should take note of hibernation events and execute 219 * a hibernation wakeup hook, but at present a hibernation wake 220 * is indistinguishable from a suspend wake. 221 */ 222 223 if (((reg = pci_conf_read(psc->psc_pc, psc->psc_tag, 224 PCI_COMMAND_STATUS_REG)) & 0xffff) != 0) 225 return; 226 #else 227 reg = pci_conf_read(psc->psc_pc, psc->psc_tag, PCI_COMMAND_STATUS_REG); 228 #endif 229 230 pci_conf_write(psc->psc_pc, psc->psc_tag, 231 PCI_COMMAND_STATUS_REG, 232 (reg & 0xffff0000) | 233 (psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] & 0xffff)); 234 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_BHLC_REG, 235 psc->psc_regs[PCI_BHLC_REG>>2]); 236 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x0, 237 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2]); 238 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x4, 239 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2]); 240 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x8, 241 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2]); 242 } 243 244 static bool 245 fxp_pci_resume(device_t dv PMF_FN_ARGS) 246 { 247 struct fxp_pci_softc *psc = device_private(dv); 248 fxp_pci_confreg_restore(psc); 249 250 return true; 251 } 252 253 static void 254 fxp_pci_attach(device_t parent, device_t self, void *aux) 255 { 256 struct fxp_pci_softc *psc = device_private(self); 257 struct fxp_softc *sc = &psc->psc_fxp; 258 struct pci_attach_args *pa = aux; 259 pci_chipset_tag_t pc = pa->pa_pc; 260 pci_intr_handle_t ih; 261 const struct fxp_pci_product *fpp; 262 const char *intrstr = NULL; 263 bus_space_tag_t iot, memt; 264 bus_space_handle_t ioh, memh; 265 int ioh_valid, memh_valid; 266 bus_addr_t addr; 267 bus_size_t size; 268 int flags; 269 int error; 270 271 aprint_naive(": Ethernet controller\n"); 272 273 /* 274 * Map control/status registers. 275 */ 276 ioh_valid = (pci_mapreg_map(pa, FXP_PCI_IOBA, 277 PCI_MAPREG_TYPE_IO, 0, 278 &iot, &ioh, NULL, NULL) == 0); 279 280 /* 281 * Version 2.1 of the PCI spec, page 196, "Address Maps": 282 * 283 * Prefetchable 284 * 285 * Set to one if there are no side effects on reads, the 286 * device returns all bytes regardless of the byte enables, 287 * and host bridges can merge processor writes into this 288 * range without causing errors. Bit must be set to zero 289 * otherwise. 290 * 291 * The 82557 incorrectly sets the "prefetchable" bit, resulting 292 * in errors on systems which will do merged reads and writes. 293 * These errors manifest themselves as all-bits-set when reading 294 * from the EEPROM or other < 4 byte registers. 295 * 296 * We must work around this problem by always forcing the mapping 297 * for memory space to be uncacheable. On systems which cannot 298 * create an uncacheable mapping (because the firmware mapped it 299 * into only cacheable/prefetchable space due to the "prefetchable" 300 * bit), we can fall back onto i/o mapped access. 301 */ 302 memh_valid = 0; 303 memt = pa->pa_memt; 304 if (((pa->pa_flags & PCI_FLAGS_MEM_ENABLED) != 0) && 305 pci_mapreg_info(pa->pa_pc, pa->pa_tag, FXP_PCI_MMBA, 306 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 307 &addr, &size, &flags) == 0) { 308 flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 309 if (bus_space_map(memt, addr, size, flags, &memh) == 0) 310 memh_valid = 1; 311 } 312 313 if (memh_valid) { 314 sc->sc_st = memt; 315 sc->sc_sh = memh; 316 } else if (ioh_valid) { 317 sc->sc_st = iot; 318 sc->sc_sh = ioh; 319 } else { 320 aprint_error(": unable to map device registers\n"); 321 return; 322 } 323 324 sc->sc_dmat = pa->pa_dmat; 325 326 fpp = fxp_pci_lookup(pa); 327 if (fpp == NULL) { 328 printf("\n"); 329 panic("fxp_pci_attach: impossible"); 330 } 331 332 sc->sc_rev = PCI_REVISION(pa->pa_class); 333 334 switch (fpp->fpp_prodid) { 335 case PCI_PRODUCT_INTEL_82557: 336 case PCI_PRODUCT_INTEL_82559ER: 337 case PCI_PRODUCT_INTEL_IN_BUSINESS: 338 { 339 const char *chipname = NULL; 340 341 if (sc->sc_rev >= FXP_REV_82558_A4) { 342 chipname = "i82558 Ethernet"; 343 /* 344 * Enable the MWI command for memory writes. 345 */ 346 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 347 sc->sc_flags |= FXPF_MWI; 348 } 349 if (sc->sc_rev >= FXP_REV_82559_A0) 350 chipname = "i82559 Ethernet"; 351 if (sc->sc_rev >= FXP_REV_82559S_A) 352 chipname = "i82559S Ethernet"; 353 if (sc->sc_rev >= FXP_REV_82550) 354 chipname = "i82550 Ethernet"; 355 356 /* 357 * Mark all i82559 and i82550 revisions as having 358 * the "resume bug". See i82557.c for details. 359 */ 360 if (sc->sc_rev >= FXP_REV_82559_A0) 361 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 362 363 aprint_normal(": %s, rev %d\n", chipname != NULL ? chipname : 364 fpp->fpp_name, sc->sc_rev); 365 break; 366 } 367 368 case PCI_PRODUCT_INTEL_82801BA_LAN: 369 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 370 371 /* 372 * The 82801BA Ethernet has a bug which requires us to send a 373 * NOP before a CU_RESUME if we're in 10baseT mode. 374 */ 375 if (fpp->fpp_prodid == PCI_PRODUCT_INTEL_82801BA_LAN) 376 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 377 break; 378 379 case PCI_PRODUCT_INTEL_PRO_100_VE_0: 380 case PCI_PRODUCT_INTEL_PRO_100_VE_1: 381 case PCI_PRODUCT_INTEL_PRO_100_VM_0: 382 case PCI_PRODUCT_INTEL_PRO_100_VM_1: 383 case PCI_PRODUCT_INTEL_82562EH_HPNA_0: 384 case PCI_PRODUCT_INTEL_82562EH_HPNA_1: 385 case PCI_PRODUCT_INTEL_82562EH_HPNA_2: 386 case PCI_PRODUCT_INTEL_PRO_100_VM_2: 387 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 388 389 /* 390 * ICH3 chips apparently have problems with the enhanced 391 * features, so just treat them as an i82557. It also 392 * has the resume bug that the ICH2 has. 393 */ 394 sc->sc_rev = 1; 395 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 396 break; 397 case PCI_PRODUCT_INTEL_82801E_LAN_1: 398 case PCI_PRODUCT_INTEL_82801E_LAN_2: 399 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 400 401 /* 402 * XXX We have to read the C-ICH's developer's manual 403 * in detail 404 */ 405 break; 406 case PCI_PRODUCT_INTEL_PRO_100_VE_2: 407 case PCI_PRODUCT_INTEL_PRO_100_VE_3: 408 case PCI_PRODUCT_INTEL_PRO_100_VE_4: 409 case PCI_PRODUCT_INTEL_PRO_100_VE_5: 410 case PCI_PRODUCT_INTEL_PRO_100_VM_3: 411 case PCI_PRODUCT_INTEL_PRO_100_VM_4: 412 case PCI_PRODUCT_INTEL_PRO_100_VM_5: 413 case PCI_PRODUCT_INTEL_PRO_100_VM_6: 414 case PCI_PRODUCT_INTEL_82801EB_LAN: 415 case PCI_PRODUCT_INTEL_82801FB_LAN: 416 case PCI_PRODUCT_INTEL_82801G_LAN: 417 default: 418 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 419 420 /* 421 * No particular quirks. 422 */ 423 break; 424 } 425 426 /* Make sure bus-mastering is enabled. */ 427 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 428 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 429 PCI_COMMAND_MASTER_ENABLE); 430 431 /* 432 * Under some circumstances (such as APM suspend/resume 433 * cycles, and across ACPI power state changes), the 434 * i82257-family can lose the contents of critical PCI 435 * configuration registers, causing the card to be 436 * non-responsive and useless. This occurs on the Sony VAIO 437 * Z505-series, among others. Preserve them here so they can 438 * be later restored (by fxp_pci_confreg_restore()). 439 */ 440 psc->psc_pc = pc; 441 psc->psc_tag = pa->pa_tag; 442 psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] = 443 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 444 psc->psc_regs[PCI_BHLC_REG>>2] = 445 pci_conf_read(pc, pa->pa_tag, PCI_BHLC_REG); 446 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2] = 447 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x0); 448 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2] = 449 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x4); 450 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2] = 451 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x8); 452 453 /* power up chip */ 454 switch ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 455 pci_activate_null))) { 456 case EOPNOTSUPP: 457 break; 458 case 0: 459 sc->sc_enable = fxp_pci_enable; 460 sc->sc_disable = fxp_pci_disable; 461 break; 462 default: 463 aprint_error("%s: cannot activate %d\n", sc->sc_dev.dv_xname, 464 error); 465 return; 466 } 467 468 /* Restore PCI configuration registers. */ 469 fxp_pci_confreg_restore(psc); 470 471 sc->sc_enabled = 1; 472 473 /* 474 * Map and establish our interrupt. 475 */ 476 if (pci_intr_map(pa, &ih)) { 477 aprint_error("%s: couldn't map interrupt\n", 478 sc->sc_dev.dv_xname); 479 return; 480 } 481 intrstr = pci_intr_string(pc, ih); 482 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, fxp_intr, sc); 483 if (sc->sc_ih == NULL) { 484 aprint_error("%s: couldn't establish interrupt", 485 sc->sc_dev.dv_xname); 486 if (intrstr != NULL) 487 aprint_normal(" at %s", intrstr); 488 aprint_normal("\n"); 489 return; 490 } 491 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 492 493 /* Finish off the attach. */ 494 fxp_attach(sc); 495 if (sc->sc_disable != NULL) 496 fxp_disable(sc); 497 498 /* Add a suspend hook to restore PCI config state */ 499 if (!pmf_device_register(self, NULL, fxp_pci_resume)) 500 aprint_error_dev(self, "couldn't establish power handler\n"); 501 else 502 pmf_class_network_register(self, &sc->sc_ethercom.ec_if); 503 } 504 505 static int 506 fxp_pci_enable(struct fxp_softc *sc) 507 { 508 struct fxp_pci_softc *psc = (void *) sc; 509 510 #if 0 511 printf("%s: going to power state D0\n", sc->sc_dev.dv_xname); 512 #endif 513 514 /* Bring the device into D0 power state. */ 515 pci_conf_write(psc->psc_pc, psc->psc_tag, 516 psc->psc_pwrmgmt_csr_reg, psc->psc_pwrmgmt_csr); 517 518 /* Now restore the configuration registers. */ 519 fxp_pci_confreg_restore(psc); 520 521 return (0); 522 } 523 524 static void 525 fxp_pci_disable(struct fxp_softc *sc) 526 { 527 struct fxp_pci_softc *psc = (void *) sc; 528 529 /* 530 * for some 82558_A4 and 82558_B0, entering D3 state makes 531 * media detection disordered. 532 */ 533 if (sc->sc_rev <= FXP_REV_82558_B0) 534 return; 535 536 #if 0 537 printf("%s: going to power state D3\n", sc->sc_dev.dv_xname); 538 #endif 539 540 /* Put the device into D3 state. */ 541 pci_conf_write(psc->psc_pc, psc->psc_tag, 542 psc->psc_pwrmgmt_csr_reg, (psc->psc_pwrmgmt_csr & 543 ~PCI_PMCSR_STATE_MASK) | PCI_PMCSR_STATE_D3); 544 } 545
Indexes created Thu Sep 25 08:09:54 GMT 2025