if_fxp_pci.c revision 1.75
1 /* $NetBSD: if_fxp_pci.c,v 1.75 2011/05/17 17:34:54 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * PCI bus front-end for the Intel i82557 fast Ethernet controller 35 * driver. Works with Intel Etherexpress Pro 10+, 100B, 100+ cards. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: if_fxp_pci.c,v 1.75 2011/05/17 17:34:54 dyoung Exp $"); 40 41 #include "rnd.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/mbuf.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #include <sys/socket.h> 49 #include <sys/ioctl.h> 50 #include <sys/errno.h> 51 #include <sys/device.h> 52 53 #if NRND > 0 54 #include <sys/rnd.h> 55 #endif 56 57 #include <machine/endian.h> 58 59 #include <net/if.h> 60 #include <net/if_dl.h> 61 #include <net/if_media.h> 62 #include <net/if_ether.h> 63 64 #include <sys/bus.h> 65 #include <sys/intr.h> 66 67 #include <dev/mii/miivar.h> 68 69 #include <dev/ic/i82557reg.h> 70 #include <dev/ic/i82557var.h> 71 72 #include <dev/pci/pcivar.h> 73 #include <dev/pci/pcireg.h> 74 #include <dev/pci/pcidevs.h> 75 76 struct fxp_pci_softc { 77 struct fxp_softc psc_fxp; 78 79 pci_chipset_tag_t psc_pc; /* pci chipset tag */ 80 pcireg_t psc_regs[0x20>>2]; /* saved PCI config regs (sparse) */ 81 pcitag_t psc_tag; /* pci register tag */ 82 83 struct pci_conf_state psc_pciconf; /* standard PCI configuration regs */ 84 }; 85 86 static int fxp_pci_match(device_t, cfdata_t, void *); 87 static void fxp_pci_attach(device_t, device_t, void *); 88 static int fxp_pci_detach(device_t, int); 89 90 static int fxp_pci_enable(struct fxp_softc *); 91 92 static void fxp_pci_confreg_restore(struct fxp_pci_softc *psc); 93 static bool fxp_pci_resume(device_t dv, const pmf_qual_t *); 94 95 CFATTACH_DECL3_NEW(fxp_pci, sizeof(struct fxp_pci_softc), 96 fxp_pci_match, fxp_pci_attach, fxp_pci_detach, NULL, NULL, 97 null_childdetached, DVF_DETACH_SHUTDOWN); 98 99 static const struct fxp_pci_product { 100 uint32_t fpp_prodid; /* PCI product ID */ 101 const char *fpp_name; /* device name */ 102 } fxp_pci_products[] = { 103 { PCI_PRODUCT_INTEL_82557, 104 "Intel i82557 Ethernet" }, 105 { PCI_PRODUCT_INTEL_82559ER, 106 "Intel i82559ER Ethernet" }, 107 { PCI_PRODUCT_INTEL_IN_BUSINESS, 108 "Intel InBusiness Ethernet" }, 109 { PCI_PRODUCT_INTEL_82801BA_LAN, 110 "Intel i82562 Ethernet" }, 111 { PCI_PRODUCT_INTEL_82801E_LAN_1, 112 "Intel i82801E Ethernet" }, 113 { PCI_PRODUCT_INTEL_82801E_LAN_2, 114 "Intel i82801E Ethernet" }, 115 { PCI_PRODUCT_INTEL_PRO_100_VE_0, 116 "Intel PRO/100 VE Network Controller" }, 117 { PCI_PRODUCT_INTEL_PRO_100_VE_1, 118 "Intel PRO/100 VE Network Controller" }, 119 { PCI_PRODUCT_INTEL_PRO_100_VE_2, 120 "Intel PRO/100 VE Network Controller with 82562ET/EZ PHY" }, 121 { PCI_PRODUCT_INTEL_PRO_100_VE_3, 122 "Intel PRO/100 VE Network Controller with 82562ET/EZ (CNR) PHY" }, 123 { PCI_PRODUCT_INTEL_PRO_100_VE_4, 124 "Intel PRO/100 VE (MOB) Network Controller" }, 125 { PCI_PRODUCT_INTEL_PRO_100_VE_5, 126 "Intel PRO/100 VE (LOM) Network Controller" }, 127 { PCI_PRODUCT_INTEL_PRO_100_VE_6, 128 "Intel PRO/100 VE Network Controller" }, 129 { PCI_PRODUCT_INTEL_PRO_100_VE_7, 130 "Intel PRO/100 VE Network Controller" }, 131 { PCI_PRODUCT_INTEL_PRO_100_VE_8, 132 "Intel PRO/100 VE Network Controller" }, 133 { PCI_PRODUCT_INTEL_PRO_100_VM_0, 134 "Intel PRO/100 VM Network Controller" }, 135 { PCI_PRODUCT_INTEL_PRO_100_VM_1, 136 "Intel PRO/100 VM Network Controller" }, 137 { PCI_PRODUCT_INTEL_PRO_100_VM_2, 138 "Intel PRO/100 VM Network Controller" }, 139 { PCI_PRODUCT_INTEL_PRO_100_VM_3, 140 "Intel PRO/100 VM Network Controller with 82562EM/EX PHY" }, 141 { PCI_PRODUCT_INTEL_PRO_100_VM_4, 142 "Intel PRO/100 VM Network Controller with 82562EM/EX (CNR) PHY" }, 143 { PCI_PRODUCT_INTEL_PRO_100_VM_5, 144 "Intel PRO/100 VM (MOB) Network Controller" }, 145 { PCI_PRODUCT_INTEL_PRO_100_VM_6, 146 "Intel PRO/100 VM Network Controller with 82562ET/EZ PHY" }, 147 { PCI_PRODUCT_INTEL_PRO_100_M, 148 "Intel PRO/100 M Network Controller" }, 149 { PCI_PRODUCT_INTEL_82801EB_LAN, 150 "Intel 82801EB/ER (ICH5) Network Controller" }, 151 { PCI_PRODUCT_INTEL_82801FB_LAN, 152 "Intel 82562EZ (ICH6)" }, 153 { PCI_PRODUCT_INTEL_82801G_LAN, 154 "Intel 82801GB/GR (ICH7) Network Controller" }, 155 { PCI_PRODUCT_INTEL_82801GB_LAN, 156 "Intel 82801GB 10/100 Network Controller" }, 157 { 0, 158 NULL }, 159 }; 160 161 static const struct fxp_pci_product * 162 fxp_pci_lookup(const struct pci_attach_args *pa) 163 { 164 const struct fxp_pci_product *fpp; 165 166 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 167 return (NULL); 168 169 for (fpp = fxp_pci_products; fpp->fpp_name != NULL; fpp++) 170 if (PCI_PRODUCT(pa->pa_id) == fpp->fpp_prodid) 171 return (fpp); 172 173 return (NULL); 174 } 175 176 static int 177 fxp_pci_match(device_t parent, cfdata_t match, void *aux) 178 { 179 struct pci_attach_args *pa = aux; 180 181 if (fxp_pci_lookup(pa) != NULL) 182 return (1); 183 184 return (0); 185 } 186 187 /* 188 * On resume : (XXX it is necessary with new pmf framework ?) 189 * Restore PCI configuration registers that may have been clobbered. 190 * This is necessary due to bugs on the Sony VAIO Z505-series on-board 191 * ethernet, after an APM suspend/resume, as well as after an ACPI 192 * D3->D0 transition. We call this function from a power hook after 193 * APM resume events, as well as after the ACPI D3->D0 transition. 194 */ 195 static void 196 fxp_pci_confreg_restore(struct fxp_pci_softc *psc) 197 { 198 pcireg_t reg; 199 200 #if 0 201 /* 202 * Check to see if the command register is blank -- if so, then 203 * we'll assume that all the clobberable-registers have been 204 * clobbered. 205 */ 206 207 /* 208 * In general, the above metric is accurate. Unfortunately, 209 * it is inaccurate across a hibernation. Ideally APM/ACPI 210 * code should take note of hibernation events and execute 211 * a hibernation wakeup hook, but at present a hibernation wake 212 * is indistinguishable from a suspend wake. 213 */ 214 215 if (((reg = pci_conf_read(psc->psc_pc, psc->psc_tag, 216 PCI_COMMAND_STATUS_REG)) & 0xffff) != 0) 217 return; 218 #else 219 reg = pci_conf_read(psc->psc_pc, psc->psc_tag, PCI_COMMAND_STATUS_REG); 220 #endif 221 222 pci_conf_write(psc->psc_pc, psc->psc_tag, 223 PCI_COMMAND_STATUS_REG, 224 (reg & 0xffff0000) | 225 (psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] & 0xffff)); 226 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_BHLC_REG, 227 psc->psc_regs[PCI_BHLC_REG>>2]); 228 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x0, 229 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2]); 230 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x4, 231 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2]); 232 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x8, 233 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2]); 234 } 235 236 static bool 237 fxp_pci_resume(device_t dv, const pmf_qual_t *qual) 238 { 239 struct fxp_pci_softc *psc = device_private(dv); 240 fxp_pci_confreg_restore(psc); 241 242 return true; 243 } 244 245 static int 246 fxp_pci_detach(device_t self, int flags) 247 { 248 struct fxp_pci_softc *psc = device_private(self); 249 struct fxp_softc *sc = &psc->psc_fxp; 250 int error; 251 252 /* Finish off the attach. */ 253 if ((error = fxp_detach(sc, flags)) != 0) 254 return error; 255 256 pmf_device_deregister(self); 257 258 pci_intr_disestablish(psc->psc_pc, sc->sc_ih); 259 260 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_size); 261 262 return 0; 263 } 264 265 static void 266 fxp_pci_attach(device_t parent, device_t self, void *aux) 267 { 268 struct fxp_pci_softc *psc = device_private(self); 269 struct fxp_softc *sc = &psc->psc_fxp; 270 const struct pci_attach_args *pa = aux; 271 pci_chipset_tag_t pc = pa->pa_pc; 272 pci_intr_handle_t ih; 273 const struct fxp_pci_product *fpp; 274 const char *chipname = NULL; 275 const char *intrstr = NULL; 276 bus_space_tag_t iot, memt; 277 bus_space_handle_t ioh, memh; 278 int ioh_valid, memh_valid; 279 bus_addr_t addr; 280 int flags; 281 int error; 282 283 sc->sc_dev = self; 284 285 aprint_naive(": Ethernet controller\n"); 286 287 /* 288 * Map control/status registers. 289 */ 290 ioh_valid = (pci_mapreg_map(pa, FXP_PCI_IOBA, 291 PCI_MAPREG_TYPE_IO, 0, 292 &iot, &ioh, NULL, NULL) == 0); 293 294 /* 295 * Version 2.1 of the PCI spec, page 196, "Address Maps": 296 * 297 * Prefetchable 298 * 299 * Set to one if there are no side effects on reads, the 300 * device returns all bytes regardless of the byte enables, 301 * and host bridges can merge processor writes into this 302 * range without causing errors. Bit must be set to zero 303 * otherwise. 304 * 305 * The 82557 incorrectly sets the "prefetchable" bit, resulting 306 * in errors on systems which will do merged reads and writes. 307 * These errors manifest themselves as all-bits-set when reading 308 * from the EEPROM or other < 4 byte registers. 309 * 310 * We must work around this problem by always forcing the mapping 311 * for memory space to be uncacheable. On systems which cannot 312 * create an uncacheable mapping (because the firmware mapped it 313 * into only cacheable/prefetchable space due to the "prefetchable" 314 * bit), we can fall back onto i/o mapped access. 315 */ 316 memh_valid = 0; 317 memt = pa->pa_memt; 318 if (((pa->pa_flags & PCI_FLAGS_MEM_OKAY) != 0) && 319 pci_mapreg_info(pa->pa_pc, pa->pa_tag, FXP_PCI_MMBA, 320 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 321 &addr, &sc->sc_size, &flags) == 0) { 322 flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 323 if (bus_space_map(memt, addr, sc->sc_size, flags, &memh) == 0) 324 memh_valid = 1; 325 } 326 327 if (memh_valid) { 328 sc->sc_st = memt; 329 sc->sc_sh = memh; 330 } else if (ioh_valid) { 331 sc->sc_st = iot; 332 sc->sc_sh = ioh; 333 } else { 334 aprint_error(": unable to map device registers\n"); 335 return; 336 } 337 338 sc->sc_dmat = pa->pa_dmat; 339 340 fpp = fxp_pci_lookup(pa); 341 if (fpp == NULL) { 342 printf("\n"); 343 panic("fxp_pci_attach: impossible"); 344 } 345 346 sc->sc_rev = PCI_REVISION(pa->pa_class); 347 348 switch (fpp->fpp_prodid) { 349 case PCI_PRODUCT_INTEL_82557: 350 case PCI_PRODUCT_INTEL_IN_BUSINESS: 351 352 if (sc->sc_rev >= FXP_REV_82558_A4) { 353 chipname = "i82558 Ethernet"; 354 sc->sc_flags |= FXPF_FC|FXPF_EXT_TXCB; 355 /* 356 * Enable the MWI command for memory writes. 357 */ 358 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 359 sc->sc_flags |= FXPF_MWI; 360 } 361 if (sc->sc_rev >= FXP_REV_82559_A0) { 362 chipname = "i82559 Ethernet"; 363 sc->sc_flags |= FXPF_82559_RXCSUM; 364 } 365 if (sc->sc_rev >= FXP_REV_82559S_A) 366 chipname = "i82559S Ethernet"; 367 if (sc->sc_rev >= FXP_REV_82550) { 368 chipname = "i82550 Ethernet"; 369 sc->sc_flags &= ~FXPF_82559_RXCSUM; 370 sc->sc_flags |= FXPF_EXT_RFA; 371 } 372 if (sc->sc_rev >= FXP_REV_82551) 373 chipname = "i82551 Ethernet"; 374 375 /* 376 * Mark all i82559 and i82550 revisions as having 377 * the "resume bug". See i82557.c for details. 378 */ 379 if (sc->sc_rev >= FXP_REV_82559_A0) 380 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 381 382 aprint_normal(": %s, rev %d\n", chipname != NULL ? chipname : 383 fpp->fpp_name, sc->sc_rev); 384 break; 385 386 case PCI_PRODUCT_INTEL_82559ER: 387 sc->sc_flags |= FXPF_FC|FXPF_EXT_TXCB; 388 389 /* 390 * i82559ER/82551ER don't support RX hardware checksumming 391 * even though it has a newer revision number than 82559_A0. 392 */ 393 394 /* All i82559 have the "resume bug". */ 395 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 396 397 /* Enable the MWI command for memory writes. */ 398 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 399 sc->sc_flags |= FXPF_MWI; 400 401 if (sc->sc_rev >= FXP_REV_82551) 402 chipname = "Intel i82551ER Ethernet"; 403 404 aprint_normal(": %s, rev %d\n", chipname != NULL ? chipname : 405 fpp->fpp_name, sc->sc_rev); 406 break; 407 408 case PCI_PRODUCT_INTEL_82801BA_LAN: 409 case PCI_PRODUCT_INTEL_PRO_100_VE_0: 410 case PCI_PRODUCT_INTEL_PRO_100_VE_1: 411 case PCI_PRODUCT_INTEL_PRO_100_VM_0: 412 case PCI_PRODUCT_INTEL_PRO_100_VM_1: 413 case PCI_PRODUCT_INTEL_82562EH_HPNA_0: 414 case PCI_PRODUCT_INTEL_82562EH_HPNA_1: 415 case PCI_PRODUCT_INTEL_82562EH_HPNA_2: 416 case PCI_PRODUCT_INTEL_PRO_100_VM_2: 417 /* 418 * The ICH-2 and ICH-3 have the "resume bug". 419 */ 420 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 421 /* FALLTHROUGH */ 422 423 default: 424 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 425 if (sc->sc_rev >= FXP_REV_82558_A4) 426 sc->sc_flags |= FXPF_FC|FXPF_EXT_TXCB; 427 if (sc->sc_rev >= FXP_REV_82559_A0) 428 sc->sc_flags |= FXPF_82559_RXCSUM; 429 430 break; 431 } 432 433 /* Make sure bus-mastering is enabled. */ 434 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 435 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 436 PCI_COMMAND_MASTER_ENABLE); 437 438 /* 439 * Under some circumstances (such as APM suspend/resume 440 * cycles, and across ACPI power state changes), the 441 * i82257-family can lose the contents of critical PCI 442 * configuration registers, causing the card to be 443 * non-responsive and useless. This occurs on the Sony VAIO 444 * Z505-series, among others. Preserve them here so they can 445 * be later restored (by fxp_pci_confreg_restore()). 446 */ 447 psc->psc_pc = pc; 448 psc->psc_tag = pa->pa_tag; 449 psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] = 450 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 451 psc->psc_regs[PCI_BHLC_REG>>2] = 452 pci_conf_read(pc, pa->pa_tag, PCI_BHLC_REG); 453 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2] = 454 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x0); 455 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2] = 456 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x4); 457 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2] = 458 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x8); 459 460 /* power up chip */ 461 switch ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 462 pci_activate_null))) { 463 case EOPNOTSUPP: 464 break; 465 case 0: 466 sc->sc_enable = fxp_pci_enable; 467 sc->sc_disable = NULL; 468 break; 469 default: 470 aprint_error_dev(self, "cannot activate %d\n", error); 471 return; 472 } 473 474 /* Restore PCI configuration registers. */ 475 fxp_pci_confreg_restore(psc); 476 477 sc->sc_enabled = 1; 478 479 /* 480 * Map and establish our interrupt. 481 */ 482 if (pci_intr_map(pa, &ih)) { 483 aprint_error_dev(self, "couldn't map interrupt\n"); 484 return; 485 } 486 intrstr = pci_intr_string(pc, ih); 487 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, fxp_intr, sc); 488 if (sc->sc_ih == NULL) { 489 aprint_error_dev(self, "couldn't establish interrupt"); 490 if (intrstr != NULL) 491 aprint_error(" at %s", intrstr); 492 aprint_error("\n"); 493 return; 494 } 495 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 496 497 /* Finish off the attach. */ 498 fxp_attach(sc); 499 if (sc->sc_disable != NULL) 500 fxp_disable(sc); 501 502 /* Add a suspend hook to restore PCI config state */ 503 if (pmf_device_register(self, NULL, fxp_pci_resume)) 504 pmf_class_network_register(self, &sc->sc_ethercom.ec_if); 505 else 506 aprint_error_dev(self, "couldn't establish power handler\n"); 507 } 508 509 static int 510 fxp_pci_enable(struct fxp_softc *sc) 511 { 512 struct fxp_pci_softc *psc = (void *) sc; 513 514 #if 0 515 printf("%s: going to power state D0\n", device_xname(self)); 516 #endif 517 518 /* Now restore the configuration registers. */ 519 fxp_pci_confreg_restore(psc); 520 521 return (0); 522 } 523
Indexes created Wed Sep 24 14:09:57 GMT 2025