if_fxp_pci.c revision 1.8.4.3
1 /* $NetBSD: if_fxp_pci.c,v 1.8.4.3 2001/08/16 17:37:40 tv Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * PCI bus front-end for the Intel i82557 fast Ethernet controller 42 * driver. Works with Intel Etherexpress Pro 10+, 100B, 100+ cards. 43 */ 44 45 #include "opt_inet.h" 46 #include "opt_ns.h" 47 #include "bpfilter.h" 48 #include "rnd.h" 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/mbuf.h> 53 #include <sys/malloc.h> 54 #include <sys/kernel.h> 55 #include <sys/socket.h> 56 #include <sys/ioctl.h> 57 #include <sys/errno.h> 58 #include <sys/device.h> 59 60 #if NRND > 0 61 #include <sys/rnd.h> 62 #endif 63 64 #include <machine/endian.h> 65 66 #include <net/if.h> 67 #include <net/if_dl.h> 68 #include <net/if_media.h> 69 #include <net/if_ether.h> 70 71 #if NBPFILTER > 0 72 #include <net/bpf.h> 73 #endif 74 75 #ifdef INET 76 #include <netinet/in.h> 77 #include <netinet/if_inarp.h> 78 #endif 79 80 #ifdef NS 81 #include <netns/ns.h> 82 #include <netns/ns_if.h> 83 #endif 84 85 #include <machine/bus.h> 86 #include <machine/intr.h> 87 88 #include <dev/mii/miivar.h> 89 90 #include <dev/ic/i82557reg.h> 91 #include <dev/ic/i82557var.h> 92 93 #include <dev/pci/pcivar.h> 94 #include <dev/pci/pcireg.h> 95 #include <dev/pci/pcidevs.h> 96 97 struct fxp_pci_softc { 98 struct fxp_softc psc_fxp; 99 100 pci_chipset_tag_t psc_pc; /* pci chipset tag */ 101 pcireg_t psc_regs[0x20>>2]; /* saved PCI config regs (sparse) */ 102 pcitag_t psc_tag; /* pci register tag */ 103 void *psc_powerhook; /* power hook */ 104 105 int psc_pwrmgmt_csr_reg; /* ACPI power management register */ 106 pcireg_t psc_pwrmgmt_csr; /* ...and the contents at D0 */ 107 }; 108 109 int fxp_pci_match __P((struct device *, struct cfdata *, void *)); 110 void fxp_pci_attach __P((struct device *, struct device *, void *)); 111 112 int fxp_pci_enable __P((struct fxp_softc *)); 113 void fxp_pci_disable __P((struct fxp_softc *)); 114 115 static void fxp_pci_confreg_restore __P((struct fxp_pci_softc *psc)); 116 static void fxp_pci_power __P((int why, void *arg)); 117 118 struct cfattach fxp_pci_ca = { 119 sizeof(struct fxp_pci_softc), fxp_pci_match, fxp_pci_attach 120 }; 121 122 const struct fxp_pci_product { 123 u_int32_t fpp_prodid; /* PCI product ID */ 124 const char *fpp_name; /* device name */ 125 } fxp_pci_products[] = { 126 { PCI_PRODUCT_INTEL_82557, 127 "Intel i82557 Ethernet" }, 128 { PCI_PRODUCT_INTEL_82559ER, 129 "Intel i82559ER Ethernet" }, 130 { PCI_PRODUCT_INTEL_IN_BUSINESS, 131 "Intel InBusiness Ethernet" }, 132 { PCI_PRODUCT_INTEL_82801BA_LAN, 133 "Intel i82562 Ethernet" }, 134 { 0, 135 NULL }, 136 }; 137 138 const struct fxp_pci_product *fxp_pci_lookup 139 __P((const struct pci_attach_args *)); 140 141 const struct fxp_pci_product * 142 fxp_pci_lookup(pa) 143 const struct pci_attach_args *pa; 144 { 145 const struct fxp_pci_product *fpp; 146 147 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 148 return (NULL); 149 150 for (fpp = fxp_pci_products; fpp->fpp_name != NULL; fpp++) 151 if (PCI_PRODUCT(pa->pa_id) == fpp->fpp_prodid) 152 return (fpp); 153 154 return (NULL); 155 } 156 157 int 158 fxp_pci_match(parent, match, aux) 159 struct device *parent; 160 struct cfdata *match; 161 void *aux; 162 { 163 struct pci_attach_args *pa = aux; 164 165 if (fxp_pci_lookup(pa) != NULL) 166 return (1); 167 168 return (0); 169 } 170 171 /* 172 * Restore PCI configuration registers that may have been clobbered. 173 * This is necessary due to bugs on the Sony VAIO Z505-series on-board 174 * ethernet, after an APM suspend/resume, as well as after an ACPI 175 * D3->D0 transition. We call this function from a power hook after 176 * APM resume events, as well as after the ACPI D3->D0 transition. 177 */ 178 static void 179 fxp_pci_confreg_restore(psc) 180 struct fxp_pci_softc *psc; 181 { 182 pcireg_t reg; 183 184 #if 0 185 /* 186 * Check to see if the command register is blank -- if so, then 187 * we'll assume that all the clobberable-registers have been 188 * clobbered. 189 */ 190 191 /* 192 * In general, the above metric is accurate. Unfortunately, 193 * it is inaccurate across a hibernation. Ideally APM/ACPI 194 * code should take note of hibernation events and execute 195 * a hibernation wakeup hook, but at present a hibernation wake 196 * is indistinguishable from a suspend wake. 197 */ 198 199 if (((reg = pci_conf_read(psc->psc_pc, psc->psc_tag, 200 PCI_COMMAND_STATUS_REG)) & 0xffff) != 0) 201 return; 202 #else 203 reg = pci_conf_read(psc->psc_pc, psc->psc_tag, PCI_COMMAND_STATUS_REG); 204 #endif 205 206 pci_conf_write(psc->psc_pc, psc->psc_tag, 207 PCI_COMMAND_STATUS_REG, 208 (reg & 0xffff0000) | 209 (psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] & 0xffff)); 210 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_BHLC_REG, 211 psc->psc_regs[PCI_BHLC_REG>>2]); 212 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x0, 213 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2]); 214 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x4, 215 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2]); 216 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x8, 217 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2]); 218 } 219 220 221 /* 222 * Power handler routine. Called when the system is transitioning into/out 223 * of power save modes. We restore the (bashed) PCI configuration registers 224 * on a resume. 225 */ 226 static void 227 fxp_pci_power(why, arg) 228 int why; 229 void *arg; 230 { 231 struct fxp_pci_softc *psc = arg; 232 233 if (why == PWR_RESUME) 234 fxp_pci_confreg_restore(psc); 235 236 } 237 238 239 void 240 fxp_pci_attach(parent, self, aux) 241 struct device *parent, *self; 242 void *aux; 243 { 244 struct fxp_pci_softc *psc = (struct fxp_pci_softc *)self; 245 struct fxp_softc *sc = (struct fxp_softc *)self; 246 struct pci_attach_args *pa = aux; 247 pci_chipset_tag_t pc = pa->pa_pc; 248 pci_intr_handle_t ih; 249 const struct fxp_pci_product *fpp; 250 const char *intrstr = NULL; 251 bus_space_tag_t iot, memt; 252 bus_space_handle_t ioh, memh; 253 int ioh_valid, memh_valid; 254 bus_addr_t addr; 255 bus_size_t size; 256 int flags; 257 int pci_pwrmgmt_cap_reg; 258 259 /* 260 * Map control/status registers. 261 */ 262 ioh_valid = (pci_mapreg_map(pa, FXP_PCI_IOBA, 263 PCI_MAPREG_TYPE_IO, 0, 264 &iot, &ioh, NULL, NULL) == 0); 265 266 /* 267 * Version 2.1 of the PCI spec, page 196, "Address Maps": 268 * 269 * Prefetchable 270 * 271 * Set to one if there are no side effects on reads, the 272 * device returns all bytes regardless of the byte enables, 273 * and host bridges can merge processor writes into this 274 * range without causing errors. Bit must be set to zero 275 * otherwise. 276 * 277 * The 82557 incorrectly sets the "prefetchable" bit, resulting 278 * in errors on systems which will do merged reads and writes. 279 * These errors manifest themselves as all-bits-set when reading 280 * from the EEPROM or other < 4 byte registers. 281 * 282 * We must work around this problem by always forcing the mapping 283 * for memory space to be uncacheable. On systems which cannot 284 * create an uncacheable mapping (because the firmware mapped it 285 * into only cacheable/prefetchable space due to the "prefetchable" 286 * bit), we can fall back onto i/o mapped access. 287 */ 288 memh_valid = 0; 289 memt = pa->pa_memt; 290 if (((pa->pa_flags & PCI_FLAGS_MEM_ENABLED) != 0) && 291 pci_mapreg_info(pa->pa_pc, pa->pa_tag, FXP_PCI_MMBA, 292 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 293 &addr, &size, &flags) == 0) { 294 flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 295 if (bus_space_map(memt, addr, size, flags, &memh) == 0) 296 memh_valid = 1; 297 } 298 299 if (memh_valid) { 300 sc->sc_st = memt; 301 sc->sc_sh = memh; 302 } else if (ioh_valid) { 303 sc->sc_st = iot; 304 sc->sc_sh = ioh; 305 } else { 306 printf(": unable to map device registers\n"); 307 return; 308 } 309 310 sc->sc_dmat = pa->pa_dmat; 311 312 fpp = fxp_pci_lookup(pa); 313 if (fpp == NULL) { 314 printf("\n"); 315 panic("fxp_pci_attach: impossible"); 316 } 317 318 /* 319 * XXX Perhaps report '557, '558, '559 based on revision? 320 */ 321 printf(": %s, rev %d\n", fpp->fpp_name, PCI_REVISION(pa->pa_class)); 322 323 /* Make sure bus-mastering is enabled. */ 324 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 325 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 326 PCI_COMMAND_MASTER_ENABLE); 327 328 /* 329 * Under some circumstances (such as APM suspend/resume 330 * cycles, and across ACPI power state changes), the 331 * i82257-family can lose the contents of critical PCI 332 * configuration registers, causing the card to be 333 * non-responsive and useless. This occurs on the Sony VAIO 334 * Z505-series, among others. Preserve them here so they can 335 * be later restored (by fxp_pci_confreg_restore()). 336 */ 337 psc->psc_pc = pc; 338 psc->psc_tag = pa->pa_tag; 339 psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] = 340 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 341 psc->psc_regs[PCI_BHLC_REG>>2] = 342 pci_conf_read(pc, pa->pa_tag, PCI_BHLC_REG); 343 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2] = 344 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x0); 345 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2] = 346 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x4); 347 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2] = 348 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x8); 349 350 /* 351 * Work around BIOS ACPI bugs where the chip is inadvertantly 352 * left in ACPI D3 (lowest power state). First confirm the device 353 * supports ACPI power management, then move it to the D0 (fully 354 * functional) state if it is not already there. 355 */ 356 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 357 &pci_pwrmgmt_cap_reg, 0)) { 358 pcireg_t reg; 359 360 sc->sc_enable = fxp_pci_enable; 361 sc->sc_disable = fxp_pci_disable; 362 363 psc->psc_pwrmgmt_csr_reg = pci_pwrmgmt_cap_reg + 4; 364 reg = pci_conf_read(pc, pa->pa_tag, psc->psc_pwrmgmt_csr_reg); 365 psc->psc_pwrmgmt_csr = (reg & ~PCI_PMCSR_STATE_MASK) | 366 PCI_PMCSR_STATE_D0; 367 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0) 368 pci_conf_write(pc, pa->pa_tag, psc->psc_pwrmgmt_csr_reg, 369 psc->psc_pwrmgmt_csr); 370 } 371 /* Restore PCI configuration registers. */ 372 fxp_pci_confreg_restore(psc); 373 374 sc->sc_enabled = 1; 375 376 /* 377 * Map and establish our interrupt. 378 */ 379 if (pci_intr_map(pc, pa->pa_intrtag, pa->pa_intrpin, 380 pa->pa_intrline, &ih)) { 381 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 382 return; 383 } 384 intrstr = pci_intr_string(pc, ih); 385 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, fxp_intr, sc); 386 if (sc->sc_ih == NULL) { 387 printf("%s: couldn't establish interrupt", 388 sc->sc_dev.dv_xname); 389 if (intrstr != NULL) 390 printf(" at %s", intrstr); 391 printf("\n"); 392 return; 393 } 394 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 395 396 /* Finish off the attach. */ 397 fxp_attach(sc); 398 if (sc->sc_disable != NULL) 399 fxp_disable(sc); 400 401 /* Add a suspend hook to restore PCI config state */ 402 psc->psc_powerhook = powerhook_establish(fxp_pci_power, psc); 403 if (psc->psc_powerhook == NULL) 404 printf ("%s: WARNING: unable to establish pci power hook\n", 405 sc->sc_dev.dv_xname); 406 } 407 408 int 409 fxp_pci_enable(struct fxp_softc *sc) 410 { 411 struct fxp_pci_softc *psc = (void *) sc; 412 413 #if 0 414 printf("%s: going to power state D0\n", sc->sc_dev.dv_xname); 415 #endif 416 417 /* Bring the device into D0 power state. */ 418 pci_conf_write(psc->psc_pc, psc->psc_tag, 419 psc->psc_pwrmgmt_csr_reg, psc->psc_pwrmgmt_csr); 420 421 /* Now restore the configuration registers. */ 422 fxp_pci_confreg_restore(psc); 423 424 return (0); 425 } 426 427 void 428 fxp_pci_disable(struct fxp_softc *sc) 429 { 430 struct fxp_pci_softc *psc = (void *) sc; 431 432 #if 0 433 printf("%s: going to power state D3\n", sc->sc_dev.dv_xname); 434 #endif 435 436 /* Put the device into D3 state. */ 437 pci_conf_write(psc->psc_pc, psc->psc_tag, 438 psc->psc_pwrmgmt_csr_reg, (psc->psc_pwrmgmt_csr & 439 ~PCI_PMCSR_STATE_MASK) | PCI_PMCSR_STATE_D3); 440 } 441
Indexes created Thu Oct 02 01:09:59 GMT 2025