if_fxp_pci.c revision 1.80.4.1
1 /* $NetBSD: if_fxp_pci.c,v 1.80.4.1 2014/05/18 17:45:40 rmind Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * PCI bus front-end for the Intel i82557 fast Ethernet controller 35 * driver. Works with Intel Etherexpress Pro 10+, 100B, 100+ cards. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: if_fxp_pci.c,v 1.80.4.1 2014/05/18 17:45:40 rmind Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/mbuf.h> 44 #include <sys/malloc.h> 45 #include <sys/kernel.h> 46 #include <sys/socket.h> 47 #include <sys/ioctl.h> 48 #include <sys/errno.h> 49 #include <sys/device.h> 50 51 #include <sys/rnd.h> 52 53 #include <machine/endian.h> 54 55 #include <net/if.h> 56 #include <net/if_dl.h> 57 #include <net/if_media.h> 58 #include <net/if_ether.h> 59 60 #include <sys/bus.h> 61 #include <sys/intr.h> 62 63 #include <dev/mii/miivar.h> 64 65 #include <dev/ic/i82557reg.h> 66 #include <dev/ic/i82557var.h> 67 68 #include <dev/pci/pcivar.h> 69 #include <dev/pci/pcireg.h> 70 #include <dev/pci/pcidevs.h> 71 72 struct fxp_pci_softc { 73 struct fxp_softc psc_fxp; 74 75 pci_chipset_tag_t psc_pc; /* pci chipset tag */ 76 pcireg_t psc_regs[0x20>>2]; /* saved PCI config regs (sparse) */ 77 pcitag_t psc_tag; /* pci register tag */ 78 79 struct pci_conf_state psc_pciconf; /* standard PCI configuration regs */ 80 }; 81 82 static int fxp_pci_match(device_t, cfdata_t, void *); 83 static void fxp_pci_attach(device_t, device_t, void *); 84 static int fxp_pci_detach(device_t, int); 85 86 static int fxp_pci_enable(struct fxp_softc *); 87 88 static void fxp_pci_confreg_restore(struct fxp_pci_softc *psc); 89 static bool fxp_pci_resume(device_t dv, const pmf_qual_t *); 90 91 CFATTACH_DECL3_NEW(fxp_pci, sizeof(struct fxp_pci_softc), 92 fxp_pci_match, fxp_pci_attach, fxp_pci_detach, NULL, NULL, 93 null_childdetached, DVF_DETACH_SHUTDOWN); 94 95 static const struct fxp_pci_product { 96 uint32_t fpp_prodid; /* PCI product ID */ 97 const char *fpp_name; /* device name */ 98 } fxp_pci_products[] = { 99 { PCI_PRODUCT_INTEL_82552, 100 "Intel i82552 10/100 Network Connection" }, 101 { PCI_PRODUCT_INTEL_8255X, 102 "Intel i8255x Ethernet" }, 103 { PCI_PRODUCT_INTEL_82559ER, 104 "Intel i82559ER Ethernet" }, 105 { PCI_PRODUCT_INTEL_IN_BUSINESS, 106 "Intel InBusiness Ethernet" }, 107 { PCI_PRODUCT_INTEL_PRO_100, 108 "Intel PRO/100 Ethernet" }, 109 { PCI_PRODUCT_INTEL_PRO_100_VE_0, 110 "Intel PRO/100 VE Network Controller" }, 111 { PCI_PRODUCT_INTEL_PRO_100_VE_1, 112 "Intel PRO/100 VE Network Controller" }, 113 { PCI_PRODUCT_INTEL_PRO_100_VE_2, 114 "Intel PRO/100 VE Network Controller with 82562ET/EZ PHY" }, 115 { PCI_PRODUCT_INTEL_PRO_100_VE_3, 116 "Intel PRO/100 VE Network Controller with 82562ET/EZ (CNR) PHY" }, 117 { PCI_PRODUCT_INTEL_PRO_100_VE_4, 118 "Intel PRO/100 VE (MOB) Network Controller" }, 119 { PCI_PRODUCT_INTEL_PRO_100_VE_5, 120 "Intel PRO/100 VE (LOM) Network Controller" }, 121 { PCI_PRODUCT_INTEL_PRO_100_VE_6, 122 "Intel PRO/100 VE Network Controller" }, 123 { PCI_PRODUCT_INTEL_PRO_100_VE_7, 124 "Intel PRO/100 VE Network Controller" }, 125 { PCI_PRODUCT_INTEL_PRO_100_VE_8, 126 "Intel PRO/100 VE Network Controller" }, 127 { PCI_PRODUCT_INTEL_PRO_100_VE_9, 128 "Intel PRO/100 VE Network Controller" }, 129 { PCI_PRODUCT_INTEL_PRO_100_VE_10, 130 "Intel PRO/100 VE Network Controller" }, 131 { PCI_PRODUCT_INTEL_PRO_100_VE_11, 132 "Intel PRO/100 VE Network Controller" }, 133 { PCI_PRODUCT_INTEL_PRO_100_VM_0, 134 "Intel PRO/100 VM Network Controller" }, 135 { PCI_PRODUCT_INTEL_PRO_100_VM_1, 136 "Intel PRO/100 VM Network Controller" }, 137 { PCI_PRODUCT_INTEL_PRO_100_VM_2, 138 "Intel PRO/100 VM Network Controller" }, 139 { PCI_PRODUCT_INTEL_PRO_100_VM_3, 140 "Intel PRO/100 VM Network Controller with 82562EM/EX PHY" }, 141 { PCI_PRODUCT_INTEL_PRO_100_VM_4, 142 "Intel PRO/100 VM Network Controller with 82562EM/EX (CNR) PHY" }, 143 { PCI_PRODUCT_INTEL_PRO_100_VM_5, 144 "Intel PRO/100 VM (MOB) Network Controller" }, 145 { PCI_PRODUCT_INTEL_PRO_100_VM_6, 146 "Intel PRO/100 VM Network Controller with 82562ET/EZ PHY" }, 147 { PCI_PRODUCT_INTEL_PRO_100_VM_7, 148 "Intel PRO/100 VM Network Connection" }, 149 { PCI_PRODUCT_INTEL_PRO_100_VM_8, 150 "Intel PRO/100 VM Network Connection" }, 151 { PCI_PRODUCT_INTEL_PRO_100_VM_9, 152 "Intel PRO/100 VM Network Connection" }, 153 { PCI_PRODUCT_INTEL_PRO_100_VM_10, 154 "Intel PRO/100 VM Network Connection" }, 155 { PCI_PRODUCT_INTEL_PRO_100_VM_11, 156 "Intel PRO/100 VM Network Connection" }, 157 { PCI_PRODUCT_INTEL_PRO_100_VM_12, 158 "Intel PRO/100 VM Network Connection" }, 159 { PCI_PRODUCT_INTEL_PRO_100_VM_13, 160 "Intel PRO/100 VM Network Connection" }, 161 { PCI_PRODUCT_INTEL_PRO_100_VM_14, 162 "Intel PRO/100 VM Network Connection" }, 163 { PCI_PRODUCT_INTEL_PRO_100_VM_15, 164 "Intel PRO/100 VM Network Connection" }, 165 { PCI_PRODUCT_INTEL_PRO_100_VM_16, 166 "Intel PRO/100 VM Network Connection" }, 167 { PCI_PRODUCT_INTEL_PRO_100_M, 168 "Intel PRO/100 M Network Controller" }, 169 { PCI_PRODUCT_INTEL_82801BA_LAN, 170 "Intel i82562 Ethernet" }, 171 { PCI_PRODUCT_INTEL_82801E_LAN_1, 172 "Intel i82801E Ethernet" }, 173 { PCI_PRODUCT_INTEL_82801E_LAN_2, 174 "Intel i82801E Ethernet" }, 175 { PCI_PRODUCT_INTEL_82801EB_LAN, 176 "Intel 82801EB/ER (ICH5) Network Controller" }, 177 { PCI_PRODUCT_INTEL_82801FB_LAN, 178 "Intel i82801FB LAN Controller" }, 179 { PCI_PRODUCT_INTEL_82801FB_LAN_2, 180 "Intel i82801FB LAN Controller" }, 181 { PCI_PRODUCT_INTEL_82801G_LAN, 182 "Intel 82801GB/GR (ICH7) Network Controller" }, 183 { PCI_PRODUCT_INTEL_82801GB_LAN, 184 "Intel 82801GB 10/100 Network Controller" }, 185 { 0, 186 NULL }, 187 }; 188 189 static const struct fxp_pci_product * 190 fxp_pci_lookup(const struct pci_attach_args *pa) 191 { 192 const struct fxp_pci_product *fpp; 193 194 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 195 return (NULL); 196 197 for (fpp = fxp_pci_products; fpp->fpp_name != NULL; fpp++) 198 if (PCI_PRODUCT(pa->pa_id) == fpp->fpp_prodid) 199 return (fpp); 200 201 return (NULL); 202 } 203 204 static int 205 fxp_pci_match(device_t parent, cfdata_t match, void *aux) 206 { 207 struct pci_attach_args *pa = aux; 208 209 if (fxp_pci_lookup(pa) != NULL) 210 return (1); 211 212 return (0); 213 } 214 215 /* 216 * On resume : (XXX it is necessary with new pmf framework ?) 217 * Restore PCI configuration registers that may have been clobbered. 218 * This is necessary due to bugs on the Sony VAIO Z505-series on-board 219 * ethernet, after an APM suspend/resume, as well as after an ACPI 220 * D3->D0 transition. We call this function from a power hook after 221 * APM resume events, as well as after the ACPI D3->D0 transition. 222 */ 223 static void 224 fxp_pci_confreg_restore(struct fxp_pci_softc *psc) 225 { 226 pcireg_t reg; 227 228 #if 0 229 /* 230 * Check to see if the command register is blank -- if so, then 231 * we'll assume that all the clobberable-registers have been 232 * clobbered. 233 */ 234 235 /* 236 * In general, the above metric is accurate. Unfortunately, 237 * it is inaccurate across a hibernation. Ideally APM/ACPI 238 * code should take note of hibernation events and execute 239 * a hibernation wakeup hook, but at present a hibernation wake 240 * is indistinguishable from a suspend wake. 241 */ 242 243 if (((reg = pci_conf_read(psc->psc_pc, psc->psc_tag, 244 PCI_COMMAND_STATUS_REG)) & 0xffff) != 0) 245 return; 246 #else 247 reg = pci_conf_read(psc->psc_pc, psc->psc_tag, PCI_COMMAND_STATUS_REG); 248 #endif 249 250 pci_conf_write(psc->psc_pc, psc->psc_tag, 251 PCI_COMMAND_STATUS_REG, 252 (reg & 0xffff0000) | 253 (psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] & 0xffff)); 254 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_BHLC_REG, 255 psc->psc_regs[PCI_BHLC_REG>>2]); 256 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x0, 257 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2]); 258 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x4, 259 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2]); 260 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x8, 261 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2]); 262 } 263 264 static bool 265 fxp_pci_resume(device_t dv, const pmf_qual_t *qual) 266 { 267 struct fxp_pci_softc *psc = device_private(dv); 268 fxp_pci_confreg_restore(psc); 269 270 return true; 271 } 272 273 static int 274 fxp_pci_detach(device_t self, int flags) 275 { 276 struct fxp_pci_softc *psc = device_private(self); 277 struct fxp_softc *sc = &psc->psc_fxp; 278 int error; 279 280 /* Finish off the attach. */ 281 if ((error = fxp_detach(sc, flags)) != 0) 282 return error; 283 284 pmf_device_deregister(self); 285 286 pci_intr_disestablish(psc->psc_pc, sc->sc_ih); 287 288 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_size); 289 290 return 0; 291 } 292 293 static void 294 fxp_pci_attach(device_t parent, device_t self, void *aux) 295 { 296 struct fxp_pci_softc *psc = device_private(self); 297 struct fxp_softc *sc = &psc->psc_fxp; 298 const struct pci_attach_args *pa = aux; 299 pci_chipset_tag_t pc = pa->pa_pc; 300 pci_intr_handle_t ih; 301 const struct fxp_pci_product *fpp; 302 const char *chipname = NULL; 303 const char *intrstr = NULL; 304 bus_space_tag_t iot, memt; 305 bus_space_handle_t ioh, memh; 306 int ioh_valid, memh_valid; 307 bus_addr_t addr; 308 int flags; 309 int error; 310 char intrbuf[PCI_INTRSTR_LEN]; 311 312 sc->sc_dev = self; 313 314 /* 315 * Map control/status registers. 316 */ 317 ioh_valid = (pci_mapreg_map(pa, FXP_PCI_IOBA, 318 PCI_MAPREG_TYPE_IO, 0, 319 &iot, &ioh, NULL, NULL) == 0); 320 321 /* 322 * Version 2.1 of the PCI spec, page 196, "Address Maps": 323 * 324 * Prefetchable 325 * 326 * Set to one if there are no side effects on reads, the 327 * device returns all bytes regardless of the byte enables, 328 * and host bridges can merge processor writes into this 329 * range without causing errors. Bit must be set to zero 330 * otherwise. 331 * 332 * The 82557 incorrectly sets the "prefetchable" bit, resulting 333 * in errors on systems which will do merged reads and writes. 334 * These errors manifest themselves as all-bits-set when reading 335 * from the EEPROM or other < 4 byte registers. 336 * 337 * We must work around this problem by always forcing the mapping 338 * for memory space to be uncacheable. On systems which cannot 339 * create an uncacheable mapping (because the firmware mapped it 340 * into only cacheable/prefetchable space due to the "prefetchable" 341 * bit), we can fall back onto i/o mapped access. 342 */ 343 memh_valid = 0; 344 memt = pa->pa_memt; 345 if (((pa->pa_flags & PCI_FLAGS_MEM_OKAY) != 0) && 346 pci_mapreg_info(pa->pa_pc, pa->pa_tag, FXP_PCI_MMBA, 347 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 348 &addr, &sc->sc_size, &flags) == 0) { 349 flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 350 if (bus_space_map(memt, addr, sc->sc_size, flags, &memh) == 0) 351 memh_valid = 1; 352 } 353 354 if (memh_valid) { 355 sc->sc_st = memt; 356 sc->sc_sh = memh; 357 } else if (ioh_valid) { 358 sc->sc_st = iot; 359 sc->sc_sh = ioh; 360 } else { 361 aprint_error(": unable to map device registers\n"); 362 return; 363 } 364 365 sc->sc_dmat = pa->pa_dmat; 366 367 fpp = fxp_pci_lookup(pa); 368 if (fpp == NULL) { 369 printf("\n"); 370 panic("fxp_pci_attach: impossible"); 371 } 372 373 sc->sc_rev = PCI_REVISION(pa->pa_class); 374 375 switch (fpp->fpp_prodid) { 376 case PCI_PRODUCT_INTEL_8255X: 377 case PCI_PRODUCT_INTEL_IN_BUSINESS: 378 379 if (sc->sc_rev >= FXP_REV_82558_A4) { 380 chipname = "i82558 Ethernet"; 381 sc->sc_flags |= FXPF_FC|FXPF_EXT_TXCB; 382 /* 383 * Enable the MWI command for memory writes. 384 */ 385 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 386 sc->sc_flags |= FXPF_MWI; 387 } 388 if (sc->sc_rev >= FXP_REV_82559_A0) { 389 chipname = "i82559 Ethernet"; 390 sc->sc_flags |= FXPF_82559_RXCSUM; 391 } 392 if (sc->sc_rev >= FXP_REV_82559S_A) 393 chipname = "i82559S Ethernet"; 394 if (sc->sc_rev >= FXP_REV_82550) { 395 chipname = "i82550 Ethernet"; 396 sc->sc_flags &= ~FXPF_82559_RXCSUM; 397 sc->sc_flags |= FXPF_EXT_RFA; 398 } 399 if (sc->sc_rev >= FXP_REV_82551_E) 400 chipname = "i82551 Ethernet"; 401 402 /* 403 * Mark all i82559 and i82550 revisions as having 404 * the "resume bug". See i82557.c for details. 405 */ 406 if (sc->sc_rev >= FXP_REV_82559_A0) 407 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 408 409 break; 410 411 case PCI_PRODUCT_INTEL_82559ER: 412 sc->sc_flags |= FXPF_FC|FXPF_EXT_TXCB; 413 414 /* 415 * i82559ER/82551ER don't support RX hardware checksumming 416 * even though it has a newer revision number than 82559_A0. 417 */ 418 419 /* All i82559 have the "resume bug". */ 420 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 421 422 /* Enable the MWI command for memory writes. */ 423 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 424 sc->sc_flags |= FXPF_MWI; 425 426 if (sc->sc_rev >= FXP_REV_82551_E) 427 chipname = "Intel i82551ER Ethernet"; 428 429 break; 430 431 case PCI_PRODUCT_INTEL_82801BA_LAN: 432 case PCI_PRODUCT_INTEL_PRO_100_VE_0: 433 case PCI_PRODUCT_INTEL_PRO_100_VE_1: 434 case PCI_PRODUCT_INTEL_PRO_100_VM_0: 435 case PCI_PRODUCT_INTEL_PRO_100_VM_1: 436 case PCI_PRODUCT_INTEL_82562EH_HPNA_0: 437 case PCI_PRODUCT_INTEL_82562EH_HPNA_1: 438 case PCI_PRODUCT_INTEL_82562EH_HPNA_2: 439 case PCI_PRODUCT_INTEL_PRO_100_VM_2: 440 /* 441 * The ICH-2 and ICH-3 have the "resume bug". 442 */ 443 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 444 /* FALLTHROUGH */ 445 446 default: 447 if (sc->sc_rev >= FXP_REV_82558_A4) 448 sc->sc_flags |= FXPF_FC|FXPF_EXT_TXCB; 449 if (sc->sc_rev >= FXP_REV_82559_A0) 450 sc->sc_flags |= FXPF_82559_RXCSUM; 451 452 break; 453 } 454 455 pci_aprint_devinfo_fancy(pa, "Ethernet controller", 456 (chipname ? chipname : fpp->fpp_name), 1); 457 458 /* Make sure bus-mastering is enabled. */ 459 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 460 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 461 PCI_COMMAND_MASTER_ENABLE); 462 463 /* 464 * Under some circumstances (such as APM suspend/resume 465 * cycles, and across ACPI power state changes), the 466 * i82257-family can lose the contents of critical PCI 467 * configuration registers, causing the card to be 468 * non-responsive and useless. This occurs on the Sony VAIO 469 * Z505-series, among others. Preserve them here so they can 470 * be later restored (by fxp_pci_confreg_restore()). 471 */ 472 psc->psc_pc = pc; 473 psc->psc_tag = pa->pa_tag; 474 psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] = 475 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 476 psc->psc_regs[PCI_BHLC_REG>>2] = 477 pci_conf_read(pc, pa->pa_tag, PCI_BHLC_REG); 478 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2] = 479 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x0); 480 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2] = 481 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x4); 482 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2] = 483 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x8); 484 485 /* power up chip */ 486 switch ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 487 pci_activate_null))) { 488 case EOPNOTSUPP: 489 break; 490 case 0: 491 sc->sc_enable = fxp_pci_enable; 492 sc->sc_disable = NULL; 493 break; 494 default: 495 aprint_error_dev(self, "cannot activate %d\n", error); 496 return; 497 } 498 499 /* Restore PCI configuration registers. */ 500 fxp_pci_confreg_restore(psc); 501 502 sc->sc_enabled = 1; 503 504 /* 505 * Map and establish our interrupt. 506 */ 507 if (pci_intr_map(pa, &ih)) { 508 aprint_error_dev(self, "couldn't map interrupt\n"); 509 return; 510 } 511 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 512 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, fxp_intr, sc); 513 if (sc->sc_ih == NULL) { 514 aprint_error_dev(self, "couldn't establish interrupt"); 515 if (intrstr != NULL) 516 aprint_error(" at %s", intrstr); 517 aprint_error("\n"); 518 return; 519 } 520 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 521 522 /* Finish off the attach. */ 523 fxp_attach(sc); 524 if (sc->sc_disable != NULL) 525 fxp_disable(sc); 526 527 /* Add a suspend hook to restore PCI config state */ 528 if (pmf_device_register(self, NULL, fxp_pci_resume)) 529 pmf_class_network_register(self, &sc->sc_ethercom.ec_if); 530 else 531 aprint_error_dev(self, "couldn't establish power handler\n"); 532 } 533 534 static int 535 fxp_pci_enable(struct fxp_softc *sc) 536 { 537 struct fxp_pci_softc *psc = (void *) sc; 538 539 #if 0 540 printf("%s: going to power state D0\n", device_xname(self)); 541 #endif 542 543 /* Now restore the configuration registers. */ 544 fxp_pci_confreg_restore(psc); 545 546 return (0); 547 } 548
Indexes created Thu Oct 02 01:09:59 GMT 2025