if_fxp_pci.c revision 1.84
1 /* $NetBSD: if_fxp_pci.c,v 1.84 2019/01/23 05:50:34 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * PCI bus front-end for the Intel i82557 fast Ethernet controller 35 * driver. Works with Intel Etherexpress Pro 10+, 100B, 100+ cards. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: if_fxp_pci.c,v 1.84 2019/01/23 05:50:34 msaitoh Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/mbuf.h> 44 #include <sys/malloc.h> 45 #include <sys/kernel.h> 46 #include <sys/socket.h> 47 #include <sys/ioctl.h> 48 #include <sys/errno.h> 49 #include <sys/device.h> 50 51 #include <machine/endian.h> 52 53 #include <net/if.h> 54 #include <net/if_dl.h> 55 #include <net/if_media.h> 56 #include <net/if_ether.h> 57 58 #include <sys/bus.h> 59 #include <sys/intr.h> 60 61 #include <dev/mii/miivar.h> 62 63 #include <dev/ic/i82557reg.h> 64 #include <dev/ic/i82557var.h> 65 66 #include <dev/pci/pcivar.h> 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcidevs.h> 69 70 struct fxp_pci_softc { 71 struct fxp_softc psc_fxp; 72 73 pci_chipset_tag_t psc_pc; /* pci chipset tag */ 74 pcireg_t psc_regs[0x20>>2]; /* saved PCI config regs (sparse) */ 75 pcitag_t psc_tag; /* pci register tag */ 76 77 struct pci_conf_state psc_pciconf; /* standard PCI configuration regs */ 78 }; 79 80 static int fxp_pci_match(device_t, cfdata_t, void *); 81 static void fxp_pci_attach(device_t, device_t, void *); 82 static int fxp_pci_detach(device_t, int); 83 84 static int fxp_pci_enable(struct fxp_softc *); 85 86 static void fxp_pci_confreg_restore(struct fxp_pci_softc *psc); 87 static bool fxp_pci_resume(device_t dv, const pmf_qual_t *); 88 89 CFATTACH_DECL3_NEW(fxp_pci, sizeof(struct fxp_pci_softc), 90 fxp_pci_match, fxp_pci_attach, fxp_pci_detach, NULL, NULL, 91 null_childdetached, DVF_DETACH_SHUTDOWN); 92 93 static const struct fxp_pci_product { 94 uint32_t fpp_prodid; /* PCI product ID */ 95 const char *fpp_name; /* device name */ 96 } fxp_pci_products[] = { 97 { PCI_PRODUCT_INTEL_82552, 98 "Intel i82552 10/100 Network Connection" }, 99 { PCI_PRODUCT_INTEL_8255X, 100 "Intel i8255x Ethernet" }, 101 { PCI_PRODUCT_INTEL_82559ER, 102 "Intel i82559ER Ethernet" }, 103 { PCI_PRODUCT_INTEL_IN_BUSINESS, 104 "Intel InBusiness Ethernet" }, 105 { PCI_PRODUCT_INTEL_PRO_100, 106 "Intel PRO/100 Ethernet" }, 107 { PCI_PRODUCT_INTEL_PRO_100_VE_0, 108 "Intel PRO/100 VE Network Controller" }, 109 { PCI_PRODUCT_INTEL_PRO_100_VE_1, 110 "Intel PRO/100 VE Network Controller" }, 111 { PCI_PRODUCT_INTEL_PRO_100_VE_2, 112 "Intel PRO/100 VE Network Controller with 82562ET/EZ PHY" }, 113 { PCI_PRODUCT_INTEL_PRO_100_VE_3, 114 "Intel PRO/100 VE Network Controller with 82562ET/EZ (CNR) PHY" }, 115 { PCI_PRODUCT_INTEL_PRO_100_VE_4, 116 "Intel PRO/100 VE (MOB) Network Controller" }, 117 { PCI_PRODUCT_INTEL_PRO_100_VE_5, 118 "Intel PRO/100 VE (LOM) Network Controller" }, 119 { PCI_PRODUCT_INTEL_PRO_100_VE_6, 120 "Intel PRO/100 VE Network Controller" }, 121 { PCI_PRODUCT_INTEL_PRO_100_VE_7, 122 "Intel PRO/100 VE Network Controller" }, 123 { PCI_PRODUCT_INTEL_PRO_100_VE_8, 124 "Intel PRO/100 VE Network Controller" }, 125 { PCI_PRODUCT_INTEL_PRO_100_VE_9, 126 "Intel PRO/100 VE Network Controller" }, 127 { PCI_PRODUCT_INTEL_PRO_100_VE_10, 128 "Intel PRO/100 VE Network Controller" }, 129 { PCI_PRODUCT_INTEL_PRO_100_VE_11, 130 "Intel PRO/100 VE Network Controller" }, 131 { PCI_PRODUCT_INTEL_PRO_100_VM_0, 132 "Intel PRO/100 VM Network Controller" }, 133 { PCI_PRODUCT_INTEL_PRO_100_VM_1, 134 "Intel PRO/100 VM Network Controller" }, 135 { PCI_PRODUCT_INTEL_PRO_100_VM_2, 136 "Intel PRO/100 VM Network Controller" }, 137 { PCI_PRODUCT_INTEL_PRO_100_VM_3, 138 "Intel PRO/100 VM Network Controller with 82562EM/EX PHY" }, 139 { PCI_PRODUCT_INTEL_PRO_100_VM_4, 140 "Intel PRO/100 VM Network Controller with 82562EM/EX (CNR) PHY" }, 141 { PCI_PRODUCT_INTEL_PRO_100_VM_5, 142 "Intel PRO/100 VM (MOB) Network Controller" }, 143 { PCI_PRODUCT_INTEL_PRO_100_VM_6, 144 "Intel PRO/100 VM Network Controller with 82562ET/EZ PHY" }, 145 { PCI_PRODUCT_INTEL_PRO_100_VM_7, 146 "Intel PRO/100 VM Network Connection" }, 147 { PCI_PRODUCT_INTEL_PRO_100_VM_8, 148 "Intel PRO/100 VM Network Connection" }, 149 { PCI_PRODUCT_INTEL_PRO_100_VM_9, 150 "Intel PRO/100 VM Network Connection" }, 151 { PCI_PRODUCT_INTEL_PRO_100_VM_10, 152 "Intel PRO/100 VM Network Connection" }, 153 { PCI_PRODUCT_INTEL_PRO_100_VM_11, 154 "Intel PRO/100 VM Network Connection" }, 155 { PCI_PRODUCT_INTEL_PRO_100_VM_12, 156 "Intel PRO/100 VM Network Connection" }, 157 { PCI_PRODUCT_INTEL_PRO_100_VM_13, 158 "Intel PRO/100 VM Network Connection" }, 159 { PCI_PRODUCT_INTEL_PRO_100_VM_14, 160 "Intel PRO/100 VM Network Connection" }, 161 { PCI_PRODUCT_INTEL_PRO_100_VM_15, 162 "Intel PRO/100 VM Network Connection" }, 163 { PCI_PRODUCT_INTEL_PRO_100_VM_16, 164 "Intel PRO/100 VM Network Connection" }, 165 { PCI_PRODUCT_INTEL_PRO_100_M, 166 "Intel PRO/100 M Network Controller" }, 167 { PCI_PRODUCT_INTEL_82801BA_LAN, 168 "Intel i82562 Ethernet" }, 169 { PCI_PRODUCT_INTEL_82801E_LAN_1, 170 "Intel i82801E Ethernet" }, 171 { PCI_PRODUCT_INTEL_82801E_LAN_2, 172 "Intel i82801E Ethernet" }, 173 { PCI_PRODUCT_INTEL_82801EB_LAN, 174 "Intel 82801EB/ER (ICH5) Network Controller" }, 175 { PCI_PRODUCT_INTEL_82801FB_LAN, 176 "Intel i82801FB LAN Controller" }, 177 { PCI_PRODUCT_INTEL_82801FB_LAN_2, 178 "Intel i82801FB LAN Controller" }, 179 { PCI_PRODUCT_INTEL_82801G_LAN, 180 "Intel 82801GB/GR (ICH7) Network Controller" }, 181 { PCI_PRODUCT_INTEL_82801GB_LAN, 182 "Intel 82801GB 10/100 Network Controller" }, 183 { 0, 184 NULL }, 185 }; 186 187 static const struct fxp_pci_product * 188 fxp_pci_lookup(const struct pci_attach_args *pa) 189 { 190 const struct fxp_pci_product *fpp; 191 192 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 193 return NULL; 194 195 for (fpp = fxp_pci_products; fpp->fpp_name != NULL; fpp++) 196 if (PCI_PRODUCT(pa->pa_id) == fpp->fpp_prodid) 197 return fpp; 198 199 return NULL; 200 } 201 202 static int 203 fxp_pci_match(device_t parent, cfdata_t match, void *aux) 204 { 205 struct pci_attach_args *pa = aux; 206 207 if (fxp_pci_lookup(pa) != NULL) 208 return 1; 209 210 return 0; 211 } 212 213 /* 214 * On resume : (XXX it is necessary with new pmf framework ?) 215 * Restore PCI configuration registers that may have been clobbered. 216 * This is necessary due to bugs on the Sony VAIO Z505-series on-board 217 * ethernet, after an APM suspend/resume, as well as after an ACPI 218 * D3->D0 transition. We call this function from a power hook after 219 * APM resume events, as well as after the ACPI D3->D0 transition. 220 */ 221 static void 222 fxp_pci_confreg_restore(struct fxp_pci_softc *psc) 223 { 224 pcireg_t reg; 225 226 #if 0 227 /* 228 * Check to see if the command register is blank -- if so, then 229 * we'll assume that all the clobberable-registers have been 230 * clobbered. 231 */ 232 233 /* 234 * In general, the above metric is accurate. Unfortunately, 235 * it is inaccurate across a hibernation. Ideally APM/ACPI 236 * code should take note of hibernation events and execute 237 * a hibernation wakeup hook, but at present a hibernation wake 238 * is indistinguishable from a suspend wake. 239 */ 240 241 if (((reg = pci_conf_read(psc->psc_pc, psc->psc_tag, 242 PCI_COMMAND_STATUS_REG)) & 0xffff) != 0) 243 return; 244 #else 245 reg = pci_conf_read(psc->psc_pc, psc->psc_tag, PCI_COMMAND_STATUS_REG); 246 #endif 247 248 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_COMMAND_STATUS_REG, 249 (reg & 0xffff0000) | 250 (psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] & 0xffff)); 251 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_BHLC_REG, 252 psc->psc_regs[PCI_BHLC_REG>>2]); 253 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x0, 254 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2]); 255 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x4, 256 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2]); 257 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x8, 258 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2]); 259 } 260 261 static bool 262 fxp_pci_resume(device_t dv, const pmf_qual_t *qual) 263 { 264 struct fxp_pci_softc *psc = device_private(dv); 265 fxp_pci_confreg_restore(psc); 266 267 return true; 268 } 269 270 static int 271 fxp_pci_detach(device_t self, int flags) 272 { 273 struct fxp_pci_softc *psc = device_private(self); 274 struct fxp_softc *sc = &psc->psc_fxp; 275 int error; 276 277 /* Finish off the attach. */ 278 if ((error = fxp_detach(sc, flags)) != 0) 279 return error; 280 281 pmf_device_deregister(self); 282 283 pci_intr_disestablish(psc->psc_pc, sc->sc_ih); 284 285 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_size); 286 287 return 0; 288 } 289 290 static void 291 fxp_pci_attach(device_t parent, device_t self, void *aux) 292 { 293 struct fxp_pci_softc *psc = device_private(self); 294 struct fxp_softc *sc = &psc->psc_fxp; 295 const struct pci_attach_args *pa = aux; 296 pci_chipset_tag_t pc = pa->pa_pc; 297 pci_intr_handle_t ih; 298 const struct fxp_pci_product *fpp; 299 const char *chipname = NULL; 300 const char *intrstr = NULL; 301 bus_space_tag_t iot, memt; 302 bus_space_handle_t ioh, memh; 303 int ioh_valid, memh_valid; 304 bus_addr_t addr; 305 int flags; 306 int error; 307 char intrbuf[PCI_INTRSTR_LEN]; 308 309 sc->sc_dev = self; 310 311 /* 312 * Map control/status registers. 313 */ 314 ioh_valid = (pci_mapreg_map(pa, FXP_PCI_IOBA, PCI_MAPREG_TYPE_IO, 0, 315 &iot, &ioh, NULL, NULL) == 0); 316 317 /* 318 * Version 2.1 of the PCI spec, page 196, "Address Maps": 319 * 320 * Prefetchable 321 * 322 * Set to one if there are no side effects on reads, the 323 * device returns all bytes regardless of the byte enables, 324 * and host bridges can merge processor writes into this 325 * range without causing errors. Bit must be set to zero 326 * otherwise. 327 * 328 * The 82557 incorrectly sets the "prefetchable" bit, resulting 329 * in errors on systems which will do merged reads and writes. 330 * These errors manifest themselves as all-bits-set when reading 331 * from the EEPROM or other < 4 byte registers. 332 * 333 * We must work around this problem by always forcing the mapping 334 * for memory space to be uncacheable. On systems which cannot 335 * create an uncacheable mapping (because the firmware mapped it 336 * into only cacheable/prefetchable space due to the "prefetchable" 337 * bit), we can fall back onto i/o mapped access. 338 */ 339 memh_valid = 0; 340 memt = pa->pa_memt; 341 if (((pa->pa_flags & PCI_FLAGS_MEM_OKAY) != 0) && 342 pci_mapreg_info(pa->pa_pc, pa->pa_tag, FXP_PCI_MMBA, 343 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 344 &addr, &sc->sc_size, &flags) == 0) { 345 flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 346 if (bus_space_map(memt, addr, sc->sc_size, flags, &memh) == 0) 347 memh_valid = 1; 348 } 349 350 if (memh_valid) { 351 sc->sc_st = memt; 352 sc->sc_sh = memh; 353 } else if (ioh_valid) { 354 sc->sc_st = iot; 355 sc->sc_sh = ioh; 356 } else { 357 aprint_error(": unable to map device registers\n"); 358 return; 359 } 360 361 sc->sc_dmat = pa->pa_dmat; 362 363 fpp = fxp_pci_lookup(pa); 364 if (fpp == NULL) { 365 printf("\n"); 366 panic("fxp_pci_attach: impossible"); 367 } 368 369 sc->sc_rev = PCI_REVISION(pa->pa_class); 370 371 switch (fpp->fpp_prodid) { 372 case PCI_PRODUCT_INTEL_8255X: 373 case PCI_PRODUCT_INTEL_IN_BUSINESS: 374 375 if (sc->sc_rev >= FXP_REV_82558_A4) { 376 chipname = "i82558 Ethernet"; 377 sc->sc_flags |= FXPF_FC|FXPF_EXT_TXCB; 378 /* 379 * Enable the MWI command for memory writes. 380 */ 381 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 382 sc->sc_flags |= FXPF_MWI; 383 } 384 if (sc->sc_rev >= FXP_REV_82559_A0) { 385 chipname = "i82559 Ethernet"; 386 sc->sc_flags |= FXPF_82559_RXCSUM; 387 } 388 if (sc->sc_rev >= FXP_REV_82559S_A) 389 chipname = "i82559S Ethernet"; 390 if (sc->sc_rev >= FXP_REV_82550) { 391 chipname = "i82550 Ethernet"; 392 sc->sc_flags &= ~FXPF_82559_RXCSUM; 393 sc->sc_flags |= FXPF_EXT_RFA; 394 } 395 if (sc->sc_rev >= FXP_REV_82551_E) 396 chipname = "i82551 Ethernet"; 397 398 /* 399 * Mark all i82559 and i82550 revisions as having 400 * the "resume bug". See i82557.c for details. 401 */ 402 if (sc->sc_rev >= FXP_REV_82559_A0) 403 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 404 405 break; 406 407 case PCI_PRODUCT_INTEL_82559ER: 408 sc->sc_flags |= FXPF_FC|FXPF_EXT_TXCB; 409 410 /* 411 * i82559ER/82551ER don't support RX hardware checksumming 412 * even though it has a newer revision number than 82559_A0. 413 */ 414 415 /* All i82559 have the "resume bug". */ 416 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 417 418 /* Enable the MWI command for memory writes. */ 419 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 420 sc->sc_flags |= FXPF_MWI; 421 422 if (sc->sc_rev >= FXP_REV_82551_E) 423 chipname = "Intel i82551ER Ethernet"; 424 425 break; 426 427 case PCI_PRODUCT_INTEL_82801BA_LAN: 428 case PCI_PRODUCT_INTEL_PRO_100_VE_0: 429 case PCI_PRODUCT_INTEL_PRO_100_VE_1: 430 case PCI_PRODUCT_INTEL_PRO_100_VM_0: 431 case PCI_PRODUCT_INTEL_PRO_100_VM_1: 432 case PCI_PRODUCT_INTEL_82562EH_HPNA_0: 433 case PCI_PRODUCT_INTEL_82562EH_HPNA_1: 434 case PCI_PRODUCT_INTEL_82562EH_HPNA_2: 435 case PCI_PRODUCT_INTEL_PRO_100_VM_2: 436 /* 437 * The ICH-2 and ICH-3 have the "resume bug". 438 */ 439 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 440 /* FALLTHROUGH */ 441 442 default: 443 if (sc->sc_rev >= FXP_REV_82558_A4) 444 sc->sc_flags |= FXPF_FC|FXPF_EXT_TXCB; 445 if (sc->sc_rev >= FXP_REV_82559_A0) 446 sc->sc_flags |= FXPF_82559_RXCSUM; 447 448 break; 449 } 450 451 pci_aprint_devinfo_fancy(pa, "Ethernet controller", 452 (chipname ? chipname : fpp->fpp_name), 1); 453 454 /* Make sure bus-mastering is enabled. */ 455 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 456 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 457 PCI_COMMAND_MASTER_ENABLE); 458 459 /* 460 * Under some circumstances (such as APM suspend/resume 461 * cycles, and across ACPI power state changes), the 462 * i82257-family can lose the contents of critical PCI 463 * configuration registers, causing the card to be 464 * non-responsive and useless. This occurs on the Sony VAIO 465 * Z505-series, among others. Preserve them here so they can 466 * be later restored (by fxp_pci_confreg_restore()). 467 */ 468 psc->psc_pc = pc; 469 psc->psc_tag = pa->pa_tag; 470 psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] = 471 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 472 psc->psc_regs[PCI_BHLC_REG>>2] = 473 pci_conf_read(pc, pa->pa_tag, PCI_BHLC_REG); 474 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2] = 475 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x0); 476 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2] = 477 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x4); 478 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2] = 479 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x8); 480 481 /* power up chip */ 482 switch ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 483 pci_activate_null))) { 484 case EOPNOTSUPP: 485 break; 486 case 0: 487 sc->sc_enable = fxp_pci_enable; 488 sc->sc_disable = NULL; 489 break; 490 default: 491 aprint_error_dev(self, "cannot activate %d\n", error); 492 return; 493 } 494 495 /* Restore PCI configuration registers. */ 496 fxp_pci_confreg_restore(psc); 497 498 sc->sc_enabled = 1; 499 500 /* 501 * Map and establish our interrupt. 502 */ 503 if (pci_intr_map(pa, &ih)) { 504 aprint_error_dev(self, "couldn't map interrupt\n"); 505 return; 506 } 507 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 508 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, fxp_intr, sc, 509 device_xname(self)); 510 if (sc->sc_ih == NULL) { 511 aprint_error_dev(self, "couldn't establish interrupt"); 512 if (intrstr != NULL) 513 aprint_error(" at %s", intrstr); 514 aprint_error("\n"); 515 return; 516 } 517 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 518 519 /* Finish off the attach. */ 520 fxp_attach(sc); 521 if (sc->sc_disable != NULL) 522 fxp_disable(sc); 523 524 /* Add a suspend hook to restore PCI config state */ 525 if (pmf_device_register(self, NULL, fxp_pci_resume)) 526 pmf_class_network_register(self, &sc->sc_ethercom.ec_if); 527 else 528 aprint_error_dev(self, "couldn't establish power handler\n"); 529 } 530 531 static int 532 fxp_pci_enable(struct fxp_softc *sc) 533 { 534 struct fxp_pci_softc *psc = (void *) sc; 535 536 #if 0 537 printf("%s: going to power state D0\n", device_xname(self)); 538 #endif 539 540 /* Now restore the configuration registers. */ 541 fxp_pci_confreg_restore(psc); 542 543 return 0; 544 } 545
Indexes created Tue Sep 23 23:09:58 GMT 2025