if_fxp_pci.c revision 1.85.16.1
1 /* $NetBSD: if_fxp_pci.c,v 1.85.16.1 2021/05/13 00:47:31 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * PCI bus front-end for the Intel i82557 fast Ethernet controller 35 * driver. Works with Intel Etherexpress Pro 10+, 100B, 100+ cards. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: if_fxp_pci.c,v 1.85.16.1 2021/05/13 00:47:31 thorpej Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/mbuf.h> 44 #include <sys/malloc.h> 45 #include <sys/kernel.h> 46 #include <sys/socket.h> 47 #include <sys/ioctl.h> 48 #include <sys/errno.h> 49 #include <sys/device.h> 50 51 #include <machine/endian.h> 52 53 #include <net/if.h> 54 #include <net/if_dl.h> 55 #include <net/if_media.h> 56 #include <net/if_ether.h> 57 58 #include <sys/bus.h> 59 #include <sys/intr.h> 60 61 #include <dev/mii/miivar.h> 62 63 #include <dev/ic/i82557reg.h> 64 #include <dev/ic/i82557var.h> 65 66 #include <dev/pci/pcivar.h> 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcidevs.h> 69 70 struct fxp_pci_softc { 71 struct fxp_softc psc_fxp; 72 73 pci_chipset_tag_t psc_pc; /* pci chipset tag */ 74 pcireg_t psc_regs[0x20>>2]; /* saved PCI config regs (sparse) */ 75 pcitag_t psc_tag; /* pci register tag */ 76 77 struct pci_conf_state psc_pciconf; /* standard PCI configuration regs */ 78 }; 79 80 static int fxp_pci_match(device_t, cfdata_t, void *); 81 static void fxp_pci_attach(device_t, device_t, void *); 82 static int fxp_pci_detach(device_t, int); 83 84 static int fxp_pci_enable(struct fxp_softc *); 85 86 static void fxp_pci_confreg_restore(struct fxp_pci_softc *psc); 87 static bool fxp_pci_resume(device_t dv, const pmf_qual_t *); 88 89 CFATTACH_DECL3_NEW(fxp_pci, sizeof(struct fxp_pci_softc), 90 fxp_pci_match, fxp_pci_attach, fxp_pci_detach, NULL, NULL, 91 null_childdetached, DVF_DETACH_SHUTDOWN); 92 93 static const struct device_compatible_entry compat_data[] = { 94 { .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82552), 95 .data = "Intel i82552 10/100 Network Connection" }, 96 97 { .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_8255X), 98 .data = "Intel i8255x Ethernet" }, 99 100 { .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82559ER), 101 .data = "Intel i82559ER Ethernet" }, 102 103 { .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_IN_BUSINESS), 104 .data = "Intel InBusiness Ethernet" }, 105 106 { .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100), 107 .data = "Intel PRO/100 Ethernet" }, 108 109 { .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VE_0), 110 .data = "Intel PRO/100 VE Network Controller" }, 111 112 { .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VE_1), 113 .data = "Intel PRO/100 VE Network Controller" }, 114 115 { .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VE_2), 116 .data = "Intel PRO/100 VE Network Controller with 82562ET/EZ PHY" }, 117 118 { .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VE_3), 119 .data = "Intel PRO/100 VE Network Controller with 82562ET/EZ (CNR) PHY" }, 120 121 { .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VE_4), 122 .data = "Intel PRO/100 VE (MOB) Network Controller" }, 123 124 { .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VE_5), 125 .data = "Intel PRO/100 VE (LOM) Network Controller" }, 126 127 { .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VE_6), 128 .data = "Intel PRO/100 VE Network Controller" }, 129 130 { .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VE_7), 131 .data = "Intel PRO/100 VE Network Controller" }, 132 133 { .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VE_8), 134 .data = "Intel PRO/100 VE Network Controller" }, 135 136 { .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VE_9), 137 .data = "Intel PRO/100 VE Network Controller" }, 138 139 { .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VE_10), 140 .data = "Intel PRO/100 VE Network Controller" }, 141 142 { .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VE_11), 143 .data = "Intel PRO/100 VE Network Controller" }, 144 145 { .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VM_0), 146 .data = "Intel PRO/100 VM Network Controller" }, 147 148 { .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VM_1), 149 .data = "Intel PRO/100 VM Network Controller" }, 150 151 { .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VM_2), 152 .data = "Intel PRO/100 VM Network Controller" }, 153 154 { .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VM_3), 155 .data = "Intel PRO/100 VM Network Controller with 82562EM/EX PHY" }, 156 157 { .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VM_4), 158 .data = "Intel PRO/100 VM Network Controller with 82562EM/EX (CNR) PHY" }, 159 160 { .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VM_5), 161 .data = "Intel PRO/100 VM (MOB) Network Controller" }, 162 163 { .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VM_6), 164 .data = "Intel PRO/100 VM Network Controller with 82562ET/EZ PHY" }, 165 166 { .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VM_7), 167 .data = "Intel PRO/100 VM Network Connection" }, 168 169 { .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VM_8), 170 .data = "Intel PRO/100 VM Network Connection" }, 171 172 { .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VM_9), 173 .data = "Intel PRO/100 VM Network Connection" }, 174 175 { .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VM_10), 176 .data = "Intel PRO/100 VM Network Connection" }, 177 178 { .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VM_11), 179 .data = "Intel PRO/100 VM Network Connection" }, 180 181 { .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VM_12), 182 .data = "Intel PRO/100 VM Network Connection" }, 183 184 { .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VM_13), 185 .data = "Intel PRO/100 VM Network Connection" }, 186 187 { .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VM_14), 188 .data = "Intel PRO/100 VM Network Connection" }, 189 190 { .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VM_15), 191 .data = "Intel PRO/100 VM Network Connection" }, 192 193 { .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VM_16), 194 .data = "Intel PRO/100 VM Network Connection" }, 195 196 { .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_M), 197 .data = "Intel PRO/100 M Network Controller" }, 198 199 { .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_LAN), 200 .data = "Intel i82562 Ethernet" }, 201 202 { .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801E_LAN_1), 203 .data = "Intel i82801E Ethernet" }, 204 205 { .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801E_LAN_2), 206 .data = "Intel i82801E Ethernet" }, 207 208 { .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_LAN), 209 .data = "Intel 82801EB/ER (ICH5) Network Controller" }, 210 211 { .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_LAN), 212 .data = "Intel i82801FB LAN Controller" }, 213 214 { .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_LAN_2), 215 .data = "Intel i82801FB LAN Controller" }, 216 217 { .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801G_LAN), 218 .data = "Intel 82801GB/GR (ICH7) Network Controller" }, 219 220 { .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GB_LAN), 221 .data = "Intel 82801GB 10/100 Network Controller" }, 222 223 PCI_COMPAT_EOL 224 }; 225 226 static int 227 fxp_pci_match(device_t parent, cfdata_t match, void *aux) 228 { 229 struct pci_attach_args *pa = aux; 230 231 return pci_compatible_match(pa, compat_data); 232 } 233 234 /* 235 * On resume : (XXX it is necessary with new pmf framework ?) 236 * Restore PCI configuration registers that may have been clobbered. 237 * This is necessary due to bugs on the Sony VAIO Z505-series on-board 238 * ethernet, after an APM suspend/resume, as well as after an ACPI 239 * D3->D0 transition. We call this function from a power hook after 240 * APM resume events, as well as after the ACPI D3->D0 transition. 241 */ 242 static void 243 fxp_pci_confreg_restore(struct fxp_pci_softc *psc) 244 { 245 pcireg_t reg; 246 247 #if 0 248 /* 249 * Check to see if the command register is blank -- if so, then 250 * we'll assume that all the clobberable-registers have been 251 * clobbered. 252 */ 253 254 /* 255 * In general, the above metric is accurate. Unfortunately, 256 * it is inaccurate across a hibernation. Ideally APM/ACPI 257 * code should take note of hibernation events and execute 258 * a hibernation wakeup hook, but at present a hibernation wake 259 * is indistinguishable from a suspend wake. 260 */ 261 262 if (((reg = pci_conf_read(psc->psc_pc, psc->psc_tag, 263 PCI_COMMAND_STATUS_REG)) & 0xffff) != 0) 264 return; 265 #else 266 reg = pci_conf_read(psc->psc_pc, psc->psc_tag, PCI_COMMAND_STATUS_REG); 267 #endif 268 269 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_COMMAND_STATUS_REG, 270 (reg & 0xffff0000) | 271 (psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] & 0xffff)); 272 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_BHLC_REG, 273 psc->psc_regs[PCI_BHLC_REG>>2]); 274 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x0, 275 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2]); 276 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x4, 277 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2]); 278 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x8, 279 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2]); 280 } 281 282 static bool 283 fxp_pci_resume(device_t dv, const pmf_qual_t *qual) 284 { 285 struct fxp_pci_softc *psc = device_private(dv); 286 fxp_pci_confreg_restore(psc); 287 288 return true; 289 } 290 291 static int 292 fxp_pci_detach(device_t self, int flags) 293 { 294 struct fxp_pci_softc *psc = device_private(self); 295 struct fxp_softc *sc = &psc->psc_fxp; 296 int error; 297 298 /* Finish off the attach. */ 299 if ((error = fxp_detach(sc, flags)) != 0) 300 return error; 301 302 pmf_device_deregister(self); 303 304 pci_intr_disestablish(psc->psc_pc, sc->sc_ih); 305 306 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_size); 307 308 return 0; 309 } 310 311 static void 312 fxp_pci_attach(device_t parent, device_t self, void *aux) 313 { 314 struct fxp_pci_softc *psc = device_private(self); 315 struct fxp_softc *sc = &psc->psc_fxp; 316 const struct pci_attach_args *pa = aux; 317 pci_chipset_tag_t pc = pa->pa_pc; 318 pci_intr_handle_t ih; 319 const struct device_compatible_entry *dce; 320 const char *chipname = NULL; 321 const char *intrstr = NULL; 322 bus_space_tag_t iot, memt; 323 bus_space_handle_t ioh, memh; 324 int ioh_valid, memh_valid; 325 bus_addr_t addr; 326 pcireg_t csr; 327 int flags; 328 int error; 329 char intrbuf[PCI_INTRSTR_LEN]; 330 331 sc->sc_dev = self; 332 333 /* 334 * Map control/status registers. 335 */ 336 ioh_valid = (pci_mapreg_map(pa, FXP_PCI_IOBA, PCI_MAPREG_TYPE_IO, 0, 337 &iot, &ioh, NULL, NULL) == 0); 338 339 /* 340 * Version 2.1 of the PCI spec, page 196, "Address Maps": 341 * 342 * Prefetchable 343 * 344 * Set to one if there are no side effects on reads, the 345 * device returns all bytes regardless of the byte enables, 346 * and host bridges can merge processor writes into this 347 * range without causing errors. Bit must be set to zero 348 * otherwise. 349 * 350 * The 82557 incorrectly sets the "prefetchable" bit, resulting 351 * in errors on systems which will do merged reads and writes. 352 * These errors manifest themselves as all-bits-set when reading 353 * from the EEPROM or other < 4 byte registers. 354 * 355 * We must work around this problem by always forcing the mapping 356 * for memory space to be uncacheable. On systems which cannot 357 * create an uncacheable mapping (because the firmware mapped it 358 * into only cacheable/prefetchable space due to the "prefetchable" 359 * bit), we can fall back onto i/o mapped access. 360 */ 361 memh_valid = 0; 362 memt = pa->pa_memt; 363 if (((pa->pa_flags & PCI_FLAGS_MEM_OKAY) != 0) && 364 pci_mapreg_info(pa->pa_pc, pa->pa_tag, FXP_PCI_MMBA, 365 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 366 &addr, &sc->sc_size, &flags) == 0) { 367 flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 368 if (bus_space_map(memt, addr, sc->sc_size, flags, &memh) == 0) 369 memh_valid = 1; 370 } 371 372 if (memh_valid) { 373 sc->sc_st = memt; 374 sc->sc_sh = memh; 375 /* 376 * Enable address decoding for memory range in case BIOS or 377 * UEFI didn't set it. 378 */ 379 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, 380 PCI_COMMAND_STATUS_REG); 381 csr |= PCI_COMMAND_MEM_ENABLE; 382 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 383 csr); 384 } else if (ioh_valid) { 385 sc->sc_st = iot; 386 sc->sc_sh = ioh; 387 } else { 388 aprint_error(": unable to map device registers\n"); 389 return; 390 } 391 392 sc->sc_dmat = pa->pa_dmat; 393 394 dce = pci_compatible_lookup(pa, compat_data); 395 KASSERT(dce != NULL); 396 397 sc->sc_rev = PCI_REVISION(pa->pa_class); 398 399 switch (PCI_PRODUCT(dce->id)) { 400 case PCI_PRODUCT_INTEL_8255X: 401 case PCI_PRODUCT_INTEL_IN_BUSINESS: 402 403 if (sc->sc_rev >= FXP_REV_82558_A4) { 404 chipname = "i82558 Ethernet"; 405 sc->sc_flags |= FXPF_FC|FXPF_EXT_TXCB; 406 /* 407 * Enable the MWI command for memory writes. 408 */ 409 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 410 sc->sc_flags |= FXPF_MWI; 411 } 412 if (sc->sc_rev >= FXP_REV_82559_A0) { 413 chipname = "i82559 Ethernet"; 414 sc->sc_flags |= FXPF_82559_RXCSUM; 415 } 416 if (sc->sc_rev >= FXP_REV_82559S_A) 417 chipname = "i82559S Ethernet"; 418 if (sc->sc_rev >= FXP_REV_82550) { 419 chipname = "i82550 Ethernet"; 420 sc->sc_flags &= ~FXPF_82559_RXCSUM; 421 sc->sc_flags |= FXPF_EXT_RFA; 422 } 423 if (sc->sc_rev >= FXP_REV_82551_E) 424 chipname = "i82551 Ethernet"; 425 426 /* 427 * Mark all i82559 and i82550 revisions as having 428 * the "resume bug". See i82557.c for details. 429 */ 430 if (sc->sc_rev >= FXP_REV_82559_A0) 431 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 432 433 break; 434 435 case PCI_PRODUCT_INTEL_82559ER: 436 sc->sc_flags |= FXPF_FC|FXPF_EXT_TXCB; 437 438 /* 439 * i82559ER/82551ER don't support RX hardware checksumming 440 * even though it has a newer revision number than 82559_A0. 441 */ 442 443 /* All i82559 have the "resume bug". */ 444 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 445 446 /* Enable the MWI command for memory writes. */ 447 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 448 sc->sc_flags |= FXPF_MWI; 449 450 if (sc->sc_rev >= FXP_REV_82551_E) 451 chipname = "Intel i82551ER Ethernet"; 452 453 break; 454 455 case PCI_PRODUCT_INTEL_82801BA_LAN: 456 case PCI_PRODUCT_INTEL_PRO_100_VE_0: 457 case PCI_PRODUCT_INTEL_PRO_100_VE_1: 458 case PCI_PRODUCT_INTEL_PRO_100_VM_0: 459 case PCI_PRODUCT_INTEL_PRO_100_VM_1: 460 case PCI_PRODUCT_INTEL_82562EH_HPNA_0: 461 case PCI_PRODUCT_INTEL_82562EH_HPNA_1: 462 case PCI_PRODUCT_INTEL_82562EH_HPNA_2: 463 case PCI_PRODUCT_INTEL_PRO_100_VM_2: 464 /* 465 * The ICH-2 and ICH-3 have the "resume bug". 466 */ 467 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 468 /* FALLTHROUGH */ 469 470 default: 471 if (sc->sc_rev >= FXP_REV_82558_A4) 472 sc->sc_flags |= FXPF_FC|FXPF_EXT_TXCB; 473 if (sc->sc_rev >= FXP_REV_82559_A0) 474 sc->sc_flags |= FXPF_82559_RXCSUM; 475 476 break; 477 } 478 479 pci_aprint_devinfo_fancy(pa, "Ethernet controller", 480 (chipname != NULL ? chipname : dce->data), 1); 481 482 /* Make sure bus-mastering is enabled. */ 483 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 484 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 485 PCI_COMMAND_MASTER_ENABLE); 486 487 /* 488 * Under some circumstances (such as APM suspend/resume 489 * cycles, and across ACPI power state changes), the 490 * i82257-family can lose the contents of critical PCI 491 * configuration registers, causing the card to be 492 * non-responsive and useless. This occurs on the Sony VAIO 493 * Z505-series, among others. Preserve them here so they can 494 * be later restored (by fxp_pci_confreg_restore()). 495 */ 496 psc->psc_pc = pc; 497 psc->psc_tag = pa->pa_tag; 498 psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] = 499 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 500 psc->psc_regs[PCI_BHLC_REG>>2] = 501 pci_conf_read(pc, pa->pa_tag, PCI_BHLC_REG); 502 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2] = 503 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x0); 504 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2] = 505 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x4); 506 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2] = 507 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x8); 508 509 /* power up chip */ 510 switch ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 511 pci_activate_null))) { 512 case EOPNOTSUPP: 513 break; 514 case 0: 515 sc->sc_enable = fxp_pci_enable; 516 sc->sc_disable = NULL; 517 break; 518 default: 519 aprint_error_dev(self, "cannot activate %d\n", error); 520 return; 521 } 522 523 /* Restore PCI configuration registers. */ 524 fxp_pci_confreg_restore(psc); 525 526 sc->sc_enabled = 1; 527 528 /* 529 * Map and establish our interrupt. 530 */ 531 if (pci_intr_map(pa, &ih)) { 532 aprint_error_dev(self, "couldn't map interrupt\n"); 533 return; 534 } 535 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 536 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, fxp_intr, sc, 537 device_xname(self)); 538 if (sc->sc_ih == NULL) { 539 aprint_error_dev(self, "couldn't establish interrupt"); 540 if (intrstr != NULL) 541 aprint_error(" at %s", intrstr); 542 aprint_error("\n"); 543 return; 544 } 545 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 546 547 /* Finish off the attach. */ 548 fxp_attach(sc); 549 if (sc->sc_disable != NULL) 550 fxp_disable(sc); 551 552 /* Add a suspend hook to restore PCI config state */ 553 if (pmf_device_register(self, NULL, fxp_pci_resume)) 554 pmf_class_network_register(self, &sc->sc_ethercom.ec_if); 555 else 556 aprint_error_dev(self, "couldn't establish power handler\n"); 557 } 558 559 static int 560 fxp_pci_enable(struct fxp_softc *sc) 561 { 562 struct fxp_pci_softc *psc = (void *) sc; 563 564 #if 0 565 printf("%s: going to power state D0\n", device_xname(self)); 566 #endif 567 568 /* Now restore the configuration registers. */ 569 fxp_pci_confreg_restore(psc); 570 571 return 0; 572 } 573
Indexes created Thu Oct 02 01:09:59 GMT 2025