if_gem_pci.c revision 1.29.4.5
1 /* $NetBSD: if_gem_pci.c,v 1.29.4.5 2010/03/11 15:03:46 yamt Exp $ */ 2 3 /* 4 * 5 * Copyright (C) 2001 Eduardo Horvath. 6 * All rights reserved. 7 * 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31 32 /* 33 * PCI bindings for Apple GMAC, Sun ERI and Sun GEM Ethernet controllers 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: if_gem_pci.c,v 1.29.4.5 2010/03/11 15:03:46 yamt Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/malloc.h> 42 #include <sys/kernel.h> 43 #include <sys/socket.h> 44 #include <sys/errno.h> 45 #include <sys/device.h> 46 47 #include <machine/endian.h> 48 49 #include <uvm/uvm_extern.h> 50 51 #include <net/if.h> 52 #include <net/if_dl.h> 53 #include <net/if_media.h> 54 #include <net/if_ether.h> 55 56 #include <net/bpf.h> 57 58 #include <sys/bus.h> 59 #include <sys/intr.h> 60 61 #include <dev/mii/mii.h> 62 #include <dev/mii/miivar.h> 63 #include <dev/mii/mii_bitbang.h> 64 65 #include <dev/ic/gemreg.h> 66 #include <dev/ic/gemvar.h> 67 68 #include <dev/pci/pcivar.h> 69 #include <dev/pci/pcireg.h> 70 #include <dev/pci/pcidevs.h> 71 #include <prop/proplib.h> 72 73 struct gem_pci_softc { 74 struct gem_softc gsc_gem; /* GEM device */ 75 void *gsc_ih; 76 pci_chipset_tag_t gsc_pc; 77 pci_intr_handle_t gsc_handle; 78 }; 79 80 static bool gem_pci_estintr(struct gem_pci_softc *); 81 static bool gem_pci_suspend(device_t, const pmf_qual_t *); 82 static bool gem_pci_resume(device_t, const pmf_qual_t *); 83 static int gem_pci_detach(device_t, int); 84 85 int gem_pci_match(device_t, cfdata_t, void *); 86 void gem_pci_attach(device_t, device_t, void *); 87 88 CFATTACH_DECL3_NEW(gem_pci, sizeof(struct gem_pci_softc), 89 gem_pci_match, gem_pci_attach, gem_pci_detach, NULL, NULL, NULL, 90 DVF_DETACH_SHUTDOWN); 91 92 /* 93 * Attach routines need to be split out to different bus-specific files. 94 */ 95 96 int 97 gem_pci_match(device_t parent, cfdata_t cf, void *aux) 98 { 99 struct pci_attach_args *pa = aux; 100 101 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SUN && 102 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SUN_ERINETWORK || 103 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SUN_GEMNETWORK)) 104 return (1); 105 106 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_APPLE && 107 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_APPLE_GMAC || 108 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_APPLE_GMAC2 || 109 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_APPLE_GMAC3 || 110 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_APPLE_SHASTA_GMAC || 111 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_APPLE_K2_GMAC || 112 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_APPLE_SHASTA_GMAC || 113 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_APPLE_INTREPID2_GMAC)) 114 return (1); 115 116 117 return (0); 118 } 119 120 static inline int 121 gempromvalid(u_int8_t* buf) 122 { 123 return buf[0] == 0x18 && buf[1] == 0x00 && /* structure length */ 124 buf[2] == 0x00 && /* revision */ 125 (buf[3] == 0x00 || /* hme */ 126 buf[3] == 0x80) && /* qfe */ 127 buf[4] == PCI_SUBCLASS_NETWORK_ETHERNET && /* subclass code */ 128 buf[5] == PCI_CLASS_NETWORK; /* class code */ 129 } 130 131 static inline int 132 isshared_pins(u_int8_t* buf) 133 { 134 return buf[0] == 's' && buf[1] == 'h' && buf[2] == 'a' && 135 buf[3] == 'r' && buf[4] == 'e' && buf[5] == 'd' && 136 buf[6] == '-' && buf[7] == 'p' && buf[8] == 'i' && 137 buf[9] == 'n' && buf[10] == 's'; 138 } 139 140 static inline int 141 isserdes(u_int8_t* buf) 142 { 143 return buf[0] == 's' && buf[1] == 'e' && buf[2] == 'r' && 144 buf[3] == 'd' && buf[4] == 'e' && buf[5] == 's'; 145 } 146 147 void 148 gem_pci_attach(device_t parent, device_t self, void *aux) 149 { 150 struct pci_attach_args *pa = aux; 151 struct gem_pci_softc *gsc = device_private(self); 152 struct gem_softc *sc = &gsc->gsc_gem; 153 char devinfo[256]; 154 prop_data_t data; 155 uint8_t enaddr[ETHER_ADDR_LEN]; 156 u_int8_t *enp; 157 bus_space_handle_t romh; 158 u_int8_t buf[0x0800]; 159 int dataoff, vpdoff, serdes; 160 int i, got_addr = 0; 161 #ifdef GEM_DEBUG 162 int j; 163 #endif 164 struct pci_vpd *vpd; 165 static const u_int8_t promhdr[] = { 0x55, 0xaa }; 166 #define PROMHDR_PTR_DATA 0x18 167 static const u_int8_t promdat[] = { 168 0x50, 0x43, 0x49, 0x52, /* "PCIR" */ 169 PCI_VENDOR_SUN & 0xff, PCI_VENDOR_SUN >> 8, 170 PCI_PRODUCT_SUN_GEMNETWORK & 0xff, 171 PCI_PRODUCT_SUN_GEMNETWORK >> 8 172 }; 173 #define PROMDATA_PTR_VPD 0x08 174 #define PROMDATA_DATA2 0x0a 175 176 aprint_naive(": Ethernet controller\n"); 177 178 sc->sc_dev = self; 179 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 180 sc->sc_chiprev = PCI_REVISION(pa->pa_class); 181 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, sc->sc_chiprev); 182 183 /* 184 * Some Sun GEMs/ERIs do have their intpin register bogusly set to 0, 185 * although it should be 1. correct that. 186 */ 187 if (pa->pa_intrpin == 0) 188 pa->pa_intrpin = 1; 189 190 sc->sc_variant = GEM_UNKNOWN; 191 192 sc->sc_dmatag = pa->pa_dmat; 193 194 sc->sc_flags |= GEM_PCI; 195 196 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SUN) { 197 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SUN_GEMNETWORK) 198 sc->sc_variant = GEM_SUN_GEM; 199 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SUN_ERINETWORK) 200 sc->sc_variant = GEM_SUN_ERI; 201 } else if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_APPLE) { 202 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_APPLE_GMAC || 203 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_APPLE_GMAC2 || 204 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_APPLE_GMAC3 || 205 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_APPLE_SHASTA_GMAC || 206 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_APPLE_INTREPID2_GMAC) 207 sc->sc_variant = GEM_APPLE_GMAC; 208 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_APPLE_K2_GMAC) 209 sc->sc_variant = GEM_APPLE_K2_GMAC; 210 } 211 212 if (sc->sc_variant == GEM_UNKNOWN) { 213 aprint_error_dev(sc->sc_dev, "unknown adaptor\n"); 214 return; 215 } 216 217 #define PCI_GEM_BASEADDR (PCI_MAPREG_START + 0x00) 218 219 /* XXX Need to check for a 64-bit mem BAR? */ 220 if (pci_mapreg_map(pa, PCI_GEM_BASEADDR, 221 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 222 &sc->sc_bustag, &sc->sc_h1, NULL, &sc->sc_size) != 0) 223 { 224 aprint_error_dev(sc->sc_dev, "unable to map device registers\n"); 225 return; 226 } 227 if (bus_space_subregion(sc->sc_bustag, sc->sc_h1, 228 GEM_PCI_BANK2_OFFSET, GEM_PCI_BANK2_SIZE, &sc->sc_h2)) { 229 aprint_error_dev(sc->sc_dev, "unable to create bank 2 subregion\n"); 230 return; 231 } 232 233 if ((data = prop_dictionary_get(device_properties(sc->sc_dev), 234 "mac-address")) != NULL) { 235 memcpy(enaddr, prop_data_data_nocopy(data), ETHER_ADDR_LEN); 236 got_addr = 1; 237 if ((data = prop_dictionary_get(device_properties(sc->sc_dev), 238 "shared-pins")) != NULL) { 239 memcpy(buf, prop_data_data_nocopy(data), 240 prop_data_size(data)); 241 if (isserdes(buf)) { 242 sc->sc_flags |= GEM_SERDES; 243 } 244 } 245 } else { 246 /* 247 * Dig out VPD (vital product data) and acquire Ethernet address. 248 * The VPD of gem resides in the PCI PROM (PCI FCode). 249 */ 250 /* 251 * ``Writing FCode 3.x Programs'' (newer ones, dated 1997 and later) 252 * chapter 2 describes the data structure. 253 */ 254 255 enp = NULL; 256 257 if (sc->sc_variant == GEM_SUN_GEM && 258 (bus_space_subregion(sc->sc_bustag, sc->sc_h1, 259 GEM_PCI_ROM_OFFSET, GEM_PCI_ROM_SIZE, &romh)) == 0) { 260 261 /* read PCI Expansion PROM Header */ 262 bus_space_read_region_1(sc->sc_bustag, 263 romh, 0, buf, sizeof buf); 264 265 /* Check for "shared-pins = serdes" in FCode. */ 266 i = 0; 267 serdes = 0; 268 while (i < (sizeof buf) - sizeof "serdes") { 269 if (!serdes) { 270 if (isserdes(&buf[i])) 271 serdes = 1; 272 } else { 273 if (isshared_pins(&buf[i])) 274 serdes = 2; 275 } 276 if (serdes == 2) { 277 sc->sc_flags |= GEM_SERDES; 278 break; 279 } 280 i++; 281 } 282 #ifdef GEM_DEBUG 283 /* PROM dump */ 284 printf("%s: PROM dump (0x0000 to %04lx)\n", device_xname(sc->sc_dev), 285 (sizeof buf) - 1); 286 i = 0; 287 j = 0; 288 printf(" %04x ", i); 289 while (i < sizeof buf) { 290 printf("%02x ", buf[i]); 291 if (i && !(i % 8)) 292 printf(" "); 293 if (i && !(i % 16)) { 294 printf(" "); 295 while (j < i) { 296 if (buf[j] > 31 && buf[j] < 128) 297 printf("%c", buf[j]); 298 else 299 printf("."); 300 j++; 301 } 302 j = i; 303 printf("\n %04x ", i); 304 } 305 i++; 306 } 307 printf("\n"); 308 #endif 309 310 if (memcmp(buf, promhdr, sizeof promhdr) == 0 && 311 (dataoff = (buf[PROMHDR_PTR_DATA] | 312 (buf[PROMHDR_PTR_DATA + 1] << 8))) >= 0x1c) { 313 314 /* read PCI Expansion PROM Data */ 315 bus_space_read_region_1(sc->sc_bustag, romh, dataoff, 316 buf, 64); 317 if (memcmp(buf, promdat, sizeof promdat) == 0 && 318 gempromvalid(buf + PROMDATA_DATA2) && 319 (vpdoff = (buf[PROMDATA_PTR_VPD] | 320 (buf[PROMDATA_PTR_VPD + 1] << 8))) >= 0x1c) { 321 322 /* 323 * The VPD of gem is not in PCI 2.2 standard 324 * format. The length in the resource header 325 * is in big endian, and resources are not 326 * properly terminated (only one resource 327 * and no end tag). 328 */ 329 /* read PCI VPD */ 330 bus_space_read_region_1(sc->sc_bustag, romh, 331 vpdoff, buf, 64); 332 vpd = (void *)(buf + 3); 333 if (PCI_VPDRES_ISLARGE(buf[0]) && 334 PCI_VPDRES_LARGE_NAME(buf[0]) 335 == PCI_VPDRES_TYPE_VPD && 336 vpd->vpd_key0 == 0x4e /* N */ && 337 vpd->vpd_key1 == 0x41 /* A */ && 338 vpd->vpd_len == ETHER_ADDR_LEN) { 339 /* 340 * Ethernet address found 341 */ 342 enp = buf + 6; 343 } 344 } 345 } 346 } 347 348 if (enp) { 349 memcpy(enaddr, enp, ETHER_ADDR_LEN); 350 got_addr = 1; 351 } 352 } 353 if (!got_addr) { 354 printf("%s: no Ethernet address found\n", device_xname(sc->sc_dev)); 355 /* should we bail here? */ 356 } 357 358 if (pci_intr_map(pa, &gsc->gsc_handle) != 0) { 359 aprint_error_dev(sc->sc_dev, "unable to map interrupt\n"); 360 return; 361 } 362 gsc->gsc_pc = pa->pa_pc; 363 gem_pci_estintr(gsc); 364 365 /* Finish off the attach. */ 366 gem_attach(sc, enaddr); 367 368 if (pmf_device_register1(sc->sc_dev, 369 gem_pci_suspend, gem_pci_resume, gem_shutdown)) 370 pmf_class_network_register(sc->sc_dev, &sc->sc_ethercom.ec_if); 371 else 372 aprint_error_dev(sc->sc_dev, 373 "could not establish power handlers\n"); 374 } 375 376 static bool 377 gem_pci_suspend(device_t self, const pmf_qual_t *qual) 378 { 379 struct gem_pci_softc *gsc = device_private(self); 380 381 if (gsc->gsc_ih != NULL) { 382 pci_intr_disestablish(gsc->gsc_pc, gsc->gsc_ih); 383 gsc->gsc_ih = NULL; 384 } 385 386 return true; 387 } 388 389 static bool 390 gem_pci_estintr(struct gem_pci_softc *gsc) 391 { 392 struct gem_softc *sc = &gsc->gsc_gem; 393 const char *intrstr; 394 395 intrstr = pci_intr_string(gsc->gsc_pc, gsc->gsc_handle); 396 gsc->gsc_ih = pci_intr_establish(gsc->gsc_pc, gsc->gsc_handle, IPL_NET, 397 gem_intr, sc); 398 if (gsc->gsc_ih == NULL) { 399 aprint_error_dev(sc->sc_dev, "unable to establish interrupt"); 400 if (intrstr != NULL) 401 aprint_error(" at %s", intrstr); 402 aprint_error("\n"); 403 return false; 404 } 405 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 406 return true; 407 } 408 409 static bool 410 gem_pci_resume(device_t self, const pmf_qual_t *qual) 411 { 412 struct gem_pci_softc *gsc = device_private(self); 413 414 return gem_pci_estintr(gsc); 415 } 416 417 static int 418 gem_pci_detach(device_t self, int flags) 419 { 420 int rc; 421 struct gem_pci_softc *gsc = device_private(self); 422 struct gem_softc *sc = &gsc->gsc_gem; 423 424 switch (sc->sc_att_stage) { 425 case GEM_ATT_BACKEND_2: 426 pmf_device_deregister(self); 427 sc->sc_att_stage = GEM_ATT_FINISHED; 428 /*FALLTHROUGH*/ 429 default: 430 if ((rc = gem_detach(sc, flags)) != 0) 431 return rc; 432 /*FALLTHROUGH*/ 433 case GEM_ATT_BACKEND_1: 434 if (gsc->gsc_ih != NULL) 435 pci_intr_disestablish(gsc->gsc_pc, gsc->gsc_ih); 436 437 bus_space_unmap(sc->sc_bustag, sc->sc_h1, sc->sc_size); 438 /*FALLTHROUGH*/ 439 case GEM_ATT_BACKEND_0: 440 sc->sc_att_stage = GEM_ATT_BACKEND_0; 441 break; 442 } 443 return 0; 444 } 445
Indexes created Wed Oct 01 13:09:50 GMT 2025