if_iavf.c revision 1.14
1 /* $NetBSD: if_iavf.c,v 1.14 2021/06/16 00:21:18 riastradh Exp $ */ 2 3 /* 4 * Copyright (c) 2013-2015, Intel Corporation 5 * All rights reserved. 6 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * 3. Neither the name of the Intel Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived from 19 * this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Copyright (c) 2016,2017 David Gwynne <dlg (at) openbsd.org> 36 * Copyright (c) 2019 Jonathan Matthew <jmatthew (at) openbsd.org> 37 * 38 * Permission to use, copy, modify, and distribute this software for any 39 * purpose with or without fee is hereby granted, provided that the above 40 * copyright notice and this permission notice appear in all copies. 41 * 42 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 43 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 44 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 45 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 46 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 47 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 48 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 49 */ 50 51 /* 52 * Copyright (c) 2020 Internet Initiative Japan, Inc. 53 * All rights reserved. 54 * 55 * Redistribution and use in source and binary forms, with or without 56 * modification, are permitted provided that the following conditions 57 * are met: 58 * 1. Redistributions of source code must retain the above copyright 59 * notice, this list of conditions and the following disclaimer. 60 * 2. Redistributions in binary form must reproduce the above copyright 61 * notice, this list of conditions and the following disclaimer in the 62 * documentation and/or other materials provided with the distribution. 63 * 64 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 65 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 66 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 67 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 68 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 69 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 70 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 71 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 72 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 73 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 74 * POSSIBILITY OF SUCH DAMAGE. 75 */ 76 77 #include <sys/cdefs.h> 78 __KERNEL_RCSID(0, "$NetBSD: if_iavf.c,v 1.14 2021/06/16 00:21:18 riastradh Exp $"); 79 80 #include <sys/param.h> 81 #include <sys/types.h> 82 83 #include <sys/bitops.h> 84 #include <sys/bus.h> 85 #include <sys/cprng.h> 86 #include <sys/cpu.h> 87 #include <sys/device.h> 88 #include <sys/evcnt.h> 89 #include <sys/interrupt.h> 90 #include <sys/kmem.h> 91 #include <sys/module.h> 92 #include <sys/mutex.h> 93 #include <sys/pcq.h> 94 #include <sys/queue.h> 95 #include <sys/syslog.h> 96 #include <sys/workqueue.h> 97 #include <sys/xcall.h> 98 99 #include <net/bpf.h> 100 #include <net/if.h> 101 #include <net/if_dl.h> 102 #include <net/if_media.h> 103 #include <net/if_ether.h> 104 #include <net/rss_config.h> 105 106 #include <netinet/tcp.h> /* for struct tcphdr */ 107 #include <netinet/udp.h> /* for struct udphdr */ 108 109 #include <dev/pci/pcivar.h> 110 #include <dev/pci/pcidevs.h> 111 112 #include <dev/pci/if_ixlreg.h> 113 #include <dev/pci/if_ixlvar.h> 114 #include <dev/pci/if_iavfvar.h> 115 116 #include <prop/proplib.h> 117 118 #define IAVF_PCIREG PCI_MAPREG_START 119 #define IAVF_AQ_NUM 256 120 #define IAVF_AQ_MASK (IAVF_AQ_NUM-1) 121 #define IAVF_AQ_ALIGN 64 122 #define IAVF_AQ_BUFLEN 4096 123 #define I40E_AQ_LARGE_BUF 512 124 #define IAVF_VF_MAJOR 1 125 #define IAVF_VF_MINOR 1 126 127 #define IAVF_VFR_INPROGRESS 0 128 #define IAVF_VFR_COMPLETED 1 129 #define IAVF_VFR_VFACTIVE 2 130 131 #define IAVF_REG_VFR 0xdeadbeef 132 133 #define IAVF_ITR_RX 0x0 134 #define IAVF_ITR_TX 0x1 135 #define IAVF_ITR_MISC 0x2 136 #define IAVF_NOITR 0x3 137 138 #define IAVF_MTU_ETHERLEN (ETHER_HDR_LEN \ 139 + ETHER_CRC_LEN) 140 #define IAVF_MAX_MTU (9600 - IAVF_MTU_ETHERLEN) 141 #define IAVF_MIN_MTU (ETHER_MIN_LEN - ETHER_CRC_LEN) 142 143 #define IAVF_WORKQUEUE_PRI PRI_SOFTNET 144 145 #define IAVF_TX_PKT_DESCS 8 146 #define IAVF_TX_QUEUE_ALIGN 128 147 #define IAVF_RX_QUEUE_ALIGN 128 148 #define IAVF_TX_PKT_MAXSIZE (MCLBYTES * IAVF_TX_PKT_DESCS) 149 #define IAVF_MCLBYTES (MCLBYTES - ETHER_ALIGN) 150 151 #define IAVF_TICK_INTERVAL (5 * hz) 152 #define IAVF_WATCHDOG_TICKS 3 153 #define IAVF_WATCHDOG_STOP 0 154 155 #define IAVF_TXRX_PROCESS_UNLIMIT UINT_MAX 156 #define IAVF_TX_PROCESS_LIMIT 256 157 #define IAVF_RX_PROCESS_LIMIT 256 158 #define IAVF_TX_INTR_PROCESS_LIMIT 256 159 #define IAVF_RX_INTR_PROCESS_LIMIT 0U 160 161 #define IAVF_EXEC_TIMEOUT 3000 162 163 #define IAVF_IFCAP_RXCSUM (IFCAP_CSUM_IPv4_Rx | \ 164 IFCAP_CSUM_TCPv4_Rx | \ 165 IFCAP_CSUM_UDPv4_Rx | \ 166 IFCAP_CSUM_TCPv6_Rx | \ 167 IFCAP_CSUM_UDPv6_Rx) 168 #define IAVF_IFCAP_TXCSUM (IFCAP_CSUM_IPv4_Tx | \ 169 IFCAP_CSUM_TCPv4_Tx | \ 170 IFCAP_CSUM_UDPv4_Tx | \ 171 IFCAP_CSUM_TCPv6_Tx | \ 172 IFCAP_CSUM_UDPv6_Tx) 173 #define IAVF_CSUM_ALL_OFFLOAD (M_CSUM_IPv4 | \ 174 M_CSUM_TCPv4 | M_CSUM_TCPv6 | \ 175 M_CSUM_UDPv4 | M_CSUM_UDPv6) 176 177 struct iavf_softc; /* defined */ 178 179 struct iavf_module_params { 180 int debug; 181 uint32_t rx_itr; 182 uint32_t tx_itr; 183 unsigned int rx_ndescs; 184 unsigned int tx_ndescs; 185 int max_qps; 186 }; 187 188 struct iavf_product { 189 unsigned int vendor_id; 190 unsigned int product_id; 191 }; 192 193 struct iavf_link_speed { 194 uint64_t baudrate; 195 uint64_t media; 196 }; 197 198 struct iavf_aq_regs { 199 bus_size_t atq_tail; 200 bus_size_t atq_head; 201 bus_size_t atq_len; 202 bus_size_t atq_bal; 203 bus_size_t atq_bah; 204 205 bus_size_t arq_tail; 206 bus_size_t arq_head; 207 bus_size_t arq_len; 208 bus_size_t arq_bal; 209 bus_size_t arq_bah; 210 211 uint32_t atq_len_enable; 212 uint32_t atq_tail_mask; 213 uint32_t atq_head_mask; 214 215 uint32_t arq_len_enable; 216 uint32_t arq_tail_mask; 217 uint32_t arq_head_mask; 218 }; 219 220 struct iavf_work { 221 struct work ixw_cookie; 222 void (*ixw_func)(void *); 223 void *ixw_arg; 224 unsigned int ixw_added; 225 }; 226 227 struct iavf_tx_map { 228 struct mbuf *txm_m; 229 bus_dmamap_t txm_map; 230 unsigned int txm_eop; 231 }; 232 233 struct iavf_tx_ring { 234 unsigned int txr_qid; 235 char txr_name[16]; 236 237 struct iavf_softc *txr_sc; 238 kmutex_t txr_lock; 239 pcq_t *txr_intrq; 240 void *txr_si; 241 unsigned int txr_prod; 242 unsigned int txr_cons; 243 244 struct iavf_tx_map *txr_maps; 245 struct ixl_dmamem txr_mem; 246 bus_size_t txr_tail; 247 248 int txr_watchdog; 249 250 struct evcnt txr_defragged; 251 struct evcnt txr_defrag_failed; 252 struct evcnt txr_pcqdrop; 253 struct evcnt txr_transmitdef; 254 struct evcnt txr_defer; 255 struct evcnt txr_watchdogto; 256 struct evcnt txr_intr; 257 }; 258 259 struct iavf_rx_map { 260 struct mbuf *rxm_m; 261 bus_dmamap_t rxm_map; 262 }; 263 264 struct iavf_rx_ring { 265 unsigned int rxr_qid; 266 char rxr_name[16]; 267 268 struct iavf_softc *rxr_sc; 269 kmutex_t rxr_lock; 270 271 unsigned int rxr_prod; 272 unsigned int rxr_cons; 273 274 struct iavf_rx_map *rxr_maps; 275 struct ixl_dmamem rxr_mem; 276 bus_size_t rxr_tail; 277 278 struct mbuf *rxr_m_head; 279 struct mbuf **rxr_m_tail; 280 281 struct evcnt rxr_mgethdr_failed; 282 struct evcnt rxr_mgetcl_failed; 283 struct evcnt rxr_mbuf_load_failed; 284 struct evcnt rxr_defer; 285 struct evcnt rxr_intr; 286 }; 287 288 struct iavf_queue_pair { 289 struct iavf_tx_ring *qp_txr; 290 struct iavf_rx_ring *qp_rxr; 291 struct work qp_work; 292 void *qp_si; 293 bool qp_workqueue; 294 }; 295 296 struct iavf_stat_counters { 297 struct evcnt isc_rx_bytes; 298 struct evcnt isc_rx_unicast; 299 struct evcnt isc_rx_multicast; 300 struct evcnt isc_rx_broadcast; 301 struct evcnt isc_rx_discards; 302 struct evcnt isc_rx_unknown_protocol; 303 struct evcnt isc_tx_bytes; 304 struct evcnt isc_tx_unicast; 305 struct evcnt isc_tx_multicast; 306 struct evcnt isc_tx_broadcast; 307 struct evcnt isc_tx_discards; 308 struct evcnt isc_tx_errors; 309 }; 310 311 /* 312 * Locking notes: 313 * + A field in iavf_tx_ring is protected by txr_lock (a spin mutex), and 314 * A field in iavf_rx_ring is protected by rxr_lock (a spin mutex). 315 * - more than one lock must not be held at once. 316 * + fields named sc_atq_*, sc_arq_*, and sc_adminq_* are protected by 317 * sc_adminq_lock(a spin mutex). 318 * - The lock is held while accessing sc_aq_regs 319 * and is not held with txr_lock and rxr_lock together. 320 * + Other fields in iavf_softc is protected by sc_cfg_lock 321 * (an adaptive mutex). 322 * - The lock must be held before acquiring another lock. 323 * 324 * Locking order: 325 * - IFNET_LOCK => sc_cfg_lock => sc_adminq_lock 326 * - sc_cfg_lock => ETHER_LOCK => sc_adminq_lock 327 * - sc_cfg_lock => txr_lock 328 * - sc_cfg_lock => rxr_lock 329 */ 330 331 struct iavf_softc { 332 device_t sc_dev; 333 enum i40e_mac_type sc_mac_type; 334 int sc_debuglevel; 335 bool sc_attached; 336 bool sc_dead; 337 kmutex_t sc_cfg_lock; 338 callout_t sc_tick; 339 struct ifmedia sc_media; 340 uint64_t sc_media_status; 341 uint64_t sc_media_active; 342 int sc_link_state; 343 344 const struct iavf_aq_regs * 345 sc_aq_regs; 346 347 struct ethercom sc_ec; 348 uint8_t sc_enaddr[ETHER_ADDR_LEN]; 349 uint8_t sc_enaddr_fake[ETHER_ADDR_LEN]; 350 uint8_t sc_enaddr_added[ETHER_ADDR_LEN]; 351 uint8_t sc_enaddr_reset[ETHER_ADDR_LEN]; 352 struct if_percpuq *sc_ipq; 353 354 struct pci_attach_args sc_pa; 355 bus_dma_tag_t sc_dmat; 356 bus_space_tag_t sc_memt; 357 bus_space_handle_t sc_memh; 358 bus_size_t sc_mems; 359 pci_intr_handle_t *sc_ihp; 360 void **sc_ihs; 361 unsigned int sc_nintrs; 362 363 uint32_t sc_major_ver; 364 uint32_t sc_minor_ver; 365 uint32_t sc_vf_id; 366 uint32_t sc_vf_cap; 367 uint16_t sc_vsi_id; 368 uint16_t sc_qset_handle; 369 uint16_t sc_max_mtu; 370 bool sc_got_vf_resources; 371 bool sc_got_irq_map; 372 unsigned int sc_max_vectors; 373 374 kmutex_t sc_adminq_lock; 375 kcondvar_t sc_adminq_cv; 376 struct ixl_dmamem sc_atq; 377 unsigned int sc_atq_prod; 378 unsigned int sc_atq_cons; 379 struct ixl_aq_bufs sc_atq_idle; 380 struct ixl_aq_bufs sc_atq_live; 381 struct ixl_dmamem sc_arq; 382 struct ixl_aq_bufs sc_arq_idle; 383 struct ixl_aq_bufs sc_arq_live; 384 unsigned int sc_arq_prod; 385 unsigned int sc_arq_cons; 386 struct iavf_work sc_arq_refill; 387 uint32_t sc_arq_opcode; 388 uint32_t sc_arq_retval; 389 390 uint32_t sc_tx_itr; 391 uint32_t sc_rx_itr; 392 unsigned int sc_tx_ring_ndescs; 393 unsigned int sc_rx_ring_ndescs; 394 unsigned int sc_nqueue_pairs; 395 unsigned int sc_nqps_alloc; 396 unsigned int sc_nqps_vsi; 397 unsigned int sc_nqps_req; 398 struct iavf_queue_pair *sc_qps; 399 bool sc_txrx_workqueue; 400 u_int sc_tx_intr_process_limit; 401 u_int sc_tx_process_limit; 402 u_int sc_rx_intr_process_limit; 403 u_int sc_rx_process_limit; 404 405 struct workqueue *sc_workq; 406 struct workqueue *sc_workq_txrx; 407 struct iavf_work sc_reset_task; 408 struct iavf_work sc_wdto_task; 409 struct iavf_work sc_req_queues_task; 410 bool sc_req_queues_retried; 411 bool sc_resetting; 412 bool sc_reset_up; 413 414 struct sysctllog *sc_sysctllog; 415 struct iavf_stat_counters 416 sc_stat_counters; 417 }; 418 419 #define IAVF_LOG(_sc, _lvl, _fmt, _args...) \ 420 do { \ 421 if (!(_sc)->sc_attached) { \ 422 switch (_lvl) { \ 423 case LOG_ERR: \ 424 case LOG_WARNING: \ 425 aprint_error_dev((_sc)->sc_dev, _fmt, ##_args); \ 426 break; \ 427 case LOG_INFO: \ 428 aprint_normal_dev((_sc)->sc_dev,_fmt, ##_args); \ 429 break; \ 430 case LOG_DEBUG: \ 431 default: \ 432 aprint_debug_dev((_sc)->sc_dev, _fmt, ##_args); \ 433 } \ 434 } else { \ 435 struct ifnet *_ifp = &(_sc)->sc_ec.ec_if; \ 436 log((_lvl), "%s: " _fmt, _ifp->if_xname, ##_args); \ 437 } \ 438 } while (0) 439 440 static int iavf_dmamem_alloc(bus_dma_tag_t, struct ixl_dmamem *, 441 bus_size_t, bus_size_t); 442 static void iavf_dmamem_free(bus_dma_tag_t, struct ixl_dmamem *); 443 static struct ixl_aq_buf * 444 iavf_aqb_get(struct iavf_softc *, struct ixl_aq_bufs *); 445 static struct ixl_aq_buf * 446 iavf_aqb_get_locked(struct ixl_aq_bufs *); 447 static void iavf_aqb_put_locked(struct ixl_aq_bufs *, struct ixl_aq_buf *); 448 static void iavf_aqb_clean(struct ixl_aq_bufs *, bus_dma_tag_t); 449 450 static const struct iavf_product * 451 iavf_lookup(const struct pci_attach_args *); 452 static enum i40e_mac_type 453 iavf_mactype(pci_product_id_t); 454 static void iavf_pci_csr_setup(pci_chipset_tag_t, pcitag_t); 455 static int iavf_wait_active(struct iavf_softc *); 456 static bool iavf_is_etheranyaddr(const uint8_t *); 457 static void iavf_prepare_fakeaddr(struct iavf_softc *); 458 static int iavf_replace_lla(struct ifnet *, 459 const uint8_t *, const uint8_t *); 460 static void iavf_evcnt_attach(struct evcnt *, 461 const char *, const char *); 462 static int iavf_setup_interrupts(struct iavf_softc *); 463 static void iavf_teardown_interrupts(struct iavf_softc *); 464 static int iavf_setup_sysctls(struct iavf_softc *); 465 static void iavf_teardown_sysctls(struct iavf_softc *); 466 static int iavf_setup_stats(struct iavf_softc *); 467 static void iavf_teardown_stats(struct iavf_softc *); 468 static struct workqueue * 469 iavf_workq_create(const char *, pri_t, int, int); 470 static void iavf_workq_destroy(struct workqueue *); 471 static int iavf_work_set(struct iavf_work *, void (*)(void *), void *); 472 static void iavf_work_add(struct workqueue *, struct iavf_work *); 473 static void iavf_work_wait(struct workqueue *, struct iavf_work *); 474 static unsigned int 475 iavf_calc_msix_count(struct iavf_softc *); 476 static unsigned int 477 iavf_calc_queue_pair_size(struct iavf_softc *); 478 static int iavf_queue_pairs_alloc(struct iavf_softc *); 479 static void iavf_queue_pairs_free(struct iavf_softc *); 480 static int iavf_arq_fill(struct iavf_softc *); 481 static void iavf_arq_refill(void *); 482 static int iavf_arq_poll(struct iavf_softc *, uint32_t, int); 483 static void iavf_atq_done(struct iavf_softc *); 484 static int iavf_init_admin_queue(struct iavf_softc *); 485 static void iavf_cleanup_admin_queue(struct iavf_softc *); 486 static int iavf_arq(struct iavf_softc *); 487 static int iavf_adminq_exec(struct iavf_softc *, 488 struct ixl_aq_desc *, struct ixl_aq_buf *); 489 static int iavf_adminq_poll(struct iavf_softc *, 490 struct ixl_aq_desc *, struct ixl_aq_buf *, int); 491 static int iavf_adminq_poll_locked(struct iavf_softc *, 492 struct ixl_aq_desc *, struct ixl_aq_buf *, int); 493 static int iavf_add_multi(struct iavf_softc *, uint8_t *, uint8_t *); 494 static int iavf_del_multi(struct iavf_softc *, uint8_t *, uint8_t *); 495 static void iavf_del_all_multi(struct iavf_softc *); 496 497 static int iavf_get_version(struct iavf_softc *, struct ixl_aq_buf *); 498 static int iavf_get_vf_resources(struct iavf_softc *, struct ixl_aq_buf *); 499 static int iavf_get_stats(struct iavf_softc *); 500 static int iavf_config_irq_map(struct iavf_softc *, struct ixl_aq_buf *); 501 static int iavf_config_vsi_queues(struct iavf_softc *); 502 static int iavf_config_hena(struct iavf_softc *); 503 static int iavf_config_rss_key(struct iavf_softc *); 504 static int iavf_config_rss_lut(struct iavf_softc *); 505 static int iavf_config_promisc_mode(struct iavf_softc *, int, int); 506 static int iavf_config_vlan_stripping(struct iavf_softc *, int); 507 static int iavf_config_vlan_id(struct iavf_softc *, uint16_t, uint32_t); 508 static int iavf_queue_select(struct iavf_softc *, int); 509 static int iavf_request_queues(struct iavf_softc *, unsigned int); 510 static int iavf_reset_vf(struct iavf_softc *); 511 static int iavf_eth_addr(struct iavf_softc *, const uint8_t *, uint32_t); 512 static void iavf_process_version(struct iavf_softc *, 513 struct ixl_aq_desc *, struct ixl_aq_buf *); 514 static void iavf_process_vf_resources(struct iavf_softc *, 515 struct ixl_aq_desc *, struct ixl_aq_buf *); 516 static void iavf_process_irq_map(struct iavf_softc *, 517 struct ixl_aq_desc *); 518 static void iavf_process_vc_event(struct iavf_softc *, 519 struct ixl_aq_desc *, struct ixl_aq_buf *); 520 static void iavf_process_stats(struct iavf_softc *, 521 struct ixl_aq_desc *, struct ixl_aq_buf *); 522 static void iavf_process_req_queues(struct iavf_softc *, 523 struct ixl_aq_desc *, struct ixl_aq_buf *); 524 525 static int iavf_intr(void *); 526 static int iavf_queue_intr(void *); 527 static void iavf_tick(void *); 528 static void iavf_tick_halt(void *); 529 static void iavf_reset_request(void *); 530 static void iavf_reset_start(void *); 531 static void iavf_reset(void *); 532 static void iavf_reset_finish(struct iavf_softc *); 533 static int iavf_init(struct ifnet *); 534 static int iavf_init_locked(struct iavf_softc *); 535 static void iavf_stop(struct ifnet *, int); 536 static void iavf_stop_locked(struct iavf_softc *); 537 static int iavf_ioctl(struct ifnet *, u_long, void *); 538 static void iavf_start(struct ifnet *); 539 static int iavf_transmit(struct ifnet *, struct mbuf*); 540 static int iavf_watchdog(struct iavf_tx_ring *); 541 static void iavf_watchdog_timeout(void *); 542 static int iavf_media_change(struct ifnet *); 543 static void iavf_media_status(struct ifnet *, struct ifmediareq *); 544 static int iavf_ifflags_cb(struct ethercom *); 545 static int iavf_vlan_cb(struct ethercom *, uint16_t, bool); 546 static void iavf_deferred_transmit(void *); 547 static void iavf_handle_queue(void *); 548 static void iavf_handle_queue_wk(struct work *, void *); 549 static int iavf_reinit(struct iavf_softc *); 550 static int iavf_rxfill(struct iavf_softc *, struct iavf_rx_ring *); 551 static void iavf_txr_clean(struct iavf_softc *, struct iavf_tx_ring *); 552 static void iavf_rxr_clean(struct iavf_softc *, struct iavf_rx_ring *); 553 static int iavf_txeof(struct iavf_softc *, struct iavf_tx_ring *, 554 u_int, struct evcnt *); 555 static int iavf_rxeof(struct iavf_softc *, struct iavf_rx_ring *, 556 u_int, struct evcnt *); 557 static int iavf_iff(struct iavf_softc *); 558 static int iavf_iff_locked(struct iavf_softc *); 559 static void iavf_post_request_queues(void *); 560 static int iavf_sysctl_itr_handler(SYSCTLFN_PROTO); 561 562 static int iavf_match(device_t, cfdata_t, void *); 563 static void iavf_attach(device_t, device_t, void*); 564 static int iavf_detach(device_t, int); 565 static int iavf_finalize_teardown(device_t); 566 567 CFATTACH_DECL3_NEW(iavf, sizeof(struct iavf_softc), 568 iavf_match, iavf_attach, iavf_detach, NULL, NULL, NULL, 569 DVF_DETACH_SHUTDOWN); 570 571 static const struct iavf_product iavf_products[] = { 572 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XL710_VF }, 573 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XL710_VF_HV }, 574 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X722_VF }, 575 /* required last entry */ 576 {0, 0} 577 }; 578 579 static const struct iavf_link_speed iavf_link_speeds[] = { 580 { 0, 0 }, 581 { IF_Mbps(100), IFM_100_TX }, 582 { IF_Mbps(1000), IFM_1000_T }, 583 { IF_Gbps(10), IFM_10G_T }, 584 { IF_Gbps(40), IFM_40G_CR4 }, 585 { IF_Gbps(20), IFM_20G_KR2 }, 586 { IF_Gbps(25), IFM_25G_CR } 587 }; 588 589 static const struct iavf_aq_regs iavf_aq_regs = { 590 .atq_tail = I40E_VF_ATQT1, 591 .atq_tail_mask = I40E_VF_ATQT1_ATQT_MASK, 592 .atq_head = I40E_VF_ATQH1, 593 .atq_head_mask = I40E_VF_ARQH1_ARQH_MASK, 594 .atq_len = I40E_VF_ATQLEN1, 595 .atq_bal = I40E_VF_ATQBAL1, 596 .atq_bah = I40E_VF_ATQBAH1, 597 .atq_len_enable = I40E_VF_ATQLEN1_ATQENABLE_MASK, 598 599 .arq_tail = I40E_VF_ARQT1, 600 .arq_tail_mask = I40E_VF_ARQT1_ARQT_MASK, 601 .arq_head = I40E_VF_ARQH1, 602 .arq_head_mask = I40E_VF_ARQH1_ARQH_MASK, 603 .arq_len = I40E_VF_ARQLEN1, 604 .arq_bal = I40E_VF_ARQBAL1, 605 .arq_bah = I40E_VF_ARQBAH1, 606 .arq_len_enable = I40E_VF_ARQLEN1_ARQENABLE_MASK, 607 }; 608 609 static struct iavf_module_params iavf_params = { 610 .debug = 0, 611 .rx_itr = 0x07a, /* 4K intrs/sec */ 612 .tx_itr = 0x07a, /* 4K intrs/sec */ 613 .tx_ndescs = 512, 614 .rx_ndescs = 256, 615 .max_qps = INT_MAX, 616 }; 617 618 #define delaymsec(_x) DELAY(1000 * (_x)) 619 #define iavf_rd(_s, _r) \ 620 bus_space_read_4((_s)->sc_memt, (_s)->sc_memh, (_r)) 621 #define iavf_wr(_s, _r, _v) \ 622 bus_space_write_4((_s)->sc_memt, (_s)->sc_memh, (_r), (_v)) 623 #define iavf_barrier(_s, _r, _l, _o) \ 624 bus_space_barrier((_s)->sc_memt, (_s)->sc_memh, (_r), (_l), (_o)) 625 #define iavf_flush(_s) (void)iavf_rd((_s), I40E_VFGEN_RSTAT) 626 #define iavf_nqueues(_sc) (1 << ((_sc)->sc_nqueue_pairs - 1)) 627 #define iavf_allqueues(_sc) ((1 << ((_sc)->sc_nqueue_pairs)) - 1) 628 629 static inline void 630 iavf_intr_barrier(void) 631 { 632 633 /* make all interrupt handler finished */ 634 xc_barrier(0); 635 } 636 static inline void 637 iavf_intr_enable(struct iavf_softc *sc) 638 { 639 640 iavf_wr(sc, I40E_VFINT_DYN_CTL01, I40E_VFINT_DYN_CTL0_INTENA_MASK | 641 I40E_VFINT_DYN_CTL0_CLEARPBA_MASK | 642 (IAVF_NOITR << I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT)); 643 iavf_wr(sc, I40E_VFINT_ICR0_ENA1, I40E_VFINT_ICR0_ENA1_ADMINQ_MASK); 644 iavf_flush(sc); 645 } 646 647 static inline void 648 iavf_intr_disable(struct iavf_softc *sc) 649 { 650 651 iavf_wr(sc, I40E_VFINT_DYN_CTL01, 652 (IAVF_NOITR << I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT)); 653 iavf_wr(sc, I40E_VFINT_ICR0_ENA1, 0); 654 iavf_flush(sc); 655 } 656 657 static inline void 658 iavf_queue_intr_enable(struct iavf_softc *sc, unsigned int qid) 659 { 660 661 iavf_wr(sc, I40E_VFINT_DYN_CTLN1(qid), 662 I40E_VFINT_DYN_CTLN1_INTENA_MASK | 663 I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK | 664 (IAVF_NOITR << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT)); 665 iavf_flush(sc); 666 } 667 668 static inline void 669 iavf_queue_intr_disable(struct iavf_softc *sc, unsigned int qid) 670 { 671 672 iavf_wr(sc, I40E_VFINT_DYN_CTLN1(qid), 673 (IAVF_NOITR << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT)); 674 iavf_flush(sc); 675 } 676 677 static inline void 678 iavf_aq_vc_set_opcode(struct ixl_aq_desc *iaq, uint32_t opcode) 679 { 680 struct iavf_aq_vc *vc; 681 682 vc = (struct iavf_aq_vc *)&iaq->iaq_cookie; 683 vc->iaq_vc_opcode = htole32(opcode); 684 } 685 686 static inline uint32_t 687 iavf_aq_vc_get_opcode(const struct ixl_aq_desc *iaq) 688 { 689 const struct iavf_aq_vc *vc; 690 691 vc = (const struct iavf_aq_vc *)&iaq->iaq_cookie; 692 return le32toh(vc->iaq_vc_opcode); 693 } 694 695 static inline uint32_t 696 iavf_aq_vc_get_retval(const struct ixl_aq_desc *iaq) 697 { 698 const struct iavf_aq_vc *vc; 699 700 vc = (const struct iavf_aq_vc *)&iaq->iaq_cookie; 701 return le32toh(vc->iaq_vc_retval); 702 } 703 704 static int 705 iavf_match(device_t parent, cfdata_t match, void *aux) 706 { 707 const struct pci_attach_args *pa = aux; 708 709 return (iavf_lookup(pa) != NULL) ? 1 : 0; 710 } 711 712 static void 713 iavf_attach(device_t parent, device_t self, void *aux) 714 { 715 struct iavf_softc *sc; 716 struct pci_attach_args *pa = aux; 717 struct ifnet *ifp; 718 struct ixl_aq_buf *aqb; 719 pcireg_t memtype; 720 char xnamebuf[MAXCOMLEN]; 721 int error, i; 722 723 sc = device_private(self); 724 sc->sc_dev = self; 725 ifp = &sc->sc_ec.ec_if; 726 727 sc->sc_pa = *pa; 728 sc->sc_dmat = (pci_dma64_available(pa)) ? pa->pa_dmat64 : pa->pa_dmat; 729 sc->sc_aq_regs = &iavf_aq_regs; 730 sc->sc_debuglevel = iavf_params.debug; 731 sc->sc_tx_ring_ndescs = iavf_params.tx_ndescs; 732 sc->sc_rx_ring_ndescs = iavf_params.rx_ndescs; 733 sc->sc_tx_itr = iavf_params.tx_itr; 734 sc->sc_rx_itr = iavf_params.rx_itr; 735 sc->sc_nqps_req = MIN(ncpu, iavf_params.max_qps); 736 iavf_prepare_fakeaddr(sc); 737 738 sc->sc_mac_type = iavf_mactype(PCI_PRODUCT(pa->pa_id)); 739 iavf_pci_csr_setup(pa->pa_pc, pa->pa_tag); 740 741 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, IAVF_PCIREG); 742 if (pci_mapreg_map(pa, IAVF_PCIREG, memtype, 0, 743 &sc->sc_memt, &sc->sc_memh, NULL, &sc->sc_mems)) { 744 aprint_error(": unable to map registers\n"); 745 return; 746 } 747 748 if (iavf_wait_active(sc) != 0) { 749 aprint_error(": VF reset timed out\n"); 750 goto unmap; 751 } 752 753 mutex_init(&sc->sc_cfg_lock, MUTEX_DEFAULT, IPL_SOFTNET); 754 mutex_init(&sc->sc_adminq_lock, MUTEX_DEFAULT, IPL_NET); 755 SIMPLEQ_INIT(&sc->sc_atq_idle); 756 SIMPLEQ_INIT(&sc->sc_atq_live); 757 SIMPLEQ_INIT(&sc->sc_arq_idle); 758 SIMPLEQ_INIT(&sc->sc_arq_live); 759 sc->sc_arq_cons = 0; 760 sc->sc_arq_prod = 0; 761 aqb = NULL; 762 763 if (iavf_dmamem_alloc(sc->sc_dmat, &sc->sc_atq, 764 sizeof(struct ixl_aq_desc) * IAVF_AQ_NUM, IAVF_AQ_ALIGN) != 0) { 765 aprint_error(": unable to allocate atq\n"); 766 goto free_mutex; 767 } 768 769 if (iavf_dmamem_alloc(sc->sc_dmat, &sc->sc_arq, 770 sizeof(struct ixl_aq_desc) * IAVF_AQ_NUM, IAVF_AQ_ALIGN) != 0) { 771 aprint_error(": unable to allocate arq\n"); 772 goto free_atq; 773 } 774 775 for (i = 0; i < IAVF_AQ_NUM; i++) { 776 aqb = iavf_aqb_get(sc, NULL); 777 if (aqb != NULL) { 778 iavf_aqb_put_locked(&sc->sc_arq_idle, aqb); 779 } 780 } 781 aqb = NULL; 782 783 if (!iavf_arq_fill(sc)) { 784 aprint_error(": unable to fill arq descriptors\n"); 785 goto free_arq; 786 } 787 788 if (iavf_init_admin_queue(sc) != 0) { 789 aprint_error(": unable to initialize admin queue\n"); 790 goto shutdown; 791 } 792 793 aqb = iavf_aqb_get(sc, NULL); 794 if (aqb == NULL) { 795 aprint_error(": unable to allocate buffer for ATQ\n"); 796 goto shutdown; 797 } 798 799 error = iavf_get_version(sc, aqb); 800 switch (error) { 801 case 0: 802 break; 803 case ETIMEDOUT: 804 aprint_error(": timeout waiting for VF version\n"); 805 goto shutdown; 806 case ENOTSUP: 807 aprint_error(": unsupported VF version %d\n", sc->sc_major_ver); 808 goto shutdown; 809 default: 810 aprint_error(":unable to get VF interface version\n"); 811 goto shutdown; 812 } 813 814 if (iavf_get_vf_resources(sc, aqb) != 0) { 815 aprint_error(": timeout waiting for VF resources\n"); 816 goto shutdown; 817 } 818 819 aprint_normal(", VF version %d.%d%s", 820 sc->sc_major_ver, sc->sc_minor_ver, 821 (sc->sc_minor_ver > IAVF_VF_MINOR) ? "(minor mismatch)" : ""); 822 aprint_normal(", VF %d, VSI %d", sc->sc_vf_id, sc->sc_vsi_id); 823 aprint_normal("\n"); 824 aprint_naive("\n"); 825 826 aprint_normal_dev(self, "Ethernet address %s\n", 827 ether_sprintf(sc->sc_enaddr)); 828 829 if (iavf_queue_pairs_alloc(sc) != 0) { 830 goto shutdown; 831 } 832 833 if (iavf_setup_interrupts(sc) != 0) { 834 goto free_queue_pairs; 835 } 836 837 if (iavf_config_irq_map(sc, aqb) != 0) { 838 aprint_error(", timed out waiting for IRQ map response\n"); 839 goto teardown_intrs; 840 } 841 842 if (iavf_setup_sysctls(sc) != 0) { 843 goto teardown_intrs; 844 } 845 846 if (iavf_setup_stats(sc) != 0) { 847 goto teardown_sysctls; 848 } 849 850 iavf_aqb_put_locked(&sc->sc_atq_idle, aqb); 851 aqb = NULL; 852 853 snprintf(xnamebuf, sizeof(xnamebuf), 854 "%s_adminq_cv", device_xname(self)); 855 cv_init(&sc->sc_adminq_cv, xnamebuf); 856 857 callout_init(&sc->sc_tick, CALLOUT_MPSAFE); 858 callout_setfunc(&sc->sc_tick, iavf_tick, sc); 859 860 iavf_work_set(&sc->sc_reset_task, iavf_reset_start, sc); 861 iavf_work_set(&sc->sc_arq_refill, iavf_arq_refill, sc); 862 iavf_work_set(&sc->sc_wdto_task, iavf_watchdog_timeout, sc); 863 iavf_work_set(&sc->sc_req_queues_task, iavf_post_request_queues, sc); 864 snprintf(xnamebuf, sizeof(xnamebuf), "%s_wq_cfg", device_xname(self)); 865 sc->sc_workq = iavf_workq_create(xnamebuf, IAVF_WORKQUEUE_PRI, 866 IPL_NET, WQ_MPSAFE); 867 if (sc->sc_workq == NULL) 868 goto destroy_cv; 869 870 snprintf(xnamebuf, sizeof(xnamebuf), "%s_wq_txrx", device_xname(self)); 871 error = workqueue_create(&sc->sc_workq_txrx, xnamebuf, 872 iavf_handle_queue_wk, sc, IAVF_WORKQUEUE_PRI, IPL_NET, 873 WQ_PERCPU|WQ_MPSAFE); 874 if (error != 0) { 875 sc->sc_workq_txrx = NULL; 876 goto teardown_wqs; 877 } 878 879 if_initialize(ifp); 880 881 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 882 883 ifp->if_softc = sc; 884 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 885 ifp->if_extflags = IFEF_MPSAFE; 886 ifp->if_ioctl = iavf_ioctl; 887 ifp->if_start = iavf_start; 888 ifp->if_transmit = iavf_transmit; 889 ifp->if_watchdog = NULL; 890 ifp->if_init = iavf_init; 891 ifp->if_stop = iavf_stop; 892 893 IFQ_SET_MAXLEN(&ifp->if_snd, sc->sc_tx_ring_ndescs); 894 IFQ_SET_READY(&ifp->if_snd); 895 sc->sc_ipq = if_percpuq_create(ifp); 896 897 ifp->if_capabilities |= IAVF_IFCAP_RXCSUM; 898 ifp->if_capabilities |= IAVF_IFCAP_TXCSUM; 899 900 ether_set_vlan_cb(&sc->sc_ec, iavf_vlan_cb); 901 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 902 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_HWFILTER; 903 sc->sc_ec.ec_capenable = sc->sc_ec.ec_capabilities; 904 905 ether_set_ifflags_cb(&sc->sc_ec, iavf_ifflags_cb); 906 907 sc->sc_ec.ec_ifmedia = &sc->sc_media; 908 ifmedia_init_with_lock(&sc->sc_media, IFM_IMASK, iavf_media_change, 909 iavf_media_status, &sc->sc_cfg_lock); 910 911 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_AUTO, 0, NULL); 912 ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_AUTO); 913 914 if_deferred_start_init(ifp, NULL); 915 ether_ifattach(ifp, sc->sc_enaddr); 916 917 sc->sc_txrx_workqueue = true; 918 sc->sc_tx_process_limit = IAVF_TX_PROCESS_LIMIT; 919 sc->sc_rx_process_limit = IAVF_RX_PROCESS_LIMIT; 920 sc->sc_tx_intr_process_limit = IAVF_TX_INTR_PROCESS_LIMIT; 921 sc->sc_rx_intr_process_limit = IAVF_RX_INTR_PROCESS_LIMIT; 922 923 if_register(ifp); 924 if_link_state_change(ifp, sc->sc_link_state); 925 iavf_intr_enable(sc); 926 if (sc->sc_nqps_vsi < sc->sc_nqps_req) 927 iavf_work_add(sc->sc_workq, &sc->sc_req_queues_task); 928 sc->sc_attached = true; 929 return; 930 931 teardown_wqs: 932 config_finalize_register(self, iavf_finalize_teardown); 933 destroy_cv: 934 cv_destroy(&sc->sc_adminq_cv); 935 callout_destroy(&sc->sc_tick); 936 iavf_teardown_stats(sc); 937 teardown_sysctls: 938 iavf_teardown_sysctls(sc); 939 teardown_intrs: 940 iavf_teardown_interrupts(sc); 941 free_queue_pairs: 942 iavf_queue_pairs_free(sc); 943 shutdown: 944 if (aqb != NULL) 945 iavf_aqb_put_locked(&sc->sc_atq_idle, aqb); 946 iavf_cleanup_admin_queue(sc); 947 iavf_aqb_clean(&sc->sc_atq_idle, sc->sc_dmat); 948 iavf_aqb_clean(&sc->sc_arq_idle, sc->sc_dmat); 949 free_arq: 950 iavf_dmamem_free(sc->sc_dmat, &sc->sc_arq); 951 free_atq: 952 iavf_dmamem_free(sc->sc_dmat, &sc->sc_atq); 953 free_mutex: 954 mutex_destroy(&sc->sc_cfg_lock); 955 mutex_destroy(&sc->sc_adminq_lock); 956 unmap: 957 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems); 958 sc->sc_mems = 0; 959 sc->sc_attached = false; 960 } 961 962 static int 963 iavf_detach(device_t self, int flags) 964 { 965 struct iavf_softc *sc = device_private(self); 966 struct ifnet *ifp = &sc->sc_ec.ec_if; 967 968 if (!sc->sc_attached) 969 return 0; 970 971 iavf_stop(ifp, 1); 972 973 /* 974 * set a dummy function to halt callout safely 975 * even if a workqueue entry calls callout_schedule() 976 */ 977 callout_setfunc(&sc->sc_tick, iavf_tick_halt, sc); 978 iavf_work_wait(sc->sc_workq, &sc->sc_reset_task); 979 iavf_work_wait(sc->sc_workq, &sc->sc_wdto_task); 980 981 callout_halt(&sc->sc_tick, NULL); 982 callout_destroy(&sc->sc_tick); 983 984 /* detach the I/F before stop adminq due to callbacks */ 985 ether_ifdetach(ifp); 986 if_detach(ifp); 987 ifmedia_fini(&sc->sc_media); 988 if_percpuq_destroy(sc->sc_ipq); 989 990 iavf_intr_disable(sc); 991 iavf_intr_barrier(); 992 iavf_work_wait(sc->sc_workq, &sc->sc_arq_refill); 993 994 mutex_enter(&sc->sc_adminq_lock); 995 iavf_cleanup_admin_queue(sc); 996 mutex_exit(&sc->sc_adminq_lock); 997 iavf_aqb_clean(&sc->sc_atq_idle, sc->sc_dmat); 998 iavf_aqb_clean(&sc->sc_arq_idle, sc->sc_dmat); 999 iavf_dmamem_free(sc->sc_dmat, &sc->sc_arq); 1000 iavf_dmamem_free(sc->sc_dmat, &sc->sc_atq); 1001 cv_destroy(&sc->sc_adminq_cv); 1002 1003 iavf_workq_destroy(sc->sc_workq); 1004 sc->sc_workq = NULL; 1005 1006 iavf_queue_pairs_free(sc); 1007 iavf_teardown_interrupts(sc); 1008 iavf_teardown_sysctls(sc); 1009 iavf_teardown_stats(sc); 1010 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems); 1011 1012 mutex_destroy(&sc->sc_adminq_lock); 1013 mutex_destroy(&sc->sc_cfg_lock); 1014 1015 return 0; 1016 } 1017 1018 static int 1019 iavf_finalize_teardown(device_t self) 1020 { 1021 struct iavf_softc *sc = device_private(self); 1022 1023 if (sc->sc_workq != NULL) { 1024 iavf_workq_destroy(sc->sc_workq); 1025 sc->sc_workq = NULL; 1026 } 1027 1028 if (sc->sc_workq_txrx != NULL) { 1029 workqueue_destroy(sc->sc_workq_txrx); 1030 sc->sc_workq_txrx = NULL; 1031 } 1032 1033 return 0; 1034 } 1035 1036 static int 1037 iavf_init(struct ifnet *ifp) 1038 { 1039 struct iavf_softc *sc; 1040 int rv; 1041 1042 sc = ifp->if_softc; 1043 mutex_enter(&sc->sc_cfg_lock); 1044 rv = iavf_init_locked(sc); 1045 mutex_exit(&sc->sc_cfg_lock); 1046 1047 return rv; 1048 } 1049 1050 static int 1051 iavf_init_locked(struct iavf_softc *sc) 1052 { 1053 struct ifnet *ifp = &sc->sc_ec.ec_if; 1054 unsigned int i; 1055 int error; 1056 1057 KASSERT(mutex_owned(&sc->sc_cfg_lock)); 1058 1059 if (ISSET(ifp->if_flags, IFF_RUNNING)) 1060 iavf_stop_locked(sc); 1061 1062 if (sc->sc_resetting) 1063 return ENXIO; 1064 1065 error = iavf_reinit(sc); 1066 if (error) { 1067 iavf_stop_locked(sc); 1068 return error; 1069 } 1070 1071 SET(ifp->if_flags, IFF_RUNNING); 1072 CLR(ifp->if_flags, IFF_OACTIVE); 1073 1074 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 1075 iavf_wr(sc, I40E_VFINT_ITRN1(IAVF_ITR_RX, i), sc->sc_rx_itr); 1076 iavf_wr(sc, I40E_VFINT_ITRN1(IAVF_ITR_TX, i), sc->sc_tx_itr); 1077 } 1078 iavf_wr(sc, I40E_VFINT_ITR01(IAVF_ITR_RX), sc->sc_rx_itr); 1079 iavf_wr(sc, I40E_VFINT_ITR01(IAVF_ITR_TX), sc->sc_tx_itr); 1080 iavf_wr(sc, I40E_VFINT_ITR01(IAVF_ITR_MISC), 0); 1081 1082 error = iavf_iff_locked(sc); 1083 if (error) { 1084 iavf_stop_locked(sc); 1085 return error; 1086 }; 1087 1088 /* ETHERCAP_VLAN_HWFILTER can not be disabled */ 1089 SET(sc->sc_ec.ec_capenable, ETHERCAP_VLAN_HWFILTER); 1090 1091 callout_schedule(&sc->sc_tick, IAVF_TICK_INTERVAL); 1092 return 0; 1093 } 1094 1095 static int 1096 iavf_reinit(struct iavf_softc *sc) 1097 { 1098 struct iavf_rx_ring *rxr; 1099 struct iavf_tx_ring *txr; 1100 unsigned int i; 1101 uint32_t reg; 1102 1103 KASSERT(mutex_owned(&sc->sc_cfg_lock)); 1104 1105 sc->sc_reset_up = true; 1106 sc->sc_nqueue_pairs = MIN(sc->sc_nqps_alloc, sc->sc_nintrs - 1); 1107 1108 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 1109 rxr = sc->sc_qps[i].qp_rxr; 1110 txr = sc->sc_qps[i].qp_txr; 1111 1112 iavf_rxfill(sc, rxr); 1113 txr->txr_watchdog = IAVF_WATCHDOG_STOP; 1114 } 1115 1116 if (iavf_config_vsi_queues(sc) != 0) 1117 return EIO; 1118 1119 if (iavf_config_hena(sc) != 0) 1120 return EIO; 1121 1122 iavf_config_rss_key(sc); 1123 iavf_config_rss_lut(sc); 1124 1125 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 1126 iavf_queue_intr_enable(sc, i); 1127 } 1128 /* unmask */ 1129 reg = iavf_rd(sc, I40E_VFINT_DYN_CTL01); 1130 reg |= (IAVF_NOITR << I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT); 1131 iavf_wr(sc, I40E_VFINT_DYN_CTL01, reg); 1132 1133 if (iavf_queue_select(sc, IAVF_VC_OP_ENABLE_QUEUES) != 0) 1134 return EIO; 1135 1136 return 0; 1137 } 1138 1139 static void 1140 iavf_stop(struct ifnet *ifp, int disable) 1141 { 1142 struct iavf_softc *sc; 1143 1144 sc = ifp->if_softc; 1145 mutex_enter(&sc->sc_cfg_lock); 1146 iavf_stop_locked(sc); 1147 mutex_exit(&sc->sc_cfg_lock); 1148 } 1149 1150 static void 1151 iavf_stop_locked(struct iavf_softc *sc) 1152 { 1153 struct ifnet *ifp = &sc->sc_ec.ec_if; 1154 struct iavf_rx_ring *rxr; 1155 struct iavf_tx_ring *txr; 1156 uint32_t reg; 1157 unsigned int i; 1158 1159 KASSERT(mutex_owned(&sc->sc_cfg_lock)); 1160 1161 CLR(ifp->if_flags, IFF_RUNNING); 1162 sc->sc_reset_up = false; 1163 callout_stop(&sc->sc_tick); 1164 1165 if (!sc->sc_resetting) { 1166 /* disable queues*/ 1167 if (iavf_queue_select(sc, IAVF_VC_OP_DISABLE_QUEUES) != 0) { 1168 goto die; 1169 } 1170 } 1171 1172 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 1173 iavf_queue_intr_disable(sc, i); 1174 } 1175 1176 /* mask interrupts */ 1177 reg = iavf_rd(sc, I40E_VFINT_DYN_CTL01); 1178 reg |= I40E_VFINT_DYN_CTL0_INTENA_MSK_MASK | 1179 (IAVF_NOITR << I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT); 1180 iavf_wr(sc, I40E_VFINT_DYN_CTL01, reg); 1181 1182 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 1183 rxr = sc->sc_qps[i].qp_rxr; 1184 txr = sc->sc_qps[i].qp_txr; 1185 1186 mutex_enter(&rxr->rxr_lock); 1187 iavf_rxr_clean(sc, rxr); 1188 mutex_exit(&rxr->rxr_lock); 1189 1190 mutex_enter(&txr->txr_lock); 1191 iavf_txr_clean(sc, txr); 1192 mutex_exit(&txr->txr_lock); 1193 1194 workqueue_wait(sc->sc_workq_txrx, 1195 &sc->sc_qps[i].qp_work); 1196 } 1197 1198 return; 1199 die: 1200 if (!sc->sc_dead) { 1201 sc->sc_dead = true; 1202 log(LOG_INFO, "%s: Request VF reset\n", ifp->if_xname); 1203 1204 iavf_work_set(&sc->sc_reset_task, iavf_reset_request, sc); 1205 iavf_work_add(sc->sc_workq, &sc->sc_reset_task); 1206 } 1207 log(LOG_CRIT, "%s: failed to shut down rings\n", ifp->if_xname); 1208 } 1209 1210 static int 1211 iavf_watchdog(struct iavf_tx_ring *txr) 1212 { 1213 struct iavf_softc *sc; 1214 1215 sc = txr->txr_sc; 1216 1217 mutex_enter(&txr->txr_lock); 1218 1219 if (txr->txr_watchdog == IAVF_WATCHDOG_STOP 1220 || --txr->txr_watchdog > 0) { 1221 mutex_exit(&txr->txr_lock); 1222 return 0; 1223 } 1224 1225 txr->txr_watchdog = IAVF_WATCHDOG_STOP; 1226 txr->txr_watchdogto.ev_count++; 1227 mutex_exit(&txr->txr_lock); 1228 1229 device_printf(sc->sc_dev, "watchdog timeout on queue %d\n", 1230 txr->txr_qid); 1231 return 1; 1232 } 1233 1234 static void 1235 iavf_watchdog_timeout(void *xsc) 1236 { 1237 struct iavf_softc *sc; 1238 struct ifnet *ifp; 1239 1240 sc = xsc; 1241 ifp = &sc->sc_ec.ec_if; 1242 1243 mutex_enter(&sc->sc_cfg_lock); 1244 if (ISSET(ifp->if_flags, IFF_RUNNING)) 1245 iavf_init_locked(sc); 1246 mutex_exit(&sc->sc_cfg_lock); 1247 } 1248 1249 static int 1250 iavf_media_change(struct ifnet *ifp) 1251 { 1252 struct iavf_softc *sc; 1253 struct ifmedia *ifm; 1254 1255 sc = ifp->if_softc; 1256 ifm = &sc->sc_media; 1257 1258 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1259 return EINVAL; 1260 1261 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1262 case IFM_AUTO: 1263 break; 1264 default: 1265 return EINVAL; 1266 } 1267 1268 return 0; 1269 } 1270 1271 static void 1272 iavf_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 1273 { 1274 struct iavf_softc *sc = ifp->if_softc; 1275 1276 KASSERT(mutex_owned(&sc->sc_cfg_lock)); 1277 1278 ifmr->ifm_status = sc->sc_media_status; 1279 ifmr->ifm_active = sc->sc_media_active; 1280 } 1281 1282 static int 1283 iavf_ifflags_cb(struct ethercom *ec) 1284 { 1285 struct ifnet *ifp = &ec->ec_if; 1286 struct iavf_softc *sc = ifp->if_softc; 1287 1288 /* vlan hwfilter can not be disabled */ 1289 SET(ec->ec_capenable, ETHERCAP_VLAN_HWFILTER); 1290 1291 return iavf_iff(sc); 1292 } 1293 1294 static int 1295 iavf_vlan_cb(struct ethercom *ec, uint16_t vid, bool set) 1296 { 1297 struct ifnet *ifp = &ec->ec_if; 1298 struct iavf_softc *sc = ifp->if_softc; 1299 int rv; 1300 1301 mutex_enter(&sc->sc_cfg_lock); 1302 1303 if (sc->sc_resetting) { 1304 mutex_exit(&sc->sc_cfg_lock); 1305 1306 /* all vlan id was already removed */ 1307 if (!set) 1308 return 0; 1309 1310 return ENXIO; 1311 } 1312 1313 /* ETHERCAP_VLAN_HWFILTER can not be disabled */ 1314 SET(sc->sc_ec.ec_capenable, ETHERCAP_VLAN_HWFILTER); 1315 1316 if (set) { 1317 rv = iavf_config_vlan_id(sc, vid, IAVF_VC_OP_ADD_VLAN); 1318 if (!ISSET(sc->sc_ec.ec_capenable, ETHERCAP_VLAN_HWTAGGING)) { 1319 iavf_config_vlan_stripping(sc, 1320 sc->sc_ec.ec_capenable); 1321 } 1322 } else { 1323 rv = iavf_config_vlan_id(sc, vid, IAVF_VC_OP_DEL_VLAN); 1324 } 1325 1326 mutex_exit(&sc->sc_cfg_lock); 1327 1328 if (rv != 0) 1329 return EIO; 1330 1331 return 0; 1332 } 1333 1334 static int 1335 iavf_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1336 { 1337 struct ifreq *ifr = (struct ifreq *)data; 1338 struct iavf_softc *sc = (struct iavf_softc *)ifp->if_softc; 1339 const struct sockaddr *sa; 1340 uint8_t addrhi[ETHER_ADDR_LEN], addrlo[ETHER_ADDR_LEN]; 1341 int s, error = 0; 1342 unsigned int nmtu; 1343 1344 switch (cmd) { 1345 case SIOCSIFMTU: 1346 nmtu = ifr->ifr_mtu; 1347 1348 if (nmtu < IAVF_MIN_MTU || nmtu > IAVF_MAX_MTU) { 1349 error = EINVAL; 1350 break; 1351 } 1352 if (ifp->if_mtu != nmtu) { 1353 s = splnet(); 1354 error = ether_ioctl(ifp, cmd, data); 1355 splx(s); 1356 if (error == ENETRESET) 1357 error = iavf_init(ifp); 1358 } 1359 break; 1360 case SIOCADDMULTI: 1361 sa = ifreq_getaddr(SIOCADDMULTI, ifr); 1362 if (ether_addmulti(sa, &sc->sc_ec) == ENETRESET) { 1363 error = ether_multiaddr(sa, addrlo, addrhi); 1364 if (error != 0) 1365 return error; 1366 1367 error = iavf_add_multi(sc, addrlo, addrhi); 1368 if (error != 0 && error != ENETRESET) { 1369 ether_delmulti(sa, &sc->sc_ec); 1370 error = EIO; 1371 } 1372 } 1373 break; 1374 1375 case SIOCDELMULTI: 1376 sa = ifreq_getaddr(SIOCDELMULTI, ifr); 1377 if (ether_delmulti(sa, &sc->sc_ec) == ENETRESET) { 1378 error = ether_multiaddr(sa, addrlo, addrhi); 1379 if (error != 0) 1380 return error; 1381 1382 error = iavf_del_multi(sc, addrlo, addrhi); 1383 } 1384 break; 1385 1386 default: 1387 s = splnet(); 1388 error = ether_ioctl(ifp, cmd, data); 1389 splx(s); 1390 } 1391 1392 if (error == ENETRESET) 1393 error = iavf_iff(sc); 1394 1395 return error; 1396 } 1397 1398 static int 1399 iavf_iff(struct iavf_softc *sc) 1400 { 1401 int error; 1402 1403 mutex_enter(&sc->sc_cfg_lock); 1404 error = iavf_iff_locked(sc); 1405 mutex_exit(&sc->sc_cfg_lock); 1406 1407 return error; 1408 } 1409 1410 static int 1411 iavf_iff_locked(struct iavf_softc *sc) 1412 { 1413 struct ifnet *ifp = &sc->sc_ec.ec_if; 1414 int unicast, multicast; 1415 const uint8_t *enaddr; 1416 1417 KASSERT(mutex_owned(&sc->sc_cfg_lock)); 1418 1419 if (!ISSET(ifp->if_flags, IFF_RUNNING)) 1420 return 0; 1421 1422 unicast = 0; 1423 multicast = 0; 1424 if (ISSET(ifp->if_flags, IFF_PROMISC)) { 1425 unicast = 1; 1426 multicast = 1; 1427 } else if (ISSET(ifp->if_flags, IFF_ALLMULTI)) { 1428 multicast = 1; 1429 } 1430 1431 iavf_config_promisc_mode(sc, unicast, multicast); 1432 1433 iavf_config_vlan_stripping(sc, sc->sc_ec.ec_capenable); 1434 1435 enaddr = CLLADDR(ifp->if_sadl); 1436 if (memcmp(enaddr, sc->sc_enaddr_added, ETHER_ADDR_LEN) != 0) { 1437 if (!iavf_is_etheranyaddr(sc->sc_enaddr_added)) { 1438 iavf_eth_addr(sc, sc->sc_enaddr_added, 1439 IAVF_VC_OP_DEL_ETH_ADDR); 1440 } 1441 memcpy(sc->sc_enaddr_added, enaddr, ETHER_ADDR_LEN); 1442 iavf_eth_addr(sc, enaddr, IAVF_VC_OP_ADD_ETH_ADDR); 1443 } 1444 1445 return 0; 1446 } 1447 1448 static const struct iavf_product * 1449 iavf_lookup(const struct pci_attach_args *pa) 1450 { 1451 const struct iavf_product *iavfp; 1452 1453 for (iavfp = iavf_products; iavfp->vendor_id != 0; iavfp++) { 1454 if (PCI_VENDOR(pa->pa_id) == iavfp->vendor_id && 1455 PCI_PRODUCT(pa->pa_id) == iavfp->product_id) 1456 return iavfp; 1457 } 1458 1459 return NULL; 1460 } 1461 1462 static enum i40e_mac_type 1463 iavf_mactype(pci_product_id_t id) 1464 { 1465 1466 switch (id) { 1467 case PCI_PRODUCT_INTEL_XL710_VF: 1468 case PCI_PRODUCT_INTEL_XL710_VF_HV: 1469 return I40E_MAC_VF; 1470 case PCI_PRODUCT_INTEL_X722_VF: 1471 return I40E_MAC_X722_VF; 1472 } 1473 1474 return I40E_MAC_GENERIC; 1475 } 1476 1477 static const struct iavf_link_speed * 1478 iavf_find_link_speed(struct iavf_softc *sc, uint32_t link_speed) 1479 { 1480 size_t i; 1481 1482 for (i = 0; i < __arraycount(iavf_link_speeds); i++) { 1483 if (link_speed & (1 << i)) 1484 return (&iavf_link_speeds[i]); 1485 } 1486 1487 return NULL; 1488 } 1489 1490 static void 1491 iavf_pci_csr_setup(pci_chipset_tag_t pc, pcitag_t tag) 1492 { 1493 pcireg_t csr; 1494 1495 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 1496 csr |= (PCI_COMMAND_MASTER_ENABLE | 1497 PCI_COMMAND_MEM_ENABLE); 1498 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 1499 } 1500 1501 static int 1502 iavf_wait_active(struct iavf_softc *sc) 1503 { 1504 int tries; 1505 uint32_t reg; 1506 1507 for (tries = 0; tries < 100; tries++) { 1508 reg = iavf_rd(sc, I40E_VFGEN_RSTAT) & 1509 I40E_VFGEN_RSTAT_VFR_STATE_MASK; 1510 if (reg == IAVF_VFR_VFACTIVE || 1511 reg == IAVF_VFR_COMPLETED) 1512 return 0; 1513 1514 delaymsec(10); 1515 } 1516 1517 return -1; 1518 } 1519 1520 static bool 1521 iavf_is_etheranyaddr(const uint8_t *enaddr) 1522 { 1523 static const uint8_t etheranyaddr[ETHER_ADDR_LEN] = { 1524 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1525 }; 1526 1527 if (memcmp(enaddr, etheranyaddr, ETHER_ADDR_LEN) != 0) 1528 return false; 1529 1530 return true; 1531 } 1532 1533 static void 1534 iavf_prepare_fakeaddr(struct iavf_softc *sc) 1535 { 1536 uint64_t rndval; 1537 1538 if (!iavf_is_etheranyaddr(sc->sc_enaddr_fake)) 1539 return; 1540 1541 rndval = cprng_strong64(); 1542 1543 memcpy(sc->sc_enaddr_fake, &rndval, sizeof(sc->sc_enaddr_fake)); 1544 sc->sc_enaddr_fake[0] &= 0xFE; 1545 sc->sc_enaddr_fake[0] |= 0x02; 1546 } 1547 1548 static int 1549 iavf_replace_lla(struct ifnet *ifp, const uint8_t *prev, const uint8_t *next) 1550 { 1551 union { 1552 struct sockaddr sa; 1553 struct sockaddr_dl sdl; 1554 struct sockaddr_storage ss; 1555 } u; 1556 struct psref psref_prev, psref_next; 1557 struct ifaddr *ifa_prev, *ifa_next; 1558 const struct sockaddr_dl *nsdl; 1559 int s, error; 1560 1561 KASSERT(IFNET_LOCKED(ifp)); 1562 1563 error = 0; 1564 ifa_prev = ifa_next = NULL; 1565 1566 if (memcmp(prev, next, ETHER_ADDR_LEN) == 0) { 1567 goto done; 1568 } 1569 1570 if (sockaddr_dl_init(&u.sdl, sizeof(u.ss), ifp->if_index, 1571 ifp->if_type, ifp->if_xname, strlen(ifp->if_xname), 1572 prev, ETHER_ADDR_LEN) == NULL) { 1573 error = EINVAL; 1574 goto done; 1575 } 1576 1577 s = pserialize_read_enter(); 1578 IFADDR_READER_FOREACH(ifa_prev, ifp) { 1579 if (sockaddr_cmp(&u.sa, ifa_prev->ifa_addr) == 0) { 1580 ifa_acquire(ifa_prev, &psref_prev); 1581 break; 1582 } 1583 } 1584 pserialize_read_exit(s); 1585 1586 if (sockaddr_dl_init(&u.sdl, sizeof(u.ss), ifp->if_index, 1587 ifp->if_type, ifp->if_xname, strlen(ifp->if_xname), 1588 next, ETHER_ADDR_LEN) == NULL) { 1589 error = EINVAL; 1590 goto done; 1591 } 1592 1593 s = pserialize_read_enter(); 1594 IFADDR_READER_FOREACH(ifa_next, ifp) { 1595 if (sockaddr_cmp(&u.sa, ifa_next->ifa_addr) == 0) { 1596 ifa_acquire(ifa_next, &psref_next); 1597 break; 1598 } 1599 } 1600 pserialize_read_exit(s); 1601 1602 if (ifa_next == NULL) { 1603 nsdl = &u.sdl; 1604 ifa_next = if_dl_create(ifp, &nsdl); 1605 if (ifa_next == NULL) { 1606 error = ENOMEM; 1607 goto done; 1608 } 1609 1610 s = pserialize_read_enter(); 1611 ifa_acquire(ifa_next, &psref_next); 1612 pserialize_read_exit(s); 1613 1614 sockaddr_copy(ifa_next->ifa_addr, 1615 ifa_next->ifa_addr->sa_len, &u.sa); 1616 ifa_insert(ifp, ifa_next); 1617 } else { 1618 nsdl = NULL; 1619 } 1620 1621 if (ifa_prev != NULL && ifa_prev == ifp->if_dl) { 1622 if_activate_sadl(ifp, ifa_next, nsdl); 1623 } 1624 1625 ifa_release(ifa_next, &psref_next); 1626 ifa_next = NULL; 1627 1628 if (ifa_prev != NULL && ifa_prev != ifp->if_hwdl) { 1629 ifaref(ifa_prev); 1630 ifa_release(ifa_prev, &psref_prev); 1631 ifa_remove(ifp, ifa_prev); 1632 KASSERTMSG(ifa_prev->ifa_refcnt == 1, "ifa_refcnt=%d", 1633 ifa_prev->ifa_refcnt); 1634 ifafree(ifa_prev); 1635 ifa_prev = NULL; 1636 } 1637 1638 if (ISSET(ifp->if_flags, IFF_RUNNING)) 1639 error = ENETRESET; 1640 1641 done: 1642 if (ifa_prev != NULL) 1643 ifa_release(ifa_prev, &psref_prev); 1644 if (ifa_next != NULL) 1645 ifa_release(ifa_next, &psref_next); 1646 1647 return error; 1648 } 1649 static int 1650 iavf_add_multi(struct iavf_softc *sc, uint8_t *addrlo, uint8_t *addrhi) 1651 { 1652 struct ifnet *ifp = &sc->sc_ec.ec_if; 1653 int rv; 1654 1655 if (ISSET(ifp->if_flags, IFF_ALLMULTI)) 1656 return 0; 1657 1658 if (memcmp(addrlo, addrhi, ETHER_ADDR_LEN) != 0) { 1659 iavf_del_all_multi(sc); 1660 SET(ifp->if_flags, IFF_ALLMULTI); 1661 return ENETRESET; 1662 } 1663 1664 rv = iavf_eth_addr(sc, addrlo, IAVF_VC_OP_ADD_ETH_ADDR); 1665 1666 if (rv == ENOSPC) { 1667 iavf_del_all_multi(sc); 1668 SET(ifp->if_flags, IFF_ALLMULTI); 1669 return ENETRESET; 1670 } 1671 1672 return rv; 1673 } 1674 1675 static int 1676 iavf_del_multi(struct iavf_softc *sc, uint8_t *addrlo, uint8_t *addrhi) 1677 { 1678 struct ifnet *ifp = &sc->sc_ec.ec_if; 1679 struct ethercom *ec = &sc->sc_ec; 1680 struct ether_multi *enm, *enm_last; 1681 struct ether_multistep step; 1682 int error, rv = 0; 1683 1684 if (!ISSET(ifp->if_flags, IFF_ALLMULTI)) { 1685 if (memcmp(addrlo, addrhi, ETHER_ADDR_LEN) != 0) 1686 return 0; 1687 1688 iavf_eth_addr(sc, addrlo, IAVF_VC_OP_DEL_ETH_ADDR); 1689 return 0; 1690 } 1691 1692 ETHER_LOCK(ec); 1693 for (ETHER_FIRST_MULTI(step, ec, enm); enm != NULL; 1694 ETHER_NEXT_MULTI(step, enm)) { 1695 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1696 ETHER_ADDR_LEN) != 0) { 1697 goto out; 1698 } 1699 } 1700 1701 for (ETHER_FIRST_MULTI(step, ec, enm); enm != NULL; 1702 ETHER_NEXT_MULTI(step, enm)) { 1703 error = iavf_eth_addr(sc, enm->enm_addrlo, 1704 IAVF_VC_OP_ADD_ETH_ADDR); 1705 if (error != 0) 1706 break; 1707 } 1708 1709 if (enm != NULL) { 1710 enm_last = enm; 1711 for (ETHER_FIRST_MULTI(step, ec, enm); enm != NULL; 1712 ETHER_NEXT_MULTI(step, enm)) { 1713 if (enm == enm_last) 1714 break; 1715 1716 iavf_eth_addr(sc, enm->enm_addrlo, 1717 IAVF_VC_OP_DEL_ETH_ADDR); 1718 } 1719 } else { 1720 CLR(ifp->if_flags, IFF_ALLMULTI); 1721 rv = ENETRESET; 1722 } 1723 1724 out: 1725 ETHER_UNLOCK(ec); 1726 return rv; 1727 } 1728 1729 static void 1730 iavf_del_all_multi(struct iavf_softc *sc) 1731 { 1732 struct ethercom *ec = &sc->sc_ec; 1733 struct ether_multi *enm; 1734 struct ether_multistep step; 1735 1736 ETHER_LOCK(ec); 1737 for (ETHER_FIRST_MULTI(step, ec, enm); enm != NULL; 1738 ETHER_NEXT_MULTI(step, enm)) { 1739 iavf_eth_addr(sc, enm->enm_addrlo, 1740 IAVF_VC_OP_DEL_ETH_ADDR); 1741 } 1742 ETHER_UNLOCK(ec); 1743 } 1744 1745 static int 1746 iavf_setup_interrupts(struct iavf_softc *sc) 1747 { 1748 struct pci_attach_args *pa; 1749 kcpuset_t *affinity = NULL; 1750 char intrbuf[PCI_INTRSTR_LEN], xnamebuf[32]; 1751 char const *intrstr; 1752 int counts[PCI_INTR_TYPE_SIZE]; 1753 int error, affinity_to; 1754 unsigned int vector, qid, num; 1755 1756 /* queue pairs + misc interrupt */ 1757 num = sc->sc_nqps_alloc + 1; 1758 1759 num = MIN(num, iavf_calc_msix_count(sc)); 1760 if (num <= 0) { 1761 return -1; 1762 } 1763 1764 KASSERT(sc->sc_nqps_alloc > 0); 1765 num = MIN(num, sc->sc_nqps_alloc + 1); 1766 1767 pa = &sc->sc_pa; 1768 memset(counts, 0, sizeof(counts)); 1769 counts[PCI_INTR_TYPE_MSIX] = num; 1770 1771 error = pci_intr_alloc(pa, &sc->sc_ihp, counts, PCI_INTR_TYPE_MSIX); 1772 if (error != 0) { 1773 IAVF_LOG(sc, LOG_WARNING, "couldn't allocate interrupts\n"); 1774 return -1; 1775 } 1776 1777 KASSERT(pci_intr_type(pa->pa_pc, sc->sc_ihp[0]) == PCI_INTR_TYPE_MSIX); 1778 1779 if (counts[PCI_INTR_TYPE_MSIX] < 1) { 1780 IAVF_LOG(sc, LOG_ERR, "couldn't allocate interrupts\n"); 1781 } else if (counts[PCI_INTR_TYPE_MSIX] != (int)num) { 1782 IAVF_LOG(sc, LOG_DEBUG, 1783 "request %u intruppts, but allocate %d interrupts\n", 1784 num, counts[PCI_INTR_TYPE_MSIX]); 1785 num = counts[PCI_INTR_TYPE_MSIX]; 1786 } 1787 1788 sc->sc_ihs = kmem_zalloc(sizeof(sc->sc_ihs[0]) * num, KM_NOSLEEP); 1789 if (sc->sc_ihs == NULL) { 1790 IAVF_LOG(sc, LOG_ERR, 1791 "couldn't allocate memory for interrupts\n"); 1792 goto fail; 1793 } 1794 1795 /* vector #0 is Misc interrupt */ 1796 vector = 0; 1797 pci_intr_setattr(pa->pa_pc, &sc->sc_ihp[vector], PCI_INTR_MPSAFE, true); 1798 intrstr = pci_intr_string(pa->pa_pc, sc->sc_ihp[vector], 1799 intrbuf, sizeof(intrbuf)); 1800 snprintf(xnamebuf, sizeof(xnamebuf), "%s-Misc", 1801 device_xname(sc->sc_dev)); 1802 1803 sc->sc_ihs[vector] = pci_intr_establish_xname(pa->pa_pc, 1804 sc->sc_ihp[vector], IPL_NET, iavf_intr, sc, xnamebuf); 1805 if (sc->sc_ihs[vector] == NULL) { 1806 IAVF_LOG(sc, LOG_WARNING, 1807 "unable to establish interrupt at %s", intrstr); 1808 goto fail; 1809 } 1810 1811 kcpuset_create(&affinity, false); 1812 affinity_to = 0; 1813 qid = 0; 1814 for (vector = 1; vector < num; vector++) { 1815 pci_intr_setattr(pa->pa_pc, &sc->sc_ihp[vector], 1816 PCI_INTR_MPSAFE, true); 1817 intrstr = pci_intr_string(pa->pa_pc, sc->sc_ihp[vector], 1818 intrbuf, sizeof(intrbuf)); 1819 snprintf(xnamebuf, sizeof(xnamebuf), "%s-TXRX%u", 1820 device_xname(sc->sc_dev), qid); 1821 1822 sc->sc_ihs[vector] = pci_intr_establish_xname(pa->pa_pc, 1823 sc->sc_ihp[vector], IPL_NET, iavf_queue_intr, 1824 (void *)&sc->sc_qps[qid], xnamebuf); 1825 if (sc->sc_ihs[vector] == NULL) { 1826 IAVF_LOG(sc, LOG_WARNING, 1827 "unable to establish interrupt at %s\n", intrstr); 1828 goto fail; 1829 } 1830 1831 kcpuset_zero(affinity); 1832 kcpuset_set(affinity, affinity_to); 1833 error = interrupt_distribute(sc->sc_ihs[vector], 1834 affinity, NULL); 1835 1836 if (error == 0) { 1837 IAVF_LOG(sc, LOG_INFO, 1838 "for TXRX%d interrupt at %s, affinity to %d\n", 1839 qid, intrstr, affinity_to); 1840 } else { 1841 IAVF_LOG(sc, LOG_INFO, 1842 "for TXRX%d interrupt at %s\n", 1843 qid, intrstr); 1844 } 1845 1846 qid++; 1847 affinity_to = (affinity_to + 1) % ncpu; 1848 } 1849 1850 vector = 0; 1851 kcpuset_zero(affinity); 1852 kcpuset_set(affinity, affinity_to); 1853 intrstr = pci_intr_string(pa->pa_pc, sc->sc_ihp[vector], 1854 intrbuf, sizeof(intrbuf)); 1855 error = interrupt_distribute(sc->sc_ihs[vector], affinity, NULL); 1856 if (error == 0) { 1857 IAVF_LOG(sc, LOG_INFO, 1858 "for Misc interrupt at %s, affinity to %d\n", 1859 intrstr, affinity_to); 1860 } else { 1861 IAVF_LOG(sc, LOG_INFO, 1862 "for MISC interrupt at %s\n", intrstr); 1863 } 1864 1865 kcpuset_destroy(affinity); 1866 1867 sc->sc_nintrs = num; 1868 return 0; 1869 1870 fail: 1871 if (affinity != NULL) 1872 kcpuset_destroy(affinity); 1873 for (vector = 0; vector < num; vector++) { 1874 if (sc->sc_ihs[vector] == NULL) 1875 continue; 1876 pci_intr_disestablish(pa->pa_pc, sc->sc_ihs[vector]); 1877 } 1878 kmem_free(sc->sc_ihs, sizeof(sc->sc_ihs[0]) * num); 1879 pci_intr_release(pa->pa_pc, sc->sc_ihp, num); 1880 1881 return -1; 1882 } 1883 1884 static void 1885 iavf_teardown_interrupts(struct iavf_softc *sc) 1886 { 1887 struct pci_attach_args *pa; 1888 unsigned int i; 1889 1890 if (sc->sc_ihs == NULL) 1891 return; 1892 1893 pa = &sc->sc_pa; 1894 1895 for (i = 0; i < sc->sc_nintrs; i++) { 1896 pci_intr_disestablish(pa->pa_pc, sc->sc_ihs[i]); 1897 } 1898 1899 kmem_free(sc->sc_ihs, sizeof(sc->sc_ihs[0]) * sc->sc_nintrs); 1900 sc->sc_ihs = NULL; 1901 1902 pci_intr_release(pa->pa_pc, sc->sc_ihp, sc->sc_nintrs); 1903 sc->sc_nintrs = 0; 1904 } 1905 1906 static int 1907 iavf_setup_sysctls(struct iavf_softc *sc) 1908 { 1909 const char *devname; 1910 struct sysctllog **log; 1911 const struct sysctlnode *rnode, *rxnode, *txnode; 1912 int error; 1913 1914 log = &sc->sc_sysctllog; 1915 devname = device_xname(sc->sc_dev); 1916 1917 error = sysctl_createv(log, 0, NULL, &rnode, 1918 0, CTLTYPE_NODE, devname, 1919 SYSCTL_DESCR("iavf information and settings"), 1920 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 1921 if (error) 1922 goto out; 1923 1924 error = sysctl_createv(log, 0, &rnode, NULL, 1925 CTLFLAG_READWRITE, CTLTYPE_BOOL, "txrx_workqueue", 1926 SYSCTL_DESCR("Use workqueue for packet processing"), 1927 NULL, 0, &sc->sc_txrx_workqueue, 0, CTL_CREATE, CTL_EOL); 1928 if (error) 1929 goto out; 1930 1931 error = sysctl_createv(log, 0, &rnode, NULL, 1932 CTLFLAG_READWRITE, CTLTYPE_INT, "debug_level", 1933 SYSCTL_DESCR("Debug level"), 1934 NULL, 0, &sc->sc_debuglevel, 0, CTL_CREATE, CTL_EOL); 1935 if (error) 1936 goto out; 1937 1938 error = sysctl_createv(log, 0, &rnode, &rxnode, 1939 0, CTLTYPE_NODE, "rx", 1940 SYSCTL_DESCR("iavf information and settings for Rx"), 1941 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL); 1942 if (error) 1943 goto out; 1944 1945 error = sysctl_createv(log, 0, &rxnode, NULL, 1946 CTLFLAG_READWRITE, CTLTYPE_INT, "itr", 1947 SYSCTL_DESCR("Interrupt Throttling"), 1948 iavf_sysctl_itr_handler, 0, 1949 (void *)sc, 0, CTL_CREATE, CTL_EOL); 1950 if (error) 1951 goto out; 1952 1953 error = sysctl_createv(log, 0, &rxnode, NULL, 1954 CTLFLAG_READONLY, CTLTYPE_INT, "descriptor_num", 1955 SYSCTL_DESCR("descriptor size"), 1956 NULL, 0, &sc->sc_rx_ring_ndescs, 0, CTL_CREATE, CTL_EOL); 1957 if (error) 1958 goto out; 1959 1960 error = sysctl_createv(log, 0, &rxnode, NULL, 1961 CTLFLAG_READWRITE, CTLTYPE_INT, "intr_process_limit", 1962 SYSCTL_DESCR("max number of Rx packets" 1963 " to process for interrupt processing"), 1964 NULL, 0, &sc->sc_rx_intr_process_limit, 0, CTL_CREATE, CTL_EOL); 1965 if (error) 1966 goto out; 1967 1968 error = sysctl_createv(log, 0, &rxnode, NULL, 1969 CTLFLAG_READWRITE, CTLTYPE_INT, "process_limit", 1970 SYSCTL_DESCR("max number of Rx packets" 1971 " to process for deferred processing"), 1972 NULL, 0, &sc->sc_rx_process_limit, 0, CTL_CREATE, CTL_EOL); 1973 if (error) 1974 goto out; 1975 1976 error = sysctl_createv(log, 0, &rnode, &txnode, 1977 0, CTLTYPE_NODE, "tx", 1978 SYSCTL_DESCR("iavf information and settings for Tx"), 1979 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL); 1980 if (error) 1981 goto out; 1982 1983 error = sysctl_createv(log, 0, &txnode, NULL, 1984 CTLFLAG_READWRITE, CTLTYPE_INT, "itr", 1985 SYSCTL_DESCR("Interrupt Throttling"), 1986 iavf_sysctl_itr_handler, 0, 1987 (void *)sc, 0, CTL_CREATE, CTL_EOL); 1988 if (error) 1989 goto out; 1990 1991 error = sysctl_createv(log, 0, &txnode, NULL, 1992 CTLFLAG_READONLY, CTLTYPE_INT, "descriptor_num", 1993 SYSCTL_DESCR("the number of Tx descriptors"), 1994 NULL, 0, &sc->sc_tx_ring_ndescs, 0, CTL_CREATE, CTL_EOL); 1995 if (error) 1996 goto out; 1997 1998 error = sysctl_createv(log, 0, &txnode, NULL, 1999 CTLFLAG_READWRITE, CTLTYPE_INT, "intr_process_limit", 2000 SYSCTL_DESCR("max number of Tx packets" 2001 " to process for interrupt processing"), 2002 NULL, 0, &sc->sc_tx_intr_process_limit, 0, CTL_CREATE, CTL_EOL); 2003 if (error) 2004 goto out; 2005 2006 error = sysctl_createv(log, 0, &txnode, NULL, 2007 CTLFLAG_READWRITE, CTLTYPE_INT, "process_limit", 2008 SYSCTL_DESCR("max number of Tx packets" 2009 " to process for deferred processing"), 2010 NULL, 0, &sc->sc_tx_process_limit, 0, CTL_CREATE, CTL_EOL); 2011 if (error) 2012 goto out; 2013 out: 2014 return error; 2015 } 2016 2017 static void 2018 iavf_teardown_sysctls(struct iavf_softc *sc) 2019 { 2020 2021 sysctl_teardown(&sc->sc_sysctllog); 2022 } 2023 2024 static int 2025 iavf_setup_stats(struct iavf_softc *sc) 2026 { 2027 struct iavf_stat_counters *isc; 2028 const char *dn; 2029 2030 dn = device_xname(sc->sc_dev); 2031 isc = &sc->sc_stat_counters; 2032 2033 iavf_evcnt_attach(&isc->isc_rx_bytes, dn, "Rx bytes"); 2034 iavf_evcnt_attach(&isc->isc_rx_unicast, dn, "Rx unicast"); 2035 iavf_evcnt_attach(&isc->isc_rx_multicast, dn, "Rx multicast"); 2036 iavf_evcnt_attach(&isc->isc_rx_broadcast, dn, "Rx broadcast"); 2037 iavf_evcnt_attach(&isc->isc_rx_discards, dn, "Rx discards"); 2038 iavf_evcnt_attach(&isc->isc_rx_unknown_protocol, 2039 dn, "Rx unknown protocol"); 2040 2041 iavf_evcnt_attach(&isc->isc_tx_bytes, dn, "Tx bytes"); 2042 iavf_evcnt_attach(&isc->isc_tx_unicast, dn, "Tx unicast"); 2043 iavf_evcnt_attach(&isc->isc_tx_multicast, dn, "Tx multicast"); 2044 iavf_evcnt_attach(&isc->isc_tx_broadcast, dn, "Tx broadcast"); 2045 iavf_evcnt_attach(&isc->isc_tx_discards, dn, "Tx discards"); 2046 iavf_evcnt_attach(&isc->isc_tx_errors, dn, "Tx errors"); 2047 2048 return 0; 2049 } 2050 2051 static void 2052 iavf_teardown_stats(struct iavf_softc *sc) 2053 { 2054 struct iavf_stat_counters *isc; 2055 2056 isc = &sc->sc_stat_counters; 2057 2058 evcnt_detach(&isc->isc_rx_bytes); 2059 evcnt_detach(&isc->isc_rx_unicast); 2060 evcnt_detach(&isc->isc_rx_multicast); 2061 evcnt_detach(&isc->isc_rx_broadcast); 2062 evcnt_detach(&isc->isc_rx_discards); 2063 evcnt_detach(&isc->isc_rx_unknown_protocol); 2064 2065 evcnt_detach(&isc->isc_tx_bytes); 2066 evcnt_detach(&isc->isc_tx_unicast); 2067 evcnt_detach(&isc->isc_tx_multicast); 2068 evcnt_detach(&isc->isc_tx_broadcast); 2069 evcnt_detach(&isc->isc_tx_discards); 2070 evcnt_detach(&isc->isc_tx_errors); 2071 2072 } 2073 2074 static int 2075 iavf_init_admin_queue(struct iavf_softc *sc) 2076 { 2077 uint32_t reg; 2078 2079 sc->sc_atq_cons = 0; 2080 sc->sc_atq_prod = 0; 2081 2082 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 2083 0, IXL_DMA_LEN(&sc->sc_atq), 2084 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2085 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_arq), 2086 0, IXL_DMA_LEN(&sc->sc_arq), 2087 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2088 2089 iavf_wr(sc, sc->sc_aq_regs->atq_head, 0); 2090 iavf_wr(sc, sc->sc_aq_regs->arq_head, 0); 2091 iavf_wr(sc, sc->sc_aq_regs->atq_tail, 0); 2092 iavf_wr(sc, sc->sc_aq_regs->arq_tail, 0); 2093 2094 iavf_barrier(sc, 0, sc->sc_mems, BUS_SPACE_BARRIER_WRITE); 2095 2096 iavf_wr(sc, sc->sc_aq_regs->atq_bal, 2097 ixl_dmamem_lo(&sc->sc_atq)); 2098 iavf_wr(sc, sc->sc_aq_regs->atq_bah, 2099 ixl_dmamem_hi(&sc->sc_atq)); 2100 iavf_wr(sc, sc->sc_aq_regs->atq_len, 2101 sc->sc_aq_regs->atq_len_enable | IAVF_AQ_NUM); 2102 2103 iavf_wr(sc, sc->sc_aq_regs->arq_bal, 2104 ixl_dmamem_lo(&sc->sc_arq)); 2105 iavf_wr(sc, sc->sc_aq_regs->arq_bah, 2106 ixl_dmamem_hi(&sc->sc_arq)); 2107 iavf_wr(sc, sc->sc_aq_regs->arq_len, 2108 sc->sc_aq_regs->arq_len_enable | IAVF_AQ_NUM); 2109 2110 iavf_wr(sc, sc->sc_aq_regs->arq_tail, sc->sc_arq_prod); 2111 2112 reg = iavf_rd(sc, sc->sc_aq_regs->atq_bal); 2113 if (reg != ixl_dmamem_lo(&sc->sc_atq)) 2114 goto fail; 2115 2116 reg = iavf_rd(sc, sc->sc_aq_regs->arq_bal); 2117 if (reg != ixl_dmamem_lo(&sc->sc_arq)) 2118 goto fail; 2119 2120 sc->sc_dead = false; 2121 return 0; 2122 2123 fail: 2124 iavf_wr(sc, sc->sc_aq_regs->atq_len, 0); 2125 iavf_wr(sc, sc->sc_aq_regs->arq_len, 0); 2126 return -1; 2127 } 2128 2129 static void 2130 iavf_cleanup_admin_queue(struct iavf_softc *sc) 2131 { 2132 struct ixl_aq_buf *aqb; 2133 2134 iavf_wr(sc, sc->sc_aq_regs->atq_head, 0); 2135 iavf_wr(sc, sc->sc_aq_regs->arq_head, 0); 2136 iavf_wr(sc, sc->sc_aq_regs->atq_tail, 0); 2137 iavf_wr(sc, sc->sc_aq_regs->arq_tail, 0); 2138 2139 iavf_wr(sc, sc->sc_aq_regs->atq_bal, 0); 2140 iavf_wr(sc, sc->sc_aq_regs->atq_bah, 0); 2141 iavf_wr(sc, sc->sc_aq_regs->atq_len, 0); 2142 2143 iavf_wr(sc, sc->sc_aq_regs->arq_bal, 0); 2144 iavf_wr(sc, sc->sc_aq_regs->arq_bah, 0); 2145 iavf_wr(sc, sc->sc_aq_regs->arq_len, 0); 2146 iavf_flush(sc); 2147 2148 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_arq), 2149 0, IXL_DMA_LEN(&sc->sc_arq), 2150 BUS_DMASYNC_POSTREAD); 2151 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 2152 0, IXL_DMA_LEN(&sc->sc_atq), 2153 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2154 2155 sc->sc_atq_cons = 0; 2156 sc->sc_atq_prod = 0; 2157 sc->sc_arq_cons = 0; 2158 sc->sc_arq_prod = 0; 2159 2160 memset(IXL_DMA_KVA(&sc->sc_arq), 0, IXL_DMA_LEN(&sc->sc_arq)); 2161 memset(IXL_DMA_KVA(&sc->sc_atq), 0, IXL_DMA_LEN(&sc->sc_atq)); 2162 2163 while ((aqb = iavf_aqb_get_locked(&sc->sc_arq_live)) != NULL) { 2164 bus_dmamap_sync(sc->sc_dmat, aqb->aqb_map, 0, aqb->aqb_size, 2165 BUS_DMASYNC_POSTREAD); 2166 iavf_aqb_put_locked(&sc->sc_arq_idle, aqb); 2167 } 2168 2169 while ((aqb = iavf_aqb_get_locked(&sc->sc_atq_live)) != NULL) { 2170 bus_dmamap_sync(sc->sc_dmat, aqb->aqb_map, 0, aqb->aqb_size, 2171 BUS_DMASYNC_POSTREAD); 2172 iavf_aqb_put_locked(&sc->sc_atq_idle, aqb); 2173 } 2174 } 2175 2176 static unsigned int 2177 iavf_calc_msix_count(struct iavf_softc *sc) 2178 { 2179 struct pci_attach_args *pa; 2180 int count; 2181 2182 pa = &sc->sc_pa; 2183 count = pci_msix_count(pa->pa_pc, pa->pa_tag); 2184 if (count < 0) { 2185 IAVF_LOG(sc, LOG_DEBUG,"MSIX config error\n"); 2186 count = 0; 2187 } 2188 2189 return MIN(sc->sc_max_vectors, (unsigned int)count); 2190 } 2191 2192 static unsigned int 2193 iavf_calc_queue_pair_size(struct iavf_softc *sc) 2194 { 2195 unsigned int nqp, nvec; 2196 2197 nvec = iavf_calc_msix_count(sc); 2198 if (sc->sc_max_vectors > 1) { 2199 /* decrease the number of misc interrupt */ 2200 nvec -= 1; 2201 } 2202 2203 nqp = ncpu; 2204 nqp = MIN(nqp, sc->sc_nqps_vsi); 2205 nqp = MIN(nqp, nvec); 2206 nqp = MIN(nqp, (unsigned int)iavf_params.max_qps); 2207 2208 return nqp; 2209 } 2210 2211 static struct iavf_tx_ring * 2212 iavf_txr_alloc(struct iavf_softc *sc, unsigned int qid) 2213 { 2214 struct iavf_tx_ring *txr; 2215 struct iavf_tx_map *maps; 2216 unsigned int i; 2217 int error; 2218 2219 txr = kmem_zalloc(sizeof(*txr), KM_NOSLEEP); 2220 if (txr == NULL) 2221 return NULL; 2222 2223 maps = kmem_zalloc(sizeof(maps[0]) * sc->sc_tx_ring_ndescs, 2224 KM_NOSLEEP); 2225 if (maps == NULL) 2226 goto free_txr; 2227 2228 if (iavf_dmamem_alloc(sc->sc_dmat, &txr->txr_mem, 2229 sizeof(struct ixl_tx_desc) * sc->sc_tx_ring_ndescs, 2230 IAVF_TX_QUEUE_ALIGN) != 0) { 2231 goto free_maps; 2232 } 2233 2234 for (i = 0; i < sc->sc_tx_ring_ndescs; i++) { 2235 error = bus_dmamap_create(sc->sc_dmat, IAVF_TX_PKT_MAXSIZE, 2236 IAVF_TX_PKT_DESCS, IAVF_TX_PKT_MAXSIZE, 0, 2237 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &maps[i].txm_map); 2238 if (error) 2239 goto destroy_maps; 2240 } 2241 2242 txr->txr_intrq = pcq_create(sc->sc_tx_ring_ndescs, KM_NOSLEEP); 2243 if (txr->txr_intrq == NULL) 2244 goto destroy_maps; 2245 2246 txr->txr_si = softint_establish(SOFTINT_NET|SOFTINT_MPSAFE, 2247 iavf_deferred_transmit, txr); 2248 if (txr->txr_si == NULL) 2249 goto destroy_pcq; 2250 2251 snprintf(txr->txr_name, sizeof(txr->txr_name), "%s-tx%d", 2252 device_xname(sc->sc_dev), qid); 2253 2254 iavf_evcnt_attach(&txr->txr_defragged, 2255 txr->txr_name, "m_defrag successed"); 2256 iavf_evcnt_attach(&txr->txr_defrag_failed, 2257 txr->txr_name, "m_defrag failed"); 2258 iavf_evcnt_attach(&txr->txr_pcqdrop, 2259 txr->txr_name, "Dropped in pcq"); 2260 iavf_evcnt_attach(&txr->txr_transmitdef, 2261 txr->txr_name, "Deferred transmit"); 2262 iavf_evcnt_attach(&txr->txr_watchdogto, 2263 txr->txr_name, "Watchdog timedout on queue"); 2264 iavf_evcnt_attach(&txr->txr_defer, 2265 txr->txr_name, "Handled queue in softint/workqueue"); 2266 2267 evcnt_attach_dynamic(&txr->txr_intr, EVCNT_TYPE_INTR, NULL, 2268 txr->txr_name, "Interrupt on queue"); 2269 2270 txr->txr_qid = qid; 2271 txr->txr_sc = sc; 2272 txr->txr_maps = maps; 2273 txr->txr_prod = txr->txr_cons = 0; 2274 txr->txr_tail = I40E_QTX_TAIL1(qid); 2275 mutex_init(&txr->txr_lock, MUTEX_DEFAULT, IPL_NET); 2276 2277 return txr; 2278 destroy_pcq: 2279 pcq_destroy(txr->txr_intrq); 2280 destroy_maps: 2281 for (i = 0; i < sc->sc_tx_ring_ndescs; i++) { 2282 if (maps[i].txm_map == NULL) 2283 continue; 2284 bus_dmamap_destroy(sc->sc_dmat, maps[i].txm_map); 2285 } 2286 2287 iavf_dmamem_free(sc->sc_dmat, &txr->txr_mem); 2288 free_maps: 2289 kmem_free(maps, sizeof(maps[0]) * sc->sc_tx_ring_ndescs); 2290 free_txr: 2291 kmem_free(txr, sizeof(*txr)); 2292 return NULL; 2293 } 2294 2295 static void 2296 iavf_txr_free(struct iavf_softc *sc, struct iavf_tx_ring *txr) 2297 { 2298 struct iavf_tx_map *maps; 2299 unsigned int i; 2300 2301 maps = txr->txr_maps; 2302 if (maps != NULL) { 2303 for (i = 0; i < sc->sc_tx_ring_ndescs; i++) { 2304 if (maps[i].txm_map == NULL) 2305 continue; 2306 bus_dmamap_destroy(sc->sc_dmat, maps[i].txm_map); 2307 } 2308 kmem_free(txr->txr_maps, 2309 sizeof(maps[0]) * sc->sc_tx_ring_ndescs); 2310 txr->txr_maps = NULL; 2311 } 2312 2313 evcnt_detach(&txr->txr_defragged); 2314 evcnt_detach(&txr->txr_defrag_failed); 2315 evcnt_detach(&txr->txr_pcqdrop); 2316 evcnt_detach(&txr->txr_transmitdef); 2317 evcnt_detach(&txr->txr_watchdogto); 2318 evcnt_detach(&txr->txr_defer); 2319 evcnt_detach(&txr->txr_intr); 2320 2321 iavf_dmamem_free(sc->sc_dmat, &txr->txr_mem); 2322 softint_disestablish(txr->txr_si); 2323 pcq_destroy(txr->txr_intrq); 2324 mutex_destroy(&txr->txr_lock); 2325 kmem_free(txr, sizeof(*txr)); 2326 } 2327 2328 static struct iavf_rx_ring * 2329 iavf_rxr_alloc(struct iavf_softc *sc, unsigned int qid) 2330 { 2331 struct iavf_rx_ring *rxr; 2332 struct iavf_rx_map *maps; 2333 unsigned int i; 2334 int error; 2335 2336 rxr = kmem_zalloc(sizeof(*rxr), KM_NOSLEEP); 2337 if (rxr == NULL) 2338 return NULL; 2339 2340 maps = kmem_zalloc(sizeof(maps[0]) * sc->sc_rx_ring_ndescs, 2341 KM_NOSLEEP); 2342 if (maps == NULL) 2343 goto free_rxr; 2344 2345 if (iavf_dmamem_alloc(sc->sc_dmat, &rxr->rxr_mem, 2346 sizeof(struct ixl_rx_rd_desc_32) * sc->sc_rx_ring_ndescs, 2347 IAVF_RX_QUEUE_ALIGN) != 0) 2348 goto free_maps; 2349 2350 for (i = 0; i < sc->sc_rx_ring_ndescs; i++) { 2351 error = bus_dmamap_create(sc->sc_dmat, IAVF_MCLBYTES, 2352 1, IAVF_MCLBYTES, 0, 2353 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &maps[i].rxm_map); 2354 if (error) 2355 goto destroy_maps; 2356 } 2357 2358 snprintf(rxr->rxr_name, sizeof(rxr->rxr_name), "%s-rx%d", 2359 device_xname(sc->sc_dev), qid); 2360 2361 iavf_evcnt_attach(&rxr->rxr_mgethdr_failed, 2362 rxr->rxr_name, "MGETHDR failed"); 2363 iavf_evcnt_attach(&rxr->rxr_mgetcl_failed, 2364 rxr->rxr_name, "MCLGET failed"); 2365 iavf_evcnt_attach(&rxr->rxr_mbuf_load_failed, 2366 rxr->rxr_name, "bus_dmamap_load_mbuf failed"); 2367 iavf_evcnt_attach(&rxr->rxr_defer, 2368 rxr->rxr_name, "Handled queue in softint/workqueue"); 2369 2370 evcnt_attach_dynamic(&rxr->rxr_intr, EVCNT_TYPE_INTR, NULL, 2371 rxr->rxr_name, "Interrupt on queue"); 2372 2373 rxr->rxr_qid = qid; 2374 rxr->rxr_sc = sc; 2375 rxr->rxr_cons = rxr->rxr_prod = 0; 2376 rxr->rxr_m_head = NULL; 2377 rxr->rxr_m_tail = &rxr->rxr_m_head; 2378 rxr->rxr_maps = maps; 2379 rxr->rxr_tail = I40E_QRX_TAIL1(qid); 2380 mutex_init(&rxr->rxr_lock, MUTEX_DEFAULT, IPL_NET); 2381 2382 return rxr; 2383 2384 destroy_maps: 2385 for (i = 0; i < sc->sc_rx_ring_ndescs; i++) { 2386 if (maps[i].rxm_map == NULL) 2387 continue; 2388 bus_dmamap_destroy(sc->sc_dmat, maps[i].rxm_map); 2389 } 2390 iavf_dmamem_free(sc->sc_dmat, &rxr->rxr_mem); 2391 free_maps: 2392 kmem_free(maps, sizeof(maps[0]) * sc->sc_rx_ring_ndescs); 2393 free_rxr: 2394 kmem_free(rxr, sizeof(*rxr)); 2395 2396 return NULL; 2397 } 2398 2399 static void 2400 iavf_rxr_free(struct iavf_softc *sc, struct iavf_rx_ring *rxr) 2401 { 2402 struct iavf_rx_map *maps; 2403 unsigned int i; 2404 2405 maps = rxr->rxr_maps; 2406 if (maps != NULL) { 2407 for (i = 0; i < sc->sc_rx_ring_ndescs; i++) { 2408 if (maps[i].rxm_map == NULL) 2409 continue; 2410 bus_dmamap_destroy(sc->sc_dmat, maps[i].rxm_map); 2411 } 2412 kmem_free(maps, sizeof(maps[0]) * sc->sc_rx_ring_ndescs); 2413 rxr->rxr_maps = NULL; 2414 } 2415 2416 evcnt_detach(&rxr->rxr_mgethdr_failed); 2417 evcnt_detach(&rxr->rxr_mgetcl_failed); 2418 evcnt_detach(&rxr->rxr_mbuf_load_failed); 2419 evcnt_detach(&rxr->rxr_defer); 2420 evcnt_detach(&rxr->rxr_intr); 2421 2422 iavf_dmamem_free(sc->sc_dmat, &rxr->rxr_mem); 2423 mutex_destroy(&rxr->rxr_lock); 2424 kmem_free(rxr, sizeof(*rxr)); 2425 } 2426 2427 static int 2428 iavf_queue_pairs_alloc(struct iavf_softc *sc) 2429 { 2430 struct iavf_queue_pair *qp; 2431 unsigned int i, num; 2432 2433 num = iavf_calc_queue_pair_size(sc); 2434 if (num <= 0) { 2435 return -1; 2436 } 2437 2438 sc->sc_qps = kmem_zalloc(sizeof(sc->sc_qps[0]) * num, KM_NOSLEEP); 2439 if (sc->sc_qps == NULL) { 2440 return -1; 2441 } 2442 2443 for (i = 0; i < num; i++) { 2444 qp = &sc->sc_qps[i]; 2445 2446 qp->qp_rxr = iavf_rxr_alloc(sc, i); 2447 qp->qp_txr = iavf_txr_alloc(sc, i); 2448 2449 if (qp->qp_rxr == NULL || qp->qp_txr == NULL) 2450 goto free; 2451 2452 qp->qp_si = softint_establish(SOFTINT_NET|SOFTINT_MPSAFE, 2453 iavf_handle_queue, qp); 2454 if (qp->qp_si == NULL) 2455 goto free; 2456 } 2457 2458 sc->sc_nqps_alloc = num; 2459 return 0; 2460 free: 2461 for (i = 0; i < num; i++) { 2462 qp = &sc->sc_qps[i]; 2463 2464 if (qp->qp_si != NULL) 2465 softint_disestablish(qp->qp_si); 2466 if (qp->qp_rxr != NULL) 2467 iavf_rxr_free(sc, qp->qp_rxr); 2468 if (qp->qp_txr != NULL) 2469 iavf_txr_free(sc, qp->qp_txr); 2470 } 2471 2472 kmem_free(sc->sc_qps, sizeof(sc->sc_qps[0]) * num); 2473 sc->sc_qps = NULL; 2474 2475 return -1; 2476 } 2477 2478 static void 2479 iavf_queue_pairs_free(struct iavf_softc *sc) 2480 { 2481 struct iavf_queue_pair *qp; 2482 unsigned int i; 2483 size_t sz; 2484 2485 if (sc->sc_qps == NULL) 2486 return; 2487 2488 for (i = 0; i < sc->sc_nqps_alloc; i++) { 2489 qp = &sc->sc_qps[i]; 2490 2491 if (qp->qp_si != NULL) 2492 softint_disestablish(qp->qp_si); 2493 if (qp->qp_rxr != NULL) 2494 iavf_rxr_free(sc, qp->qp_rxr); 2495 if (qp->qp_txr != NULL) 2496 iavf_txr_free(sc, qp->qp_txr); 2497 } 2498 2499 sz = sizeof(sc->sc_qps[0]) * sc->sc_nqps_alloc; 2500 kmem_free(sc->sc_qps, sz); 2501 sc->sc_qps = NULL; 2502 sc->sc_nqps_alloc = 0; 2503 } 2504 2505 static int 2506 iavf_rxfill(struct iavf_softc *sc, struct iavf_rx_ring *rxr) 2507 { 2508 struct ixl_rx_rd_desc_32 *ring, *rxd; 2509 struct iavf_rx_map *rxm; 2510 bus_dmamap_t map; 2511 struct mbuf *m; 2512 unsigned int slots, prod, mask; 2513 int error, post; 2514 2515 slots = ixl_rxr_unrefreshed(rxr->rxr_prod, rxr->rxr_cons, 2516 sc->sc_rx_ring_ndescs); 2517 2518 if (slots == 0) 2519 return 0; 2520 2521 error = 0; 2522 prod = rxr->rxr_prod; 2523 2524 ring = IXL_DMA_KVA(&rxr->rxr_mem); 2525 mask = sc->sc_rx_ring_ndescs - 1; 2526 2527 do { 2528 rxm = &rxr->rxr_maps[prod]; 2529 2530 MGETHDR(m, M_DONTWAIT, MT_DATA); 2531 if (m == NULL) { 2532 rxr->rxr_mgethdr_failed.ev_count++; 2533 error = -1; 2534 break; 2535 } 2536 2537 MCLGET(m, M_DONTWAIT); 2538 if (!ISSET(m->m_flags, M_EXT)) { 2539 rxr->rxr_mgetcl_failed.ev_count++; 2540 error = -1; 2541 m_freem(m); 2542 break; 2543 } 2544 2545 m->m_len = m->m_pkthdr.len = MCLBYTES; 2546 m_adj(m, ETHER_ALIGN); 2547 2548 map = rxm->rxm_map; 2549 2550 if (bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 2551 BUS_DMA_READ|BUS_DMA_NOWAIT) != 0) { 2552 rxr->rxr_mbuf_load_failed.ev_count++; 2553 error = -1; 2554 m_freem(m); 2555 break; 2556 } 2557 2558 rxm->rxm_m = m; 2559 2560 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 2561 BUS_DMASYNC_PREREAD); 2562 2563 rxd = &ring[prod]; 2564 rxd->paddr = htole64(map->dm_segs[0].ds_addr); 2565 rxd->haddr = htole64(0); 2566 2567 prod++; 2568 prod &= mask; 2569 post = 1; 2570 } while (--slots); 2571 2572 if (post) { 2573 rxr->rxr_prod = prod; 2574 iavf_wr(sc, rxr->rxr_tail, prod); 2575 } 2576 2577 return error; 2578 } 2579 2580 static inline void 2581 iavf_rx_csum(struct mbuf *m, uint64_t qword) 2582 { 2583 int flags_mask; 2584 2585 if (!ISSET(qword, IXL_RX_DESC_L3L4P)) { 2586 /* No L3 or L4 checksum was calculated */ 2587 return; 2588 } 2589 2590 switch (__SHIFTOUT(qword, IXL_RX_DESC_PTYPE_MASK)) { 2591 case IXL_RX_DESC_PTYPE_IPV4FRAG: 2592 case IXL_RX_DESC_PTYPE_IPV4: 2593 case IXL_RX_DESC_PTYPE_SCTPV4: 2594 case IXL_RX_DESC_PTYPE_ICMPV4: 2595 flags_mask = M_CSUM_IPv4 | M_CSUM_IPv4_BAD; 2596 break; 2597 case IXL_RX_DESC_PTYPE_TCPV4: 2598 flags_mask = M_CSUM_IPv4 | M_CSUM_IPv4_BAD; 2599 flags_mask |= M_CSUM_TCPv4 | M_CSUM_TCP_UDP_BAD; 2600 break; 2601 case IXL_RX_DESC_PTYPE_UDPV4: 2602 flags_mask = M_CSUM_IPv4 | M_CSUM_IPv4_BAD; 2603 flags_mask |= M_CSUM_UDPv4 | M_CSUM_TCP_UDP_BAD; 2604 break; 2605 case IXL_RX_DESC_PTYPE_TCPV6: 2606 flags_mask = M_CSUM_TCPv6 | M_CSUM_TCP_UDP_BAD; 2607 break; 2608 case IXL_RX_DESC_PTYPE_UDPV6: 2609 flags_mask = M_CSUM_UDPv6 | M_CSUM_TCP_UDP_BAD; 2610 break; 2611 default: 2612 flags_mask = 0; 2613 } 2614 2615 m->m_pkthdr.csum_flags |= (flags_mask & (M_CSUM_IPv4 | 2616 M_CSUM_TCPv4 | M_CSUM_TCPv6 | M_CSUM_UDPv4 | M_CSUM_UDPv6)); 2617 2618 if (ISSET(qword, IXL_RX_DESC_IPE)) { 2619 m->m_pkthdr.csum_flags |= (flags_mask & M_CSUM_IPv4_BAD); 2620 } 2621 2622 if (ISSET(qword, IXL_RX_DESC_L4E)) { 2623 m->m_pkthdr.csum_flags |= (flags_mask & M_CSUM_TCP_UDP_BAD); 2624 } 2625 } 2626 2627 static int 2628 iavf_rxeof(struct iavf_softc *sc, struct iavf_rx_ring *rxr, u_int rxlimit, 2629 struct evcnt *ecnt) 2630 { 2631 struct ifnet *ifp = &sc->sc_ec.ec_if; 2632 struct ixl_rx_wb_desc_32 *ring, *rxd; 2633 struct iavf_rx_map *rxm; 2634 bus_dmamap_t map; 2635 unsigned int cons, prod; 2636 struct mbuf *m; 2637 uint64_t word, word0; 2638 unsigned int len; 2639 unsigned int mask; 2640 int done = 0, more = 0; 2641 2642 KASSERT(mutex_owned(&rxr->rxr_lock)); 2643 2644 if (!ISSET(ifp->if_flags, IFF_RUNNING)) 2645 return 0; 2646 2647 prod = rxr->rxr_prod; 2648 cons = rxr->rxr_cons; 2649 2650 if (cons == prod) 2651 return 0; 2652 2653 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&rxr->rxr_mem), 2654 0, IXL_DMA_LEN(&rxr->rxr_mem), 2655 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2656 2657 ring = IXL_DMA_KVA(&rxr->rxr_mem); 2658 mask = sc->sc_rx_ring_ndescs - 1; 2659 2660 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 2661 2662 do { 2663 if (rxlimit-- <= 0) { 2664 more = 1; 2665 break; 2666 } 2667 2668 rxd = &ring[cons]; 2669 2670 word = le64toh(rxd->qword1); 2671 2672 if (!ISSET(word, IXL_RX_DESC_DD)) 2673 break; 2674 2675 rxm = &rxr->rxr_maps[cons]; 2676 2677 map = rxm->rxm_map; 2678 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 2679 BUS_DMASYNC_POSTREAD); 2680 bus_dmamap_unload(sc->sc_dmat, map); 2681 2682 m = rxm->rxm_m; 2683 rxm->rxm_m = NULL; 2684 2685 KASSERT(m != NULL); 2686 2687 len = (word & IXL_RX_DESC_PLEN_MASK) >> IXL_RX_DESC_PLEN_SHIFT; 2688 m->m_len = len; 2689 m->m_pkthdr.len = 0; 2690 2691 m->m_next = NULL; 2692 *rxr->rxr_m_tail = m; 2693 rxr->rxr_m_tail = &m->m_next; 2694 2695 m = rxr->rxr_m_head; 2696 m->m_pkthdr.len += len; 2697 2698 if (ISSET(word, IXL_RX_DESC_EOP)) { 2699 word0 = le64toh(rxd->qword0); 2700 2701 if (ISSET(word, IXL_RX_DESC_L2TAG1P)) { 2702 vlan_set_tag(m, 2703 __SHIFTOUT(word0, IXL_RX_DESC_L2TAG1_MASK)); 2704 } 2705 2706 if ((ifp->if_capenable & IAVF_IFCAP_RXCSUM) != 0) 2707 iavf_rx_csum(m, word); 2708 2709 if (!ISSET(word, 2710 IXL_RX_DESC_RXE | IXL_RX_DESC_OVERSIZE)) { 2711 m_set_rcvif(m, ifp); 2712 if_statinc_ref(nsr, if_ipackets); 2713 if_statadd_ref(nsr, if_ibytes, 2714 m->m_pkthdr.len); 2715 if_percpuq_enqueue(sc->sc_ipq, m); 2716 } else { 2717 if_statinc_ref(nsr, if_ierrors); 2718 m_freem(m); 2719 } 2720 2721 rxr->rxr_m_head = NULL; 2722 rxr->rxr_m_tail = &rxr->rxr_m_head; 2723 } 2724 2725 cons++; 2726 cons &= mask; 2727 2728 done = 1; 2729 } while (cons != prod); 2730 2731 if (done) { 2732 ecnt->ev_count++; 2733 rxr->rxr_cons = cons; 2734 if (iavf_rxfill(sc, rxr) == -1) 2735 if_statinc_ref(nsr, if_iqdrops); 2736 } 2737 2738 IF_STAT_PUTREF(ifp); 2739 2740 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&rxr->rxr_mem), 2741 0, IXL_DMA_LEN(&rxr->rxr_mem), 2742 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2743 2744 return more; 2745 } 2746 2747 static void 2748 iavf_rxr_clean(struct iavf_softc *sc, struct iavf_rx_ring *rxr) 2749 { 2750 struct iavf_rx_map *maps, *rxm; 2751 bus_dmamap_t map; 2752 unsigned int i; 2753 2754 KASSERT(mutex_owned(&rxr->rxr_lock)); 2755 2756 maps = rxr->rxr_maps; 2757 for (i = 0; i < sc->sc_rx_ring_ndescs; i++) { 2758 rxm = &maps[i]; 2759 2760 if (rxm->rxm_m == NULL) 2761 continue; 2762 2763 map = rxm->rxm_map; 2764 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 2765 BUS_DMASYNC_POSTWRITE); 2766 bus_dmamap_unload(sc->sc_dmat, map); 2767 2768 m_freem(rxm->rxm_m); 2769 rxm->rxm_m = NULL; 2770 } 2771 2772 m_freem(rxr->rxr_m_head); 2773 rxr->rxr_m_head = NULL; 2774 rxr->rxr_m_tail = &rxr->rxr_m_head; 2775 2776 memset(IXL_DMA_KVA(&rxr->rxr_mem), 0, IXL_DMA_LEN(&rxr->rxr_mem)); 2777 rxr->rxr_prod = rxr->rxr_cons = 0; 2778 } 2779 2780 static int 2781 iavf_txeof(struct iavf_softc *sc, struct iavf_tx_ring *txr, u_int txlimit, 2782 struct evcnt *ecnt) 2783 { 2784 struct ifnet *ifp = &sc->sc_ec.ec_if; 2785 struct ixl_tx_desc *ring, *txd; 2786 struct iavf_tx_map *txm; 2787 struct mbuf *m; 2788 bus_dmamap_t map; 2789 unsigned int cons, prod, last; 2790 unsigned int mask; 2791 uint64_t dtype; 2792 int done = 0, more = 0; 2793 2794 KASSERT(mutex_owned(&txr->txr_lock)); 2795 2796 prod = txr->txr_prod; 2797 cons = txr->txr_cons; 2798 2799 if (cons == prod) 2800 return 0; 2801 2802 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&txr->txr_mem), 2803 0, IXL_DMA_LEN(&txr->txr_mem), BUS_DMASYNC_POSTREAD); 2804 2805 ring = IXL_DMA_KVA(&txr->txr_mem); 2806 mask = sc->sc_tx_ring_ndescs - 1; 2807 2808 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 2809 2810 do { 2811 if (txlimit-- <= 0) { 2812 more = 1; 2813 break; 2814 } 2815 2816 txm = &txr->txr_maps[cons]; 2817 last = txm->txm_eop; 2818 txd = &ring[last]; 2819 2820 dtype = txd->cmd & htole64(IXL_TX_DESC_DTYPE_MASK); 2821 if (dtype != htole64(IXL_TX_DESC_DTYPE_DONE)) 2822 break; 2823 2824 map = txm->txm_map; 2825 2826 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 2827 BUS_DMASYNC_POSTWRITE); 2828 bus_dmamap_unload(sc->sc_dmat, map); 2829 2830 m = txm->txm_m; 2831 if (m != NULL) { 2832 if_statinc_ref(nsr, if_opackets); 2833 if_statadd_ref(nsr, if_obytes, m->m_pkthdr.len); 2834 if (ISSET(m->m_flags, M_MCAST)) 2835 if_statinc_ref(nsr, if_omcasts); 2836 m_freem(m); 2837 } 2838 2839 txm->txm_m = NULL; 2840 txm->txm_eop = -1; 2841 2842 cons = last + 1; 2843 cons &= mask; 2844 done = 1; 2845 } while (cons != prod); 2846 2847 IF_STAT_PUTREF(ifp); 2848 2849 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&txr->txr_mem), 2850 0, IXL_DMA_LEN(&txr->txr_mem), BUS_DMASYNC_PREREAD); 2851 2852 txr->txr_cons = cons; 2853 2854 if (done) { 2855 ecnt->ev_count++; 2856 softint_schedule(txr->txr_si); 2857 if (txr->txr_qid == 0) { 2858 CLR(ifp->if_flags, IFF_OACTIVE); 2859 if_schedule_deferred_start(ifp); 2860 } 2861 } 2862 2863 if (txr->txr_cons == txr->txr_prod) { 2864 txr->txr_watchdog = IAVF_WATCHDOG_STOP; 2865 } 2866 2867 return more; 2868 } 2869 2870 static inline int 2871 iavf_load_mbuf(bus_dma_tag_t dmat, bus_dmamap_t map, struct mbuf **m0, 2872 struct iavf_tx_ring *txr) 2873 { 2874 struct mbuf *m; 2875 int error; 2876 2877 KASSERT(mutex_owned(&txr->txr_lock)); 2878 2879 m = *m0; 2880 2881 error = bus_dmamap_load_mbuf(dmat, map, m, 2882 BUS_DMA_STREAMING|BUS_DMA_WRITE|BUS_DMA_NOWAIT); 2883 if (error != EFBIG) 2884 return error; 2885 2886 m = m_defrag(m, M_DONTWAIT); 2887 if (m != NULL) { 2888 *m0 = m; 2889 txr->txr_defragged.ev_count++; 2890 error = bus_dmamap_load_mbuf(dmat, map, m, 2891 BUS_DMA_STREAMING|BUS_DMA_WRITE|BUS_DMA_NOWAIT); 2892 } else { 2893 txr->txr_defrag_failed.ev_count++; 2894 error = ENOBUFS; 2895 } 2896 2897 return error; 2898 } 2899 2900 static inline int 2901 iavf_tx_setup_offloads(struct mbuf *m, uint64_t *cmd_txd) 2902 { 2903 struct ether_header *eh; 2904 size_t len; 2905 uint64_t cmd; 2906 2907 cmd = 0; 2908 2909 eh = mtod(m, struct ether_header *); 2910 switch (htons(eh->ether_type)) { 2911 case ETHERTYPE_IP: 2912 case ETHERTYPE_IPV6: 2913 len = ETHER_HDR_LEN; 2914 break; 2915 case ETHERTYPE_VLAN: 2916 len = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2917 break; 2918 default: 2919 len = 0; 2920 } 2921 cmd |= ((len >> 1) << IXL_TX_DESC_MACLEN_SHIFT); 2922 2923 if (m->m_pkthdr.csum_flags & 2924 (M_CSUM_TSOv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 2925 cmd |= IXL_TX_DESC_CMD_IIPT_IPV4; 2926 } 2927 if (m->m_pkthdr.csum_flags & M_CSUM_IPv4) { 2928 cmd |= IXL_TX_DESC_CMD_IIPT_IPV4_CSUM; 2929 } 2930 2931 if (m->m_pkthdr.csum_flags & 2932 (M_CSUM_TSOv6 | M_CSUM_TCPv6 | M_CSUM_UDPv6)) { 2933 cmd |= IXL_TX_DESC_CMD_IIPT_IPV6; 2934 } 2935 2936 switch (cmd & IXL_TX_DESC_CMD_IIPT_MASK) { 2937 case IXL_TX_DESC_CMD_IIPT_IPV4: 2938 case IXL_TX_DESC_CMD_IIPT_IPV4_CSUM: 2939 len = M_CSUM_DATA_IPv4_IPHL(m->m_pkthdr.csum_data); 2940 break; 2941 case IXL_TX_DESC_CMD_IIPT_IPV6: 2942 len = M_CSUM_DATA_IPv6_IPHL(m->m_pkthdr.csum_data); 2943 break; 2944 default: 2945 len = 0; 2946 } 2947 cmd |= ((len >> 2) << IXL_TX_DESC_IPLEN_SHIFT); 2948 2949 if (m->m_pkthdr.csum_flags & 2950 (M_CSUM_TSOv4 | M_CSUM_TSOv6 | M_CSUM_TCPv4 | M_CSUM_TCPv6)) { 2951 len = sizeof(struct tcphdr); 2952 cmd |= IXL_TX_DESC_CMD_L4T_EOFT_TCP; 2953 } else if (m->m_pkthdr.csum_flags & (M_CSUM_UDPv4 | M_CSUM_UDPv6)) { 2954 len = sizeof(struct udphdr); 2955 cmd |= IXL_TX_DESC_CMD_L4T_EOFT_UDP; 2956 } else { 2957 len = 0; 2958 } 2959 cmd |= ((len >> 2) << IXL_TX_DESC_L4LEN_SHIFT); 2960 2961 *cmd_txd |= cmd; 2962 return 0; 2963 } 2964 2965 static void 2966 iavf_tx_common_locked(struct ifnet *ifp, struct iavf_tx_ring *txr, 2967 bool is_transmit) 2968 { 2969 struct iavf_softc *sc; 2970 struct ixl_tx_desc *ring, *txd; 2971 struct iavf_tx_map *txm; 2972 bus_dmamap_t map; 2973 struct mbuf *m; 2974 unsigned int prod, free, last, i; 2975 unsigned int mask; 2976 uint64_t cmd, cmd_txd; 2977 int post = 0; 2978 2979 KASSERT(mutex_owned(&txr->txr_lock)); 2980 2981 sc = ifp->if_softc; 2982 2983 if (!ISSET(ifp->if_flags, IFF_RUNNING) 2984 || (!is_transmit && ISSET(ifp->if_flags, IFF_OACTIVE))) { 2985 if (!is_transmit) 2986 IFQ_PURGE(&ifp->if_snd); 2987 return; 2988 } 2989 2990 prod = txr->txr_prod; 2991 free = txr->txr_cons; 2992 2993 if (free <= prod) 2994 free += sc->sc_tx_ring_ndescs; 2995 free -= prod; 2996 2997 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&txr->txr_mem), 2998 0, IXL_DMA_LEN(&txr->txr_mem), BUS_DMASYNC_POSTWRITE); 2999 3000 ring = IXL_DMA_KVA(&txr->txr_mem); 3001 mask = sc->sc_tx_ring_ndescs - 1; 3002 last = prod; 3003 cmd = 0; 3004 txd = NULL; 3005 3006 for (;;) { 3007 if (free < IAVF_TX_PKT_DESCS) { 3008 if (!is_transmit) 3009 SET(ifp->if_flags, IFF_OACTIVE); 3010 break; 3011 } 3012 3013 if (is_transmit) 3014 m = pcq_get(txr->txr_intrq); 3015 else 3016 IFQ_DEQUEUE(&ifp->if_snd, m); 3017 3018 if (m == NULL) 3019 break; 3020 3021 txm = &txr->txr_maps[prod]; 3022 map = txm->txm_map; 3023 3024 if (iavf_load_mbuf(sc->sc_dmat, map, &m, txr) != 0) { 3025 if_statinc(ifp, if_oerrors); 3026 m_freem(m); 3027 continue; 3028 } 3029 3030 cmd_txd = 0; 3031 if (m->m_pkthdr.csum_flags & IAVF_CSUM_ALL_OFFLOAD) { 3032 iavf_tx_setup_offloads(m, &cmd_txd); 3033 } 3034 if (vlan_has_tag(m)) { 3035 cmd_txd |= IXL_TX_DESC_CMD_IL2TAG1 | 3036 ((uint64_t)vlan_get_tag(m) 3037 << IXL_TX_DESC_L2TAG1_SHIFT); 3038 } 3039 3040 bus_dmamap_sync(sc->sc_dmat, map, 0, 3041 map->dm_mapsize, BUS_DMASYNC_PREWRITE); 3042 3043 for (i = 0; i < (unsigned int)map->dm_nsegs; i++) { 3044 txd = &ring[prod]; 3045 3046 cmd = (uint64_t)map->dm_segs[i].ds_len << 3047 IXL_TX_DESC_BSIZE_SHIFT; 3048 cmd |= IXL_TX_DESC_DTYPE_DATA|IXL_TX_DESC_CMD_ICRC| 3049 cmd_txd; 3050 3051 txd->addr = htole64(map->dm_segs[i].ds_addr); 3052 txd->cmd = htole64(cmd); 3053 3054 last = prod; 3055 prod++; 3056 prod &= mask; 3057 } 3058 3059 cmd |= IXL_TX_DESC_CMD_EOP|IXL_TX_DESC_CMD_RS; 3060 txd->cmd = htole64(cmd); 3061 txm->txm_m = m; 3062 txm->txm_eop = last; 3063 3064 bpf_mtap(ifp, m, BPF_D_OUT); 3065 free -= i; 3066 post = 1; 3067 } 3068 3069 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&txr->txr_mem), 3070 0, IXL_DMA_LEN(&txr->txr_mem), BUS_DMASYNC_PREWRITE); 3071 3072 if (post) { 3073 txr->txr_prod = prod; 3074 iavf_wr(sc, txr->txr_tail, prod); 3075 txr->txr_watchdog = IAVF_WATCHDOG_TICKS; 3076 } 3077 } 3078 3079 static inline int 3080 iavf_handle_queue_common(struct iavf_softc *sc, struct iavf_queue_pair *qp, 3081 u_int txlimit, struct evcnt *txevcnt, 3082 u_int rxlimit, struct evcnt *rxevcnt) 3083 { 3084 struct iavf_tx_ring *txr; 3085 struct iavf_rx_ring *rxr; 3086 int txmore, rxmore; 3087 int rv; 3088 3089 txr = qp->qp_txr; 3090 rxr = qp->qp_rxr; 3091 3092 mutex_enter(&txr->txr_lock); 3093 txmore = iavf_txeof(sc, txr, txlimit, txevcnt); 3094 mutex_exit(&txr->txr_lock); 3095 3096 mutex_enter(&rxr->rxr_lock); 3097 rxmore = iavf_rxeof(sc, rxr, rxlimit, rxevcnt); 3098 mutex_exit(&rxr->rxr_lock); 3099 3100 rv = txmore | (rxmore << 1); 3101 3102 return rv; 3103 } 3104 3105 static void 3106 iavf_sched_handle_queue(struct iavf_softc *sc, struct iavf_queue_pair *qp) 3107 { 3108 3109 if (qp->qp_workqueue) 3110 workqueue_enqueue(sc->sc_workq_txrx, &qp->qp_work, NULL); 3111 else 3112 softint_schedule(qp->qp_si); 3113 } 3114 3115 static void 3116 iavf_start(struct ifnet *ifp) 3117 { 3118 struct iavf_softc *sc; 3119 struct iavf_tx_ring *txr; 3120 3121 sc = ifp->if_softc; 3122 txr = sc->sc_qps[0].qp_txr; 3123 3124 mutex_enter(&txr->txr_lock); 3125 iavf_tx_common_locked(ifp, txr, false); 3126 mutex_exit(&txr->txr_lock); 3127 3128 } 3129 3130 static inline unsigned int 3131 iavf_select_txqueue(struct iavf_softc *sc, struct mbuf *m) 3132 { 3133 u_int cpuid; 3134 3135 cpuid = cpu_index(curcpu()); 3136 3137 return (unsigned int)(cpuid % sc->sc_nqueue_pairs); 3138 } 3139 3140 static int 3141 iavf_transmit(struct ifnet *ifp, struct mbuf *m) 3142 { 3143 struct iavf_softc *sc; 3144 struct iavf_tx_ring *txr; 3145 unsigned int qid; 3146 3147 sc = ifp->if_softc; 3148 qid = iavf_select_txqueue(sc, m); 3149 3150 txr = sc->sc_qps[qid].qp_txr; 3151 3152 if (__predict_false(!pcq_put(txr->txr_intrq, m))) { 3153 mutex_enter(&txr->txr_lock); 3154 txr->txr_pcqdrop.ev_count++; 3155 mutex_exit(&txr->txr_lock); 3156 3157 m_freem(m); 3158 return ENOBUFS; 3159 } 3160 3161 if (mutex_tryenter(&txr->txr_lock)) { 3162 iavf_tx_common_locked(ifp, txr, true); 3163 mutex_exit(&txr->txr_lock); 3164 } else { 3165 kpreempt_disable(); 3166 softint_schedule(txr->txr_si); 3167 kpreempt_enable(); 3168 } 3169 return 0; 3170 } 3171 3172 static void 3173 iavf_deferred_transmit(void *xtxr) 3174 { 3175 struct iavf_tx_ring *txr; 3176 struct iavf_softc *sc; 3177 struct ifnet *ifp; 3178 3179 txr = xtxr; 3180 sc = txr->txr_sc; 3181 ifp = &sc->sc_ec.ec_if; 3182 3183 mutex_enter(&txr->txr_lock); 3184 txr->txr_transmitdef.ev_count++; 3185 if (pcq_peek(txr->txr_intrq) != NULL) 3186 iavf_tx_common_locked(ifp, txr, true); 3187 mutex_exit(&txr->txr_lock); 3188 } 3189 3190 static void 3191 iavf_txr_clean(struct iavf_softc *sc, struct iavf_tx_ring *txr) 3192 { 3193 struct iavf_tx_map *maps, *txm; 3194 bus_dmamap_t map; 3195 unsigned int i; 3196 3197 KASSERT(mutex_owned(&txr->txr_lock)); 3198 3199 maps = txr->txr_maps; 3200 for (i = 0; i < sc->sc_tx_ring_ndescs; i++) { 3201 txm = &maps[i]; 3202 3203 if (txm->txm_m == NULL) 3204 continue; 3205 3206 map = txm->txm_map; 3207 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 3208 BUS_DMASYNC_POSTWRITE); 3209 bus_dmamap_unload(sc->sc_dmat, map); 3210 3211 m_freem(txm->txm_m); 3212 txm->txm_m = NULL; 3213 } 3214 3215 memset(IXL_DMA_KVA(&txr->txr_mem), 0, IXL_DMA_LEN(&txr->txr_mem)); 3216 txr->txr_prod = txr->txr_cons = 0; 3217 } 3218 3219 static int 3220 iavf_intr(void *xsc) 3221 { 3222 struct iavf_softc *sc = xsc; 3223 struct ifnet *ifp = &sc->sc_ec.ec_if; 3224 struct iavf_rx_ring *rxr; 3225 struct iavf_tx_ring *txr; 3226 uint32_t icr; 3227 unsigned int i; 3228 3229 /* read I40E_VFINT_ICR_ENA1 to clear status */ 3230 (void)iavf_rd(sc, I40E_VFINT_ICR0_ENA1); 3231 3232 iavf_intr_enable(sc); 3233 icr = iavf_rd(sc, I40E_VFINT_ICR01); 3234 3235 if (icr == IAVF_REG_VFR) { 3236 log(LOG_INFO, "%s: VF reset in progress\n", 3237 ifp->if_xname); 3238 iavf_work_set(&sc->sc_reset_task, iavf_reset_start, sc); 3239 iavf_work_add(sc->sc_workq, &sc->sc_reset_task); 3240 return 1; 3241 } 3242 3243 if (ISSET(icr, I40E_VFINT_ICR01_ADMINQ_MASK)) { 3244 mutex_enter(&sc->sc_adminq_lock); 3245 iavf_atq_done(sc); 3246 iavf_arq(sc); 3247 mutex_exit(&sc->sc_adminq_lock); 3248 } 3249 3250 if (ISSET(icr, I40E_VFINT_ICR01_QUEUE_0_MASK)) { 3251 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 3252 rxr = sc->sc_qps[i].qp_rxr; 3253 txr = sc->sc_qps[i].qp_txr; 3254 3255 mutex_enter(&rxr->rxr_lock); 3256 while (iavf_rxeof(sc, rxr, UINT_MAX, 3257 &rxr->rxr_intr) != 0) { 3258 /* do nothing */ 3259 } 3260 mutex_exit(&rxr->rxr_lock); 3261 3262 mutex_enter(&txr->txr_lock); 3263 while (iavf_txeof(sc, txr, UINT_MAX, 3264 &txr->txr_intr) != 0) { 3265 /* do nothing */ 3266 } 3267 mutex_exit(&txr->txr_lock); 3268 } 3269 } 3270 3271 return 0; 3272 } 3273 3274 static int 3275 iavf_queue_intr(void *xqp) 3276 { 3277 struct iavf_queue_pair *qp = xqp; 3278 struct iavf_tx_ring *txr; 3279 struct iavf_rx_ring *rxr; 3280 struct iavf_softc *sc; 3281 unsigned int qid; 3282 u_int txlimit, rxlimit; 3283 int more; 3284 3285 txr = qp->qp_txr; 3286 rxr = qp->qp_rxr; 3287 sc = txr->txr_sc; 3288 qid = txr->txr_qid; 3289 3290 txlimit = sc->sc_tx_intr_process_limit; 3291 rxlimit = sc->sc_rx_intr_process_limit; 3292 qp->qp_workqueue = sc->sc_txrx_workqueue; 3293 3294 more = iavf_handle_queue_common(sc, qp, 3295 txlimit, &txr->txr_intr, rxlimit, &rxr->rxr_intr); 3296 3297 if (more != 0) { 3298 iavf_sched_handle_queue(sc, qp); 3299 } else { 3300 /* for ALTQ */ 3301 if (txr->txr_qid == 0) 3302 if_schedule_deferred_start(&sc->sc_ec.ec_if); 3303 softint_schedule(txr->txr_si); 3304 3305 iavf_queue_intr_enable(sc, qid); 3306 } 3307 3308 return 0; 3309 } 3310 3311 static void 3312 iavf_handle_queue_wk(struct work *wk, void *xsc __unused) 3313 { 3314 struct iavf_queue_pair *qp; 3315 3316 qp = container_of(wk, struct iavf_queue_pair, qp_work); 3317 iavf_handle_queue(qp); 3318 } 3319 3320 static void 3321 iavf_handle_queue(void *xqp) 3322 { 3323 struct iavf_queue_pair *qp = xqp; 3324 struct iavf_tx_ring *txr; 3325 struct iavf_rx_ring *rxr; 3326 struct iavf_softc *sc; 3327 unsigned int qid; 3328 u_int txlimit, rxlimit; 3329 int more; 3330 3331 txr = qp->qp_txr; 3332 rxr = qp->qp_rxr; 3333 sc = txr->txr_sc; 3334 qid = txr->txr_qid; 3335 3336 txlimit = sc->sc_tx_process_limit; 3337 rxlimit = sc->sc_rx_process_limit; 3338 3339 more = iavf_handle_queue_common(sc, qp, 3340 txlimit, &txr->txr_defer, rxlimit, &rxr->rxr_defer); 3341 3342 if (more != 0) 3343 iavf_sched_handle_queue(sc, qp); 3344 else 3345 iavf_queue_intr_enable(sc, qid); 3346 } 3347 3348 static void 3349 iavf_tick(void *xsc) 3350 { 3351 struct iavf_softc *sc; 3352 unsigned int i; 3353 int timedout; 3354 3355 sc = xsc; 3356 timedout = 0; 3357 3358 mutex_enter(&sc->sc_cfg_lock); 3359 3360 if (sc->sc_resetting) { 3361 iavf_work_add(sc->sc_workq, &sc->sc_reset_task); 3362 mutex_exit(&sc->sc_cfg_lock); 3363 return; 3364 } 3365 3366 iavf_get_stats(sc); 3367 3368 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 3369 timedout |= iavf_watchdog(sc->sc_qps[i].qp_txr); 3370 } 3371 3372 if (timedout != 0) { 3373 iavf_work_add(sc->sc_workq, &sc->sc_wdto_task); 3374 } else { 3375 callout_schedule(&sc->sc_tick, IAVF_TICK_INTERVAL); 3376 } 3377 3378 mutex_exit(&sc->sc_cfg_lock); 3379 } 3380 3381 static void 3382 iavf_tick_halt(void *unused __unused) 3383 { 3384 3385 /* do nothing */ 3386 } 3387 3388 static void 3389 iavf_reset_request(void *xsc) 3390 { 3391 struct iavf_softc *sc = xsc; 3392 3393 iavf_reset_vf(sc); 3394 iavf_reset_start(sc); 3395 } 3396 3397 static void 3398 iavf_reset_start(void *xsc) 3399 { 3400 struct iavf_softc *sc = xsc; 3401 struct ifnet *ifp = &sc->sc_ec.ec_if; 3402 3403 mutex_enter(&sc->sc_cfg_lock); 3404 3405 if (sc->sc_resetting) 3406 goto do_reset; 3407 3408 sc->sc_resetting = true; 3409 if_link_state_change(ifp, LINK_STATE_DOWN); 3410 3411 if (ISSET(ifp->if_flags, IFF_RUNNING)) { 3412 iavf_stop_locked(sc); 3413 sc->sc_reset_up = true; 3414 } 3415 3416 memcpy(sc->sc_enaddr_reset, sc->sc_enaddr, ETHER_ADDR_LEN); 3417 3418 do_reset: 3419 iavf_work_set(&sc->sc_reset_task, iavf_reset, sc); 3420 3421 mutex_exit(&sc->sc_cfg_lock); 3422 3423 iavf_reset((void *)sc); 3424 } 3425 3426 static void 3427 iavf_reset(void *xsc) 3428 { 3429 struct iavf_softc *sc = xsc; 3430 struct ifnet *ifp = &sc->sc_ec.ec_if; 3431 struct ixl_aq_buf *aqb; 3432 bool realloc_qps, realloc_intrs; 3433 3434 mutex_enter(&sc->sc_cfg_lock); 3435 3436 mutex_enter(&sc->sc_adminq_lock); 3437 iavf_cleanup_admin_queue(sc); 3438 mutex_exit(&sc->sc_adminq_lock); 3439 3440 sc->sc_major_ver = UINT_MAX; 3441 sc->sc_minor_ver = UINT_MAX; 3442 sc->sc_got_vf_resources = 0; 3443 sc->sc_got_irq_map = 0; 3444 3445 aqb = iavf_aqb_get(sc, &sc->sc_atq_idle); 3446 if (aqb == NULL) 3447 goto failed; 3448 3449 if (iavf_wait_active(sc) != 0) { 3450 log(LOG_WARNING, "%s: VF reset timed out\n", 3451 ifp->if_xname); 3452 goto failed; 3453 } 3454 3455 if (!iavf_arq_fill(sc)) { 3456 log(LOG_ERR, "%s: unable to fill arq descriptors\n", 3457 ifp->if_xname); 3458 goto failed; 3459 } 3460 3461 if (iavf_init_admin_queue(sc) != 0) { 3462 log(LOG_ERR, "%s: unable to initialize admin queue\n", 3463 ifp->if_xname); 3464 goto failed; 3465 } 3466 3467 if (iavf_get_version(sc, aqb) != 0) { 3468 log(LOG_ERR, "%s: unable to get VF interface version\n", 3469 ifp->if_xname); 3470 goto failed; 3471 } 3472 3473 if (iavf_get_vf_resources(sc, aqb) != 0) { 3474 log(LOG_ERR, "%s: timed out waiting for VF resources\n", 3475 ifp->if_xname); 3476 goto failed; 3477 } 3478 3479 if (sc->sc_nqps_alloc < iavf_calc_queue_pair_size(sc)) { 3480 realloc_qps = true; 3481 } else { 3482 realloc_qps = false; 3483 } 3484 3485 if (sc->sc_nintrs < iavf_calc_msix_count(sc)) { 3486 realloc_intrs = true; 3487 } else { 3488 realloc_intrs = false; 3489 } 3490 3491 if (realloc_qps || realloc_intrs) 3492 iavf_teardown_interrupts(sc); 3493 3494 if (realloc_qps) { 3495 iavf_queue_pairs_free(sc); 3496 if (iavf_queue_pairs_alloc(sc) != 0) { 3497 log(LOG_ERR, "%s: failed to allocate queue pairs\n", 3498 ifp->if_xname); 3499 goto failed; 3500 } 3501 } 3502 3503 if (realloc_qps || realloc_intrs) { 3504 if (iavf_setup_interrupts(sc) != 0) { 3505 sc->sc_nintrs = 0; 3506 log(LOG_ERR, "%s: failed to allocate interrupts\n", 3507 ifp->if_xname); 3508 goto failed; 3509 } 3510 log(LOG_INFO, "%s: reallocated queues\n", ifp->if_xname); 3511 } 3512 3513 if (iavf_config_irq_map(sc, aqb) != 0) { 3514 log(LOG_ERR, "%s: timed out configuring IRQ map\n", 3515 ifp->if_xname); 3516 goto failed; 3517 } 3518 3519 mutex_enter(&sc->sc_adminq_lock); 3520 iavf_aqb_put_locked(&sc->sc_atq_idle, aqb); 3521 mutex_exit(&sc->sc_adminq_lock); 3522 3523 iavf_reset_finish(sc); 3524 3525 mutex_exit(&sc->sc_cfg_lock); 3526 return; 3527 3528 failed: 3529 mutex_enter(&sc->sc_adminq_lock); 3530 iavf_cleanup_admin_queue(sc); 3531 if (aqb != NULL) { 3532 iavf_aqb_put_locked(&sc->sc_atq_idle, aqb); 3533 } 3534 mutex_exit(&sc->sc_adminq_lock); 3535 callout_schedule(&sc->sc_tick, IAVF_TICK_INTERVAL); 3536 mutex_exit(&sc->sc_cfg_lock); 3537 } 3538 3539 static void 3540 iavf_reset_finish(struct iavf_softc *sc) 3541 { 3542 struct ethercom *ec = &sc->sc_ec; 3543 struct ether_multi *enm; 3544 struct ether_multistep step; 3545 struct ifnet *ifp = &ec->ec_if; 3546 struct vlanid_list *vlanidp; 3547 uint8_t enaddr_prev[ETHER_ADDR_LEN], enaddr_next[ETHER_ADDR_LEN]; 3548 3549 KASSERT(mutex_owned(&sc->sc_cfg_lock)); 3550 3551 callout_stop(&sc->sc_tick); 3552 3553 iavf_intr_enable(sc); 3554 3555 if (!iavf_is_etheranyaddr(sc->sc_enaddr_added)) { 3556 iavf_eth_addr(sc, sc->sc_enaddr_added, IAVF_VC_OP_ADD_ETH_ADDR); 3557 } 3558 3559 ETHER_LOCK(ec); 3560 if (!ISSET(ifp->if_flags, IFF_ALLMULTI)) { 3561 for (ETHER_FIRST_MULTI(step, ec, enm); enm != NULL; 3562 ETHER_NEXT_MULTI(step, enm)) { 3563 iavf_add_multi(sc, enm->enm_addrlo, enm->enm_addrhi); 3564 } 3565 } 3566 3567 SIMPLEQ_FOREACH(vlanidp, &ec->ec_vids, vid_list) { 3568 ETHER_UNLOCK(ec); 3569 iavf_config_vlan_id(sc, vlanidp->vid, IAVF_VC_OP_ADD_VLAN); 3570 ETHER_LOCK(ec); 3571 } 3572 ETHER_UNLOCK(ec); 3573 3574 if (memcmp(sc->sc_enaddr, sc->sc_enaddr_reset, ETHER_ADDR_LEN) != 0) { 3575 memcpy(enaddr_prev, sc->sc_enaddr_reset, sizeof(enaddr_prev)); 3576 memcpy(enaddr_next, sc->sc_enaddr, sizeof(enaddr_next)); 3577 log(LOG_INFO, "%s: Ethernet address changed to %s\n", 3578 ifp->if_xname, ether_sprintf(enaddr_next)); 3579 3580 mutex_exit(&sc->sc_cfg_lock); 3581 IFNET_LOCK(ifp); 3582 kpreempt_disable(); 3583 /*XXX we need an API to change ethernet address. */ 3584 iavf_replace_lla(ifp, enaddr_prev, enaddr_next); 3585 kpreempt_enable(); 3586 IFNET_UNLOCK(ifp); 3587 mutex_enter(&sc->sc_cfg_lock); 3588 } 3589 3590 sc->sc_resetting = false; 3591 3592 if (sc->sc_reset_up) { 3593 iavf_init_locked(sc); 3594 } 3595 3596 if (sc->sc_link_state != LINK_STATE_DOWN) { 3597 if_link_state_change(ifp, sc->sc_link_state); 3598 } 3599 3600 } 3601 3602 static int 3603 iavf_dmamem_alloc(bus_dma_tag_t dmat, struct ixl_dmamem *ixm, 3604 bus_size_t size, bus_size_t align) 3605 { 3606 ixm->ixm_size = size; 3607 3608 if (bus_dmamap_create(dmat, ixm->ixm_size, 1, 3609 ixm->ixm_size, 0, 3610 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 3611 &ixm->ixm_map) != 0) 3612 return 1; 3613 if (bus_dmamem_alloc(dmat, ixm->ixm_size, 3614 align, 0, &ixm->ixm_seg, 1, &ixm->ixm_nsegs, 3615 BUS_DMA_WAITOK) != 0) 3616 goto destroy; 3617 if (bus_dmamem_map(dmat, &ixm->ixm_seg, ixm->ixm_nsegs, 3618 ixm->ixm_size, &ixm->ixm_kva, BUS_DMA_WAITOK) != 0) 3619 goto free; 3620 if (bus_dmamap_load(dmat, ixm->ixm_map, ixm->ixm_kva, 3621 ixm->ixm_size, NULL, BUS_DMA_WAITOK) != 0) 3622 goto unmap; 3623 3624 memset(ixm->ixm_kva, 0, ixm->ixm_size); 3625 3626 return 0; 3627 unmap: 3628 bus_dmamem_unmap(dmat, ixm->ixm_kva, ixm->ixm_size); 3629 free: 3630 bus_dmamem_free(dmat, &ixm->ixm_seg, 1); 3631 destroy: 3632 bus_dmamap_destroy(dmat, ixm->ixm_map); 3633 return 1; 3634 } 3635 3636 static void 3637 iavf_dmamem_free(bus_dma_tag_t dmat, struct ixl_dmamem *ixm) 3638 { 3639 3640 bus_dmamap_unload(dmat, ixm->ixm_map); 3641 bus_dmamem_unmap(dmat, ixm->ixm_kva, ixm->ixm_size); 3642 bus_dmamem_free(dmat, &ixm->ixm_seg, 1); 3643 bus_dmamap_destroy(dmat, ixm->ixm_map); 3644 } 3645 3646 static struct ixl_aq_buf * 3647 iavf_aqb_alloc(bus_dma_tag_t dmat, size_t buflen) 3648 { 3649 struct ixl_aq_buf *aqb; 3650 3651 aqb = kmem_alloc(sizeof(*aqb), KM_NOSLEEP); 3652 if (aqb == NULL) 3653 return NULL; 3654 3655 aqb->aqb_size = buflen; 3656 3657 if (bus_dmamap_create(dmat, aqb->aqb_size, 1, 3658 aqb->aqb_size, 0, 3659 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, &aqb->aqb_map) != 0) 3660 goto free; 3661 if (bus_dmamem_alloc(dmat, aqb->aqb_size, 3662 IAVF_AQ_ALIGN, 0, &aqb->aqb_seg, 1, &aqb->aqb_nsegs, 3663 BUS_DMA_WAITOK) != 0) 3664 goto destroy; 3665 if (bus_dmamem_map(dmat, &aqb->aqb_seg, aqb->aqb_nsegs, 3666 aqb->aqb_size, &aqb->aqb_data, BUS_DMA_WAITOK) != 0) 3667 goto dma_free; 3668 if (bus_dmamap_load(dmat, aqb->aqb_map, aqb->aqb_data, 3669 aqb->aqb_size, NULL, BUS_DMA_WAITOK) != 0) 3670 goto unmap; 3671 3672 return aqb; 3673 unmap: 3674 bus_dmamem_unmap(dmat, aqb->aqb_data, aqb->aqb_size); 3675 dma_free: 3676 bus_dmamem_free(dmat, &aqb->aqb_seg, 1); 3677 destroy: 3678 bus_dmamap_destroy(dmat, aqb->aqb_map); 3679 free: 3680 kmem_free(aqb, sizeof(*aqb)); 3681 3682 return NULL; 3683 } 3684 3685 static void 3686 iavf_aqb_free(bus_dma_tag_t dmat, struct ixl_aq_buf *aqb) 3687 { 3688 3689 bus_dmamap_unload(dmat, aqb->aqb_map); 3690 bus_dmamem_unmap(dmat, aqb->aqb_data, aqb->aqb_size); 3691 bus_dmamem_free(dmat, &aqb->aqb_seg, 1); 3692 bus_dmamap_destroy(dmat, aqb->aqb_map); 3693 kmem_free(aqb, sizeof(*aqb)); 3694 } 3695 3696 static struct ixl_aq_buf * 3697 iavf_aqb_get_locked(struct ixl_aq_bufs *q) 3698 { 3699 struct ixl_aq_buf *aqb; 3700 3701 aqb = SIMPLEQ_FIRST(q); 3702 if (aqb != NULL) { 3703 SIMPLEQ_REMOVE(q, aqb, ixl_aq_buf, aqb_entry); 3704 } 3705 3706 return aqb; 3707 } 3708 3709 static struct ixl_aq_buf * 3710 iavf_aqb_get(struct iavf_softc *sc, struct ixl_aq_bufs *q) 3711 { 3712 struct ixl_aq_buf *aqb; 3713 3714 if (q != NULL) { 3715 mutex_enter(&sc->sc_adminq_lock); 3716 aqb = iavf_aqb_get_locked(q); 3717 mutex_exit(&sc->sc_adminq_lock); 3718 } else { 3719 aqb = NULL; 3720 } 3721 3722 if (aqb == NULL) { 3723 aqb = iavf_aqb_alloc(sc->sc_dmat, IAVF_AQ_BUFLEN); 3724 } 3725 3726 return aqb; 3727 } 3728 3729 static void 3730 iavf_aqb_put_locked(struct ixl_aq_bufs *q, struct ixl_aq_buf *aqb) 3731 { 3732 3733 SIMPLEQ_INSERT_TAIL(q, aqb, aqb_entry); 3734 } 3735 3736 static void 3737 iavf_aqb_clean(struct ixl_aq_bufs *q, bus_dma_tag_t dmat) 3738 { 3739 struct ixl_aq_buf *aqb; 3740 3741 while ((aqb = SIMPLEQ_FIRST(q)) != NULL) { 3742 SIMPLEQ_REMOVE(q, aqb, ixl_aq_buf, aqb_entry); 3743 iavf_aqb_free(dmat, aqb); 3744 } 3745 } 3746 3747 static const char * 3748 iavf_aq_vc_opcode_str(const struct ixl_aq_desc *iaq) 3749 { 3750 3751 switch (iavf_aq_vc_get_opcode(iaq)) { 3752 case IAVF_VC_OP_VERSION: 3753 return "GET_VERSION"; 3754 case IAVF_VC_OP_RESET_VF: 3755 return "RESET_VF"; 3756 case IAVF_VC_OP_GET_VF_RESOURCES: 3757 return "GET_VF_RESOURCES"; 3758 case IAVF_VC_OP_CONFIG_TX_QUEUE: 3759 return "CONFIG_TX_QUEUE"; 3760 case IAVF_VC_OP_CONFIG_RX_QUEUE: 3761 return "CONFIG_RX_QUEUE"; 3762 case IAVF_VC_OP_CONFIG_VSI_QUEUES: 3763 return "CONFIG_VSI_QUEUES"; 3764 case IAVF_VC_OP_CONFIG_IRQ_MAP: 3765 return "CONFIG_IRQ_MAP"; 3766 case IAVF_VC_OP_ENABLE_QUEUES: 3767 return "ENABLE_QUEUES"; 3768 case IAVF_VC_OP_DISABLE_QUEUES: 3769 return "DISABLE_QUEUES"; 3770 case IAVF_VC_OP_ADD_ETH_ADDR: 3771 return "ADD_ETH_ADDR"; 3772 case IAVF_VC_OP_DEL_ETH_ADDR: 3773 return "DEL_ETH_ADDR"; 3774 case IAVF_VC_OP_CONFIG_PROMISC: 3775 return "CONFIG_PROMISC"; 3776 case IAVF_VC_OP_GET_STATS: 3777 return "GET_STATS"; 3778 case IAVF_VC_OP_EVENT: 3779 return "EVENT"; 3780 case IAVF_VC_OP_CONFIG_RSS_KEY: 3781 return "CONFIG_RSS_KEY"; 3782 case IAVF_VC_OP_CONFIG_RSS_LUT: 3783 return "CONFIG_RSS_LUT"; 3784 case IAVF_VC_OP_GET_RSS_HENA_CAPS: 3785 return "GET_RS_HENA_CAPS"; 3786 case IAVF_VC_OP_SET_RSS_HENA: 3787 return "SET_RSS_HENA"; 3788 case IAVF_VC_OP_ENABLE_VLAN_STRIP: 3789 return "ENABLE_VLAN_STRIPPING"; 3790 case IAVF_VC_OP_DISABLE_VLAN_STRIP: 3791 return "DISABLE_VLAN_STRIPPING"; 3792 case IAVF_VC_OP_REQUEST_QUEUES: 3793 return "REQUEST_QUEUES"; 3794 } 3795 3796 return "unknown"; 3797 } 3798 3799 static void 3800 iavf_aq_dump(const struct iavf_softc *sc, const struct ixl_aq_desc *iaq, 3801 const char *msg) 3802 { 3803 char buf[512]; 3804 size_t len; 3805 3806 len = sizeof(buf); 3807 buf[--len] = '\0'; 3808 3809 device_printf(sc->sc_dev, "%s\n", msg); 3810 snprintb(buf, len, IXL_AQ_FLAGS_FMT, le16toh(iaq->iaq_flags)); 3811 device_printf(sc->sc_dev, "flags %s opcode %04x\n", 3812 buf, le16toh(iaq->iaq_opcode)); 3813 device_printf(sc->sc_dev, "datalen %u retval %u\n", 3814 le16toh(iaq->iaq_datalen), le16toh(iaq->iaq_retval)); 3815 device_printf(sc->sc_dev, "vc-opcode %u (%s)\n", 3816 iavf_aq_vc_get_opcode(iaq), 3817 iavf_aq_vc_opcode_str(iaq)); 3818 device_printf(sc->sc_dev, "vc-retval %u\n", 3819 iavf_aq_vc_get_retval(iaq)); 3820 device_printf(sc->sc_dev, "cookie %016" PRIx64 "\n", iaq->iaq_cookie); 3821 device_printf(sc->sc_dev, "%08x %08x %08x %08x\n", 3822 le32toh(iaq->iaq_param[0]), le32toh(iaq->iaq_param[1]), 3823 le32toh(iaq->iaq_param[2]), le32toh(iaq->iaq_param[3])); 3824 } 3825 3826 static int 3827 iavf_arq_fill(struct iavf_softc *sc) 3828 { 3829 struct ixl_aq_buf *aqb; 3830 struct ixl_aq_desc *arq, *iaq; 3831 unsigned int prod = sc->sc_arq_prod; 3832 unsigned int n; 3833 int filled; 3834 3835 n = ixl_rxr_unrefreshed(sc->sc_arq_prod, sc->sc_arq_cons, 3836 IAVF_AQ_NUM); 3837 3838 if (__predict_false(n <= 0)) 3839 return 0; 3840 3841 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_arq), 3842 0, IXL_DMA_LEN(&sc->sc_arq), 3843 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3844 3845 arq = IXL_DMA_KVA(&sc->sc_arq); 3846 3847 do { 3848 iaq = &arq[prod]; 3849 3850 if (ixl_aq_has_dva(iaq)) { 3851 /* already filled */ 3852 break; 3853 } 3854 3855 aqb = iavf_aqb_get_locked(&sc->sc_arq_idle); 3856 if (aqb == NULL) 3857 break; 3858 3859 memset(aqb->aqb_data, 0, aqb->aqb_size); 3860 3861 bus_dmamap_sync(sc->sc_dmat, aqb->aqb_map, 0, 3862 aqb->aqb_size, BUS_DMASYNC_PREREAD); 3863 3864 iaq->iaq_flags = htole16(IXL_AQ_BUF | 3865 (aqb->aqb_size > I40E_AQ_LARGE_BUF ? 3866 IXL_AQ_LB : 0)); 3867 iaq->iaq_opcode = 0; 3868 iaq->iaq_datalen = htole16(aqb->aqb_size); 3869 iaq->iaq_retval = 0; 3870 iaq->iaq_cookie = 0; 3871 iaq->iaq_param[0] = 0; 3872 iaq->iaq_param[1] = 0; 3873 ixl_aq_dva(iaq, IXL_AQB_DVA(aqb)); 3874 iavf_aqb_put_locked(&sc->sc_arq_live, aqb); 3875 3876 prod++; 3877 prod &= IAVF_AQ_MASK; 3878 filled = 1; 3879 } while (--n); 3880 3881 sc->sc_arq_prod = prod; 3882 3883 if (filled) { 3884 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_arq), 3885 0, IXL_DMA_LEN(&sc->sc_arq), 3886 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3887 iavf_wr(sc, sc->sc_aq_regs->arq_tail, sc->sc_arq_prod); 3888 } 3889 3890 return filled; 3891 } 3892 3893 static int 3894 iavf_arq_wait(struct iavf_softc *sc, uint32_t opcode) 3895 { 3896 int error; 3897 3898 KASSERT(mutex_owned(&sc->sc_adminq_lock)); 3899 3900 while ((error = cv_timedwait(&sc->sc_adminq_cv, 3901 &sc->sc_adminq_lock, mstohz(IAVF_EXEC_TIMEOUT))) == 0) { 3902 if (opcode == sc->sc_arq_opcode) 3903 break; 3904 } 3905 3906 if (error != 0 && 3907 atomic_load_relaxed(&sc->sc_debuglevel) >= 2) 3908 device_printf(sc->sc_dev, "cv_timedwait error=%d\n", error); 3909 3910 return error; 3911 } 3912 3913 static void 3914 iavf_arq_refill(void *xsc) 3915 { 3916 struct iavf_softc *sc = xsc; 3917 struct ixl_aq_bufs aqbs; 3918 struct ixl_aq_buf *aqb; 3919 unsigned int n, i; 3920 3921 mutex_enter(&sc->sc_adminq_lock); 3922 iavf_arq_fill(sc); 3923 n = ixl_rxr_unrefreshed(sc->sc_arq_prod, sc->sc_arq_cons, 3924 IAVF_AQ_NUM); 3925 mutex_exit(&sc->sc_adminq_lock); 3926 3927 if (n == 0) 3928 return; 3929 3930 if (atomic_load_relaxed(&sc->sc_debuglevel) >= 1) 3931 device_printf(sc->sc_dev, "Allocate %d bufs for arq\n", n); 3932 3933 SIMPLEQ_INIT(&aqbs); 3934 for (i = 0; i < n; i++) { 3935 aqb = iavf_aqb_get(sc, NULL); 3936 if (aqb == NULL) 3937 continue; 3938 SIMPLEQ_INSERT_TAIL(&aqbs, aqb, aqb_entry); 3939 } 3940 3941 mutex_enter(&sc->sc_adminq_lock); 3942 while ((aqb = SIMPLEQ_FIRST(&aqbs)) != NULL) { 3943 SIMPLEQ_REMOVE(&aqbs, aqb, ixl_aq_buf, aqb_entry); 3944 iavf_aqb_put_locked(&sc->sc_arq_idle, aqb); 3945 } 3946 iavf_arq_fill(sc); 3947 mutex_exit(&sc->sc_adminq_lock); 3948 } 3949 3950 static uint32_t 3951 iavf_process_arq(struct iavf_softc *sc, struct ixl_aq_desc *iaq, 3952 struct ixl_aq_buf *aqb) 3953 { 3954 uint32_t vc_retval, vc_opcode; 3955 int dbg; 3956 3957 dbg = atomic_load_relaxed(&sc->sc_debuglevel); 3958 if (dbg >= 3) 3959 iavf_aq_dump(sc, iaq, "arq proc"); 3960 3961 if (dbg >= 2) { 3962 vc_retval = iavf_aq_vc_get_retval(iaq); 3963 if (vc_retval != IAVF_VC_RC_SUCCESS) { 3964 device_printf(sc->sc_dev, "%s failed=%d(arq)\n", 3965 iavf_aq_vc_opcode_str(iaq), vc_retval); 3966 } 3967 } 3968 3969 vc_opcode = iavf_aq_vc_get_opcode(iaq); 3970 switch (vc_opcode) { 3971 case IAVF_VC_OP_VERSION: 3972 iavf_process_version(sc, iaq, aqb); 3973 break; 3974 case IAVF_VC_OP_GET_VF_RESOURCES: 3975 iavf_process_vf_resources(sc, iaq, aqb); 3976 break; 3977 case IAVF_VC_OP_CONFIG_IRQ_MAP: 3978 iavf_process_irq_map(sc, iaq); 3979 break; 3980 case IAVF_VC_OP_EVENT: 3981 iavf_process_vc_event(sc, iaq, aqb); 3982 break; 3983 case IAVF_VC_OP_GET_STATS: 3984 iavf_process_stats(sc, iaq, aqb); 3985 break; 3986 case IAVF_VC_OP_REQUEST_QUEUES: 3987 iavf_process_req_queues(sc, iaq, aqb); 3988 break; 3989 } 3990 3991 return vc_opcode; 3992 } 3993 3994 static int 3995 iavf_arq_poll(struct iavf_softc *sc, uint32_t wait_opcode, int retry) 3996 { 3997 struct ixl_aq_desc *arq, *iaq; 3998 struct ixl_aq_buf *aqb; 3999 unsigned int cons = sc->sc_arq_cons; 4000 unsigned int prod; 4001 uint32_t vc_opcode; 4002 bool received; 4003 int i; 4004 4005 for (i = 0, received = false; i < retry && !received; i++) { 4006 prod = iavf_rd(sc, sc->sc_aq_regs->arq_head); 4007 prod &= sc->sc_aq_regs->arq_head_mask; 4008 4009 if (prod == cons) { 4010 delaymsec(1); 4011 continue; 4012 } 4013 4014 if (prod >= IAVF_AQ_NUM) { 4015 return EIO; 4016 } 4017 4018 arq = IXL_DMA_KVA(&sc->sc_arq); 4019 4020 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_arq), 4021 0, IXL_DMA_LEN(&sc->sc_arq), 4022 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4023 4024 do { 4025 iaq = &arq[cons]; 4026 aqb = iavf_aqb_get_locked(&sc->sc_arq_live); 4027 KASSERT(aqb != NULL); 4028 4029 bus_dmamap_sync(sc->sc_dmat, aqb->aqb_map, 0, 4030 IAVF_AQ_BUFLEN, BUS_DMASYNC_POSTREAD); 4031 4032 vc_opcode = iavf_process_arq(sc, iaq, aqb); 4033 4034 if (vc_opcode == wait_opcode) 4035 received = true; 4036 4037 memset(iaq, 0, sizeof(*iaq)); 4038 iavf_aqb_put_locked(&sc->sc_arq_idle, aqb); 4039 4040 cons++; 4041 cons &= IAVF_AQ_MASK; 4042 4043 } while (cons != prod); 4044 4045 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_arq), 4046 0, IXL_DMA_LEN(&sc->sc_arq), 4047 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 4048 4049 sc->sc_arq_cons = cons; 4050 iavf_arq_fill(sc); 4051 4052 } 4053 4054 if (!received) 4055 return ETIMEDOUT; 4056 4057 return 0; 4058 } 4059 4060 static int 4061 iavf_arq(struct iavf_softc *sc) 4062 { 4063 struct ixl_aq_desc *arq, *iaq; 4064 struct ixl_aq_buf *aqb; 4065 unsigned int cons = sc->sc_arq_cons; 4066 unsigned int prod; 4067 uint32_t vc_opcode; 4068 4069 KASSERT(mutex_owned(&sc->sc_adminq_lock)); 4070 4071 prod = iavf_rd(sc, sc->sc_aq_regs->arq_head); 4072 prod &= sc->sc_aq_regs->arq_head_mask; 4073 4074 /* broken value at resetting */ 4075 if (prod >= IAVF_AQ_NUM) { 4076 iavf_work_set(&sc->sc_reset_task, iavf_reset_start, sc); 4077 iavf_work_add(sc->sc_workq, &sc->sc_reset_task); 4078 return 0; 4079 } 4080 4081 if (cons == prod) 4082 return 0; 4083 4084 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_arq), 4085 0, IXL_DMA_LEN(&sc->sc_arq), 4086 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4087 4088 arq = IXL_DMA_KVA(&sc->sc_arq); 4089 4090 do { 4091 iaq = &arq[cons]; 4092 aqb = iavf_aqb_get_locked(&sc->sc_arq_live); 4093 4094 KASSERT(aqb != NULL); 4095 4096 bus_dmamap_sync(sc->sc_dmat, aqb->aqb_map, 0, IAVF_AQ_BUFLEN, 4097 BUS_DMASYNC_POSTREAD); 4098 4099 vc_opcode = iavf_process_arq(sc, iaq, aqb); 4100 4101 switch (vc_opcode) { 4102 case IAVF_VC_OP_CONFIG_TX_QUEUE: 4103 case IAVF_VC_OP_CONFIG_RX_QUEUE: 4104 case IAVF_VC_OP_CONFIG_VSI_QUEUES: 4105 case IAVF_VC_OP_ENABLE_QUEUES: 4106 case IAVF_VC_OP_DISABLE_QUEUES: 4107 case IAVF_VC_OP_GET_RSS_HENA_CAPS: 4108 case IAVF_VC_OP_SET_RSS_HENA: 4109 case IAVF_VC_OP_ADD_ETH_ADDR: 4110 case IAVF_VC_OP_DEL_ETH_ADDR: 4111 case IAVF_VC_OP_CONFIG_PROMISC: 4112 case IAVF_VC_OP_ADD_VLAN: 4113 case IAVF_VC_OP_DEL_VLAN: 4114 case IAVF_VC_OP_ENABLE_VLAN_STRIP: 4115 case IAVF_VC_OP_DISABLE_VLAN_STRIP: 4116 case IAVF_VC_OP_CONFIG_RSS_KEY: 4117 case IAVF_VC_OP_CONFIG_RSS_LUT: 4118 sc->sc_arq_retval = iavf_aq_vc_get_retval(iaq); 4119 sc->sc_arq_opcode = vc_opcode; 4120 cv_signal(&sc->sc_adminq_cv); 4121 break; 4122 } 4123 4124 memset(iaq, 0, sizeof(*iaq)); 4125 iavf_aqb_put_locked(&sc->sc_arq_idle, aqb); 4126 4127 cons++; 4128 cons &= IAVF_AQ_MASK; 4129 } while (cons != prod); 4130 4131 sc->sc_arq_cons = cons; 4132 iavf_work_add(sc->sc_workq, &sc->sc_arq_refill); 4133 4134 return 1; 4135 } 4136 4137 static int 4138 iavf_atq_post(struct iavf_softc *sc, struct ixl_aq_desc *iaq, 4139 struct ixl_aq_buf *aqb) 4140 { 4141 struct ixl_aq_desc *atq, *slot; 4142 unsigned int prod; 4143 4144 atq = IXL_DMA_KVA(&sc->sc_atq); 4145 prod = sc->sc_atq_prod; 4146 slot = &atq[prod]; 4147 4148 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 4149 0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_POSTWRITE); 4150 4151 *slot = *iaq; 4152 slot->iaq_flags |= htole16(IXL_AQ_SI); 4153 if (aqb != NULL) { 4154 ixl_aq_dva(slot, IXL_AQB_DVA(aqb)); 4155 bus_dmamap_sync(sc->sc_dmat, IXL_AQB_MAP(aqb), 4156 0, IXL_AQB_LEN(aqb), BUS_DMASYNC_PREWRITE); 4157 iavf_aqb_put_locked(&sc->sc_atq_live, aqb); 4158 } else { 4159 ixl_aq_dva(slot, (bus_addr_t)0); 4160 } 4161 4162 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 4163 0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_PREWRITE); 4164 4165 if (atomic_load_relaxed(&sc->sc_debuglevel) >= 3) 4166 iavf_aq_dump(sc, slot, "post"); 4167 4168 prod++; 4169 prod &= IAVF_AQ_MASK; 4170 sc->sc_atq_prod = prod; 4171 iavf_wr(sc, sc->sc_aq_regs->atq_tail, prod); 4172 return prod; 4173 } 4174 4175 static int 4176 iavf_atq_poll(struct iavf_softc *sc, unsigned int tm) 4177 { 4178 struct ixl_aq_desc *atq, *slot; 4179 struct ixl_aq_desc iaq; 4180 unsigned int prod; 4181 unsigned int t; 4182 int dbg; 4183 4184 dbg = atomic_load_relaxed(&sc->sc_debuglevel); 4185 atq = IXL_DMA_KVA(&sc->sc_atq); 4186 prod = sc->sc_atq_prod; 4187 slot = &atq[prod]; 4188 t = 0; 4189 4190 while (iavf_rd(sc, sc->sc_aq_regs->atq_head) != prod) { 4191 delaymsec(1); 4192 4193 if (t++ > tm) { 4194 if (dbg >= 2) { 4195 device_printf(sc->sc_dev, 4196 "atq timedout\n"); 4197 } 4198 return ETIMEDOUT; 4199 } 4200 } 4201 4202 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 4203 0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_POSTREAD); 4204 iaq = *slot; 4205 memset(slot, 0, sizeof(*slot)); 4206 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 4207 0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_PREREAD); 4208 4209 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) { 4210 if (dbg >= 2) { 4211 device_printf(sc->sc_dev, 4212 "atq retcode=0x%04x\n", le16toh(iaq.iaq_retval)); 4213 } 4214 return EIO; 4215 } 4216 4217 return 0; 4218 } 4219 4220 static void 4221 iavf_atq_done(struct iavf_softc *sc) 4222 { 4223 struct ixl_aq_desc *atq, *slot; 4224 struct ixl_aq_buf *aqb; 4225 unsigned int cons; 4226 unsigned int prod; 4227 4228 KASSERT(mutex_owned(&sc->sc_adminq_lock)); 4229 4230 prod = sc->sc_atq_prod; 4231 cons = sc->sc_atq_cons; 4232 4233 if (prod == cons) 4234 return; 4235 4236 atq = IXL_DMA_KVA(&sc->sc_atq); 4237 4238 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 4239 0, IXL_DMA_LEN(&sc->sc_atq), 4240 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4241 4242 do { 4243 slot = &atq[cons]; 4244 if (!ISSET(slot->iaq_flags, htole16(IXL_AQ_DD))) 4245 break; 4246 4247 if (ixl_aq_has_dva(slot) && 4248 (aqb = iavf_aqb_get_locked(&sc->sc_atq_live)) != NULL) { 4249 bus_dmamap_sync(sc->sc_dmat, IXL_AQB_MAP(aqb), 4250 0, IXL_AQB_LEN(aqb), BUS_DMASYNC_POSTWRITE); 4251 iavf_aqb_put_locked(&sc->sc_atq_idle, aqb); 4252 } 4253 4254 memset(slot, 0, sizeof(*slot)); 4255 4256 cons++; 4257 cons &= IAVF_AQ_MASK; 4258 } while (cons != prod); 4259 4260 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 4261 0, IXL_DMA_LEN(&sc->sc_atq), 4262 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 4263 4264 sc->sc_atq_cons = cons; 4265 } 4266 4267 static int 4268 iavf_adminq_poll(struct iavf_softc *sc, struct ixl_aq_desc *iaq, 4269 struct ixl_aq_buf *aqb, int retry) 4270 { 4271 int error; 4272 4273 mutex_enter(&sc->sc_adminq_lock); 4274 error = iavf_adminq_poll_locked(sc, iaq, aqb, retry); 4275 mutex_exit(&sc->sc_adminq_lock); 4276 4277 return error; 4278 } 4279 4280 static int 4281 iavf_adminq_poll_locked(struct iavf_softc *sc, 4282 struct ixl_aq_desc *iaq, struct ixl_aq_buf *aqb, int retry) 4283 { 4284 uint32_t opcode; 4285 int error; 4286 4287 KASSERT(!sc->sc_attached || mutex_owned(&sc->sc_adminq_lock)); 4288 4289 opcode = iavf_aq_vc_get_opcode(iaq); 4290 4291 iavf_atq_post(sc, iaq, aqb); 4292 4293 error = iavf_atq_poll(sc, retry); 4294 4295 /* 4296 * collect the aqb used in the current command and 4297 * added to sc_atq_live at iavf_atq_post(), 4298 * whether or not the command succeeded. 4299 */ 4300 if (aqb != NULL) { 4301 (void)iavf_aqb_get_locked(&sc->sc_atq_live); 4302 bus_dmamap_sync(sc->sc_dmat, IXL_AQB_MAP(aqb), 4303 0, IXL_AQB_LEN(aqb), BUS_DMASYNC_POSTWRITE); 4304 } 4305 4306 if (error) 4307 return error; 4308 4309 error = iavf_arq_poll(sc, opcode, retry); 4310 4311 if (error != 0 && 4312 atomic_load_relaxed(&sc->sc_debuglevel) >= 1) { 4313 device_printf(sc->sc_dev, "%s failed=%d(polling)\n", 4314 iavf_aq_vc_opcode_str(iaq), error); 4315 } 4316 4317 return error; 4318 } 4319 4320 static int 4321 iavf_adminq_exec(struct iavf_softc *sc, struct ixl_aq_desc *iaq, 4322 struct ixl_aq_buf *aqb) 4323 { 4324 int error; 4325 uint32_t opcode; 4326 4327 opcode = iavf_aq_vc_get_opcode(iaq); 4328 4329 mutex_enter(&sc->sc_adminq_lock); 4330 iavf_atq_post(sc, iaq, aqb); 4331 4332 error = iavf_arq_wait(sc, opcode); 4333 if (error == 0) { 4334 error = sc->sc_arq_retval; 4335 if (error != IAVF_VC_RC_SUCCESS && 4336 atomic_load_relaxed(&sc->sc_debuglevel) >= 1) { 4337 device_printf(sc->sc_dev, "%s failed=%d\n", 4338 iavf_aq_vc_opcode_str(iaq), error); 4339 } 4340 } 4341 4342 mutex_exit(&sc->sc_adminq_lock); 4343 return error; 4344 } 4345 4346 static void 4347 iavf_process_version(struct iavf_softc *sc, struct ixl_aq_desc *iaq, 4348 struct ixl_aq_buf *aqb) 4349 { 4350 struct iavf_vc_version_info *ver; 4351 4352 ver = (struct iavf_vc_version_info *)aqb->aqb_data; 4353 sc->sc_major_ver = le32toh(ver->major); 4354 sc->sc_minor_ver = le32toh(ver->minor); 4355 } 4356 4357 static void 4358 iavf_process_vf_resources(struct iavf_softc *sc, struct ixl_aq_desc *iaq, 4359 struct ixl_aq_buf *aqb) 4360 { 4361 struct iavf_vc_vf_resource *vf_res; 4362 struct iavf_vc_vsi_resource *vsi_res; 4363 uint8_t *enaddr; 4364 int mtu, dbg; 4365 char buf[512]; 4366 4367 dbg = atomic_load_relaxed(&sc->sc_debuglevel); 4368 sc->sc_got_vf_resources = 1; 4369 4370 vf_res = aqb->aqb_data; 4371 sc->sc_max_vectors = le16toh(vf_res->max_vectors); 4372 if (le16toh(vf_res->num_vsis) == 0) { 4373 if (dbg >= 1) { 4374 device_printf(sc->sc_dev, "no vsi available\n"); 4375 } 4376 return; 4377 } 4378 sc->sc_vf_cap = le32toh(vf_res->offload_flags); 4379 if (dbg >= 2) { 4380 snprintb(buf, sizeof(buf), 4381 IAVF_VC_OFFLOAD_FMT, sc->sc_vf_cap); 4382 device_printf(sc->sc_dev, "VF cap=%s\n", buf); 4383 } 4384 4385 mtu = le16toh(vf_res->max_mtu); 4386 if (IAVF_MIN_MTU < mtu && mtu < IAVF_MAX_MTU) { 4387 sc->sc_max_mtu = MIN(IAVF_MAX_MTU, mtu); 4388 } 4389 4390 vsi_res = &vf_res->vsi_res[0]; 4391 sc->sc_vsi_id = le16toh(vsi_res->vsi_id); 4392 sc->sc_vf_id = le32toh(iaq->iaq_param[0]); 4393 sc->sc_qset_handle = le16toh(vsi_res->qset_handle); 4394 sc->sc_nqps_vsi = le16toh(vsi_res->num_queue_pairs); 4395 if (!iavf_is_etheranyaddr(vsi_res->default_mac)) { 4396 enaddr = vsi_res->default_mac; 4397 } else { 4398 enaddr = sc->sc_enaddr_fake; 4399 } 4400 memcpy(sc->sc_enaddr, enaddr, ETHER_ADDR_LEN); 4401 } 4402 4403 static void 4404 iavf_process_irq_map(struct iavf_softc *sc, struct ixl_aq_desc *iaq) 4405 { 4406 uint32_t retval; 4407 4408 retval = iavf_aq_vc_get_retval(iaq); 4409 if (retval != IAVF_VC_RC_SUCCESS) { 4410 return; 4411 } 4412 4413 sc->sc_got_irq_map = 1; 4414 } 4415 4416 static void 4417 iavf_process_vc_event(struct iavf_softc *sc, struct ixl_aq_desc *iaq, 4418 struct ixl_aq_buf *aqb) 4419 { 4420 struct iavf_vc_pf_event *event; 4421 struct ifnet *ifp = &sc->sc_ec.ec_if; 4422 const struct iavf_link_speed *speed; 4423 int link; 4424 4425 event = aqb->aqb_data; 4426 switch (event->event) { 4427 case IAVF_VC_EVENT_LINK_CHANGE: 4428 sc->sc_media_status = IFM_AVALID; 4429 sc->sc_media_active = IFM_ETHER; 4430 link = LINK_STATE_DOWN; 4431 if (event->link_status) { 4432 link = LINK_STATE_UP; 4433 sc->sc_media_status |= IFM_ACTIVE; 4434 sc->sc_media_active |= IFM_FDX; 4435 4436 ifp->if_baudrate = 0; 4437 speed = iavf_find_link_speed(sc, event->link_speed); 4438 if (speed != NULL) { 4439 sc->sc_media_active |= speed->media; 4440 ifp->if_baudrate = speed->baudrate; 4441 } 4442 } 4443 4444 if (sc->sc_link_state != link) { 4445 sc->sc_link_state = link; 4446 if (sc->sc_attached) { 4447 if_link_state_change(ifp, link); 4448 } 4449 } 4450 break; 4451 case IAVF_VC_EVENT_RESET_IMPENDING: 4452 log(LOG_INFO, "%s: Reset warning received from the PF\n", 4453 ifp->if_xname); 4454 iavf_work_set(&sc->sc_reset_task, iavf_reset_request, sc); 4455 iavf_work_add(sc->sc_workq, &sc->sc_reset_task); 4456 break; 4457 } 4458 } 4459 4460 static void 4461 iavf_process_stats(struct iavf_softc *sc, struct ixl_aq_desc *iaq, 4462 struct ixl_aq_buf *aqb) 4463 { 4464 struct iavf_stat_counters *isc; 4465 struct i40e_eth_stats *st; 4466 4467 KASSERT(mutex_owned(&sc->sc_adminq_lock)); 4468 4469 st = aqb->aqb_data; 4470 isc = &sc->sc_stat_counters; 4471 4472 isc->isc_rx_bytes.ev_count = st->rx_bytes; 4473 isc->isc_rx_unicast.ev_count = st->rx_unicast; 4474 isc->isc_rx_multicast.ev_count = st->rx_multicast; 4475 isc->isc_rx_broadcast.ev_count = st->rx_broadcast; 4476 isc->isc_rx_discards.ev_count = st->rx_discards; 4477 isc->isc_rx_unknown_protocol.ev_count = st->rx_unknown_protocol; 4478 4479 isc->isc_tx_bytes.ev_count = st->tx_bytes; 4480 isc->isc_tx_unicast.ev_count = st->tx_unicast; 4481 isc->isc_tx_multicast.ev_count = st->tx_multicast; 4482 isc->isc_tx_broadcast.ev_count = st->tx_broadcast; 4483 isc->isc_tx_discards.ev_count = st->tx_discards; 4484 isc->isc_tx_errors.ev_count = st->tx_errors; 4485 } 4486 4487 static void 4488 iavf_process_req_queues(struct iavf_softc *sc, struct ixl_aq_desc *iaq, 4489 struct ixl_aq_buf *aqb) 4490 { 4491 struct iavf_vc_res_request *req; 4492 struct ifnet *ifp; 4493 uint32_t vc_retval; 4494 4495 ifp = &sc->sc_ec.ec_if; 4496 req = aqb->aqb_data; 4497 4498 vc_retval = iavf_aq_vc_get_retval(iaq); 4499 if (vc_retval != IAVF_VC_RC_SUCCESS) { 4500 return; 4501 } 4502 4503 if (sc->sc_nqps_req < req->num_queue_pairs) { 4504 log(LOG_INFO, 4505 "%s: requested %d queues, but only %d left.\n", 4506 ifp->if_xname, 4507 sc->sc_nqps_req, req->num_queue_pairs); 4508 } 4509 4510 if (sc->sc_nqps_vsi < req->num_queue_pairs) { 4511 if (!sc->sc_req_queues_retried) { 4512 /* req->num_queue_pairs indicates max qps */ 4513 sc->sc_nqps_req = req->num_queue_pairs; 4514 4515 sc->sc_req_queues_retried = true; 4516 iavf_work_add(sc->sc_workq, &sc->sc_req_queues_task); 4517 } 4518 } 4519 } 4520 4521 static int 4522 iavf_get_version(struct iavf_softc *sc, struct ixl_aq_buf *aqb) 4523 { 4524 struct ixl_aq_desc iaq; 4525 struct iavf_vc_version_info *ver; 4526 int error; 4527 4528 memset(&iaq, 0, sizeof(iaq)); 4529 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD); 4530 iaq.iaq_opcode = htole16(IAVF_AQ_OP_SEND_TO_PF); 4531 iavf_aq_vc_set_opcode(&iaq, IAVF_VC_OP_VERSION); 4532 iaq.iaq_datalen = htole16(sizeof(struct iavf_vc_version_info)); 4533 4534 ver = IXL_AQB_KVA(aqb); 4535 ver->major = htole32(IAVF_VF_MAJOR); 4536 ver->minor = htole32(IAVF_VF_MINOR); 4537 4538 sc->sc_major_ver = UINT_MAX; 4539 sc->sc_minor_ver = UINT_MAX; 4540 4541 if (sc->sc_attached) { 4542 error = iavf_adminq_poll(sc, &iaq, aqb, 250); 4543 } else { 4544 error = iavf_adminq_poll_locked(sc, &iaq, aqb, 250); 4545 } 4546 4547 if (error) 4548 return -1; 4549 4550 return 0; 4551 } 4552 4553 static int 4554 iavf_get_vf_resources(struct iavf_softc *sc, struct ixl_aq_buf *aqb) 4555 { 4556 struct ixl_aq_desc iaq; 4557 uint32_t *cap, cap0; 4558 int error; 4559 4560 memset(&iaq, 0, sizeof(iaq)); 4561 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD); 4562 iaq.iaq_opcode = htole16(IAVF_AQ_OP_SEND_TO_PF); 4563 iavf_aq_vc_set_opcode(&iaq, IAVF_VC_OP_GET_VF_RESOURCES); 4564 4565 if (sc->sc_major_ver > 0) { 4566 cap0 = IAVF_VC_OFFLOAD_L2 | 4567 IAVF_VC_OFFLOAD_VLAN | 4568 IAVF_VC_OFFLOAD_RSS_PF | 4569 IAVF_VC_OFFLOAD_REQ_QUEUES; 4570 4571 cap = IXL_AQB_KVA(aqb); 4572 *cap = htole32(cap0); 4573 iaq.iaq_datalen = htole16(sizeof(*cap)); 4574 } 4575 4576 sc->sc_got_vf_resources = 0; 4577 if (sc->sc_attached) { 4578 error = iavf_adminq_poll(sc, &iaq, aqb, 250); 4579 } else { 4580 error = iavf_adminq_poll_locked(sc, &iaq, aqb, 250); 4581 } 4582 4583 if (error) 4584 return -1; 4585 return 0; 4586 } 4587 4588 static int 4589 iavf_get_stats(struct iavf_softc *sc) 4590 { 4591 struct ixl_aq_desc iaq; 4592 struct ixl_aq_buf *aqb; 4593 struct iavf_vc_queue_select *qsel; 4594 int error; 4595 4596 mutex_enter(&sc->sc_adminq_lock); 4597 aqb = iavf_aqb_get_locked(&sc->sc_atq_idle); 4598 mutex_exit(&sc->sc_adminq_lock); 4599 4600 if (aqb == NULL) 4601 return ENOMEM; 4602 4603 qsel = IXL_AQB_KVA(aqb); 4604 memset(qsel, 0, sizeof(*qsel)); 4605 qsel->vsi_id = htole16(sc->sc_vsi_id); 4606 4607 memset(&iaq, 0, sizeof(iaq)); 4608 4609 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD); 4610 iaq.iaq_opcode = htole16(IAVF_AQ_OP_SEND_TO_PF); 4611 iavf_aq_vc_set_opcode(&iaq, IAVF_VC_OP_GET_STATS); 4612 iaq.iaq_datalen = htole16(sizeof(*qsel)); 4613 4614 if (atomic_load_relaxed(&sc->sc_debuglevel) >= 3) { 4615 device_printf(sc->sc_dev, "post GET_STATS command\n"); 4616 } 4617 4618 mutex_enter(&sc->sc_adminq_lock); 4619 error = iavf_atq_post(sc, &iaq, aqb); 4620 mutex_exit(&sc->sc_adminq_lock); 4621 4622 return error; 4623 } 4624 4625 static int 4626 iavf_config_irq_map(struct iavf_softc *sc, struct ixl_aq_buf *aqb) 4627 { 4628 struct ixl_aq_desc iaq; 4629 struct iavf_vc_vector_map *vec; 4630 struct iavf_vc_irq_map_info *map; 4631 struct iavf_rx_ring *rxr; 4632 struct iavf_tx_ring *txr; 4633 unsigned int num_vec; 4634 int error; 4635 4636 map = IXL_AQB_KVA(aqb); 4637 vec = map->vecmap; 4638 num_vec = 0; 4639 4640 if (sc->sc_nintrs == 1) { 4641 vec[0].vsi_id = htole16(sc->sc_vsi_id); 4642 vec[0].vector_id = htole16(0); 4643 vec[0].rxq_map = htole16(iavf_allqueues(sc)); 4644 vec[0].txq_map = htole16(iavf_allqueues(sc)); 4645 vec[0].rxitr_idx = htole16(IAVF_NOITR); 4646 vec[0].rxitr_idx = htole16(IAVF_NOITR); 4647 num_vec = 1; 4648 } else if (sc->sc_nintrs > 1) { 4649 KASSERT(sc->sc_nqps_alloc >= (sc->sc_nintrs - 1)); 4650 for (; num_vec < (sc->sc_nintrs - 1); num_vec++) { 4651 rxr = sc->sc_qps[num_vec].qp_rxr; 4652 txr = sc->sc_qps[num_vec].qp_txr; 4653 4654 vec[num_vec].vsi_id = htole16(sc->sc_vsi_id); 4655 vec[num_vec].vector_id = htole16(num_vec + 1); 4656 vec[num_vec].rxq_map = htole16(__BIT(rxr->rxr_qid)); 4657 vec[num_vec].txq_map = htole16(__BIT(txr->txr_qid)); 4658 vec[num_vec].rxitr_idx = htole16(IAVF_ITR_RX); 4659 vec[num_vec].txitr_idx = htole16(IAVF_ITR_TX); 4660 } 4661 4662 vec[num_vec].vsi_id = htole16(sc->sc_vsi_id); 4663 vec[num_vec].vector_id = htole16(0); 4664 vec[num_vec].rxq_map = htole16(0); 4665 vec[num_vec].txq_map = htole16(0); 4666 num_vec++; 4667 } 4668 4669 map->num_vectors = htole16(num_vec); 4670 4671 memset(&iaq, 0, sizeof(iaq)); 4672 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD); 4673 iaq.iaq_opcode = htole16(IAVF_AQ_OP_SEND_TO_PF); 4674 iavf_aq_vc_set_opcode(&iaq, IAVF_VC_OP_CONFIG_IRQ_MAP); 4675 iaq.iaq_datalen = htole16(sizeof(*map) + sizeof(*vec) * num_vec); 4676 4677 if (sc->sc_attached) { 4678 error = iavf_adminq_poll(sc, &iaq, aqb, 250); 4679 } else { 4680 error = iavf_adminq_poll_locked(sc, &iaq, aqb, 250); 4681 } 4682 4683 if (error) 4684 return -1; 4685 4686 return 0; 4687 } 4688 4689 static int 4690 iavf_config_vsi_queues(struct iavf_softc *sc) 4691 { 4692 struct ifnet *ifp = &sc->sc_ec.ec_if; 4693 struct ixl_aq_desc iaq; 4694 struct ixl_aq_buf *aqb; 4695 struct iavf_vc_queue_config_info *config; 4696 struct iavf_vc_txq_info *txq; 4697 struct iavf_vc_rxq_info *rxq; 4698 struct iavf_rx_ring *rxr; 4699 struct iavf_tx_ring *txr; 4700 uint32_t rxmtu_max; 4701 unsigned int i; 4702 int error; 4703 4704 rxmtu_max = ifp->if_mtu + IAVF_MTU_ETHERLEN; 4705 4706 aqb = iavf_aqb_get(sc, &sc->sc_atq_idle); 4707 4708 if (aqb == NULL) 4709 return -1; 4710 4711 config = IXL_AQB_KVA(aqb); 4712 memset(config, 0, sizeof(*config)); 4713 config->vsi_id = htole16(sc->sc_vsi_id); 4714 config->num_queue_pairs = htole16(sc->sc_nqueue_pairs); 4715 4716 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 4717 rxr = sc->sc_qps[i].qp_rxr; 4718 txr = sc->sc_qps[i].qp_txr; 4719 4720 txq = &config->qpair[i].txq; 4721 txq->vsi_id = htole16(sc->sc_vsi_id); 4722 txq->queue_id = htole16(txr->txr_qid); 4723 txq->ring_len = htole16(sc->sc_tx_ring_ndescs); 4724 txq->headwb_ena = 0; 4725 txq->dma_ring_addr = htole64(IXL_DMA_DVA(&txr->txr_mem)); 4726 txq->dma_headwb_addr = 0; 4727 4728 rxq = &config->qpair[i].rxq; 4729 rxq->vsi_id = htole16(sc->sc_vsi_id); 4730 rxq->queue_id = htole16(rxr->rxr_qid); 4731 rxq->ring_len = htole16(sc->sc_rx_ring_ndescs); 4732 rxq->splithdr_ena = 0; 4733 rxq->databuf_size = htole32(IAVF_MCLBYTES); 4734 rxq->max_pkt_size = htole32(rxmtu_max); 4735 rxq->dma_ring_addr = htole64(IXL_DMA_DVA(&rxr->rxr_mem)); 4736 rxq->rx_split_pos = 0; 4737 } 4738 4739 memset(&iaq, 0, sizeof(iaq)); 4740 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD); 4741 iaq.iaq_opcode = htole16(IAVF_AQ_OP_SEND_TO_PF); 4742 iavf_aq_vc_set_opcode(&iaq, IAVF_VC_OP_CONFIG_VSI_QUEUES); 4743 iaq.iaq_datalen = htole16(sizeof(*config) + 4744 sizeof(config->qpair[0]) * sc->sc_nqueue_pairs); 4745 4746 error = iavf_adminq_exec(sc, &iaq, aqb); 4747 if (error != IAVF_VC_RC_SUCCESS) { 4748 return -1; 4749 } 4750 4751 return 0; 4752 } 4753 4754 static int 4755 iavf_config_hena(struct iavf_softc *sc) 4756 { 4757 struct ixl_aq_desc iaq; 4758 struct ixl_aq_buf *aqb; 4759 uint64_t *caps; 4760 int error; 4761 4762 aqb = iavf_aqb_get(sc, &sc->sc_atq_idle); 4763 4764 if (aqb == NULL) 4765 return -1; 4766 4767 caps = IXL_AQB_KVA(aqb); 4768 if (sc->sc_mac_type == I40E_MAC_X722_VF) 4769 *caps = IXL_RSS_HENA_DEFAULT_X722; 4770 else 4771 *caps = IXL_RSS_HENA_DEFAULT_XL710; 4772 4773 memset(&iaq, 0, sizeof(iaq)); 4774 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD); 4775 iaq.iaq_opcode = htole16(IAVF_AQ_OP_SEND_TO_PF); 4776 iavf_aq_vc_set_opcode(&iaq, IAVF_VC_OP_SET_RSS_HENA); 4777 iaq.iaq_datalen = htole16(sizeof(*caps)); 4778 4779 error = iavf_adminq_exec(sc, &iaq, aqb); 4780 if (error != IAVF_VC_RC_SUCCESS) { 4781 return -1; 4782 } 4783 4784 return 0; 4785 } 4786 4787 static inline void 4788 iavf_get_default_rss_key(uint8_t *buf, size_t len) 4789 { 4790 uint8_t rss_seed[RSS_KEYSIZE]; 4791 size_t cplen; 4792 4793 cplen = MIN(len, sizeof(rss_seed)); 4794 rss_getkey(rss_seed); 4795 4796 memcpy(buf, rss_seed, cplen); 4797 if (cplen < len) 4798 memset(buf + cplen, 0, len - cplen); 4799 } 4800 4801 static int 4802 iavf_config_rss_key(struct iavf_softc *sc) 4803 { 4804 struct ixl_aq_desc iaq; 4805 struct ixl_aq_buf *aqb; 4806 struct iavf_vc_rss_key *rss_key; 4807 size_t key_len; 4808 int rv; 4809 4810 aqb = iavf_aqb_get(sc, &sc->sc_atq_idle); 4811 if (aqb == NULL) 4812 return -1; 4813 4814 rss_key = IXL_AQB_KVA(aqb); 4815 rss_key->vsi_id = htole16(sc->sc_vsi_id); 4816 key_len = IXL_RSS_KEY_SIZE; 4817 iavf_get_default_rss_key(rss_key->key, key_len); 4818 rss_key->key_len = key_len; 4819 4820 memset(&iaq, 0, sizeof(iaq)); 4821 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD); 4822 iaq.iaq_opcode = htole16(IAVF_AQ_OP_SEND_TO_PF); 4823 iavf_aq_vc_set_opcode(&iaq, IAVF_VC_OP_CONFIG_RSS_KEY); 4824 iaq.iaq_datalen = htole16(sizeof(*rss_key) - sizeof(rss_key->pad) 4825 + (sizeof(rss_key->key[0]) * key_len)); 4826 4827 rv = iavf_adminq_exec(sc, &iaq, aqb); 4828 if (rv != IAVF_VC_RC_SUCCESS) { 4829 return -1; 4830 } 4831 4832 return 0; 4833 } 4834 4835 static int 4836 iavf_config_rss_lut(struct iavf_softc *sc) 4837 { 4838 struct ixl_aq_desc iaq; 4839 struct ixl_aq_buf *aqb; 4840 struct iavf_vc_rss_lut *rss_lut; 4841 uint8_t *lut, v; 4842 int rv, i; 4843 4844 aqb = iavf_aqb_get(sc, &sc->sc_atq_idle); 4845 if (aqb == NULL) 4846 return -1; 4847 4848 rss_lut = IXL_AQB_KVA(aqb); 4849 rss_lut->vsi_id = htole16(sc->sc_vsi_id); 4850 rss_lut->lut_entries = htole16(IXL_RSS_VSI_LUT_SIZE); 4851 4852 lut = rss_lut->lut; 4853 for (i = 0; i < IXL_RSS_VSI_LUT_SIZE; i++) { 4854 v = i % sc->sc_nqueue_pairs; 4855 v &= IAVF_RSS_VSI_LUT_ENTRY_MASK; 4856 lut[i] = v; 4857 } 4858 4859 memset(&iaq, 0, sizeof(iaq)); 4860 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD); 4861 iaq.iaq_opcode = htole16(IAVF_AQ_OP_SEND_TO_PF); 4862 iavf_aq_vc_set_opcode(&iaq, IAVF_VC_OP_CONFIG_RSS_LUT); 4863 iaq.iaq_datalen = htole16(sizeof(*rss_lut) - sizeof(rss_lut->pad) 4864 + (sizeof(rss_lut->lut[0]) * IXL_RSS_VSI_LUT_SIZE)); 4865 4866 rv = iavf_adminq_exec(sc, &iaq, aqb); 4867 if (rv != IAVF_VC_RC_SUCCESS) { 4868 return -1; 4869 } 4870 4871 return 0; 4872 } 4873 4874 static int 4875 iavf_queue_select(struct iavf_softc *sc, int opcode) 4876 { 4877 struct ixl_aq_desc iaq; 4878 struct ixl_aq_buf *aqb; 4879 struct iavf_vc_queue_select *qsel; 4880 int error; 4881 4882 aqb = iavf_aqb_get(sc, &sc->sc_atq_idle); 4883 if (aqb == NULL) 4884 return -1; 4885 4886 qsel = IXL_AQB_KVA(aqb); 4887 qsel->vsi_id = htole16(sc->sc_vsi_id); 4888 qsel->rx_queues = htole32(iavf_allqueues(sc)); 4889 qsel->tx_queues = htole32(iavf_allqueues(sc)); 4890 4891 memset(&iaq, 0, sizeof(iaq)); 4892 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD); 4893 iaq.iaq_opcode = htole16(IAVF_AQ_OP_SEND_TO_PF); 4894 iavf_aq_vc_set_opcode(&iaq, opcode); 4895 iaq.iaq_datalen = htole16(sizeof(*qsel)); 4896 4897 error = iavf_adminq_exec(sc, &iaq, aqb); 4898 if (error != IAVF_VC_RC_SUCCESS) { 4899 return -1; 4900 } 4901 4902 return 0; 4903 } 4904 4905 static int 4906 iavf_request_queues(struct iavf_softc *sc, unsigned int req_num) 4907 { 4908 struct ixl_aq_desc iaq; 4909 struct ixl_aq_buf *aqb; 4910 struct iavf_vc_res_request *req; 4911 int rv; 4912 4913 aqb = iavf_aqb_get(sc, &sc->sc_atq_idle); 4914 if (aqb == NULL) 4915 return ENOMEM; 4916 4917 req = IXL_AQB_KVA(aqb); 4918 req->num_queue_pairs = req_num; 4919 4920 memset(&iaq, 0, sizeof(iaq)); 4921 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD); 4922 iaq.iaq_opcode = htole16(IAVF_AQ_OP_SEND_TO_PF); 4923 iavf_aq_vc_set_opcode(&iaq, IAVF_VC_OP_REQUEST_QUEUES); 4924 iaq.iaq_datalen = htole16(sizeof(*req)); 4925 4926 mutex_enter(&sc->sc_adminq_lock); 4927 rv = iavf_atq_post(sc, &iaq, aqb); 4928 mutex_exit(&sc->sc_adminq_lock); 4929 4930 return rv; 4931 } 4932 4933 static int 4934 iavf_reset_vf(struct iavf_softc *sc) 4935 { 4936 struct ixl_aq_desc iaq; 4937 int error; 4938 4939 memset(&iaq, 0, sizeof(iaq)); 4940 iaq.iaq_flags = htole16(IXL_AQ_RD); 4941 iaq.iaq_opcode = htole16(IAVF_AQ_OP_SEND_TO_PF); 4942 iavf_aq_vc_set_opcode(&iaq, IAVF_VC_OP_RESET_VF); 4943 iaq.iaq_datalen = htole16(0); 4944 4945 iavf_wr(sc, I40E_VFGEN_RSTAT, IAVF_VFR_INPROGRESS); 4946 4947 mutex_enter(&sc->sc_adminq_lock); 4948 error = iavf_atq_post(sc, &iaq, NULL); 4949 mutex_exit(&sc->sc_adminq_lock); 4950 4951 return error; 4952 } 4953 4954 static int 4955 iavf_eth_addr(struct iavf_softc *sc, const uint8_t *addr, uint32_t opcode) 4956 { 4957 struct ixl_aq_desc iaq; 4958 struct ixl_aq_buf *aqb; 4959 struct iavf_vc_eth_addr_list *addrs; 4960 struct iavf_vc_eth_addr *vcaddr; 4961 int rv; 4962 4963 KASSERT(sc->sc_attached); 4964 KASSERT(opcode == IAVF_VC_OP_ADD_ETH_ADDR || 4965 opcode == IAVF_VC_OP_DEL_ETH_ADDR); 4966 4967 aqb = iavf_aqb_get(sc, &sc->sc_atq_idle); 4968 if (aqb == NULL) 4969 return -1; 4970 4971 addrs = IXL_AQB_KVA(aqb); 4972 addrs->vsi_id = htole16(sc->sc_vsi_id); 4973 addrs->num_elements = htole16(1); 4974 vcaddr = addrs->list; 4975 memcpy(vcaddr->addr, addr, ETHER_ADDR_LEN); 4976 4977 memset(&iaq, 0, sizeof(iaq)); 4978 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD); 4979 iaq.iaq_opcode = htole16(IAVF_AQ_OP_SEND_TO_PF); 4980 iavf_aq_vc_set_opcode(&iaq, opcode); 4981 iaq.iaq_datalen = htole16(sizeof(*addrs) + sizeof(*vcaddr)); 4982 4983 if (sc->sc_resetting) { 4984 mutex_enter(&sc->sc_adminq_lock); 4985 rv = iavf_adminq_poll_locked(sc, &iaq, aqb, 250); 4986 iavf_aqb_put_locked(&sc->sc_atq_idle, aqb); 4987 mutex_exit(&sc->sc_adminq_lock); 4988 } else { 4989 rv = iavf_adminq_exec(sc, &iaq, aqb); 4990 } 4991 4992 if (rv != IAVF_VC_RC_SUCCESS) { 4993 return -1; 4994 } 4995 4996 return 0; 4997 } 4998 4999 static int 5000 iavf_config_promisc_mode(struct iavf_softc *sc, int unicast, int multicast) 5001 { 5002 struct ixl_aq_desc iaq; 5003 struct ixl_aq_buf *aqb; 5004 struct iavf_vc_promisc_info *promisc; 5005 int flags; 5006 5007 KASSERT(sc->sc_attached); 5008 5009 aqb = iavf_aqb_get(sc, &sc->sc_atq_idle); 5010 if (aqb == NULL) 5011 return -1; 5012 5013 flags = 0; 5014 if (unicast) 5015 flags |= IAVF_FLAG_VF_UNICAST_PROMISC; 5016 if (multicast) 5017 flags |= IAVF_FLAG_VF_MULTICAST_PROMISC; 5018 5019 promisc = IXL_AQB_KVA(aqb); 5020 promisc->vsi_id = htole16(sc->sc_vsi_id); 5021 promisc->flags = htole16(flags); 5022 5023 memset(&iaq, 0, sizeof(iaq)); 5024 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD); 5025 iaq.iaq_opcode = htole16(IAVF_AQ_OP_SEND_TO_PF); 5026 iavf_aq_vc_set_opcode(&iaq, IAVF_VC_OP_CONFIG_PROMISC); 5027 iaq.iaq_datalen = htole16(sizeof(*promisc)); 5028 5029 if (iavf_adminq_exec(sc, &iaq, aqb) != IAVF_VC_RC_SUCCESS) { 5030 return -1; 5031 } 5032 5033 return 0; 5034 } 5035 5036 static int 5037 iavf_config_vlan_stripping(struct iavf_softc *sc, int eccap) 5038 { 5039 struct ixl_aq_desc iaq; 5040 uint32_t opcode; 5041 5042 opcode = ISSET(eccap, ETHERCAP_VLAN_HWTAGGING) ? 5043 IAVF_VC_OP_ENABLE_VLAN_STRIP : IAVF_VC_OP_DISABLE_VLAN_STRIP; 5044 5045 memset(&iaq, 0, sizeof(iaq)); 5046 iaq.iaq_flags = htole16(IXL_AQ_RD); 5047 iaq.iaq_opcode = htole16(IAVF_AQ_OP_SEND_TO_PF); 5048 iavf_aq_vc_set_opcode(&iaq, opcode); 5049 iaq.iaq_datalen = htole16(0); 5050 5051 if (iavf_adminq_exec(sc, &iaq, NULL) != IAVF_VC_RC_SUCCESS) { 5052 return -1; 5053 } 5054 5055 return 0; 5056 } 5057 5058 static int 5059 iavf_config_vlan_id(struct iavf_softc *sc, uint16_t vid, uint32_t opcode) 5060 { 5061 struct ixl_aq_desc iaq; 5062 struct ixl_aq_buf *aqb; 5063 struct iavf_vc_vlan_filter *vfilter; 5064 int rv; 5065 5066 KASSERT(opcode == IAVF_VC_OP_ADD_VLAN || opcode == IAVF_VC_OP_DEL_VLAN); 5067 5068 aqb = iavf_aqb_get(sc, &sc->sc_atq_idle); 5069 5070 if (aqb == NULL) 5071 return -1; 5072 5073 vfilter = IXL_AQB_KVA(aqb); 5074 vfilter->vsi_id = htole16(sc->sc_vsi_id); 5075 vfilter->num_vlan_id = htole16(1); 5076 vfilter->vlan_id[0] = vid; 5077 5078 memset(&iaq, 0, sizeof(iaq)); 5079 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD); 5080 iaq.iaq_opcode = htole16(IAVF_AQ_OP_SEND_TO_PF); 5081 iavf_aq_vc_set_opcode(&iaq, opcode); 5082 iaq.iaq_datalen = htole16(sizeof(*vfilter) + sizeof(vid)); 5083 5084 if (sc->sc_resetting) { 5085 mutex_enter(&sc->sc_adminq_lock); 5086 rv = iavf_adminq_poll_locked(sc, &iaq, aqb, 250); 5087 iavf_aqb_put_locked(&sc->sc_atq_idle, aqb); 5088 mutex_exit(&sc->sc_adminq_lock); 5089 } else { 5090 rv = iavf_adminq_exec(sc, &iaq, aqb); 5091 } 5092 5093 if (rv != IAVF_VC_RC_SUCCESS) { 5094 return -1; 5095 } 5096 5097 return 0; 5098 } 5099 5100 static void 5101 iavf_post_request_queues(void *xsc) 5102 { 5103 struct iavf_softc *sc; 5104 struct ifnet *ifp; 5105 5106 sc = xsc; 5107 ifp = &sc->sc_ec.ec_if; 5108 5109 if (!ISSET(sc->sc_vf_cap, IAVF_VC_OFFLOAD_REQ_QUEUES)) { 5110 log(LOG_DEBUG, "%s: the VF has no REQ_QUEUES capability\n", 5111 ifp->if_xname); 5112 return; 5113 } 5114 5115 log(LOG_INFO, "%s: try to change the number of queue pairs" 5116 " (vsi %u, %u allocated, request %u)\n", 5117 ifp->if_xname, 5118 sc->sc_nqps_vsi, sc->sc_nqps_alloc, sc->sc_nqps_req); 5119 iavf_request_queues(sc, sc->sc_nqps_req); 5120 } 5121 5122 static bool 5123 iavf_sysctlnode_is_rx(struct sysctlnode *node) 5124 { 5125 5126 if (strstr(node->sysctl_parent->sysctl_name, "rx") != NULL) 5127 return true; 5128 5129 return false; 5130 } 5131 5132 static int 5133 iavf_sysctl_itr_handler(SYSCTLFN_ARGS) 5134 { 5135 struct sysctlnode node = *rnode; 5136 struct iavf_softc *sc = (struct iavf_softc *)node.sysctl_data; 5137 uint32_t newitr, *itrptr; 5138 unsigned int i; 5139 int itr, error; 5140 5141 if (iavf_sysctlnode_is_rx(&node)) { 5142 itrptr = &sc->sc_rx_itr; 5143 itr = IAVF_ITR_RX; 5144 } else { 5145 itrptr = &sc->sc_tx_itr; 5146 itr = IAVF_ITR_TX; 5147 } 5148 5149 newitr = *itrptr; 5150 node.sysctl_data = &newitr; 5151 node.sysctl_size = sizeof(newitr); 5152 5153 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 5154 if (error || newp == NULL) 5155 return error; 5156 5157 if (newitr > 0x07FF) 5158 return EINVAL; 5159 5160 *itrptr = newitr; 5161 5162 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 5163 iavf_wr(sc, I40E_VFINT_ITRN1(itr, i), *itrptr); 5164 } 5165 iavf_wr(sc, I40E_VFINT_ITR01(itr), *itrptr); 5166 5167 return 0; 5168 } 5169 5170 static void 5171 iavf_workq_work(struct work *wk, void *context) 5172 { 5173 struct iavf_work *work; 5174 5175 work = container_of(wk, struct iavf_work, ixw_cookie); 5176 5177 atomic_swap_uint(&work->ixw_added, 0); 5178 work->ixw_func(work->ixw_arg); 5179 } 5180 5181 static struct workqueue * 5182 iavf_workq_create(const char *name, pri_t prio, int ipl, int flags) 5183 { 5184 struct workqueue *wq; 5185 int error; 5186 5187 error = workqueue_create(&wq, name, iavf_workq_work, NULL, 5188 prio, ipl, flags); 5189 5190 if (error) 5191 return NULL; 5192 5193 return wq; 5194 } 5195 5196 static void 5197 iavf_workq_destroy(struct workqueue *wq) 5198 { 5199 5200 workqueue_destroy(wq); 5201 } 5202 5203 static int 5204 iavf_work_set(struct iavf_work *work, void (*func)(void *), void *arg) 5205 { 5206 5207 if (work->ixw_added != 0) 5208 return -1; 5209 5210 memset(work, 0, sizeof(*work)); 5211 work->ixw_func = func; 5212 work->ixw_arg = arg; 5213 5214 return 0; 5215 } 5216 5217 static void 5218 iavf_work_add(struct workqueue *wq, struct iavf_work *work) 5219 { 5220 if (atomic_cas_uint(&work->ixw_added, 0, 1) != 0) 5221 return; 5222 5223 kpreempt_disable(); 5224 workqueue_enqueue(wq, &work->ixw_cookie, NULL); 5225 kpreempt_enable(); 5226 } 5227 5228 static void 5229 iavf_work_wait(struct workqueue *wq, struct iavf_work *work) 5230 { 5231 5232 workqueue_wait(wq, &work->ixw_cookie); 5233 } 5234 5235 static void 5236 iavf_evcnt_attach(struct evcnt *ec, 5237 const char *n0, const char *n1) 5238 { 5239 5240 evcnt_attach_dynamic(ec, EVCNT_TYPE_MISC, 5241 NULL, n0, n1); 5242 } 5243 5244 MODULE(MODULE_CLASS_DRIVER, if_iavf, "pci"); 5245 5246 #ifdef _MODULE 5247 #include "ioconf.c" 5248 #endif 5249 5250 #ifdef _MODULE 5251 static void 5252 iavf_parse_modprop(prop_dictionary_t dict) 5253 { 5254 prop_object_t obj; 5255 int64_t val; 5256 uint32_t n; 5257 5258 if (dict == NULL) 5259 return; 5260 5261 obj = prop_dictionary_get(dict, "debug_level"); 5262 if (obj != NULL && prop_object_type(obj) == PROP_TYPE_NUMBER) { 5263 val = prop_number_signed_value((prop_number_t)obj); 5264 5265 if (val > 0) { 5266 iavf_params.debug = val; 5267 printf("iavf: debug level=%d\n", iavf_params.debug); 5268 } 5269 } 5270 5271 obj = prop_dictionary_get(dict, "max_qps"); 5272 if (obj != NULL && prop_object_type(obj) == PROP_TYPE_NUMBER) { 5273 val = prop_number_signed_value((prop_number_t)obj); 5274 5275 if (val < 1 || val > I40E_MAX_VF_QUEUES) { 5276 printf("iavf: invalid queue size(1 <= n <= %d)", 5277 I40E_MAX_VF_QUEUES); 5278 } else { 5279 iavf_params.max_qps = val; 5280 printf("iavf: request queue pair = %u\n", 5281 iavf_params.max_qps); 5282 } 5283 } 5284 5285 obj = prop_dictionary_get(dict, "tx_itr"); 5286 if (obj != NULL && prop_object_type(obj) == PROP_TYPE_NUMBER) { 5287 val = prop_number_signed_value((prop_number_t)obj); 5288 if (val > 0x07FF) { 5289 printf("iavf: TX ITR too big (%" PRId64 " <= %d)", 5290 val, 0x7FF); 5291 } else { 5292 iavf_params.tx_itr = val; 5293 printf("iavf: TX ITR = 0x%" PRIx32, 5294 iavf_params.tx_itr); 5295 } 5296 } 5297 5298 obj = prop_dictionary_get(dict, "rx_itr"); 5299 if (obj != NULL && prop_object_type(obj) == PROP_TYPE_NUMBER) { 5300 val = prop_number_signed_value((prop_number_t)obj); 5301 if (val > 0x07FF) { 5302 printf("iavf: RX ITR too big (%" PRId64 " <= %d)", 5303 val, 0x7FF); 5304 } else { 5305 iavf_params.rx_itr = val; 5306 printf("iavf: RX ITR = 0x%" PRIx32, 5307 iavf_params.rx_itr); 5308 } 5309 } 5310 5311 obj = prop_dictionary_get(dict, "tx_ndescs"); 5312 if (obj != NULL && prop_object_type(obj) == PROP_TYPE_NUMBER) { 5313 val = prop_number_signed_value((prop_number_t)obj); 5314 n = 1U << (fls32(val) - 1); 5315 if (val != (int64_t) n) { 5316 printf("iavf: TX desc invlaid size" 5317 "(%" PRId64 " != %" PRIu32 ")\n", val, n); 5318 } else if (val > (8192 - 32)) { 5319 printf("iavf: Tx desc too big (%" PRId64 " > %d)", 5320 val, (8192 - 32)); 5321 } else { 5322 iavf_params.tx_ndescs = val; 5323 printf("iavf: TX descriptors = 0x%04x", 5324 iavf_params.tx_ndescs); 5325 } 5326 } 5327 5328 obj = prop_dictionary_get(dict, "rx_ndescs"); 5329 if (obj != NULL && prop_object_type(obj) == PROP_TYPE_NUMBER) { 5330 val = prop_number_signed_value((prop_number_t)obj); 5331 n = 1U << (fls32(val) - 1); 5332 if (val != (int64_t) n) { 5333 printf("iavf: RX desc invlaid size" 5334 "(%" PRId64 " != %" PRIu32 ")\n", val, n); 5335 } else if (val > (8192 - 32)) { 5336 printf("iavf: Rx desc too big (%" PRId64 " > %d)", 5337 val, (8192 - 32)); 5338 } else { 5339 iavf_params.rx_ndescs = val; 5340 printf("iavf: RX descriptors = 0x%04x", 5341 iavf_params.rx_ndescs); 5342 } 5343 } 5344 } 5345 #endif 5346 5347 static int 5348 if_iavf_modcmd(modcmd_t cmd, void *opaque) 5349 { 5350 int error = 0; 5351 5352 #ifdef _MODULE 5353 switch (cmd) { 5354 case MODULE_CMD_INIT: 5355 iavf_parse_modprop((prop_dictionary_t)opaque); 5356 error = config_init_component(cfdriver_ioconf_if_iavf, 5357 cfattach_ioconf_if_iavf, cfdata_ioconf_if_iavf); 5358 break; 5359 case MODULE_CMD_FINI: 5360 error = config_fini_component(cfdriver_ioconf_if_iavf, 5361 cfattach_ioconf_if_iavf, cfdata_ioconf_if_iavf); 5362 break; 5363 default: 5364 error = ENOTTY; 5365 break; 5366 } 5367 #endif 5368 5369 return error; 5370 } 5371
Indexes created Tue Sep 30 11:09:46 GMT 2025