if_iavf.c revision 1.19
1 /* $NetBSD: if_iavf.c,v 1.19 2025/02/25 02:10:13 joe Exp $ */ 2 3 /* 4 * Copyright (c) 2013-2015, Intel Corporation 5 * All rights reserved. 6 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * 3. Neither the name of the Intel Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived from 19 * this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Copyright (c) 2016,2017 David Gwynne <dlg (at) openbsd.org> 36 * Copyright (c) 2019 Jonathan Matthew <jmatthew (at) openbsd.org> 37 * 38 * Permission to use, copy, modify, and distribute this software for any 39 * purpose with or without fee is hereby granted, provided that the above 40 * copyright notice and this permission notice appear in all copies. 41 * 42 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 43 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 44 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 45 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 46 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 47 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 48 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 49 */ 50 51 /* 52 * Copyright (c) 2020 Internet Initiative Japan, Inc. 53 * All rights reserved. 54 * 55 * Redistribution and use in source and binary forms, with or without 56 * modification, are permitted provided that the following conditions 57 * are met: 58 * 1. Redistributions of source code must retain the above copyright 59 * notice, this list of conditions and the following disclaimer. 60 * 2. Redistributions in binary form must reproduce the above copyright 61 * notice, this list of conditions and the following disclaimer in the 62 * documentation and/or other materials provided with the distribution. 63 * 64 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 65 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 66 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 67 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 68 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 69 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 70 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 71 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 72 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 73 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 74 * POSSIBILITY OF SUCH DAMAGE. 75 */ 76 77 #include <sys/cdefs.h> 78 __KERNEL_RCSID(0, "$NetBSD: if_iavf.c,v 1.19 2025/02/25 02:10:13 joe Exp $"); 79 80 #include <sys/param.h> 81 #include <sys/types.h> 82 83 #include <sys/bitops.h> 84 #include <sys/bus.h> 85 #include <sys/cprng.h> 86 #include <sys/cpu.h> 87 #include <sys/device.h> 88 #include <sys/evcnt.h> 89 #include <sys/interrupt.h> 90 #include <sys/kmem.h> 91 #include <sys/module.h> 92 #include <sys/mutex.h> 93 #include <sys/pcq.h> 94 #include <sys/queue.h> 95 #include <sys/syslog.h> 96 #include <sys/workqueue.h> 97 #include <sys/xcall.h> 98 99 #include <net/bpf.h> 100 #include <net/if.h> 101 #include <net/if_dl.h> 102 #include <net/if_media.h> 103 #include <net/if_ether.h> 104 #include <net/rss_config.h> 105 106 #include <netinet/tcp.h> /* for struct tcphdr */ 107 #include <netinet/udp.h> /* for struct udphdr */ 108 109 #include <dev/pci/pcivar.h> 110 #include <dev/pci/pcidevs.h> 111 112 #include <dev/pci/if_ixlreg.h> 113 #include <dev/pci/if_ixlvar.h> 114 #include <dev/pci/if_iavfvar.h> 115 116 #include <prop/proplib.h> 117 118 #define IAVF_PCIREG PCI_MAPREG_START 119 #define IAVF_AQ_NUM 256 120 #define IAVF_AQ_MASK (IAVF_AQ_NUM-1) 121 #define IAVF_AQ_ALIGN 64 122 #define IAVF_AQ_BUFLEN 4096 123 #define I40E_AQ_LARGE_BUF 512 124 #define IAVF_VF_MAJOR 1 125 #define IAVF_VF_MINOR 1 126 127 #define IAVF_VFR_INPROGRESS 0 128 #define IAVF_VFR_COMPLETED 1 129 #define IAVF_VFR_VFACTIVE 2 130 131 #define IAVF_REG_VFR 0xdeadbeef 132 133 #define IAVF_ITR_RX 0x0 134 #define IAVF_ITR_TX 0x1 135 #define IAVF_ITR_MISC 0x2 136 #define IAVF_NOITR 0x3 137 138 #define IAVF_MTU_ETHERLEN (ETHER_HDR_LEN \ 139 + ETHER_CRC_LEN) 140 #define IAVF_MAX_MTU (9600 - IAVF_MTU_ETHERLEN) 141 #define IAVF_MIN_MTU (ETHER_MIN_LEN - ETHER_CRC_LEN) 142 143 #define IAVF_WORKQUEUE_PRI PRI_SOFTNET 144 145 #define IAVF_TX_PKT_DESCS 8 146 #define IAVF_TX_QUEUE_ALIGN 128 147 #define IAVF_RX_QUEUE_ALIGN 128 148 #define IAVF_TX_PKT_MAXSIZE (MCLBYTES * IAVF_TX_PKT_DESCS) 149 #define IAVF_MCLBYTES (MCLBYTES - ETHER_ALIGN) 150 151 #define IAVF_TICK_INTERVAL (5 * hz) 152 #define IAVF_WATCHDOG_TICKS 3 153 #define IAVF_WATCHDOG_STOP 0 154 155 #define IAVF_TXRX_PROCESS_UNLIMIT UINT_MAX 156 #define IAVF_TX_PROCESS_LIMIT 256 157 #define IAVF_RX_PROCESS_LIMIT 256 158 #define IAVF_TX_INTR_PROCESS_LIMIT 256 159 #define IAVF_RX_INTR_PROCESS_LIMIT 0U 160 161 #define IAVF_EXEC_TIMEOUT 3000 162 163 #define IAVF_IFCAP_RXCSUM (IFCAP_CSUM_IPv4_Rx | \ 164 IFCAP_CSUM_TCPv4_Rx | \ 165 IFCAP_CSUM_UDPv4_Rx | \ 166 IFCAP_CSUM_TCPv6_Rx | \ 167 IFCAP_CSUM_UDPv6_Rx) 168 #define IAVF_IFCAP_TXCSUM (IFCAP_CSUM_IPv4_Tx | \ 169 IFCAP_CSUM_TCPv4_Tx | \ 170 IFCAP_CSUM_UDPv4_Tx | \ 171 IFCAP_CSUM_TCPv6_Tx | \ 172 IFCAP_CSUM_UDPv6_Tx) 173 #define IAVF_CSUM_ALL_OFFLOAD (M_CSUM_IPv4 | \ 174 M_CSUM_TCPv4 | M_CSUM_TCPv6 | \ 175 M_CSUM_UDPv4 | M_CSUM_UDPv6) 176 177 struct iavf_softc; /* defined */ 178 179 struct iavf_module_params { 180 int debug; 181 uint32_t rx_itr; 182 uint32_t tx_itr; 183 unsigned int rx_ndescs; 184 unsigned int tx_ndescs; 185 int max_qps; 186 }; 187 188 struct iavf_product { 189 unsigned int vendor_id; 190 unsigned int product_id; 191 }; 192 193 struct iavf_link_speed { 194 uint64_t baudrate; 195 uint64_t media; 196 }; 197 198 struct iavf_aq_regs { 199 bus_size_t atq_tail; 200 bus_size_t atq_head; 201 bus_size_t atq_len; 202 bus_size_t atq_bal; 203 bus_size_t atq_bah; 204 205 bus_size_t arq_tail; 206 bus_size_t arq_head; 207 bus_size_t arq_len; 208 bus_size_t arq_bal; 209 bus_size_t arq_bah; 210 211 uint32_t atq_len_enable; 212 uint32_t atq_tail_mask; 213 uint32_t atq_head_mask; 214 215 uint32_t arq_len_enable; 216 uint32_t arq_tail_mask; 217 uint32_t arq_head_mask; 218 }; 219 220 struct iavf_work { 221 struct work ixw_cookie; 222 void (*ixw_func)(void *); 223 void *ixw_arg; 224 unsigned int ixw_added; 225 }; 226 227 struct iavf_tx_map { 228 struct mbuf *txm_m; 229 bus_dmamap_t txm_map; 230 unsigned int txm_eop; 231 }; 232 233 struct iavf_tx_ring { 234 unsigned int txr_qid; 235 char txr_name[16]; 236 237 struct iavf_softc *txr_sc; 238 kmutex_t txr_lock; 239 pcq_t *txr_intrq; 240 void *txr_si; 241 unsigned int txr_prod; 242 unsigned int txr_cons; 243 244 struct iavf_tx_map *txr_maps; 245 struct ixl_dmamem txr_mem; 246 bus_size_t txr_tail; 247 248 int txr_watchdog; 249 250 struct evcnt txr_defragged; 251 struct evcnt txr_defrag_failed; 252 struct evcnt txr_pcqdrop; 253 struct evcnt txr_transmitdef; 254 struct evcnt txr_defer; 255 struct evcnt txr_watchdogto; 256 struct evcnt txr_intr; 257 }; 258 259 struct iavf_rx_map { 260 struct mbuf *rxm_m; 261 bus_dmamap_t rxm_map; 262 }; 263 264 struct iavf_rx_ring { 265 unsigned int rxr_qid; 266 char rxr_name[16]; 267 268 struct iavf_softc *rxr_sc; 269 kmutex_t rxr_lock; 270 271 unsigned int rxr_prod; 272 unsigned int rxr_cons; 273 274 struct iavf_rx_map *rxr_maps; 275 struct ixl_dmamem rxr_mem; 276 bus_size_t rxr_tail; 277 278 struct mbuf *rxr_m_head; 279 struct mbuf **rxr_m_tail; 280 281 struct evcnt rxr_mgethdr_failed; 282 struct evcnt rxr_mgetcl_failed; 283 struct evcnt rxr_mbuf_load_failed; 284 struct evcnt rxr_defer; 285 struct evcnt rxr_intr; 286 }; 287 288 struct iavf_queue_pair { 289 struct iavf_tx_ring *qp_txr; 290 struct iavf_rx_ring *qp_rxr; 291 struct work qp_work; 292 void *qp_si; 293 bool qp_workqueue; 294 }; 295 296 struct iavf_stat_counters { 297 struct evcnt isc_rx_bytes; 298 struct evcnt isc_rx_unicast; 299 struct evcnt isc_rx_multicast; 300 struct evcnt isc_rx_broadcast; 301 struct evcnt isc_rx_discards; 302 struct evcnt isc_rx_unknown_protocol; 303 struct evcnt isc_tx_bytes; 304 struct evcnt isc_tx_unicast; 305 struct evcnt isc_tx_multicast; 306 struct evcnt isc_tx_broadcast; 307 struct evcnt isc_tx_discards; 308 struct evcnt isc_tx_errors; 309 }; 310 311 /* 312 * Locking notes: 313 * + A field in iavf_tx_ring is protected by txr_lock (a spin mutex), and 314 * A field in iavf_rx_ring is protected by rxr_lock (a spin mutex). 315 * - more than one lock must not be held at once. 316 * + fields named sc_atq_*, sc_arq_*, and sc_adminq_* are protected by 317 * sc_adminq_lock(a spin mutex). 318 * - The lock is held while accessing sc_aq_regs 319 * and is not held with txr_lock and rxr_lock together. 320 * + Other fields in iavf_softc is protected by sc_cfg_lock 321 * (an adaptive mutex). 322 * - The lock must be held before acquiring another lock. 323 * 324 * Locking order: 325 * - IFNET_LOCK => sc_cfg_lock => sc_adminq_lock 326 * - sc_cfg_lock => ETHER_LOCK => sc_adminq_lock 327 * - sc_cfg_lock => txr_lock 328 * - sc_cfg_lock => rxr_lock 329 */ 330 331 struct iavf_softc { 332 device_t sc_dev; 333 enum i40e_mac_type sc_mac_type; 334 int sc_debuglevel; 335 bool sc_attached; 336 bool sc_dead; 337 kmutex_t sc_cfg_lock; 338 callout_t sc_tick; 339 struct ifmedia sc_media; 340 uint64_t sc_media_status; 341 uint64_t sc_media_active; 342 int sc_link_state; 343 344 const struct iavf_aq_regs * 345 sc_aq_regs; 346 347 struct ethercom sc_ec; 348 uint8_t sc_enaddr[ETHER_ADDR_LEN]; 349 uint8_t sc_enaddr_fake[ETHER_ADDR_LEN]; 350 uint8_t sc_enaddr_added[ETHER_ADDR_LEN]; 351 uint8_t sc_enaddr_reset[ETHER_ADDR_LEN]; 352 struct if_percpuq *sc_ipq; 353 354 struct pci_attach_args sc_pa; 355 bus_dma_tag_t sc_dmat; 356 bus_space_tag_t sc_memt; 357 bus_space_handle_t sc_memh; 358 bus_size_t sc_mems; 359 pci_intr_handle_t *sc_ihp; 360 void **sc_ihs; 361 unsigned int sc_nintrs; 362 363 uint32_t sc_major_ver; 364 uint32_t sc_minor_ver; 365 uint32_t sc_vf_id; 366 uint32_t sc_vf_cap; 367 uint16_t sc_vsi_id; 368 uint16_t sc_qset_handle; 369 uint16_t sc_max_mtu; 370 bool sc_got_vf_resources; 371 bool sc_got_irq_map; 372 unsigned int sc_max_vectors; 373 374 kmutex_t sc_adminq_lock; 375 kcondvar_t sc_adminq_cv; 376 struct ixl_dmamem sc_atq; 377 unsigned int sc_atq_prod; 378 unsigned int sc_atq_cons; 379 struct ixl_aq_bufs sc_atq_idle; 380 struct ixl_aq_bufs sc_atq_live; 381 struct ixl_dmamem sc_arq; 382 struct ixl_aq_bufs sc_arq_idle; 383 struct ixl_aq_bufs sc_arq_live; 384 unsigned int sc_arq_prod; 385 unsigned int sc_arq_cons; 386 struct iavf_work sc_arq_refill; 387 uint32_t sc_arq_opcode; 388 uint32_t sc_arq_retval; 389 390 uint32_t sc_tx_itr; 391 uint32_t sc_rx_itr; 392 unsigned int sc_tx_ring_ndescs; 393 unsigned int sc_rx_ring_ndescs; 394 unsigned int sc_nqueue_pairs; 395 unsigned int sc_nqps_alloc; 396 unsigned int sc_nqps_vsi; 397 unsigned int sc_nqps_req; 398 struct iavf_queue_pair *sc_qps; 399 bool sc_txrx_workqueue; 400 u_int sc_tx_intr_process_limit; 401 u_int sc_tx_process_limit; 402 u_int sc_rx_intr_process_limit; 403 u_int sc_rx_process_limit; 404 405 struct workqueue *sc_workq; 406 struct workqueue *sc_workq_txrx; 407 struct iavf_work sc_reset_task; 408 struct iavf_work sc_wdto_task; 409 struct iavf_work sc_req_queues_task; 410 bool sc_req_queues_retried; 411 bool sc_resetting; 412 bool sc_reset_up; 413 414 struct sysctllog *sc_sysctllog; 415 struct iavf_stat_counters 416 sc_stat_counters; 417 }; 418 419 #define IAVF_LOG(_sc, _lvl, _fmt, _args...) \ 420 do { \ 421 if (!(_sc)->sc_attached) { \ 422 switch (_lvl) { \ 423 case LOG_ERR: \ 424 case LOG_WARNING: \ 425 aprint_error_dev((_sc)->sc_dev, _fmt, ##_args); \ 426 break; \ 427 case LOG_INFO: \ 428 aprint_normal_dev((_sc)->sc_dev,_fmt, ##_args); \ 429 break; \ 430 case LOG_DEBUG: \ 431 default: \ 432 aprint_debug_dev((_sc)->sc_dev, _fmt, ##_args); \ 433 } \ 434 } else { \ 435 struct ifnet *_ifp = &(_sc)->sc_ec.ec_if; \ 436 log((_lvl), "%s: " _fmt, _ifp->if_xname, ##_args); \ 437 } \ 438 } while (0) 439 440 static int iavf_dmamem_alloc(bus_dma_tag_t, struct ixl_dmamem *, 441 bus_size_t, bus_size_t); 442 static void iavf_dmamem_free(bus_dma_tag_t, struct ixl_dmamem *); 443 static struct ixl_aq_buf * 444 iavf_aqb_get(struct iavf_softc *, struct ixl_aq_bufs *); 445 static struct ixl_aq_buf * 446 iavf_aqb_get_locked(struct ixl_aq_bufs *); 447 static void iavf_aqb_put_locked(struct ixl_aq_bufs *, struct ixl_aq_buf *); 448 static void iavf_aqb_clean(struct ixl_aq_bufs *, bus_dma_tag_t); 449 450 static const struct iavf_product * 451 iavf_lookup(const struct pci_attach_args *); 452 static enum i40e_mac_type 453 iavf_mactype(pci_product_id_t); 454 static void iavf_pci_csr_setup(pci_chipset_tag_t, pcitag_t); 455 static int iavf_wait_active(struct iavf_softc *); 456 static bool iavf_is_etheranyaddr(const uint8_t *); 457 static void iavf_prepare_fakeaddr(struct iavf_softc *); 458 static int iavf_replace_lla(struct ifnet *, 459 const uint8_t *, const uint8_t *); 460 static void iavf_evcnt_attach(struct evcnt *, 461 const char *, const char *); 462 static int iavf_setup_interrupts(struct iavf_softc *); 463 static void iavf_teardown_interrupts(struct iavf_softc *); 464 static int iavf_setup_sysctls(struct iavf_softc *); 465 static void iavf_teardown_sysctls(struct iavf_softc *); 466 static int iavf_setup_stats(struct iavf_softc *); 467 static void iavf_teardown_stats(struct iavf_softc *); 468 static struct workqueue * 469 iavf_workq_create(const char *, pri_t, int, int); 470 static void iavf_workq_destroy(struct workqueue *); 471 static int iavf_work_set(struct iavf_work *, void (*)(void *), void *); 472 static void iavf_work_add(struct workqueue *, struct iavf_work *); 473 static void iavf_work_wait(struct workqueue *, struct iavf_work *); 474 static unsigned int 475 iavf_calc_msix_count(struct iavf_softc *); 476 static unsigned int 477 iavf_calc_queue_pair_size(struct iavf_softc *); 478 static int iavf_queue_pairs_alloc(struct iavf_softc *); 479 static void iavf_queue_pairs_free(struct iavf_softc *); 480 static int iavf_arq_fill(struct iavf_softc *); 481 static void iavf_arq_refill(void *); 482 static int iavf_arq_poll(struct iavf_softc *, uint32_t, int); 483 static void iavf_atq_done(struct iavf_softc *); 484 static int iavf_init_admin_queue(struct iavf_softc *); 485 static void iavf_cleanup_admin_queue(struct iavf_softc *); 486 static int iavf_arq(struct iavf_softc *); 487 static int iavf_adminq_exec(struct iavf_softc *, 488 struct ixl_aq_desc *, struct ixl_aq_buf *); 489 static int iavf_adminq_poll(struct iavf_softc *, 490 struct ixl_aq_desc *, struct ixl_aq_buf *, int); 491 static int iavf_adminq_poll_locked(struct iavf_softc *, 492 struct ixl_aq_desc *, struct ixl_aq_buf *, int); 493 static int iavf_add_multi(struct iavf_softc *, uint8_t *, uint8_t *); 494 static int iavf_del_multi(struct iavf_softc *, uint8_t *, uint8_t *); 495 static void iavf_del_all_multi(struct iavf_softc *); 496 497 static int iavf_get_version(struct iavf_softc *, struct ixl_aq_buf *); 498 static int iavf_get_vf_resources(struct iavf_softc *, struct ixl_aq_buf *); 499 static int iavf_get_stats(struct iavf_softc *); 500 static int iavf_config_irq_map(struct iavf_softc *, struct ixl_aq_buf *); 501 static int iavf_config_vsi_queues(struct iavf_softc *); 502 static int iavf_config_hena(struct iavf_softc *); 503 static int iavf_config_rss_key(struct iavf_softc *); 504 static int iavf_config_rss_lut(struct iavf_softc *); 505 static int iavf_config_promisc_mode(struct iavf_softc *, int, int); 506 static int iavf_config_vlan_stripping(struct iavf_softc *, int); 507 static int iavf_config_vlan_id(struct iavf_softc *, uint16_t, uint32_t); 508 static int iavf_queue_select(struct iavf_softc *, int); 509 static int iavf_request_queues(struct iavf_softc *, unsigned int); 510 static int iavf_reset_vf(struct iavf_softc *); 511 static int iavf_eth_addr(struct iavf_softc *, const uint8_t *, uint32_t); 512 static void iavf_process_version(struct iavf_softc *, 513 struct ixl_aq_desc *, struct ixl_aq_buf *); 514 static void iavf_process_vf_resources(struct iavf_softc *, 515 struct ixl_aq_desc *, struct ixl_aq_buf *); 516 static void iavf_process_irq_map(struct iavf_softc *, 517 struct ixl_aq_desc *); 518 static void iavf_process_vc_event(struct iavf_softc *, 519 struct ixl_aq_desc *, struct ixl_aq_buf *); 520 static void iavf_process_stats(struct iavf_softc *, 521 struct ixl_aq_desc *, struct ixl_aq_buf *); 522 static void iavf_process_req_queues(struct iavf_softc *, 523 struct ixl_aq_desc *, struct ixl_aq_buf *); 524 525 static int iavf_intr(void *); 526 static int iavf_queue_intr(void *); 527 static void iavf_tick(void *); 528 static void iavf_tick_halt(void *); 529 static void iavf_reset_request(void *); 530 static void iavf_reset_start(void *); 531 static void iavf_reset(void *); 532 static void iavf_reset_finish(struct iavf_softc *); 533 static int iavf_init(struct ifnet *); 534 static int iavf_init_locked(struct iavf_softc *); 535 static void iavf_stop(struct ifnet *, int); 536 static void iavf_stop_locked(struct iavf_softc *); 537 static int iavf_ioctl(struct ifnet *, u_long, void *); 538 static void iavf_start(struct ifnet *); 539 static int iavf_transmit(struct ifnet *, struct mbuf*); 540 static int iavf_watchdog(struct iavf_tx_ring *); 541 static void iavf_watchdog_timeout(void *); 542 static int iavf_media_change(struct ifnet *); 543 static void iavf_media_status(struct ifnet *, struct ifmediareq *); 544 static int iavf_ifflags_cb(struct ethercom *); 545 static int iavf_vlan_cb(struct ethercom *, uint16_t, bool); 546 static void iavf_deferred_transmit(void *); 547 static void iavf_handle_queue(void *); 548 static void iavf_handle_queue_wk(struct work *, void *); 549 static int iavf_reinit(struct iavf_softc *); 550 static int iavf_rxfill(struct iavf_softc *, struct iavf_rx_ring *); 551 static void iavf_txr_clean(struct iavf_softc *, struct iavf_tx_ring *); 552 static void iavf_rxr_clean(struct iavf_softc *, struct iavf_rx_ring *); 553 static int iavf_txeof(struct iavf_softc *, struct iavf_tx_ring *, 554 u_int, struct evcnt *); 555 static int iavf_rxeof(struct iavf_softc *, struct iavf_rx_ring *, 556 u_int, struct evcnt *); 557 static int iavf_iff(struct iavf_softc *); 558 static int iavf_iff_locked(struct iavf_softc *); 559 static void iavf_post_request_queues(void *); 560 static int iavf_sysctl_itr_handler(SYSCTLFN_PROTO); 561 562 static int iavf_match(device_t, cfdata_t, void *); 563 static void iavf_attach(device_t, device_t, void*); 564 static int iavf_detach(device_t, int); 565 static int iavf_finalize_teardown(device_t); 566 567 CFATTACH_DECL3_NEW(iavf, sizeof(struct iavf_softc), 568 iavf_match, iavf_attach, iavf_detach, NULL, NULL, NULL, 569 DVF_DETACH_SHUTDOWN); 570 571 static const struct iavf_product iavf_products[] = { 572 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XL710_VF }, 573 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XL710_VF_HV }, 574 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X722_VF }, 575 /* required last entry */ 576 {0, 0} 577 }; 578 579 static const struct iavf_link_speed iavf_link_speeds[] = { 580 { 0, 0 }, 581 { IF_Mbps(100), IFM_100_TX }, 582 { IF_Mbps(1000), IFM_1000_T }, 583 { IF_Gbps(10), IFM_10G_T }, 584 { IF_Gbps(40), IFM_40G_CR4 }, 585 { IF_Gbps(20), IFM_20G_KR2 }, 586 { IF_Gbps(25), IFM_25G_CR } 587 }; 588 589 static const struct iavf_aq_regs iavf_aq_regs = { 590 .atq_tail = I40E_VF_ATQT1, 591 .atq_tail_mask = I40E_VF_ATQT1_ATQT_MASK, 592 .atq_head = I40E_VF_ATQH1, 593 .atq_head_mask = I40E_VF_ARQH1_ARQH_MASK, 594 .atq_len = I40E_VF_ATQLEN1, 595 .atq_bal = I40E_VF_ATQBAL1, 596 .atq_bah = I40E_VF_ATQBAH1, 597 .atq_len_enable = I40E_VF_ATQLEN1_ATQENABLE_MASK, 598 599 .arq_tail = I40E_VF_ARQT1, 600 .arq_tail_mask = I40E_VF_ARQT1_ARQT_MASK, 601 .arq_head = I40E_VF_ARQH1, 602 .arq_head_mask = I40E_VF_ARQH1_ARQH_MASK, 603 .arq_len = I40E_VF_ARQLEN1, 604 .arq_bal = I40E_VF_ARQBAL1, 605 .arq_bah = I40E_VF_ARQBAH1, 606 .arq_len_enable = I40E_VF_ARQLEN1_ARQENABLE_MASK, 607 }; 608 609 static struct iavf_module_params iavf_params = { 610 .debug = 0, 611 .rx_itr = 0x07a, /* 4K intrs/sec */ 612 .tx_itr = 0x07a, /* 4K intrs/sec */ 613 .tx_ndescs = 512, 614 .rx_ndescs = 256, 615 .max_qps = INT_MAX, 616 }; 617 618 #define delaymsec(_x) DELAY(1000 * (_x)) 619 #define iavf_rd(_s, _r) \ 620 bus_space_read_4((_s)->sc_memt, (_s)->sc_memh, (_r)) 621 #define iavf_wr(_s, _r, _v) \ 622 bus_space_write_4((_s)->sc_memt, (_s)->sc_memh, (_r), (_v)) 623 #define iavf_barrier(_s, _r, _l, _o) \ 624 bus_space_barrier((_s)->sc_memt, (_s)->sc_memh, (_r), (_l), (_o)) 625 #define iavf_flush(_s) (void)iavf_rd((_s), I40E_VFGEN_RSTAT) 626 #define iavf_nqueues(_sc) (1 << ((_sc)->sc_nqueue_pairs - 1)) 627 #define iavf_allqueues(_sc) ((1 << ((_sc)->sc_nqueue_pairs)) - 1) 628 629 static inline void 630 iavf_intr_barrier(void) 631 { 632 633 /* make all interrupt handler finished */ 634 xc_barrier(0); 635 } 636 static inline void 637 iavf_intr_enable(struct iavf_softc *sc) 638 { 639 640 iavf_wr(sc, I40E_VFINT_DYN_CTL01, I40E_VFINT_DYN_CTL0_INTENA_MASK | 641 I40E_VFINT_DYN_CTL0_CLEARPBA_MASK | 642 (IAVF_NOITR << I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT)); 643 iavf_wr(sc, I40E_VFINT_ICR0_ENA1, I40E_VFINT_ICR0_ENA1_ADMINQ_MASK); 644 iavf_flush(sc); 645 } 646 647 static inline void 648 iavf_intr_disable(struct iavf_softc *sc) 649 { 650 651 iavf_wr(sc, I40E_VFINT_DYN_CTL01, 652 (IAVF_NOITR << I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT)); 653 iavf_wr(sc, I40E_VFINT_ICR0_ENA1, 0); 654 iavf_flush(sc); 655 } 656 657 static inline void 658 iavf_queue_intr_enable(struct iavf_softc *sc, unsigned int qid) 659 { 660 661 iavf_wr(sc, I40E_VFINT_DYN_CTLN1(qid), 662 I40E_VFINT_DYN_CTLN1_INTENA_MASK | 663 I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK | 664 (IAVF_NOITR << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT)); 665 iavf_flush(sc); 666 } 667 668 static inline void 669 iavf_queue_intr_disable(struct iavf_softc *sc, unsigned int qid) 670 { 671 672 iavf_wr(sc, I40E_VFINT_DYN_CTLN1(qid), 673 (IAVF_NOITR << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT)); 674 iavf_flush(sc); 675 } 676 677 static inline void 678 iavf_aq_vc_set_opcode(struct ixl_aq_desc *iaq, uint32_t opcode) 679 { 680 struct iavf_aq_vc *vc; 681 682 vc = (struct iavf_aq_vc *)&iaq->iaq_cookie; 683 vc->iaq_vc_opcode = htole32(opcode); 684 } 685 686 static inline uint32_t 687 iavf_aq_vc_get_opcode(const struct ixl_aq_desc *iaq) 688 { 689 const struct iavf_aq_vc *vc; 690 691 vc = (const struct iavf_aq_vc *)&iaq->iaq_cookie; 692 return le32toh(vc->iaq_vc_opcode); 693 } 694 695 static inline uint32_t 696 iavf_aq_vc_get_retval(const struct ixl_aq_desc *iaq) 697 { 698 const struct iavf_aq_vc *vc; 699 700 vc = (const struct iavf_aq_vc *)&iaq->iaq_cookie; 701 return le32toh(vc->iaq_vc_retval); 702 } 703 704 static int 705 iavf_match(device_t parent, cfdata_t match, void *aux) 706 { 707 const struct pci_attach_args *pa = aux; 708 709 return (iavf_lookup(pa) != NULL) ? 1 : 0; 710 } 711 712 static void 713 iavf_attach(device_t parent, device_t self, void *aux) 714 { 715 struct iavf_softc *sc; 716 struct pci_attach_args *pa = aux; 717 struct ifnet *ifp; 718 struct ixl_aq_buf *aqb; 719 pcireg_t memtype; 720 char xnamebuf[MAXCOMLEN]; 721 int error, i; 722 723 sc = device_private(self); 724 sc->sc_dev = self; 725 ifp = &sc->sc_ec.ec_if; 726 727 sc->sc_pa = *pa; 728 sc->sc_dmat = (pci_dma64_available(pa)) ? pa->pa_dmat64 : pa->pa_dmat; 729 sc->sc_aq_regs = &iavf_aq_regs; 730 sc->sc_debuglevel = iavf_params.debug; 731 sc->sc_tx_ring_ndescs = iavf_params.tx_ndescs; 732 sc->sc_rx_ring_ndescs = iavf_params.rx_ndescs; 733 sc->sc_tx_itr = iavf_params.tx_itr; 734 sc->sc_rx_itr = iavf_params.rx_itr; 735 sc->sc_nqps_req = MIN(ncpu, iavf_params.max_qps); 736 iavf_prepare_fakeaddr(sc); 737 738 sc->sc_mac_type = iavf_mactype(PCI_PRODUCT(pa->pa_id)); 739 iavf_pci_csr_setup(pa->pa_pc, pa->pa_tag); 740 741 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, IAVF_PCIREG); 742 if (pci_mapreg_map(pa, IAVF_PCIREG, memtype, 0, 743 &sc->sc_memt, &sc->sc_memh, NULL, &sc->sc_mems)) { 744 aprint_error(": unable to map registers\n"); 745 return; 746 } 747 748 if (iavf_wait_active(sc) != 0) { 749 aprint_error(": VF reset timed out\n"); 750 goto unmap; 751 } 752 753 mutex_init(&sc->sc_cfg_lock, MUTEX_DEFAULT, IPL_SOFTNET); 754 mutex_init(&sc->sc_adminq_lock, MUTEX_DEFAULT, IPL_NET); 755 SIMPLEQ_INIT(&sc->sc_atq_idle); 756 SIMPLEQ_INIT(&sc->sc_atq_live); 757 SIMPLEQ_INIT(&sc->sc_arq_idle); 758 SIMPLEQ_INIT(&sc->sc_arq_live); 759 sc->sc_arq_cons = 0; 760 sc->sc_arq_prod = 0; 761 aqb = NULL; 762 763 if (iavf_dmamem_alloc(sc->sc_dmat, &sc->sc_atq, 764 sizeof(struct ixl_aq_desc) * IAVF_AQ_NUM, IAVF_AQ_ALIGN) != 0) { 765 aprint_error(": unable to allocate atq\n"); 766 goto free_mutex; 767 } 768 769 if (iavf_dmamem_alloc(sc->sc_dmat, &sc->sc_arq, 770 sizeof(struct ixl_aq_desc) * IAVF_AQ_NUM, IAVF_AQ_ALIGN) != 0) { 771 aprint_error(": unable to allocate arq\n"); 772 goto free_atq; 773 } 774 775 for (i = 0; i < IAVF_AQ_NUM; i++) { 776 aqb = iavf_aqb_get(sc, NULL); 777 if (aqb != NULL) { 778 iavf_aqb_put_locked(&sc->sc_arq_idle, aqb); 779 } 780 } 781 aqb = NULL; 782 783 if (!iavf_arq_fill(sc)) { 784 aprint_error(": unable to fill arq descriptors\n"); 785 goto free_arq; 786 } 787 788 if (iavf_init_admin_queue(sc) != 0) { 789 aprint_error(": unable to initialize admin queue\n"); 790 goto shutdown; 791 } 792 793 aqb = iavf_aqb_get(sc, NULL); 794 if (aqb == NULL) { 795 aprint_error(": unable to allocate buffer for ATQ\n"); 796 goto shutdown; 797 } 798 799 error = iavf_get_version(sc, aqb); 800 switch (error) { 801 case 0: 802 break; 803 case ETIMEDOUT: 804 aprint_error(": timeout waiting for VF version\n"); 805 goto shutdown; 806 case ENOTSUP: 807 aprint_error(": unsupported VF version %d\n", sc->sc_major_ver); 808 goto shutdown; 809 default: 810 aprint_error(":unable to get VF interface version\n"); 811 goto shutdown; 812 } 813 814 if (iavf_get_vf_resources(sc, aqb) != 0) { 815 aprint_error(": timeout waiting for VF resources\n"); 816 goto shutdown; 817 } 818 819 aprint_normal(", VF version %d.%d%s", 820 sc->sc_major_ver, sc->sc_minor_ver, 821 (sc->sc_minor_ver > IAVF_VF_MINOR) ? "(minor mismatch)" : ""); 822 aprint_normal(", VF %d, VSI %d", sc->sc_vf_id, sc->sc_vsi_id); 823 aprint_normal("\n"); 824 aprint_naive("\n"); 825 826 aprint_normal_dev(self, "Ethernet address %s\n", 827 ether_sprintf(sc->sc_enaddr)); 828 829 if (iavf_queue_pairs_alloc(sc) != 0) { 830 goto shutdown; 831 } 832 833 if (iavf_setup_interrupts(sc) != 0) { 834 goto free_queue_pairs; 835 } 836 837 if (iavf_config_irq_map(sc, aqb) != 0) { 838 aprint_error(", timed out waiting for IRQ map response\n"); 839 goto teardown_intrs; 840 } 841 842 if (iavf_setup_sysctls(sc) != 0) { 843 goto teardown_intrs; 844 } 845 846 if (iavf_setup_stats(sc) != 0) { 847 goto teardown_sysctls; 848 } 849 850 iavf_aqb_put_locked(&sc->sc_atq_idle, aqb); 851 aqb = NULL; 852 853 snprintf(xnamebuf, sizeof(xnamebuf), 854 "%s_adminq_cv", device_xname(self)); 855 cv_init(&sc->sc_adminq_cv, xnamebuf); 856 857 callout_init(&sc->sc_tick, CALLOUT_MPSAFE); 858 callout_setfunc(&sc->sc_tick, iavf_tick, sc); 859 860 iavf_work_set(&sc->sc_reset_task, iavf_reset_start, sc); 861 iavf_work_set(&sc->sc_arq_refill, iavf_arq_refill, sc); 862 iavf_work_set(&sc->sc_wdto_task, iavf_watchdog_timeout, sc); 863 iavf_work_set(&sc->sc_req_queues_task, iavf_post_request_queues, sc); 864 snprintf(xnamebuf, sizeof(xnamebuf), "%s_wq_cfg", device_xname(self)); 865 sc->sc_workq = iavf_workq_create(xnamebuf, IAVF_WORKQUEUE_PRI, 866 IPL_NET, WQ_MPSAFE); 867 if (sc->sc_workq == NULL) 868 goto destroy_cv; 869 870 snprintf(xnamebuf, sizeof(xnamebuf), "%s_wq_txrx", device_xname(self)); 871 error = workqueue_create(&sc->sc_workq_txrx, xnamebuf, 872 iavf_handle_queue_wk, sc, IAVF_WORKQUEUE_PRI, IPL_NET, 873 WQ_PERCPU|WQ_MPSAFE); 874 if (error != 0) { 875 sc->sc_workq_txrx = NULL; 876 goto teardown_wqs; 877 } 878 879 if_initialize(ifp); 880 881 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 882 883 ifp->if_softc = sc; 884 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 885 ifp->if_extflags = IFEF_MPSAFE; 886 ifp->if_ioctl = iavf_ioctl; 887 ifp->if_start = iavf_start; 888 ifp->if_transmit = iavf_transmit; 889 ifp->if_watchdog = NULL; 890 ifp->if_init = iavf_init; 891 ifp->if_stop = iavf_stop; 892 893 IFQ_SET_MAXLEN(&ifp->if_snd, sc->sc_tx_ring_ndescs); 894 IFQ_SET_READY(&ifp->if_snd); 895 sc->sc_ipq = if_percpuq_create(ifp); 896 897 ifp->if_capabilities |= IAVF_IFCAP_RXCSUM; 898 ifp->if_capabilities |= IAVF_IFCAP_TXCSUM; 899 900 ether_set_vlan_cb(&sc->sc_ec, iavf_vlan_cb); 901 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 902 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_HWFILTER; 903 sc->sc_ec.ec_capenable = sc->sc_ec.ec_capabilities; 904 905 ether_set_ifflags_cb(&sc->sc_ec, iavf_ifflags_cb); 906 907 sc->sc_ec.ec_ifmedia = &sc->sc_media; 908 ifmedia_init_with_lock(&sc->sc_media, IFM_IMASK, iavf_media_change, 909 iavf_media_status, &sc->sc_cfg_lock); 910 911 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_AUTO, 0, NULL); 912 ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_AUTO); 913 914 if_deferred_start_init(ifp, NULL); 915 ether_ifattach(ifp, sc->sc_enaddr); 916 917 sc->sc_txrx_workqueue = true; 918 sc->sc_tx_process_limit = IAVF_TX_PROCESS_LIMIT; 919 sc->sc_rx_process_limit = IAVF_RX_PROCESS_LIMIT; 920 sc->sc_tx_intr_process_limit = IAVF_TX_INTR_PROCESS_LIMIT; 921 sc->sc_rx_intr_process_limit = IAVF_RX_INTR_PROCESS_LIMIT; 922 923 if_register(ifp); 924 if_link_state_change(ifp, sc->sc_link_state); 925 iavf_intr_enable(sc); 926 if (sc->sc_nqps_vsi < sc->sc_nqps_req) 927 iavf_work_add(sc->sc_workq, &sc->sc_req_queues_task); 928 sc->sc_attached = true; 929 return; 930 931 teardown_wqs: 932 config_finalize_register(self, iavf_finalize_teardown); 933 destroy_cv: 934 cv_destroy(&sc->sc_adminq_cv); 935 callout_destroy(&sc->sc_tick); 936 iavf_teardown_stats(sc); 937 teardown_sysctls: 938 iavf_teardown_sysctls(sc); 939 teardown_intrs: 940 iavf_teardown_interrupts(sc); 941 free_queue_pairs: 942 iavf_queue_pairs_free(sc); 943 shutdown: 944 if (aqb != NULL) 945 iavf_aqb_put_locked(&sc->sc_atq_idle, aqb); 946 iavf_cleanup_admin_queue(sc); 947 iavf_aqb_clean(&sc->sc_atq_idle, sc->sc_dmat); 948 iavf_aqb_clean(&sc->sc_arq_idle, sc->sc_dmat); 949 free_arq: 950 iavf_dmamem_free(sc->sc_dmat, &sc->sc_arq); 951 free_atq: 952 iavf_dmamem_free(sc->sc_dmat, &sc->sc_atq); 953 free_mutex: 954 mutex_destroy(&sc->sc_cfg_lock); 955 mutex_destroy(&sc->sc_adminq_lock); 956 unmap: 957 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems); 958 sc->sc_mems = 0; 959 sc->sc_attached = false; 960 } 961 962 static int 963 iavf_detach(device_t self, int flags) 964 { 965 struct iavf_softc *sc = device_private(self); 966 struct ifnet *ifp = &sc->sc_ec.ec_if; 967 968 if (!sc->sc_attached) 969 return 0; 970 971 iavf_stop(ifp, 1); 972 973 /* 974 * set a dummy function to halt callout safely 975 * even if a workqueue entry calls callout_schedule() 976 */ 977 callout_setfunc(&sc->sc_tick, iavf_tick_halt, sc); 978 iavf_work_wait(sc->sc_workq, &sc->sc_reset_task); 979 iavf_work_wait(sc->sc_workq, &sc->sc_wdto_task); 980 981 callout_halt(&sc->sc_tick, NULL); 982 callout_destroy(&sc->sc_tick); 983 984 /* detach the I/F before stop adminq due to callbacks */ 985 ether_ifdetach(ifp); 986 if_detach(ifp); 987 ifmedia_fini(&sc->sc_media); 988 if_percpuq_destroy(sc->sc_ipq); 989 990 iavf_intr_disable(sc); 991 iavf_intr_barrier(); 992 iavf_work_wait(sc->sc_workq, &sc->sc_arq_refill); 993 994 mutex_enter(&sc->sc_adminq_lock); 995 iavf_cleanup_admin_queue(sc); 996 mutex_exit(&sc->sc_adminq_lock); 997 iavf_aqb_clean(&sc->sc_atq_idle, sc->sc_dmat); 998 iavf_aqb_clean(&sc->sc_arq_idle, sc->sc_dmat); 999 iavf_dmamem_free(sc->sc_dmat, &sc->sc_arq); 1000 iavf_dmamem_free(sc->sc_dmat, &sc->sc_atq); 1001 cv_destroy(&sc->sc_adminq_cv); 1002 1003 iavf_workq_destroy(sc->sc_workq); 1004 sc->sc_workq = NULL; 1005 1006 iavf_queue_pairs_free(sc); 1007 iavf_teardown_interrupts(sc); 1008 iavf_teardown_sysctls(sc); 1009 iavf_teardown_stats(sc); 1010 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems); 1011 1012 mutex_destroy(&sc->sc_adminq_lock); 1013 mutex_destroy(&sc->sc_cfg_lock); 1014 1015 return 0; 1016 } 1017 1018 static int 1019 iavf_finalize_teardown(device_t self) 1020 { 1021 struct iavf_softc *sc = device_private(self); 1022 1023 if (sc->sc_workq != NULL) { 1024 iavf_workq_destroy(sc->sc_workq); 1025 sc->sc_workq = NULL; 1026 } 1027 1028 if (sc->sc_workq_txrx != NULL) { 1029 workqueue_destroy(sc->sc_workq_txrx); 1030 sc->sc_workq_txrx = NULL; 1031 } 1032 1033 return 0; 1034 } 1035 1036 static int 1037 iavf_init(struct ifnet *ifp) 1038 { 1039 struct iavf_softc *sc; 1040 int rv; 1041 1042 sc = ifp->if_softc; 1043 mutex_enter(&sc->sc_cfg_lock); 1044 rv = iavf_init_locked(sc); 1045 mutex_exit(&sc->sc_cfg_lock); 1046 1047 return rv; 1048 } 1049 1050 static int 1051 iavf_init_locked(struct iavf_softc *sc) 1052 { 1053 struct ifnet *ifp = &sc->sc_ec.ec_if; 1054 unsigned int i; 1055 int error; 1056 1057 KASSERT(mutex_owned(&sc->sc_cfg_lock)); 1058 1059 if (ISSET(ifp->if_flags, IFF_RUNNING)) 1060 iavf_stop_locked(sc); 1061 1062 if (sc->sc_resetting) 1063 return ENXIO; 1064 1065 error = iavf_reinit(sc); 1066 if (error) { 1067 iavf_stop_locked(sc); 1068 return error; 1069 } 1070 1071 SET(ifp->if_flags, IFF_RUNNING); 1072 CLR(ifp->if_flags, IFF_OACTIVE); 1073 1074 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 1075 iavf_wr(sc, I40E_VFINT_ITRN1(IAVF_ITR_RX, i), sc->sc_rx_itr); 1076 iavf_wr(sc, I40E_VFINT_ITRN1(IAVF_ITR_TX, i), sc->sc_tx_itr); 1077 } 1078 iavf_wr(sc, I40E_VFINT_ITR01(IAVF_ITR_RX), sc->sc_rx_itr); 1079 iavf_wr(sc, I40E_VFINT_ITR01(IAVF_ITR_TX), sc->sc_tx_itr); 1080 iavf_wr(sc, I40E_VFINT_ITR01(IAVF_ITR_MISC), 0); 1081 1082 error = iavf_iff_locked(sc); 1083 if (error) { 1084 iavf_stop_locked(sc); 1085 return error; 1086 }; 1087 1088 /* ETHERCAP_VLAN_HWFILTER can not be disabled */ 1089 SET(sc->sc_ec.ec_capenable, ETHERCAP_VLAN_HWFILTER); 1090 1091 callout_schedule(&sc->sc_tick, IAVF_TICK_INTERVAL); 1092 return 0; 1093 } 1094 1095 static int 1096 iavf_reinit(struct iavf_softc *sc) 1097 { 1098 struct iavf_rx_ring *rxr; 1099 struct iavf_tx_ring *txr; 1100 unsigned int i; 1101 uint32_t reg; 1102 1103 KASSERT(mutex_owned(&sc->sc_cfg_lock)); 1104 1105 sc->sc_reset_up = true; 1106 sc->sc_nqueue_pairs = MIN(sc->sc_nqps_alloc, sc->sc_nintrs - 1); 1107 1108 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 1109 rxr = sc->sc_qps[i].qp_rxr; 1110 txr = sc->sc_qps[i].qp_txr; 1111 1112 iavf_rxfill(sc, rxr); 1113 txr->txr_watchdog = IAVF_WATCHDOG_STOP; 1114 } 1115 1116 if (iavf_config_vsi_queues(sc) != 0) 1117 return EIO; 1118 1119 if (iavf_config_hena(sc) != 0) 1120 return EIO; 1121 1122 iavf_config_rss_key(sc); 1123 iavf_config_rss_lut(sc); 1124 1125 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 1126 iavf_queue_intr_enable(sc, i); 1127 } 1128 /* unmask */ 1129 reg = iavf_rd(sc, I40E_VFINT_DYN_CTL01); 1130 reg |= (IAVF_NOITR << I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT); 1131 iavf_wr(sc, I40E_VFINT_DYN_CTL01, reg); 1132 1133 if (iavf_queue_select(sc, IAVF_VC_OP_ENABLE_QUEUES) != 0) 1134 return EIO; 1135 1136 return 0; 1137 } 1138 1139 static void 1140 iavf_stop(struct ifnet *ifp, int disable) 1141 { 1142 struct iavf_softc *sc; 1143 1144 sc = ifp->if_softc; 1145 mutex_enter(&sc->sc_cfg_lock); 1146 iavf_stop_locked(sc); 1147 mutex_exit(&sc->sc_cfg_lock); 1148 } 1149 1150 static void 1151 iavf_stop_locked(struct iavf_softc *sc) 1152 { 1153 struct ifnet *ifp = &sc->sc_ec.ec_if; 1154 struct iavf_rx_ring *rxr; 1155 struct iavf_tx_ring *txr; 1156 uint32_t reg; 1157 unsigned int i; 1158 1159 KASSERT(mutex_owned(&sc->sc_cfg_lock)); 1160 1161 CLR(ifp->if_flags, IFF_RUNNING); 1162 sc->sc_reset_up = false; 1163 callout_stop(&sc->sc_tick); 1164 1165 if (!sc->sc_resetting) { 1166 /* disable queues*/ 1167 if (iavf_queue_select(sc, IAVF_VC_OP_DISABLE_QUEUES) != 0) { 1168 goto die; 1169 } 1170 } 1171 1172 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 1173 iavf_queue_intr_disable(sc, i); 1174 } 1175 1176 /* mask interrupts */ 1177 reg = iavf_rd(sc, I40E_VFINT_DYN_CTL01); 1178 reg |= I40E_VFINT_DYN_CTL0_INTENA_MSK_MASK | 1179 (IAVF_NOITR << I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT); 1180 iavf_wr(sc, I40E_VFINT_DYN_CTL01, reg); 1181 1182 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 1183 rxr = sc->sc_qps[i].qp_rxr; 1184 txr = sc->sc_qps[i].qp_txr; 1185 1186 mutex_enter(&rxr->rxr_lock); 1187 iavf_rxr_clean(sc, rxr); 1188 mutex_exit(&rxr->rxr_lock); 1189 1190 mutex_enter(&txr->txr_lock); 1191 iavf_txr_clean(sc, txr); 1192 mutex_exit(&txr->txr_lock); 1193 1194 workqueue_wait(sc->sc_workq_txrx, 1195 &sc->sc_qps[i].qp_work); 1196 } 1197 1198 return; 1199 die: 1200 if (!sc->sc_dead) { 1201 sc->sc_dead = true; 1202 log(LOG_INFO, "%s: Request VF reset\n", ifp->if_xname); 1203 1204 iavf_work_set(&sc->sc_reset_task, iavf_reset_request, sc); 1205 iavf_work_add(sc->sc_workq, &sc->sc_reset_task); 1206 } 1207 log(LOG_CRIT, "%s: failed to shut down rings\n", ifp->if_xname); 1208 } 1209 1210 static int 1211 iavf_watchdog(struct iavf_tx_ring *txr) 1212 { 1213 struct iavf_softc *sc; 1214 1215 sc = txr->txr_sc; 1216 1217 mutex_enter(&txr->txr_lock); 1218 1219 if (txr->txr_watchdog == IAVF_WATCHDOG_STOP 1220 || --txr->txr_watchdog > 0) { 1221 mutex_exit(&txr->txr_lock); 1222 return 0; 1223 } 1224 1225 txr->txr_watchdog = IAVF_WATCHDOG_STOP; 1226 txr->txr_watchdogto.ev_count++; 1227 mutex_exit(&txr->txr_lock); 1228 1229 device_printf(sc->sc_dev, "watchdog timeout on queue %d\n", 1230 txr->txr_qid); 1231 return 1; 1232 } 1233 1234 static void 1235 iavf_watchdog_timeout(void *xsc) 1236 { 1237 struct iavf_softc *sc; 1238 struct ifnet *ifp; 1239 1240 sc = xsc; 1241 ifp = &sc->sc_ec.ec_if; 1242 1243 mutex_enter(&sc->sc_cfg_lock); 1244 if (ISSET(ifp->if_flags, IFF_RUNNING)) 1245 iavf_init_locked(sc); 1246 mutex_exit(&sc->sc_cfg_lock); 1247 } 1248 1249 static int 1250 iavf_media_change(struct ifnet *ifp) 1251 { 1252 struct iavf_softc *sc; 1253 struct ifmedia *ifm; 1254 1255 sc = ifp->if_softc; 1256 ifm = &sc->sc_media; 1257 1258 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1259 return EINVAL; 1260 1261 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1262 case IFM_AUTO: 1263 break; 1264 default: 1265 return EINVAL; 1266 } 1267 1268 return 0; 1269 } 1270 1271 static void 1272 iavf_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 1273 { 1274 struct iavf_softc *sc = ifp->if_softc; 1275 1276 KASSERT(mutex_owned(&sc->sc_cfg_lock)); 1277 1278 ifmr->ifm_status = sc->sc_media_status; 1279 ifmr->ifm_active = sc->sc_media_active; 1280 } 1281 1282 static int 1283 iavf_ifflags_cb(struct ethercom *ec) 1284 { 1285 struct ifnet *ifp = &ec->ec_if; 1286 struct iavf_softc *sc = ifp->if_softc; 1287 1288 /* vlan hwfilter can not be disabled */ 1289 SET(ec->ec_capenable, ETHERCAP_VLAN_HWFILTER); 1290 1291 return iavf_iff(sc); 1292 } 1293 1294 static int 1295 iavf_vlan_cb(struct ethercom *ec, uint16_t vid, bool set) 1296 { 1297 struct ifnet *ifp = &ec->ec_if; 1298 struct iavf_softc *sc = ifp->if_softc; 1299 int rv; 1300 1301 mutex_enter(&sc->sc_cfg_lock); 1302 1303 if (sc->sc_resetting) { 1304 mutex_exit(&sc->sc_cfg_lock); 1305 1306 /* all vlan id was already removed */ 1307 if (!set) 1308 return 0; 1309 1310 return ENXIO; 1311 } 1312 1313 /* ETHERCAP_VLAN_HWFILTER can not be disabled */ 1314 SET(sc->sc_ec.ec_capenable, ETHERCAP_VLAN_HWFILTER); 1315 1316 if (set) { 1317 rv = iavf_config_vlan_id(sc, vid, IAVF_VC_OP_ADD_VLAN); 1318 if (!ISSET(sc->sc_ec.ec_capenable, ETHERCAP_VLAN_HWTAGGING)) { 1319 iavf_config_vlan_stripping(sc, 1320 sc->sc_ec.ec_capenable); 1321 } 1322 } else { 1323 rv = iavf_config_vlan_id(sc, vid, IAVF_VC_OP_DEL_VLAN); 1324 } 1325 1326 mutex_exit(&sc->sc_cfg_lock); 1327 1328 if (rv != 0) 1329 return EIO; 1330 1331 return 0; 1332 } 1333 1334 static int 1335 iavf_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1336 { 1337 struct ifreq *ifr = (struct ifreq *)data; 1338 struct iavf_softc *sc = (struct iavf_softc *)ifp->if_softc; 1339 const struct sockaddr *sa; 1340 uint8_t addrhi[ETHER_ADDR_LEN], addrlo[ETHER_ADDR_LEN]; 1341 int s, error = 0; 1342 unsigned int nmtu; 1343 1344 switch (cmd) { 1345 case SIOCSIFMTU: 1346 nmtu = ifr->ifr_mtu; 1347 1348 if (nmtu < IAVF_MIN_MTU || nmtu > IAVF_MAX_MTU) { 1349 error = EINVAL; 1350 break; 1351 } 1352 if (ifp->if_mtu != nmtu) { 1353 s = splnet(); 1354 error = ether_ioctl(ifp, cmd, data); 1355 splx(s); 1356 if (error == ENETRESET) 1357 error = iavf_init(ifp); 1358 } 1359 break; 1360 case SIOCADDMULTI: 1361 sa = ifreq_getaddr(SIOCADDMULTI, ifr); 1362 if (ether_addmulti(sa, &sc->sc_ec) == ENETRESET) { 1363 error = ether_multiaddr(sa, addrlo, addrhi); 1364 if (error != 0) 1365 return error; 1366 1367 error = iavf_add_multi(sc, addrlo, addrhi); 1368 if (error != 0 && error != ENETRESET) { 1369 ether_delmulti(sa, &sc->sc_ec); 1370 error = EIO; 1371 } 1372 } 1373 break; 1374 1375 case SIOCDELMULTI: 1376 sa = ifreq_getaddr(SIOCDELMULTI, ifr); 1377 if (ether_delmulti(sa, &sc->sc_ec) == ENETRESET) { 1378 error = ether_multiaddr(sa, addrlo, addrhi); 1379 if (error != 0) 1380 return error; 1381 1382 error = iavf_del_multi(sc, addrlo, addrhi); 1383 } 1384 break; 1385 1386 default: 1387 s = splnet(); 1388 error = ether_ioctl(ifp, cmd, data); 1389 splx(s); 1390 } 1391 1392 if (error == ENETRESET) 1393 error = iavf_iff(sc); 1394 1395 return error; 1396 } 1397 1398 static int 1399 iavf_iff(struct iavf_softc *sc) 1400 { 1401 int error; 1402 1403 mutex_enter(&sc->sc_cfg_lock); 1404 error = iavf_iff_locked(sc); 1405 mutex_exit(&sc->sc_cfg_lock); 1406 1407 return error; 1408 } 1409 1410 static int 1411 iavf_iff_locked(struct iavf_softc *sc) 1412 { 1413 struct ifnet *ifp = &sc->sc_ec.ec_if; 1414 int unicast, multicast; 1415 const uint8_t *enaddr; 1416 1417 KASSERT(mutex_owned(&sc->sc_cfg_lock)); 1418 1419 if (!ISSET(ifp->if_flags, IFF_RUNNING)) 1420 return 0; 1421 1422 unicast = 0; 1423 multicast = 0; 1424 if (ISSET(ifp->if_flags, IFF_PROMISC)) { 1425 unicast = 1; 1426 multicast = 1; 1427 } else if (ISSET(ifp->if_flags, IFF_ALLMULTI)) { 1428 multicast = 1; 1429 } 1430 1431 iavf_config_promisc_mode(sc, unicast, multicast); 1432 1433 iavf_config_vlan_stripping(sc, sc->sc_ec.ec_capenable); 1434 1435 enaddr = CLLADDR(ifp->if_sadl); 1436 if (memcmp(enaddr, sc->sc_enaddr_added, ETHER_ADDR_LEN) != 0) { 1437 if (!iavf_is_etheranyaddr(sc->sc_enaddr_added)) { 1438 iavf_eth_addr(sc, sc->sc_enaddr_added, 1439 IAVF_VC_OP_DEL_ETH_ADDR); 1440 } 1441 memcpy(sc->sc_enaddr_added, enaddr, ETHER_ADDR_LEN); 1442 iavf_eth_addr(sc, enaddr, IAVF_VC_OP_ADD_ETH_ADDR); 1443 } 1444 1445 return 0; 1446 } 1447 1448 static const struct iavf_product * 1449 iavf_lookup(const struct pci_attach_args *pa) 1450 { 1451 const struct iavf_product *iavfp; 1452 1453 for (iavfp = iavf_products; iavfp->vendor_id != 0; iavfp++) { 1454 if (PCI_VENDOR(pa->pa_id) == iavfp->vendor_id && 1455 PCI_PRODUCT(pa->pa_id) == iavfp->product_id) 1456 return iavfp; 1457 } 1458 1459 return NULL; 1460 } 1461 1462 static enum i40e_mac_type 1463 iavf_mactype(pci_product_id_t id) 1464 { 1465 1466 switch (id) { 1467 case PCI_PRODUCT_INTEL_XL710_VF: 1468 case PCI_PRODUCT_INTEL_XL710_VF_HV: 1469 return I40E_MAC_VF; 1470 case PCI_PRODUCT_INTEL_X722_VF: 1471 return I40E_MAC_X722_VF; 1472 } 1473 1474 return I40E_MAC_GENERIC; 1475 } 1476 1477 static const struct iavf_link_speed * 1478 iavf_find_link_speed(struct iavf_softc *sc, uint32_t link_speed) 1479 { 1480 size_t i; 1481 1482 for (i = 0; i < __arraycount(iavf_link_speeds); i++) { 1483 if (link_speed & (1 << i)) 1484 return (&iavf_link_speeds[i]); 1485 } 1486 1487 return NULL; 1488 } 1489 1490 static void 1491 iavf_pci_csr_setup(pci_chipset_tag_t pc, pcitag_t tag) 1492 { 1493 pcireg_t csr; 1494 1495 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 1496 csr |= (PCI_COMMAND_MASTER_ENABLE | 1497 PCI_COMMAND_MEM_ENABLE); 1498 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 1499 } 1500 1501 static int 1502 iavf_wait_active(struct iavf_softc *sc) 1503 { 1504 int tries; 1505 uint32_t reg; 1506 1507 for (tries = 0; tries < 100; tries++) { 1508 reg = iavf_rd(sc, I40E_VFGEN_RSTAT) & 1509 I40E_VFGEN_RSTAT_VFR_STATE_MASK; 1510 if (reg == IAVF_VFR_VFACTIVE || 1511 reg == IAVF_VFR_COMPLETED) 1512 return 0; 1513 1514 delaymsec(10); 1515 } 1516 1517 return -1; 1518 } 1519 1520 static bool 1521 iavf_is_etheranyaddr(const uint8_t *enaddr) 1522 { 1523 static const uint8_t etheranyaddr[ETHER_ADDR_LEN] = { 1524 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1525 }; 1526 1527 if (memcmp(enaddr, etheranyaddr, ETHER_ADDR_LEN) != 0) 1528 return false; 1529 1530 return true; 1531 } 1532 1533 static void 1534 iavf_prepare_fakeaddr(struct iavf_softc *sc) 1535 { 1536 uint64_t rndval; 1537 1538 if (!iavf_is_etheranyaddr(sc->sc_enaddr_fake)) 1539 return; 1540 1541 rndval = cprng_strong64(); 1542 1543 memcpy(sc->sc_enaddr_fake, &rndval, sizeof(sc->sc_enaddr_fake)); 1544 sc->sc_enaddr_fake[0] &= 0xFE; 1545 sc->sc_enaddr_fake[0] |= 0x02; 1546 } 1547 1548 static int 1549 iavf_replace_lla(struct ifnet *ifp, const uint8_t *prev, const uint8_t *next) 1550 { 1551 union { 1552 struct sockaddr sa; 1553 struct sockaddr_dl sdl; 1554 struct sockaddr_storage ss; 1555 } u; 1556 struct psref psref_prev, psref_next; 1557 struct ifaddr *ifa_prev, *ifa_next; 1558 const struct sockaddr_dl *nsdl; 1559 int s, error; 1560 1561 KASSERT(IFNET_LOCKED(ifp)); 1562 1563 error = 0; 1564 ifa_prev = ifa_next = NULL; 1565 1566 if (memcmp(prev, next, ETHER_ADDR_LEN) == 0) { 1567 goto done; 1568 } 1569 1570 if (sockaddr_dl_init(&u.sdl, sizeof(u.ss), ifp->if_index, 1571 ifp->if_type, ifp->if_xname, strlen(ifp->if_xname), 1572 prev, ETHER_ADDR_LEN) == NULL) { 1573 error = EINVAL; 1574 goto done; 1575 } 1576 1577 s = pserialize_read_enter(); 1578 IFADDR_READER_FOREACH(ifa_prev, ifp) { 1579 if (sockaddr_cmp(&u.sa, ifa_prev->ifa_addr) == 0) { 1580 ifa_acquire(ifa_prev, &psref_prev); 1581 break; 1582 } 1583 } 1584 pserialize_read_exit(s); 1585 1586 if (sockaddr_dl_init(&u.sdl, sizeof(u.ss), ifp->if_index, 1587 ifp->if_type, ifp->if_xname, strlen(ifp->if_xname), 1588 next, ETHER_ADDR_LEN) == NULL) { 1589 error = EINVAL; 1590 goto done; 1591 } 1592 1593 s = pserialize_read_enter(); 1594 IFADDR_READER_FOREACH(ifa_next, ifp) { 1595 if (sockaddr_cmp(&u.sa, ifa_next->ifa_addr) == 0) { 1596 ifa_acquire(ifa_next, &psref_next); 1597 break; 1598 } 1599 } 1600 pserialize_read_exit(s); 1601 1602 if (ifa_next == NULL) { 1603 nsdl = &u.sdl; 1604 ifa_next = if_dl_create(ifp, &nsdl); 1605 if (ifa_next == NULL) { 1606 error = ENOMEM; 1607 goto done; 1608 } 1609 1610 s = pserialize_read_enter(); 1611 ifa_acquire(ifa_next, &psref_next); 1612 pserialize_read_exit(s); 1613 1614 sockaddr_copy(ifa_next->ifa_addr, 1615 ifa_next->ifa_addr->sa_len, &u.sa); 1616 ifa_insert(ifp, ifa_next); 1617 } else { 1618 nsdl = NULL; 1619 } 1620 1621 if (ifa_prev != NULL && ifa_prev == ifp->if_dl) { 1622 if_activate_sadl(ifp, ifa_next, nsdl); 1623 } 1624 1625 ifa_release(ifa_next, &psref_next); 1626 ifa_next = NULL; 1627 1628 if (ifa_prev != NULL && ifa_prev != ifp->if_hwdl) { 1629 ifaref(ifa_prev); 1630 ifa_release(ifa_prev, &psref_prev); 1631 ifa_remove(ifp, ifa_prev); 1632 KASSERTMSG(ifa_prev->ifa_refcnt == 1, "ifa_refcnt=%d", 1633 ifa_prev->ifa_refcnt); 1634 ifafree(ifa_prev); 1635 ifa_prev = NULL; 1636 } 1637 1638 if (ISSET(ifp->if_flags, IFF_RUNNING)) 1639 error = ENETRESET; 1640 1641 done: 1642 if (ifa_prev != NULL) 1643 ifa_release(ifa_prev, &psref_prev); 1644 if (ifa_next != NULL) 1645 ifa_release(ifa_next, &psref_next); 1646 1647 return error; 1648 } 1649 static int 1650 iavf_add_multi(struct iavf_softc *sc, uint8_t *addrlo, uint8_t *addrhi) 1651 { 1652 struct ifnet *ifp = &sc->sc_ec.ec_if; 1653 int rv; 1654 1655 if (ISSET(ifp->if_flags, IFF_ALLMULTI)) 1656 return 0; 1657 1658 if (memcmp(addrlo, addrhi, ETHER_ADDR_LEN) != 0) { 1659 iavf_del_all_multi(sc); 1660 SET(ifp->if_flags, IFF_ALLMULTI); 1661 return ENETRESET; 1662 } 1663 1664 rv = iavf_eth_addr(sc, addrlo, IAVF_VC_OP_ADD_ETH_ADDR); 1665 1666 if (rv == ENOSPC) { 1667 iavf_del_all_multi(sc); 1668 SET(ifp->if_flags, IFF_ALLMULTI); 1669 return ENETRESET; 1670 } 1671 1672 return rv; 1673 } 1674 1675 static int 1676 iavf_del_multi(struct iavf_softc *sc, uint8_t *addrlo, uint8_t *addrhi) 1677 { 1678 struct ifnet *ifp = &sc->sc_ec.ec_if; 1679 struct ethercom *ec = &sc->sc_ec; 1680 struct ether_multi *enm, *enm_last; 1681 struct ether_multistep step; 1682 int error, rv = 0; 1683 1684 if (!ISSET(ifp->if_flags, IFF_ALLMULTI)) { 1685 if (memcmp(addrlo, addrhi, ETHER_ADDR_LEN) != 0) 1686 return 0; 1687 1688 iavf_eth_addr(sc, addrlo, IAVF_VC_OP_DEL_ETH_ADDR); 1689 return 0; 1690 } 1691 1692 ETHER_LOCK(ec); 1693 for (ETHER_FIRST_MULTI(step, ec, enm); enm != NULL; 1694 ETHER_NEXT_MULTI(step, enm)) { 1695 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1696 ETHER_ADDR_LEN) != 0) { 1697 goto out; 1698 } 1699 } 1700 1701 for (ETHER_FIRST_MULTI(step, ec, enm); enm != NULL; 1702 ETHER_NEXT_MULTI(step, enm)) { 1703 error = iavf_eth_addr(sc, enm->enm_addrlo, 1704 IAVF_VC_OP_ADD_ETH_ADDR); 1705 if (error != 0) 1706 break; 1707 } 1708 1709 if (enm != NULL) { 1710 enm_last = enm; 1711 for (ETHER_FIRST_MULTI(step, ec, enm); enm != NULL; 1712 ETHER_NEXT_MULTI(step, enm)) { 1713 if (enm == enm_last) 1714 break; 1715 1716 iavf_eth_addr(sc, enm->enm_addrlo, 1717 IAVF_VC_OP_DEL_ETH_ADDR); 1718 } 1719 } else { 1720 CLR(ifp->if_flags, IFF_ALLMULTI); 1721 rv = ENETRESET; 1722 } 1723 1724 out: 1725 ETHER_UNLOCK(ec); 1726 return rv; 1727 } 1728 1729 static void 1730 iavf_del_all_multi(struct iavf_softc *sc) 1731 { 1732 struct ethercom *ec = &sc->sc_ec; 1733 struct ether_multi *enm; 1734 struct ether_multistep step; 1735 1736 ETHER_LOCK(ec); 1737 for (ETHER_FIRST_MULTI(step, ec, enm); enm != NULL; 1738 ETHER_NEXT_MULTI(step, enm)) { 1739 iavf_eth_addr(sc, enm->enm_addrlo, 1740 IAVF_VC_OP_DEL_ETH_ADDR); 1741 } 1742 ETHER_UNLOCK(ec); 1743 } 1744 1745 static int 1746 iavf_setup_interrupts(struct iavf_softc *sc) 1747 { 1748 struct pci_attach_args *pa; 1749 kcpuset_t *affinity = NULL; 1750 char intrbuf[PCI_INTRSTR_LEN], xnamebuf[32]; 1751 char const *intrstr; 1752 int counts[PCI_INTR_TYPE_SIZE]; 1753 int error, affinity_to; 1754 unsigned int vector, qid, num; 1755 1756 /* queue pairs + misc interrupt */ 1757 num = sc->sc_nqps_alloc + 1; 1758 1759 num = MIN(num, iavf_calc_msix_count(sc)); 1760 if (num <= 0) { 1761 return -1; 1762 } 1763 1764 KASSERT(sc->sc_nqps_alloc > 0); 1765 num = MIN(num, sc->sc_nqps_alloc + 1); 1766 1767 pa = &sc->sc_pa; 1768 memset(counts, 0, sizeof(counts)); 1769 counts[PCI_INTR_TYPE_MSIX] = num; 1770 1771 error = pci_intr_alloc(pa, &sc->sc_ihp, counts, PCI_INTR_TYPE_MSIX); 1772 if (error != 0) { 1773 IAVF_LOG(sc, LOG_WARNING, "couldn't allocate interrupts\n"); 1774 return -1; 1775 } 1776 1777 KASSERT(pci_intr_type(pa->pa_pc, sc->sc_ihp[0]) == PCI_INTR_TYPE_MSIX); 1778 1779 if (counts[PCI_INTR_TYPE_MSIX] < 1) { 1780 IAVF_LOG(sc, LOG_ERR, "couldn't allocate interrupts\n"); 1781 } else if (counts[PCI_INTR_TYPE_MSIX] != (int)num) { 1782 IAVF_LOG(sc, LOG_DEBUG, 1783 "request %u interrupts, but allocate %d interrupts\n", 1784 num, counts[PCI_INTR_TYPE_MSIX]); 1785 num = counts[PCI_INTR_TYPE_MSIX]; 1786 } 1787 1788 sc->sc_ihs = kmem_zalloc(sizeof(sc->sc_ihs[0]) * num, KM_NOSLEEP); 1789 if (sc->sc_ihs == NULL) { 1790 IAVF_LOG(sc, LOG_ERR, 1791 "couldn't allocate memory for interrupts\n"); 1792 goto fail; 1793 } 1794 1795 /* vector #0 is Misc interrupt */ 1796 vector = 0; 1797 pci_intr_setattr(pa->pa_pc, &sc->sc_ihp[vector], PCI_INTR_MPSAFE, true); 1798 intrstr = pci_intr_string(pa->pa_pc, sc->sc_ihp[vector], 1799 intrbuf, sizeof(intrbuf)); 1800 snprintf(xnamebuf, sizeof(xnamebuf), "%s-Misc", 1801 device_xname(sc->sc_dev)); 1802 1803 sc->sc_ihs[vector] = pci_intr_establish_xname(pa->pa_pc, 1804 sc->sc_ihp[vector], IPL_NET, iavf_intr, sc, xnamebuf); 1805 if (sc->sc_ihs[vector] == NULL) { 1806 IAVF_LOG(sc, LOG_WARNING, 1807 "unable to establish interrupt at %s", intrstr); 1808 goto fail; 1809 } 1810 1811 kcpuset_create(&affinity, false); 1812 affinity_to = 0; 1813 qid = 0; 1814 for (vector = 1; vector < num; vector++) { 1815 pci_intr_setattr(pa->pa_pc, &sc->sc_ihp[vector], 1816 PCI_INTR_MPSAFE, true); 1817 intrstr = pci_intr_string(pa->pa_pc, sc->sc_ihp[vector], 1818 intrbuf, sizeof(intrbuf)); 1819 snprintf(xnamebuf, sizeof(xnamebuf), "%s-TXRX%u", 1820 device_xname(sc->sc_dev), qid); 1821 1822 sc->sc_ihs[vector] = pci_intr_establish_xname(pa->pa_pc, 1823 sc->sc_ihp[vector], IPL_NET, iavf_queue_intr, 1824 (void *)&sc->sc_qps[qid], xnamebuf); 1825 if (sc->sc_ihs[vector] == NULL) { 1826 IAVF_LOG(sc, LOG_WARNING, 1827 "unable to establish interrupt at %s\n", intrstr); 1828 goto fail; 1829 } 1830 1831 kcpuset_zero(affinity); 1832 kcpuset_set(affinity, affinity_to); 1833 error = interrupt_distribute(sc->sc_ihs[vector], 1834 affinity, NULL); 1835 1836 if (error == 0) { 1837 IAVF_LOG(sc, LOG_INFO, 1838 "for TXRX%d interrupt at %s, affinity to %d\n", 1839 qid, intrstr, affinity_to); 1840 } else { 1841 IAVF_LOG(sc, LOG_INFO, 1842 "for TXRX%d interrupt at %s\n", 1843 qid, intrstr); 1844 } 1845 1846 qid++; 1847 affinity_to = (affinity_to + 1) % ncpu; 1848 } 1849 1850 vector = 0; 1851 kcpuset_zero(affinity); 1852 kcpuset_set(affinity, affinity_to); 1853 intrstr = pci_intr_string(pa->pa_pc, sc->sc_ihp[vector], 1854 intrbuf, sizeof(intrbuf)); 1855 error = interrupt_distribute(sc->sc_ihs[vector], affinity, NULL); 1856 if (error == 0) { 1857 IAVF_LOG(sc, LOG_INFO, 1858 "for Misc interrupt at %s, affinity to %d\n", 1859 intrstr, affinity_to); 1860 } else { 1861 IAVF_LOG(sc, LOG_INFO, 1862 "for MISC interrupt at %s\n", intrstr); 1863 } 1864 1865 kcpuset_destroy(affinity); 1866 1867 sc->sc_nintrs = num; 1868 return 0; 1869 1870 fail: 1871 if (affinity != NULL) 1872 kcpuset_destroy(affinity); 1873 for (vector = 0; vector < num; vector++) { 1874 if (sc->sc_ihs[vector] == NULL) 1875 continue; 1876 pci_intr_disestablish(pa->pa_pc, sc->sc_ihs[vector]); 1877 } 1878 kmem_free(sc->sc_ihs, sizeof(sc->sc_ihs[0]) * num); 1879 pci_intr_release(pa->pa_pc, sc->sc_ihp, num); 1880 1881 return -1; 1882 } 1883 1884 static void 1885 iavf_teardown_interrupts(struct iavf_softc *sc) 1886 { 1887 struct pci_attach_args *pa; 1888 unsigned int i; 1889 1890 if (sc->sc_ihs == NULL) 1891 return; 1892 1893 pa = &sc->sc_pa; 1894 1895 for (i = 0; i < sc->sc_nintrs; i++) { 1896 pci_intr_disestablish(pa->pa_pc, sc->sc_ihs[i]); 1897 } 1898 1899 kmem_free(sc->sc_ihs, sizeof(sc->sc_ihs[0]) * sc->sc_nintrs); 1900 sc->sc_ihs = NULL; 1901 1902 pci_intr_release(pa->pa_pc, sc->sc_ihp, sc->sc_nintrs); 1903 sc->sc_nintrs = 0; 1904 } 1905 1906 static int 1907 iavf_setup_sysctls(struct iavf_softc *sc) 1908 { 1909 const char *devname; 1910 struct sysctllog **log; 1911 const struct sysctlnode *rnode, *rxnode, *txnode; 1912 int error; 1913 1914 log = &sc->sc_sysctllog; 1915 devname = device_xname(sc->sc_dev); 1916 1917 error = sysctl_createv(log, 0, NULL, &rnode, 1918 0, CTLTYPE_NODE, devname, 1919 SYSCTL_DESCR("iavf information and settings"), 1920 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 1921 if (error) 1922 goto out; 1923 1924 error = sysctl_createv(log, 0, &rnode, NULL, 1925 CTLFLAG_READWRITE, CTLTYPE_BOOL, "txrx_workqueue", 1926 SYSCTL_DESCR("Use workqueue for packet processing"), 1927 NULL, 0, &sc->sc_txrx_workqueue, 0, CTL_CREATE, CTL_EOL); 1928 if (error) 1929 goto out; 1930 1931 error = sysctl_createv(log, 0, &rnode, NULL, 1932 CTLFLAG_READWRITE, CTLTYPE_INT, "debug_level", 1933 SYSCTL_DESCR("Debug level"), 1934 NULL, 0, &sc->sc_debuglevel, 0, CTL_CREATE, CTL_EOL); 1935 if (error) 1936 goto out; 1937 1938 error = sysctl_createv(log, 0, &rnode, &rxnode, 1939 0, CTLTYPE_NODE, "rx", 1940 SYSCTL_DESCR("iavf information and settings for Rx"), 1941 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL); 1942 if (error) 1943 goto out; 1944 1945 error = sysctl_createv(log, 0, &rxnode, NULL, 1946 CTLFLAG_READWRITE, CTLTYPE_INT, "itr", 1947 SYSCTL_DESCR("Interrupt Throttling"), 1948 iavf_sysctl_itr_handler, 0, 1949 (void *)sc, 0, CTL_CREATE, CTL_EOL); 1950 if (error) 1951 goto out; 1952 1953 error = sysctl_createv(log, 0, &rxnode, NULL, 1954 CTLFLAG_READONLY, CTLTYPE_INT, "descriptor_num", 1955 SYSCTL_DESCR("descriptor size"), 1956 NULL, 0, &sc->sc_rx_ring_ndescs, 0, CTL_CREATE, CTL_EOL); 1957 if (error) 1958 goto out; 1959 1960 error = sysctl_createv(log, 0, &rxnode, NULL, 1961 CTLFLAG_READWRITE, CTLTYPE_INT, "intr_process_limit", 1962 SYSCTL_DESCR("max number of Rx packets" 1963 " to process for interrupt processing"), 1964 NULL, 0, &sc->sc_rx_intr_process_limit, 0, CTL_CREATE, CTL_EOL); 1965 if (error) 1966 goto out; 1967 1968 error = sysctl_createv(log, 0, &rxnode, NULL, 1969 CTLFLAG_READWRITE, CTLTYPE_INT, "process_limit", 1970 SYSCTL_DESCR("max number of Rx packets" 1971 " to process for deferred processing"), 1972 NULL, 0, &sc->sc_rx_process_limit, 0, CTL_CREATE, CTL_EOL); 1973 if (error) 1974 goto out; 1975 1976 error = sysctl_createv(log, 0, &rnode, &txnode, 1977 0, CTLTYPE_NODE, "tx", 1978 SYSCTL_DESCR("iavf information and settings for Tx"), 1979 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL); 1980 if (error) 1981 goto out; 1982 1983 error = sysctl_createv(log, 0, &txnode, NULL, 1984 CTLFLAG_READWRITE, CTLTYPE_INT, "itr", 1985 SYSCTL_DESCR("Interrupt Throttling"), 1986 iavf_sysctl_itr_handler, 0, 1987 (void *)sc, 0, CTL_CREATE, CTL_EOL); 1988 if (error) 1989 goto out; 1990 1991 error = sysctl_createv(log, 0, &txnode, NULL, 1992 CTLFLAG_READONLY, CTLTYPE_INT, "descriptor_num", 1993 SYSCTL_DESCR("the number of Tx descriptors"), 1994 NULL, 0, &sc->sc_tx_ring_ndescs, 0, CTL_CREATE, CTL_EOL); 1995 if (error) 1996 goto out; 1997 1998 error = sysctl_createv(log, 0, &txnode, NULL, 1999 CTLFLAG_READWRITE, CTLTYPE_INT, "intr_process_limit", 2000 SYSCTL_DESCR("max number of Tx packets" 2001 " to process for interrupt processing"), 2002 NULL, 0, &sc->sc_tx_intr_process_limit, 0, CTL_CREATE, CTL_EOL); 2003 if (error) 2004 goto out; 2005 2006 error = sysctl_createv(log, 0, &txnode, NULL, 2007 CTLFLAG_READWRITE, CTLTYPE_INT, "process_limit", 2008 SYSCTL_DESCR("max number of Tx packets" 2009 " to process for deferred processing"), 2010 NULL, 0, &sc->sc_tx_process_limit, 0, CTL_CREATE, CTL_EOL); 2011 if (error) 2012 goto out; 2013 out: 2014 return error; 2015 } 2016 2017 static void 2018 iavf_teardown_sysctls(struct iavf_softc *sc) 2019 { 2020 2021 sysctl_teardown(&sc->sc_sysctllog); 2022 } 2023 2024 static int 2025 iavf_setup_stats(struct iavf_softc *sc) 2026 { 2027 struct iavf_stat_counters *isc; 2028 const char *dn; 2029 2030 dn = device_xname(sc->sc_dev); 2031 isc = &sc->sc_stat_counters; 2032 2033 iavf_evcnt_attach(&isc->isc_rx_bytes, dn, "Rx bytes"); 2034 iavf_evcnt_attach(&isc->isc_rx_unicast, dn, "Rx unicast"); 2035 iavf_evcnt_attach(&isc->isc_rx_multicast, dn, "Rx multicast"); 2036 iavf_evcnt_attach(&isc->isc_rx_broadcast, dn, "Rx broadcast"); 2037 iavf_evcnt_attach(&isc->isc_rx_discards, dn, "Rx discards"); 2038 iavf_evcnt_attach(&isc->isc_rx_unknown_protocol, 2039 dn, "Rx unknown protocol"); 2040 2041 iavf_evcnt_attach(&isc->isc_tx_bytes, dn, "Tx bytes"); 2042 iavf_evcnt_attach(&isc->isc_tx_unicast, dn, "Tx unicast"); 2043 iavf_evcnt_attach(&isc->isc_tx_multicast, dn, "Tx multicast"); 2044 iavf_evcnt_attach(&isc->isc_tx_broadcast, dn, "Tx broadcast"); 2045 iavf_evcnt_attach(&isc->isc_tx_discards, dn, "Tx discards"); 2046 iavf_evcnt_attach(&isc->isc_tx_errors, dn, "Tx errors"); 2047 2048 return 0; 2049 } 2050 2051 static void 2052 iavf_teardown_stats(struct iavf_softc *sc) 2053 { 2054 struct iavf_stat_counters *isc; 2055 2056 isc = &sc->sc_stat_counters; 2057 2058 evcnt_detach(&isc->isc_rx_bytes); 2059 evcnt_detach(&isc->isc_rx_unicast); 2060 evcnt_detach(&isc->isc_rx_multicast); 2061 evcnt_detach(&isc->isc_rx_broadcast); 2062 evcnt_detach(&isc->isc_rx_discards); 2063 evcnt_detach(&isc->isc_rx_unknown_protocol); 2064 2065 evcnt_detach(&isc->isc_tx_bytes); 2066 evcnt_detach(&isc->isc_tx_unicast); 2067 evcnt_detach(&isc->isc_tx_multicast); 2068 evcnt_detach(&isc->isc_tx_broadcast); 2069 evcnt_detach(&isc->isc_tx_discards); 2070 evcnt_detach(&isc->isc_tx_errors); 2071 2072 } 2073 2074 static int 2075 iavf_init_admin_queue(struct iavf_softc *sc) 2076 { 2077 uint32_t reg; 2078 2079 sc->sc_atq_cons = 0; 2080 sc->sc_atq_prod = 0; 2081 2082 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 2083 0, IXL_DMA_LEN(&sc->sc_atq), 2084 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2085 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_arq), 2086 0, IXL_DMA_LEN(&sc->sc_arq), 2087 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2088 2089 iavf_wr(sc, sc->sc_aq_regs->atq_head, 0); 2090 iavf_wr(sc, sc->sc_aq_regs->arq_head, 0); 2091 iavf_wr(sc, sc->sc_aq_regs->atq_tail, 0); 2092 iavf_wr(sc, sc->sc_aq_regs->arq_tail, 0); 2093 2094 iavf_barrier(sc, 0, sc->sc_mems, BUS_SPACE_BARRIER_WRITE); 2095 2096 iavf_wr(sc, sc->sc_aq_regs->atq_bal, 2097 ixl_dmamem_lo(&sc->sc_atq)); 2098 iavf_wr(sc, sc->sc_aq_regs->atq_bah, 2099 ixl_dmamem_hi(&sc->sc_atq)); 2100 iavf_wr(sc, sc->sc_aq_regs->atq_len, 2101 sc->sc_aq_regs->atq_len_enable | IAVF_AQ_NUM); 2102 2103 iavf_wr(sc, sc->sc_aq_regs->arq_bal, 2104 ixl_dmamem_lo(&sc->sc_arq)); 2105 iavf_wr(sc, sc->sc_aq_regs->arq_bah, 2106 ixl_dmamem_hi(&sc->sc_arq)); 2107 iavf_wr(sc, sc->sc_aq_regs->arq_len, 2108 sc->sc_aq_regs->arq_len_enable | IAVF_AQ_NUM); 2109 2110 iavf_wr(sc, sc->sc_aq_regs->arq_tail, sc->sc_arq_prod); 2111 2112 reg = iavf_rd(sc, sc->sc_aq_regs->atq_bal); 2113 if (reg != ixl_dmamem_lo(&sc->sc_atq)) 2114 goto fail; 2115 2116 reg = iavf_rd(sc, sc->sc_aq_regs->arq_bal); 2117 if (reg != ixl_dmamem_lo(&sc->sc_arq)) 2118 goto fail; 2119 2120 sc->sc_dead = false; 2121 return 0; 2122 2123 fail: 2124 iavf_wr(sc, sc->sc_aq_regs->atq_len, 0); 2125 iavf_wr(sc, sc->sc_aq_regs->arq_len, 0); 2126 return -1; 2127 } 2128 2129 static void 2130 iavf_cleanup_admin_queue(struct iavf_softc *sc) 2131 { 2132 struct ixl_aq_buf *aqb; 2133 2134 iavf_wr(sc, sc->sc_aq_regs->atq_head, 0); 2135 iavf_wr(sc, sc->sc_aq_regs->arq_head, 0); 2136 iavf_wr(sc, sc->sc_aq_regs->atq_tail, 0); 2137 iavf_wr(sc, sc->sc_aq_regs->arq_tail, 0); 2138 2139 iavf_wr(sc, sc->sc_aq_regs->atq_bal, 0); 2140 iavf_wr(sc, sc->sc_aq_regs->atq_bah, 0); 2141 iavf_wr(sc, sc->sc_aq_regs->atq_len, 0); 2142 2143 iavf_wr(sc, sc->sc_aq_regs->arq_bal, 0); 2144 iavf_wr(sc, sc->sc_aq_regs->arq_bah, 0); 2145 iavf_wr(sc, sc->sc_aq_regs->arq_len, 0); 2146 iavf_flush(sc); 2147 2148 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_arq), 2149 0, IXL_DMA_LEN(&sc->sc_arq), 2150 BUS_DMASYNC_POSTREAD); 2151 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 2152 0, IXL_DMA_LEN(&sc->sc_atq), 2153 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2154 2155 sc->sc_atq_cons = 0; 2156 sc->sc_atq_prod = 0; 2157 sc->sc_arq_cons = 0; 2158 sc->sc_arq_prod = 0; 2159 2160 memset(IXL_DMA_KVA(&sc->sc_arq), 0, IXL_DMA_LEN(&sc->sc_arq)); 2161 memset(IXL_DMA_KVA(&sc->sc_atq), 0, IXL_DMA_LEN(&sc->sc_atq)); 2162 2163 while ((aqb = iavf_aqb_get_locked(&sc->sc_arq_live)) != NULL) { 2164 bus_dmamap_sync(sc->sc_dmat, aqb->aqb_map, 0, aqb->aqb_size, 2165 BUS_DMASYNC_POSTREAD); 2166 iavf_aqb_put_locked(&sc->sc_arq_idle, aqb); 2167 } 2168 2169 while ((aqb = iavf_aqb_get_locked(&sc->sc_atq_live)) != NULL) { 2170 bus_dmamap_sync(sc->sc_dmat, aqb->aqb_map, 0, aqb->aqb_size, 2171 BUS_DMASYNC_POSTREAD); 2172 iavf_aqb_put_locked(&sc->sc_atq_idle, aqb); 2173 } 2174 } 2175 2176 static unsigned int 2177 iavf_calc_msix_count(struct iavf_softc *sc) 2178 { 2179 struct pci_attach_args *pa; 2180 int count; 2181 2182 pa = &sc->sc_pa; 2183 count = pci_msix_count(pa->pa_pc, pa->pa_tag); 2184 if (count < 0) { 2185 IAVF_LOG(sc, LOG_DEBUG,"MSIX config error\n"); 2186 count = 0; 2187 } 2188 2189 return MIN(sc->sc_max_vectors, (unsigned int)count); 2190 } 2191 2192 static unsigned int 2193 iavf_calc_queue_pair_size(struct iavf_softc *sc) 2194 { 2195 unsigned int nqp, nvec; 2196 2197 nvec = iavf_calc_msix_count(sc); 2198 if (sc->sc_max_vectors > 1) { 2199 /* decrease the number of misc interrupt */ 2200 nvec -= 1; 2201 } 2202 2203 nqp = ncpu; 2204 nqp = MIN(nqp, sc->sc_nqps_vsi); 2205 nqp = MIN(nqp, nvec); 2206 nqp = MIN(nqp, (unsigned int)iavf_params.max_qps); 2207 2208 return nqp; 2209 } 2210 2211 static struct iavf_tx_ring * 2212 iavf_txr_alloc(struct iavf_softc *sc, unsigned int qid) 2213 { 2214 struct iavf_tx_ring *txr; 2215 struct iavf_tx_map *maps; 2216 unsigned int i; 2217 int error; 2218 2219 txr = kmem_zalloc(sizeof(*txr), KM_NOSLEEP); 2220 if (txr == NULL) 2221 return NULL; 2222 2223 maps = kmem_zalloc(sizeof(maps[0]) * sc->sc_tx_ring_ndescs, 2224 KM_NOSLEEP); 2225 if (maps == NULL) 2226 goto free_txr; 2227 2228 if (iavf_dmamem_alloc(sc->sc_dmat, &txr->txr_mem, 2229 sizeof(struct ixl_tx_desc) * sc->sc_tx_ring_ndescs, 2230 IAVF_TX_QUEUE_ALIGN) != 0) { 2231 goto free_maps; 2232 } 2233 2234 for (i = 0; i < sc->sc_tx_ring_ndescs; i++) { 2235 error = bus_dmamap_create(sc->sc_dmat, IAVF_TX_PKT_MAXSIZE, 2236 IAVF_TX_PKT_DESCS, IAVF_TX_PKT_MAXSIZE, 0, 2237 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &maps[i].txm_map); 2238 if (error) 2239 goto destroy_maps; 2240 } 2241 2242 txr->txr_intrq = pcq_create(sc->sc_tx_ring_ndescs, KM_NOSLEEP); 2243 if (txr->txr_intrq == NULL) 2244 goto destroy_maps; 2245 2246 txr->txr_si = softint_establish(SOFTINT_NET|SOFTINT_MPSAFE, 2247 iavf_deferred_transmit, txr); 2248 if (txr->txr_si == NULL) 2249 goto destroy_pcq; 2250 2251 snprintf(txr->txr_name, sizeof(txr->txr_name), "%s-tx%d", 2252 device_xname(sc->sc_dev), qid); 2253 2254 iavf_evcnt_attach(&txr->txr_defragged, 2255 txr->txr_name, "m_defrag successed"); 2256 iavf_evcnt_attach(&txr->txr_defrag_failed, 2257 txr->txr_name, "m_defrag failed"); 2258 iavf_evcnt_attach(&txr->txr_pcqdrop, 2259 txr->txr_name, "Dropped in pcq"); 2260 iavf_evcnt_attach(&txr->txr_transmitdef, 2261 txr->txr_name, "Deferred transmit"); 2262 iavf_evcnt_attach(&txr->txr_watchdogto, 2263 txr->txr_name, "Watchdog timedout on queue"); 2264 iavf_evcnt_attach(&txr->txr_defer, 2265 txr->txr_name, "Handled queue in softint/workqueue"); 2266 2267 evcnt_attach_dynamic(&txr->txr_intr, EVCNT_TYPE_INTR, NULL, 2268 txr->txr_name, "Interrupt on queue"); 2269 2270 txr->txr_qid = qid; 2271 txr->txr_sc = sc; 2272 txr->txr_maps = maps; 2273 txr->txr_prod = txr->txr_cons = 0; 2274 txr->txr_tail = I40E_QTX_TAIL1(qid); 2275 mutex_init(&txr->txr_lock, MUTEX_DEFAULT, IPL_NET); 2276 2277 return txr; 2278 destroy_pcq: 2279 pcq_destroy(txr->txr_intrq); 2280 destroy_maps: 2281 for (i = 0; i < sc->sc_tx_ring_ndescs; i++) { 2282 if (maps[i].txm_map == NULL) 2283 continue; 2284 bus_dmamap_destroy(sc->sc_dmat, maps[i].txm_map); 2285 } 2286 2287 iavf_dmamem_free(sc->sc_dmat, &txr->txr_mem); 2288 free_maps: 2289 kmem_free(maps, sizeof(maps[0]) * sc->sc_tx_ring_ndescs); 2290 free_txr: 2291 kmem_free(txr, sizeof(*txr)); 2292 return NULL; 2293 } 2294 2295 static void 2296 iavf_txr_free(struct iavf_softc *sc, struct iavf_tx_ring *txr) 2297 { 2298 struct iavf_tx_map *maps; 2299 unsigned int i; 2300 2301 maps = txr->txr_maps; 2302 if (maps != NULL) { 2303 for (i = 0; i < sc->sc_tx_ring_ndescs; i++) { 2304 if (maps[i].txm_map == NULL) 2305 continue; 2306 bus_dmamap_destroy(sc->sc_dmat, maps[i].txm_map); 2307 } 2308 kmem_free(txr->txr_maps, 2309 sizeof(maps[0]) * sc->sc_tx_ring_ndescs); 2310 txr->txr_maps = NULL; 2311 } 2312 2313 evcnt_detach(&txr->txr_defragged); 2314 evcnt_detach(&txr->txr_defrag_failed); 2315 evcnt_detach(&txr->txr_pcqdrop); 2316 evcnt_detach(&txr->txr_transmitdef); 2317 evcnt_detach(&txr->txr_watchdogto); 2318 evcnt_detach(&txr->txr_defer); 2319 evcnt_detach(&txr->txr_intr); 2320 2321 iavf_dmamem_free(sc->sc_dmat, &txr->txr_mem); 2322 softint_disestablish(txr->txr_si); 2323 pcq_destroy(txr->txr_intrq); 2324 mutex_destroy(&txr->txr_lock); 2325 kmem_free(txr, sizeof(*txr)); 2326 } 2327 2328 static struct iavf_rx_ring * 2329 iavf_rxr_alloc(struct iavf_softc *sc, unsigned int qid) 2330 { 2331 struct iavf_rx_ring *rxr; 2332 struct iavf_rx_map *maps; 2333 unsigned int i; 2334 int error; 2335 2336 rxr = kmem_zalloc(sizeof(*rxr), KM_NOSLEEP); 2337 if (rxr == NULL) 2338 return NULL; 2339 2340 maps = kmem_zalloc(sizeof(maps[0]) * sc->sc_rx_ring_ndescs, 2341 KM_NOSLEEP); 2342 if (maps == NULL) 2343 goto free_rxr; 2344 2345 if (iavf_dmamem_alloc(sc->sc_dmat, &rxr->rxr_mem, 2346 sizeof(struct ixl_rx_rd_desc_32) * sc->sc_rx_ring_ndescs, 2347 IAVF_RX_QUEUE_ALIGN) != 0) 2348 goto free_maps; 2349 2350 for (i = 0; i < sc->sc_rx_ring_ndescs; i++) { 2351 error = bus_dmamap_create(sc->sc_dmat, IAVF_MCLBYTES, 2352 1, IAVF_MCLBYTES, 0, 2353 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &maps[i].rxm_map); 2354 if (error) 2355 goto destroy_maps; 2356 } 2357 2358 snprintf(rxr->rxr_name, sizeof(rxr->rxr_name), "%s-rx%d", 2359 device_xname(sc->sc_dev), qid); 2360 2361 iavf_evcnt_attach(&rxr->rxr_mgethdr_failed, 2362 rxr->rxr_name, "MGETHDR failed"); 2363 iavf_evcnt_attach(&rxr->rxr_mgetcl_failed, 2364 rxr->rxr_name, "MCLGET failed"); 2365 iavf_evcnt_attach(&rxr->rxr_mbuf_load_failed, 2366 rxr->rxr_name, "bus_dmamap_load_mbuf failed"); 2367 iavf_evcnt_attach(&rxr->rxr_defer, 2368 rxr->rxr_name, "Handled queue in softint/workqueue"); 2369 2370 evcnt_attach_dynamic(&rxr->rxr_intr, EVCNT_TYPE_INTR, NULL, 2371 rxr->rxr_name, "Interrupt on queue"); 2372 2373 rxr->rxr_qid = qid; 2374 rxr->rxr_sc = sc; 2375 rxr->rxr_cons = rxr->rxr_prod = 0; 2376 rxr->rxr_m_head = NULL; 2377 rxr->rxr_m_tail = &rxr->rxr_m_head; 2378 rxr->rxr_maps = maps; 2379 rxr->rxr_tail = I40E_QRX_TAIL1(qid); 2380 mutex_init(&rxr->rxr_lock, MUTEX_DEFAULT, IPL_NET); 2381 2382 return rxr; 2383 2384 destroy_maps: 2385 for (i = 0; i < sc->sc_rx_ring_ndescs; i++) { 2386 if (maps[i].rxm_map == NULL) 2387 continue; 2388 bus_dmamap_destroy(sc->sc_dmat, maps[i].rxm_map); 2389 } 2390 iavf_dmamem_free(sc->sc_dmat, &rxr->rxr_mem); 2391 free_maps: 2392 kmem_free(maps, sizeof(maps[0]) * sc->sc_rx_ring_ndescs); 2393 free_rxr: 2394 kmem_free(rxr, sizeof(*rxr)); 2395 2396 return NULL; 2397 } 2398 2399 static void 2400 iavf_rxr_free(struct iavf_softc *sc, struct iavf_rx_ring *rxr) 2401 { 2402 struct iavf_rx_map *maps; 2403 unsigned int i; 2404 2405 maps = rxr->rxr_maps; 2406 if (maps != NULL) { 2407 for (i = 0; i < sc->sc_rx_ring_ndescs; i++) { 2408 if (maps[i].rxm_map == NULL) 2409 continue; 2410 bus_dmamap_destroy(sc->sc_dmat, maps[i].rxm_map); 2411 } 2412 kmem_free(maps, sizeof(maps[0]) * sc->sc_rx_ring_ndescs); 2413 rxr->rxr_maps = NULL; 2414 } 2415 2416 evcnt_detach(&rxr->rxr_mgethdr_failed); 2417 evcnt_detach(&rxr->rxr_mgetcl_failed); 2418 evcnt_detach(&rxr->rxr_mbuf_load_failed); 2419 evcnt_detach(&rxr->rxr_defer); 2420 evcnt_detach(&rxr->rxr_intr); 2421 2422 iavf_dmamem_free(sc->sc_dmat, &rxr->rxr_mem); 2423 mutex_destroy(&rxr->rxr_lock); 2424 kmem_free(rxr, sizeof(*rxr)); 2425 } 2426 2427 static int 2428 iavf_queue_pairs_alloc(struct iavf_softc *sc) 2429 { 2430 struct iavf_queue_pair *qp; 2431 unsigned int i, num; 2432 2433 num = iavf_calc_queue_pair_size(sc); 2434 if (num <= 0) { 2435 return -1; 2436 } 2437 2438 sc->sc_qps = kmem_zalloc(sizeof(sc->sc_qps[0]) * num, KM_NOSLEEP); 2439 if (sc->sc_qps == NULL) { 2440 return -1; 2441 } 2442 2443 for (i = 0; i < num; i++) { 2444 qp = &sc->sc_qps[i]; 2445 2446 qp->qp_rxr = iavf_rxr_alloc(sc, i); 2447 qp->qp_txr = iavf_txr_alloc(sc, i); 2448 2449 if (qp->qp_rxr == NULL || qp->qp_txr == NULL) 2450 goto free; 2451 2452 qp->qp_si = softint_establish(SOFTINT_NET|SOFTINT_MPSAFE, 2453 iavf_handle_queue, qp); 2454 if (qp->qp_si == NULL) 2455 goto free; 2456 } 2457 2458 sc->sc_nqps_alloc = num; 2459 return 0; 2460 free: 2461 for (i = 0; i < num; i++) { 2462 qp = &sc->sc_qps[i]; 2463 2464 if (qp->qp_si != NULL) 2465 softint_disestablish(qp->qp_si); 2466 if (qp->qp_rxr != NULL) 2467 iavf_rxr_free(sc, qp->qp_rxr); 2468 if (qp->qp_txr != NULL) 2469 iavf_txr_free(sc, qp->qp_txr); 2470 } 2471 2472 kmem_free(sc->sc_qps, sizeof(sc->sc_qps[0]) * num); 2473 sc->sc_qps = NULL; 2474 2475 return -1; 2476 } 2477 2478 static void 2479 iavf_queue_pairs_free(struct iavf_softc *sc) 2480 { 2481 struct iavf_queue_pair *qp; 2482 unsigned int i; 2483 size_t sz; 2484 2485 if (sc->sc_qps == NULL) 2486 return; 2487 2488 for (i = 0; i < sc->sc_nqps_alloc; i++) { 2489 qp = &sc->sc_qps[i]; 2490 2491 if (qp->qp_si != NULL) 2492 softint_disestablish(qp->qp_si); 2493 if (qp->qp_rxr != NULL) 2494 iavf_rxr_free(sc, qp->qp_rxr); 2495 if (qp->qp_txr != NULL) 2496 iavf_txr_free(sc, qp->qp_txr); 2497 } 2498 2499 sz = sizeof(sc->sc_qps[0]) * sc->sc_nqps_alloc; 2500 kmem_free(sc->sc_qps, sz); 2501 sc->sc_qps = NULL; 2502 sc->sc_nqps_alloc = 0; 2503 } 2504 2505 static int 2506 iavf_rxfill(struct iavf_softc *sc, struct iavf_rx_ring *rxr) 2507 { 2508 struct ixl_rx_rd_desc_32 *ring, *rxd; 2509 struct iavf_rx_map *rxm; 2510 bus_dmamap_t map; 2511 struct mbuf *m; 2512 unsigned int slots, prod, mask; 2513 int error, post; 2514 2515 slots = ixl_rxr_unrefreshed(rxr->rxr_prod, rxr->rxr_cons, 2516 sc->sc_rx_ring_ndescs); 2517 2518 if (slots == 0) 2519 return 0; 2520 2521 post = 0; 2522 error = 0; 2523 prod = rxr->rxr_prod; 2524 2525 ring = IXL_DMA_KVA(&rxr->rxr_mem); 2526 mask = sc->sc_rx_ring_ndescs - 1; 2527 2528 do { 2529 rxm = &rxr->rxr_maps[prod]; 2530 2531 MGETHDR(m, M_DONTWAIT, MT_DATA); 2532 if (m == NULL) { 2533 rxr->rxr_mgethdr_failed.ev_count++; 2534 error = -1; 2535 break; 2536 } 2537 2538 MCLGET(m, M_DONTWAIT); 2539 if (!ISSET(m->m_flags, M_EXT)) { 2540 rxr->rxr_mgetcl_failed.ev_count++; 2541 error = -1; 2542 m_freem(m); 2543 break; 2544 } 2545 2546 m->m_len = m->m_pkthdr.len = MCLBYTES; 2547 m_adj(m, ETHER_ALIGN); 2548 2549 map = rxm->rxm_map; 2550 2551 if (bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 2552 BUS_DMA_READ|BUS_DMA_NOWAIT) != 0) { 2553 rxr->rxr_mbuf_load_failed.ev_count++; 2554 error = -1; 2555 m_freem(m); 2556 break; 2557 } 2558 2559 rxm->rxm_m = m; 2560 2561 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 2562 BUS_DMASYNC_PREREAD); 2563 2564 rxd = &ring[prod]; 2565 rxd->paddr = htole64(map->dm_segs[0].ds_addr); 2566 rxd->haddr = htole64(0); 2567 2568 prod++; 2569 prod &= mask; 2570 post = 1; 2571 } while (--slots); 2572 2573 if (post) { 2574 rxr->rxr_prod = prod; 2575 iavf_wr(sc, rxr->rxr_tail, prod); 2576 } 2577 2578 return error; 2579 } 2580 2581 static inline void 2582 iavf_rx_csum(struct mbuf *m, uint64_t qword) 2583 { 2584 int flags_mask; 2585 2586 if (!ISSET(qword, IXL_RX_DESC_L3L4P)) { 2587 /* No L3 or L4 checksum was calculated */ 2588 return; 2589 } 2590 2591 switch (__SHIFTOUT(qword, IXL_RX_DESC_PTYPE_MASK)) { 2592 case IXL_RX_DESC_PTYPE_IPV4FRAG: 2593 case IXL_RX_DESC_PTYPE_IPV4: 2594 case IXL_RX_DESC_PTYPE_SCTPV4: 2595 case IXL_RX_DESC_PTYPE_ICMPV4: 2596 flags_mask = M_CSUM_IPv4 | M_CSUM_IPv4_BAD; 2597 break; 2598 case IXL_RX_DESC_PTYPE_TCPV4: 2599 flags_mask = M_CSUM_IPv4 | M_CSUM_IPv4_BAD; 2600 flags_mask |= M_CSUM_TCPv4 | M_CSUM_TCP_UDP_BAD; 2601 break; 2602 case IXL_RX_DESC_PTYPE_UDPV4: 2603 flags_mask = M_CSUM_IPv4 | M_CSUM_IPv4_BAD; 2604 flags_mask |= M_CSUM_UDPv4 | M_CSUM_TCP_UDP_BAD; 2605 break; 2606 case IXL_RX_DESC_PTYPE_TCPV6: 2607 flags_mask = M_CSUM_TCPv6 | M_CSUM_TCP_UDP_BAD; 2608 break; 2609 case IXL_RX_DESC_PTYPE_UDPV6: 2610 flags_mask = M_CSUM_UDPv6 | M_CSUM_TCP_UDP_BAD; 2611 break; 2612 default: 2613 flags_mask = 0; 2614 } 2615 2616 m->m_pkthdr.csum_flags |= (flags_mask & (M_CSUM_IPv4 | 2617 M_CSUM_TCPv4 | M_CSUM_TCPv6 | M_CSUM_UDPv4 | M_CSUM_UDPv6)); 2618 2619 if (ISSET(qword, IXL_RX_DESC_IPE)) { 2620 m->m_pkthdr.csum_flags |= (flags_mask & M_CSUM_IPv4_BAD); 2621 } 2622 2623 if (ISSET(qword, IXL_RX_DESC_L4E)) { 2624 m->m_pkthdr.csum_flags |= (flags_mask & M_CSUM_TCP_UDP_BAD); 2625 } 2626 } 2627 2628 static int 2629 iavf_rxeof(struct iavf_softc *sc, struct iavf_rx_ring *rxr, u_int rxlimit, 2630 struct evcnt *ecnt) 2631 { 2632 struct ifnet *ifp = &sc->sc_ec.ec_if; 2633 struct ixl_rx_wb_desc_32 *ring, *rxd; 2634 struct iavf_rx_map *rxm; 2635 bus_dmamap_t map; 2636 unsigned int cons, prod; 2637 struct mbuf *m; 2638 uint64_t word, word0; 2639 unsigned int len; 2640 unsigned int mask; 2641 int done = 0, more = 0; 2642 2643 KASSERT(mutex_owned(&rxr->rxr_lock)); 2644 2645 if (!ISSET(ifp->if_flags, IFF_RUNNING)) 2646 return 0; 2647 2648 prod = rxr->rxr_prod; 2649 cons = rxr->rxr_cons; 2650 2651 if (cons == prod) 2652 return 0; 2653 2654 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&rxr->rxr_mem), 2655 0, IXL_DMA_LEN(&rxr->rxr_mem), 2656 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2657 2658 ring = IXL_DMA_KVA(&rxr->rxr_mem); 2659 mask = sc->sc_rx_ring_ndescs - 1; 2660 2661 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 2662 2663 do { 2664 if (rxlimit-- <= 0) { 2665 more = 1; 2666 break; 2667 } 2668 2669 rxd = &ring[cons]; 2670 2671 word = le64toh(rxd->qword1); 2672 2673 if (!ISSET(word, IXL_RX_DESC_DD)) 2674 break; 2675 2676 rxm = &rxr->rxr_maps[cons]; 2677 2678 map = rxm->rxm_map; 2679 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 2680 BUS_DMASYNC_POSTREAD); 2681 bus_dmamap_unload(sc->sc_dmat, map); 2682 2683 m = rxm->rxm_m; 2684 rxm->rxm_m = NULL; 2685 2686 KASSERT(m != NULL); 2687 2688 len = (word & IXL_RX_DESC_PLEN_MASK) >> IXL_RX_DESC_PLEN_SHIFT; 2689 m->m_len = len; 2690 m->m_pkthdr.len = 0; 2691 2692 m->m_next = NULL; 2693 *rxr->rxr_m_tail = m; 2694 rxr->rxr_m_tail = &m->m_next; 2695 2696 m = rxr->rxr_m_head; 2697 m->m_pkthdr.len += len; 2698 2699 if (ISSET(word, IXL_RX_DESC_EOP)) { 2700 word0 = le64toh(rxd->qword0); 2701 2702 if (ISSET(word, IXL_RX_DESC_L2TAG1P)) { 2703 uint16_t vtag; 2704 vtag = __SHIFTOUT(word0, IXL_RX_DESC_L2TAG1_MASK); 2705 vlan_set_tag(m, le16toh(vtag)); 2706 } 2707 2708 if ((ifp->if_capenable & IAVF_IFCAP_RXCSUM) != 0) 2709 iavf_rx_csum(m, word); 2710 2711 if (!ISSET(word, 2712 IXL_RX_DESC_RXE | IXL_RX_DESC_OVERSIZE)) { 2713 m_set_rcvif(m, ifp); 2714 if_statinc_ref(ifp, nsr, if_ipackets); 2715 if_statadd_ref(ifp, nsr, if_ibytes, 2716 m->m_pkthdr.len); 2717 if_percpuq_enqueue(sc->sc_ipq, m); 2718 } else { 2719 if_statinc_ref(ifp, nsr, if_ierrors); 2720 m_freem(m); 2721 } 2722 2723 rxr->rxr_m_head = NULL; 2724 rxr->rxr_m_tail = &rxr->rxr_m_head; 2725 } 2726 2727 cons++; 2728 cons &= mask; 2729 2730 done = 1; 2731 } while (cons != prod); 2732 2733 if (done) { 2734 ecnt->ev_count++; 2735 rxr->rxr_cons = cons; 2736 if (iavf_rxfill(sc, rxr) == -1) 2737 if_statinc_ref(ifp, nsr, if_iqdrops); 2738 } 2739 2740 IF_STAT_PUTREF(ifp); 2741 2742 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&rxr->rxr_mem), 2743 0, IXL_DMA_LEN(&rxr->rxr_mem), 2744 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2745 2746 return more; 2747 } 2748 2749 static void 2750 iavf_rxr_clean(struct iavf_softc *sc, struct iavf_rx_ring *rxr) 2751 { 2752 struct iavf_rx_map *maps, *rxm; 2753 bus_dmamap_t map; 2754 unsigned int i; 2755 2756 KASSERT(mutex_owned(&rxr->rxr_lock)); 2757 2758 maps = rxr->rxr_maps; 2759 for (i = 0; i < sc->sc_rx_ring_ndescs; i++) { 2760 rxm = &maps[i]; 2761 2762 if (rxm->rxm_m == NULL) 2763 continue; 2764 2765 map = rxm->rxm_map; 2766 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 2767 BUS_DMASYNC_POSTWRITE); 2768 bus_dmamap_unload(sc->sc_dmat, map); 2769 2770 m_freem(rxm->rxm_m); 2771 rxm->rxm_m = NULL; 2772 } 2773 2774 m_freem(rxr->rxr_m_head); 2775 rxr->rxr_m_head = NULL; 2776 rxr->rxr_m_tail = &rxr->rxr_m_head; 2777 2778 memset(IXL_DMA_KVA(&rxr->rxr_mem), 0, IXL_DMA_LEN(&rxr->rxr_mem)); 2779 rxr->rxr_prod = rxr->rxr_cons = 0; 2780 } 2781 2782 static int 2783 iavf_txeof(struct iavf_softc *sc, struct iavf_tx_ring *txr, u_int txlimit, 2784 struct evcnt *ecnt) 2785 { 2786 struct ifnet *ifp = &sc->sc_ec.ec_if; 2787 struct ixl_tx_desc *ring, *txd; 2788 struct iavf_tx_map *txm; 2789 struct mbuf *m; 2790 bus_dmamap_t map; 2791 unsigned int cons, prod, last; 2792 unsigned int mask; 2793 uint64_t dtype; 2794 int done = 0, more = 0; 2795 2796 KASSERT(mutex_owned(&txr->txr_lock)); 2797 2798 prod = txr->txr_prod; 2799 cons = txr->txr_cons; 2800 2801 if (cons == prod) 2802 return 0; 2803 2804 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&txr->txr_mem), 2805 0, IXL_DMA_LEN(&txr->txr_mem), BUS_DMASYNC_POSTREAD); 2806 2807 ring = IXL_DMA_KVA(&txr->txr_mem); 2808 mask = sc->sc_tx_ring_ndescs - 1; 2809 2810 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 2811 2812 do { 2813 if (txlimit-- <= 0) { 2814 more = 1; 2815 break; 2816 } 2817 2818 txm = &txr->txr_maps[cons]; 2819 last = txm->txm_eop; 2820 txd = &ring[last]; 2821 2822 dtype = txd->cmd & htole64(IXL_TX_DESC_DTYPE_MASK); 2823 if (dtype != htole64(IXL_TX_DESC_DTYPE_DONE)) 2824 break; 2825 2826 map = txm->txm_map; 2827 2828 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 2829 BUS_DMASYNC_POSTWRITE); 2830 bus_dmamap_unload(sc->sc_dmat, map); 2831 2832 m = txm->txm_m; 2833 if (m != NULL) { 2834 if_statinc_ref(ifp, nsr, if_opackets); 2835 if_statadd_ref(ifp, nsr, if_obytes, m->m_pkthdr.len); 2836 if (ISSET(m->m_flags, M_MCAST)) 2837 if_statinc_ref(ifp, nsr, if_omcasts); 2838 m_freem(m); 2839 } 2840 2841 txm->txm_m = NULL; 2842 txm->txm_eop = -1; 2843 2844 cons = last + 1; 2845 cons &= mask; 2846 done = 1; 2847 } while (cons != prod); 2848 2849 IF_STAT_PUTREF(ifp); 2850 2851 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&txr->txr_mem), 2852 0, IXL_DMA_LEN(&txr->txr_mem), BUS_DMASYNC_PREREAD); 2853 2854 txr->txr_cons = cons; 2855 2856 if (done) { 2857 ecnt->ev_count++; 2858 softint_schedule(txr->txr_si); 2859 if (txr->txr_qid == 0) { 2860 CLR(ifp->if_flags, IFF_OACTIVE); 2861 if_schedule_deferred_start(ifp); 2862 } 2863 } 2864 2865 if (txr->txr_cons == txr->txr_prod) { 2866 txr->txr_watchdog = IAVF_WATCHDOG_STOP; 2867 } 2868 2869 return more; 2870 } 2871 2872 static inline int 2873 iavf_load_mbuf(bus_dma_tag_t dmat, bus_dmamap_t map, struct mbuf **m0, 2874 struct iavf_tx_ring *txr) 2875 { 2876 struct mbuf *m; 2877 int error; 2878 2879 KASSERT(mutex_owned(&txr->txr_lock)); 2880 2881 m = *m0; 2882 2883 error = bus_dmamap_load_mbuf(dmat, map, m, 2884 BUS_DMA_STREAMING|BUS_DMA_WRITE|BUS_DMA_NOWAIT); 2885 if (error != EFBIG) 2886 return error; 2887 2888 m = m_defrag(m, M_DONTWAIT); 2889 if (m != NULL) { 2890 *m0 = m; 2891 txr->txr_defragged.ev_count++; 2892 error = bus_dmamap_load_mbuf(dmat, map, m, 2893 BUS_DMA_STREAMING|BUS_DMA_WRITE|BUS_DMA_NOWAIT); 2894 } else { 2895 txr->txr_defrag_failed.ev_count++; 2896 error = ENOBUFS; 2897 } 2898 2899 return error; 2900 } 2901 2902 static inline int 2903 iavf_tx_setup_offloads(struct mbuf *m, uint64_t *cmd_txd) 2904 { 2905 struct ether_header *eh; 2906 size_t len; 2907 uint64_t cmd; 2908 2909 cmd = 0; 2910 2911 eh = mtod(m, struct ether_header *); 2912 switch (htons(eh->ether_type)) { 2913 case ETHERTYPE_IP: 2914 case ETHERTYPE_IPV6: 2915 len = ETHER_HDR_LEN; 2916 break; 2917 case ETHERTYPE_VLAN: 2918 len = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2919 break; 2920 default: 2921 len = 0; 2922 } 2923 cmd |= ((len >> 1) << IXL_TX_DESC_MACLEN_SHIFT); 2924 2925 if (m->m_pkthdr.csum_flags & 2926 (M_CSUM_TSOv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 2927 cmd |= IXL_TX_DESC_CMD_IIPT_IPV4; 2928 } 2929 if (m->m_pkthdr.csum_flags & M_CSUM_IPv4) { 2930 cmd |= IXL_TX_DESC_CMD_IIPT_IPV4_CSUM; 2931 } 2932 2933 if (m->m_pkthdr.csum_flags & 2934 (M_CSUM_TSOv6 | M_CSUM_TCPv6 | M_CSUM_UDPv6)) { 2935 cmd |= IXL_TX_DESC_CMD_IIPT_IPV6; 2936 } 2937 2938 switch (cmd & IXL_TX_DESC_CMD_IIPT_MASK) { 2939 case IXL_TX_DESC_CMD_IIPT_IPV4: 2940 case IXL_TX_DESC_CMD_IIPT_IPV4_CSUM: 2941 len = M_CSUM_DATA_IPv4_IPHL(m->m_pkthdr.csum_data); 2942 break; 2943 case IXL_TX_DESC_CMD_IIPT_IPV6: 2944 len = M_CSUM_DATA_IPv6_IPHL(m->m_pkthdr.csum_data); 2945 break; 2946 default: 2947 len = 0; 2948 } 2949 cmd |= ((len >> 2) << IXL_TX_DESC_IPLEN_SHIFT); 2950 2951 if (m->m_pkthdr.csum_flags & 2952 (M_CSUM_TSOv4 | M_CSUM_TSOv6 | M_CSUM_TCPv4 | M_CSUM_TCPv6)) { 2953 len = sizeof(struct tcphdr); 2954 cmd |= IXL_TX_DESC_CMD_L4T_EOFT_TCP; 2955 } else if (m->m_pkthdr.csum_flags & (M_CSUM_UDPv4 | M_CSUM_UDPv6)) { 2956 len = sizeof(struct udphdr); 2957 cmd |= IXL_TX_DESC_CMD_L4T_EOFT_UDP; 2958 } else { 2959 len = 0; 2960 } 2961 cmd |= ((len >> 2) << IXL_TX_DESC_L4LEN_SHIFT); 2962 2963 *cmd_txd |= cmd; 2964 return 0; 2965 } 2966 2967 static void 2968 iavf_tx_common_locked(struct ifnet *ifp, struct iavf_tx_ring *txr, 2969 bool is_transmit) 2970 { 2971 struct iavf_softc *sc; 2972 struct ixl_tx_desc *ring, *txd; 2973 struct iavf_tx_map *txm; 2974 bus_dmamap_t map; 2975 struct mbuf *m; 2976 unsigned int prod, free, last, i; 2977 unsigned int mask; 2978 uint64_t cmd, cmd_txd; 2979 int post = 0; 2980 2981 KASSERT(mutex_owned(&txr->txr_lock)); 2982 2983 sc = ifp->if_softc; 2984 2985 if (!ISSET(ifp->if_flags, IFF_RUNNING) 2986 || (!is_transmit && ISSET(ifp->if_flags, IFF_OACTIVE))) { 2987 if (!is_transmit) 2988 IFQ_PURGE(&ifp->if_snd); 2989 return; 2990 } 2991 2992 prod = txr->txr_prod; 2993 free = txr->txr_cons; 2994 2995 if (free <= prod) 2996 free += sc->sc_tx_ring_ndescs; 2997 free -= prod; 2998 2999 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&txr->txr_mem), 3000 0, IXL_DMA_LEN(&txr->txr_mem), BUS_DMASYNC_POSTWRITE); 3001 3002 ring = IXL_DMA_KVA(&txr->txr_mem); 3003 mask = sc->sc_tx_ring_ndescs - 1; 3004 last = prod; 3005 cmd = 0; 3006 txd = NULL; 3007 3008 for (;;) { 3009 if (free < IAVF_TX_PKT_DESCS) { 3010 if (!is_transmit) 3011 SET(ifp->if_flags, IFF_OACTIVE); 3012 break; 3013 } 3014 3015 if (is_transmit) 3016 m = pcq_get(txr->txr_intrq); 3017 else 3018 IFQ_DEQUEUE(&ifp->if_snd, m); 3019 3020 if (m == NULL) 3021 break; 3022 3023 txm = &txr->txr_maps[prod]; 3024 map = txm->txm_map; 3025 3026 if (iavf_load_mbuf(sc->sc_dmat, map, &m, txr) != 0) { 3027 if_statinc(ifp, if_oerrors); 3028 m_freem(m); 3029 continue; 3030 } 3031 3032 cmd_txd = 0; 3033 if (m->m_pkthdr.csum_flags & IAVF_CSUM_ALL_OFFLOAD) { 3034 iavf_tx_setup_offloads(m, &cmd_txd); 3035 } 3036 if (vlan_has_tag(m)) { 3037 uint16_t vtag; 3038 vtag = htole16(vlan_get_tag(m)); 3039 cmd_txd |= IXL_TX_DESC_CMD_IL2TAG1 | 3040 ((uint64_t)vtag << IXL_TX_DESC_L2TAG1_SHIFT); 3041 } 3042 3043 bus_dmamap_sync(sc->sc_dmat, map, 0, 3044 map->dm_mapsize, BUS_DMASYNC_PREWRITE); 3045 3046 for (i = 0; i < (unsigned int)map->dm_nsegs; i++) { 3047 txd = &ring[prod]; 3048 3049 cmd = (uint64_t)map->dm_segs[i].ds_len << 3050 IXL_TX_DESC_BSIZE_SHIFT; 3051 cmd |= IXL_TX_DESC_DTYPE_DATA|IXL_TX_DESC_CMD_ICRC| 3052 cmd_txd; 3053 3054 txd->addr = htole64(map->dm_segs[i].ds_addr); 3055 txd->cmd = htole64(cmd); 3056 3057 last = prod; 3058 prod++; 3059 prod &= mask; 3060 } 3061 3062 cmd |= IXL_TX_DESC_CMD_EOP|IXL_TX_DESC_CMD_RS; 3063 txd->cmd = htole64(cmd); 3064 txm->txm_m = m; 3065 txm->txm_eop = last; 3066 3067 bpf_mtap(ifp, m, BPF_D_OUT); 3068 free -= i; 3069 post = 1; 3070 } 3071 3072 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&txr->txr_mem), 3073 0, IXL_DMA_LEN(&txr->txr_mem), BUS_DMASYNC_PREWRITE); 3074 3075 if (post) { 3076 txr->txr_prod = prod; 3077 iavf_wr(sc, txr->txr_tail, prod); 3078 txr->txr_watchdog = IAVF_WATCHDOG_TICKS; 3079 } 3080 } 3081 3082 static inline int 3083 iavf_handle_queue_common(struct iavf_softc *sc, struct iavf_queue_pair *qp, 3084 u_int txlimit, struct evcnt *txevcnt, 3085 u_int rxlimit, struct evcnt *rxevcnt) 3086 { 3087 struct iavf_tx_ring *txr; 3088 struct iavf_rx_ring *rxr; 3089 int txmore, rxmore; 3090 int rv; 3091 3092 txr = qp->qp_txr; 3093 rxr = qp->qp_rxr; 3094 3095 mutex_enter(&txr->txr_lock); 3096 txmore = iavf_txeof(sc, txr, txlimit, txevcnt); 3097 mutex_exit(&txr->txr_lock); 3098 3099 mutex_enter(&rxr->rxr_lock); 3100 rxmore = iavf_rxeof(sc, rxr, rxlimit, rxevcnt); 3101 mutex_exit(&rxr->rxr_lock); 3102 3103 rv = txmore | (rxmore << 1); 3104 3105 return rv; 3106 } 3107 3108 static void 3109 iavf_sched_handle_queue(struct iavf_softc *sc, struct iavf_queue_pair *qp) 3110 { 3111 3112 if (qp->qp_workqueue) 3113 workqueue_enqueue(sc->sc_workq_txrx, &qp->qp_work, NULL); 3114 else 3115 softint_schedule(qp->qp_si); 3116 } 3117 3118 static void 3119 iavf_start(struct ifnet *ifp) 3120 { 3121 struct iavf_softc *sc; 3122 struct iavf_tx_ring *txr; 3123 3124 sc = ifp->if_softc; 3125 txr = sc->sc_qps[0].qp_txr; 3126 3127 mutex_enter(&txr->txr_lock); 3128 iavf_tx_common_locked(ifp, txr, false); 3129 mutex_exit(&txr->txr_lock); 3130 3131 } 3132 3133 static inline unsigned int 3134 iavf_select_txqueue(struct iavf_softc *sc, struct mbuf *m) 3135 { 3136 u_int cpuid; 3137 3138 cpuid = cpu_index(curcpu()); 3139 3140 return (unsigned int)(cpuid % sc->sc_nqueue_pairs); 3141 } 3142 3143 static int 3144 iavf_transmit(struct ifnet *ifp, struct mbuf *m) 3145 { 3146 struct iavf_softc *sc; 3147 struct iavf_tx_ring *txr; 3148 unsigned int qid; 3149 3150 sc = ifp->if_softc; 3151 qid = iavf_select_txqueue(sc, m); 3152 3153 txr = sc->sc_qps[qid].qp_txr; 3154 3155 if (__predict_false(!pcq_put(txr->txr_intrq, m))) { 3156 mutex_enter(&txr->txr_lock); 3157 txr->txr_pcqdrop.ev_count++; 3158 mutex_exit(&txr->txr_lock); 3159 3160 m_freem(m); 3161 return ENOBUFS; 3162 } 3163 3164 if (mutex_tryenter(&txr->txr_lock)) { 3165 iavf_tx_common_locked(ifp, txr, true); 3166 mutex_exit(&txr->txr_lock); 3167 } else { 3168 kpreempt_disable(); 3169 softint_schedule(txr->txr_si); 3170 kpreempt_enable(); 3171 } 3172 return 0; 3173 } 3174 3175 static void 3176 iavf_deferred_transmit(void *xtxr) 3177 { 3178 struct iavf_tx_ring *txr; 3179 struct iavf_softc *sc; 3180 struct ifnet *ifp; 3181 3182 txr = xtxr; 3183 sc = txr->txr_sc; 3184 ifp = &sc->sc_ec.ec_if; 3185 3186 mutex_enter(&txr->txr_lock); 3187 txr->txr_transmitdef.ev_count++; 3188 if (pcq_peek(txr->txr_intrq) != NULL) 3189 iavf_tx_common_locked(ifp, txr, true); 3190 mutex_exit(&txr->txr_lock); 3191 } 3192 3193 static void 3194 iavf_txr_clean(struct iavf_softc *sc, struct iavf_tx_ring *txr) 3195 { 3196 struct iavf_tx_map *maps, *txm; 3197 bus_dmamap_t map; 3198 unsigned int i; 3199 3200 KASSERT(mutex_owned(&txr->txr_lock)); 3201 3202 maps = txr->txr_maps; 3203 for (i = 0; i < sc->sc_tx_ring_ndescs; i++) { 3204 txm = &maps[i]; 3205 3206 if (txm->txm_m == NULL) 3207 continue; 3208 3209 map = txm->txm_map; 3210 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 3211 BUS_DMASYNC_POSTWRITE); 3212 bus_dmamap_unload(sc->sc_dmat, map); 3213 3214 m_freem(txm->txm_m); 3215 txm->txm_m = NULL; 3216 } 3217 3218 memset(IXL_DMA_KVA(&txr->txr_mem), 0, IXL_DMA_LEN(&txr->txr_mem)); 3219 txr->txr_prod = txr->txr_cons = 0; 3220 } 3221 3222 static int 3223 iavf_intr(void *xsc) 3224 { 3225 struct iavf_softc *sc = xsc; 3226 struct ifnet *ifp = &sc->sc_ec.ec_if; 3227 struct iavf_rx_ring *rxr; 3228 struct iavf_tx_ring *txr; 3229 uint32_t icr; 3230 unsigned int i; 3231 3232 /* read I40E_VFINT_ICR_ENA1 to clear status */ 3233 (void)iavf_rd(sc, I40E_VFINT_ICR0_ENA1); 3234 3235 iavf_intr_enable(sc); 3236 icr = iavf_rd(sc, I40E_VFINT_ICR01); 3237 3238 if (icr == IAVF_REG_VFR) { 3239 log(LOG_INFO, "%s: VF reset in progress\n", 3240 ifp->if_xname); 3241 iavf_work_set(&sc->sc_reset_task, iavf_reset_start, sc); 3242 iavf_work_add(sc->sc_workq, &sc->sc_reset_task); 3243 return 1; 3244 } 3245 3246 if (ISSET(icr, I40E_VFINT_ICR01_ADMINQ_MASK)) { 3247 mutex_enter(&sc->sc_adminq_lock); 3248 iavf_atq_done(sc); 3249 iavf_arq(sc); 3250 mutex_exit(&sc->sc_adminq_lock); 3251 } 3252 3253 if (ISSET(icr, I40E_VFINT_ICR01_QUEUE_0_MASK)) { 3254 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 3255 rxr = sc->sc_qps[i].qp_rxr; 3256 txr = sc->sc_qps[i].qp_txr; 3257 3258 mutex_enter(&rxr->rxr_lock); 3259 while (iavf_rxeof(sc, rxr, UINT_MAX, 3260 &rxr->rxr_intr) != 0) { 3261 /* do nothing */ 3262 } 3263 mutex_exit(&rxr->rxr_lock); 3264 3265 mutex_enter(&txr->txr_lock); 3266 while (iavf_txeof(sc, txr, UINT_MAX, 3267 &txr->txr_intr) != 0) { 3268 /* do nothing */ 3269 } 3270 mutex_exit(&txr->txr_lock); 3271 } 3272 } 3273 3274 return 0; 3275 } 3276 3277 static int 3278 iavf_queue_intr(void *xqp) 3279 { 3280 struct iavf_queue_pair *qp = xqp; 3281 struct iavf_tx_ring *txr; 3282 struct iavf_rx_ring *rxr; 3283 struct iavf_softc *sc; 3284 unsigned int qid; 3285 u_int txlimit, rxlimit; 3286 int more; 3287 3288 txr = qp->qp_txr; 3289 rxr = qp->qp_rxr; 3290 sc = txr->txr_sc; 3291 qid = txr->txr_qid; 3292 3293 txlimit = sc->sc_tx_intr_process_limit; 3294 rxlimit = sc->sc_rx_intr_process_limit; 3295 qp->qp_workqueue = sc->sc_txrx_workqueue; 3296 3297 more = iavf_handle_queue_common(sc, qp, 3298 txlimit, &txr->txr_intr, rxlimit, &rxr->rxr_intr); 3299 3300 if (more != 0) { 3301 iavf_sched_handle_queue(sc, qp); 3302 } else { 3303 /* for ALTQ */ 3304 if (txr->txr_qid == 0) 3305 if_schedule_deferred_start(&sc->sc_ec.ec_if); 3306 softint_schedule(txr->txr_si); 3307 3308 iavf_queue_intr_enable(sc, qid); 3309 } 3310 3311 return 0; 3312 } 3313 3314 static void 3315 iavf_handle_queue_wk(struct work *wk, void *xsc __unused) 3316 { 3317 struct iavf_queue_pair *qp; 3318 3319 qp = container_of(wk, struct iavf_queue_pair, qp_work); 3320 iavf_handle_queue(qp); 3321 } 3322 3323 static void 3324 iavf_handle_queue(void *xqp) 3325 { 3326 struct iavf_queue_pair *qp = xqp; 3327 struct iavf_tx_ring *txr; 3328 struct iavf_rx_ring *rxr; 3329 struct iavf_softc *sc; 3330 unsigned int qid; 3331 u_int txlimit, rxlimit; 3332 int more; 3333 3334 txr = qp->qp_txr; 3335 rxr = qp->qp_rxr; 3336 sc = txr->txr_sc; 3337 qid = txr->txr_qid; 3338 3339 txlimit = sc->sc_tx_process_limit; 3340 rxlimit = sc->sc_rx_process_limit; 3341 3342 more = iavf_handle_queue_common(sc, qp, 3343 txlimit, &txr->txr_defer, rxlimit, &rxr->rxr_defer); 3344 3345 if (more != 0) 3346 iavf_sched_handle_queue(sc, qp); 3347 else 3348 iavf_queue_intr_enable(sc, qid); 3349 } 3350 3351 static void 3352 iavf_tick(void *xsc) 3353 { 3354 struct iavf_softc *sc; 3355 unsigned int i; 3356 int timedout; 3357 3358 sc = xsc; 3359 timedout = 0; 3360 3361 mutex_enter(&sc->sc_cfg_lock); 3362 3363 if (sc->sc_resetting) { 3364 iavf_work_add(sc->sc_workq, &sc->sc_reset_task); 3365 mutex_exit(&sc->sc_cfg_lock); 3366 return; 3367 } 3368 3369 iavf_get_stats(sc); 3370 3371 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 3372 timedout |= iavf_watchdog(sc->sc_qps[i].qp_txr); 3373 } 3374 3375 if (timedout != 0) { 3376 iavf_work_add(sc->sc_workq, &sc->sc_wdto_task); 3377 } else { 3378 callout_schedule(&sc->sc_tick, IAVF_TICK_INTERVAL); 3379 } 3380 3381 mutex_exit(&sc->sc_cfg_lock); 3382 } 3383 3384 static void 3385 iavf_tick_halt(void *unused __unused) 3386 { 3387 3388 /* do nothing */ 3389 } 3390 3391 static void 3392 iavf_reset_request(void *xsc) 3393 { 3394 struct iavf_softc *sc = xsc; 3395 3396 iavf_reset_vf(sc); 3397 iavf_reset_start(sc); 3398 } 3399 3400 static void 3401 iavf_reset_start(void *xsc) 3402 { 3403 struct iavf_softc *sc = xsc; 3404 struct ifnet *ifp = &sc->sc_ec.ec_if; 3405 3406 mutex_enter(&sc->sc_cfg_lock); 3407 3408 if (sc->sc_resetting) 3409 goto do_reset; 3410 3411 sc->sc_resetting = true; 3412 if_link_state_change(ifp, LINK_STATE_DOWN); 3413 3414 if (ISSET(ifp->if_flags, IFF_RUNNING)) { 3415 iavf_stop_locked(sc); 3416 sc->sc_reset_up = true; 3417 } 3418 3419 memcpy(sc->sc_enaddr_reset, sc->sc_enaddr, ETHER_ADDR_LEN); 3420 3421 do_reset: 3422 iavf_work_set(&sc->sc_reset_task, iavf_reset, sc); 3423 3424 mutex_exit(&sc->sc_cfg_lock); 3425 3426 iavf_reset((void *)sc); 3427 } 3428 3429 static void 3430 iavf_reset(void *xsc) 3431 { 3432 struct iavf_softc *sc = xsc; 3433 struct ifnet *ifp = &sc->sc_ec.ec_if; 3434 struct ixl_aq_buf *aqb; 3435 bool realloc_qps, realloc_intrs; 3436 3437 mutex_enter(&sc->sc_cfg_lock); 3438 3439 mutex_enter(&sc->sc_adminq_lock); 3440 iavf_cleanup_admin_queue(sc); 3441 mutex_exit(&sc->sc_adminq_lock); 3442 3443 sc->sc_major_ver = UINT_MAX; 3444 sc->sc_minor_ver = UINT_MAX; 3445 sc->sc_got_vf_resources = 0; 3446 sc->sc_got_irq_map = 0; 3447 3448 aqb = iavf_aqb_get(sc, &sc->sc_atq_idle); 3449 if (aqb == NULL) 3450 goto failed; 3451 3452 if (iavf_wait_active(sc) != 0) { 3453 log(LOG_WARNING, "%s: VF reset timed out\n", 3454 ifp->if_xname); 3455 goto failed; 3456 } 3457 3458 if (!iavf_arq_fill(sc)) { 3459 log(LOG_ERR, "%s: unable to fill arq descriptors\n", 3460 ifp->if_xname); 3461 goto failed; 3462 } 3463 3464 if (iavf_init_admin_queue(sc) != 0) { 3465 log(LOG_ERR, "%s: unable to initialize admin queue\n", 3466 ifp->if_xname); 3467 goto failed; 3468 } 3469 3470 if (iavf_get_version(sc, aqb) != 0) { 3471 log(LOG_ERR, "%s: unable to get VF interface version\n", 3472 ifp->if_xname); 3473 goto failed; 3474 } 3475 3476 if (iavf_get_vf_resources(sc, aqb) != 0) { 3477 log(LOG_ERR, "%s: timed out waiting for VF resources\n", 3478 ifp->if_xname); 3479 goto failed; 3480 } 3481 3482 if (sc->sc_nqps_alloc < iavf_calc_queue_pair_size(sc)) { 3483 realloc_qps = true; 3484 } else { 3485 realloc_qps = false; 3486 } 3487 3488 if (sc->sc_nintrs < iavf_calc_msix_count(sc)) { 3489 realloc_intrs = true; 3490 } else { 3491 realloc_intrs = false; 3492 } 3493 3494 if (realloc_qps || realloc_intrs) 3495 iavf_teardown_interrupts(sc); 3496 3497 if (realloc_qps) { 3498 iavf_queue_pairs_free(sc); 3499 if (iavf_queue_pairs_alloc(sc) != 0) { 3500 log(LOG_ERR, "%s: failed to allocate queue pairs\n", 3501 ifp->if_xname); 3502 goto failed; 3503 } 3504 } 3505 3506 if (realloc_qps || realloc_intrs) { 3507 if (iavf_setup_interrupts(sc) != 0) { 3508 sc->sc_nintrs = 0; 3509 log(LOG_ERR, "%s: failed to allocate interrupts\n", 3510 ifp->if_xname); 3511 goto failed; 3512 } 3513 log(LOG_INFO, "%s: reallocated queues\n", ifp->if_xname); 3514 } 3515 3516 if (iavf_config_irq_map(sc, aqb) != 0) { 3517 log(LOG_ERR, "%s: timed out configuring IRQ map\n", 3518 ifp->if_xname); 3519 goto failed; 3520 } 3521 3522 mutex_enter(&sc->sc_adminq_lock); 3523 iavf_aqb_put_locked(&sc->sc_atq_idle, aqb); 3524 mutex_exit(&sc->sc_adminq_lock); 3525 3526 iavf_reset_finish(sc); 3527 3528 mutex_exit(&sc->sc_cfg_lock); 3529 return; 3530 3531 failed: 3532 mutex_enter(&sc->sc_adminq_lock); 3533 iavf_cleanup_admin_queue(sc); 3534 if (aqb != NULL) { 3535 iavf_aqb_put_locked(&sc->sc_atq_idle, aqb); 3536 } 3537 mutex_exit(&sc->sc_adminq_lock); 3538 callout_schedule(&sc->sc_tick, IAVF_TICK_INTERVAL); 3539 mutex_exit(&sc->sc_cfg_lock); 3540 } 3541 3542 static void 3543 iavf_reset_finish(struct iavf_softc *sc) 3544 { 3545 struct ethercom *ec = &sc->sc_ec; 3546 struct ether_multi *enm; 3547 struct ether_multistep step; 3548 struct ifnet *ifp = &ec->ec_if; 3549 struct vlanid_list *vlanidp; 3550 uint8_t enaddr_prev[ETHER_ADDR_LEN], enaddr_next[ETHER_ADDR_LEN]; 3551 3552 KASSERT(mutex_owned(&sc->sc_cfg_lock)); 3553 3554 callout_stop(&sc->sc_tick); 3555 3556 iavf_intr_enable(sc); 3557 3558 if (!iavf_is_etheranyaddr(sc->sc_enaddr_added)) { 3559 iavf_eth_addr(sc, sc->sc_enaddr_added, IAVF_VC_OP_ADD_ETH_ADDR); 3560 } 3561 3562 ETHER_LOCK(ec); 3563 if (!ISSET(ifp->if_flags, IFF_ALLMULTI)) { 3564 for (ETHER_FIRST_MULTI(step, ec, enm); enm != NULL; 3565 ETHER_NEXT_MULTI(step, enm)) { 3566 iavf_add_multi(sc, enm->enm_addrlo, enm->enm_addrhi); 3567 } 3568 } 3569 3570 SIMPLEQ_FOREACH(vlanidp, &ec->ec_vids, vid_list) { 3571 ETHER_UNLOCK(ec); 3572 iavf_config_vlan_id(sc, vlanidp->vid, IAVF_VC_OP_ADD_VLAN); 3573 ETHER_LOCK(ec); 3574 } 3575 ETHER_UNLOCK(ec); 3576 3577 if (memcmp(sc->sc_enaddr, sc->sc_enaddr_reset, ETHER_ADDR_LEN) != 0) { 3578 memcpy(enaddr_prev, sc->sc_enaddr_reset, sizeof(enaddr_prev)); 3579 memcpy(enaddr_next, sc->sc_enaddr, sizeof(enaddr_next)); 3580 log(LOG_INFO, "%s: Ethernet address changed to %s\n", 3581 ifp->if_xname, ether_sprintf(enaddr_next)); 3582 3583 mutex_exit(&sc->sc_cfg_lock); 3584 IFNET_LOCK(ifp); 3585 kpreempt_disable(); 3586 /*XXX we need an API to change ethernet address. */ 3587 iavf_replace_lla(ifp, enaddr_prev, enaddr_next); 3588 kpreempt_enable(); 3589 IFNET_UNLOCK(ifp); 3590 mutex_enter(&sc->sc_cfg_lock); 3591 } 3592 3593 sc->sc_resetting = false; 3594 3595 if (sc->sc_reset_up) { 3596 iavf_init_locked(sc); 3597 } 3598 3599 if (sc->sc_link_state != LINK_STATE_DOWN) { 3600 if_link_state_change(ifp, sc->sc_link_state); 3601 } 3602 3603 } 3604 3605 static int 3606 iavf_dmamem_alloc(bus_dma_tag_t dmat, struct ixl_dmamem *ixm, 3607 bus_size_t size, bus_size_t align) 3608 { 3609 ixm->ixm_size = size; 3610 3611 if (bus_dmamap_create(dmat, ixm->ixm_size, 1, 3612 ixm->ixm_size, 0, 3613 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 3614 &ixm->ixm_map) != 0) 3615 return 1; 3616 if (bus_dmamem_alloc(dmat, ixm->ixm_size, 3617 align, 0, &ixm->ixm_seg, 1, &ixm->ixm_nsegs, 3618 BUS_DMA_WAITOK) != 0) 3619 goto destroy; 3620 if (bus_dmamem_map(dmat, &ixm->ixm_seg, ixm->ixm_nsegs, 3621 ixm->ixm_size, &ixm->ixm_kva, BUS_DMA_WAITOK) != 0) 3622 goto free; 3623 if (bus_dmamap_load(dmat, ixm->ixm_map, ixm->ixm_kva, 3624 ixm->ixm_size, NULL, BUS_DMA_WAITOK) != 0) 3625 goto unmap; 3626 3627 memset(ixm->ixm_kva, 0, ixm->ixm_size); 3628 3629 return 0; 3630 unmap: 3631 bus_dmamem_unmap(dmat, ixm->ixm_kva, ixm->ixm_size); 3632 free: 3633 bus_dmamem_free(dmat, &ixm->ixm_seg, 1); 3634 destroy: 3635 bus_dmamap_destroy(dmat, ixm->ixm_map); 3636 return 1; 3637 } 3638 3639 static void 3640 iavf_dmamem_free(bus_dma_tag_t dmat, struct ixl_dmamem *ixm) 3641 { 3642 3643 bus_dmamap_unload(dmat, ixm->ixm_map); 3644 bus_dmamem_unmap(dmat, ixm->ixm_kva, ixm->ixm_size); 3645 bus_dmamem_free(dmat, &ixm->ixm_seg, 1); 3646 bus_dmamap_destroy(dmat, ixm->ixm_map); 3647 } 3648 3649 static struct ixl_aq_buf * 3650 iavf_aqb_alloc(bus_dma_tag_t dmat, size_t buflen) 3651 { 3652 struct ixl_aq_buf *aqb; 3653 3654 aqb = kmem_alloc(sizeof(*aqb), KM_NOSLEEP); 3655 if (aqb == NULL) 3656 return NULL; 3657 3658 aqb->aqb_size = buflen; 3659 3660 if (bus_dmamap_create(dmat, aqb->aqb_size, 1, 3661 aqb->aqb_size, 0, 3662 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, &aqb->aqb_map) != 0) 3663 goto free; 3664 if (bus_dmamem_alloc(dmat, aqb->aqb_size, 3665 IAVF_AQ_ALIGN, 0, &aqb->aqb_seg, 1, &aqb->aqb_nsegs, 3666 BUS_DMA_WAITOK) != 0) 3667 goto destroy; 3668 if (bus_dmamem_map(dmat, &aqb->aqb_seg, aqb->aqb_nsegs, 3669 aqb->aqb_size, &aqb->aqb_data, BUS_DMA_WAITOK) != 0) 3670 goto dma_free; 3671 if (bus_dmamap_load(dmat, aqb->aqb_map, aqb->aqb_data, 3672 aqb->aqb_size, NULL, BUS_DMA_WAITOK) != 0) 3673 goto unmap; 3674 3675 return aqb; 3676 unmap: 3677 bus_dmamem_unmap(dmat, aqb->aqb_data, aqb->aqb_size); 3678 dma_free: 3679 bus_dmamem_free(dmat, &aqb->aqb_seg, 1); 3680 destroy: 3681 bus_dmamap_destroy(dmat, aqb->aqb_map); 3682 free: 3683 kmem_free(aqb, sizeof(*aqb)); 3684 3685 return NULL; 3686 } 3687 3688 static void 3689 iavf_aqb_free(bus_dma_tag_t dmat, struct ixl_aq_buf *aqb) 3690 { 3691 3692 bus_dmamap_unload(dmat, aqb->aqb_map); 3693 bus_dmamem_unmap(dmat, aqb->aqb_data, aqb->aqb_size); 3694 bus_dmamem_free(dmat, &aqb->aqb_seg, 1); 3695 bus_dmamap_destroy(dmat, aqb->aqb_map); 3696 kmem_free(aqb, sizeof(*aqb)); 3697 } 3698 3699 static struct ixl_aq_buf * 3700 iavf_aqb_get_locked(struct ixl_aq_bufs *q) 3701 { 3702 struct ixl_aq_buf *aqb; 3703 3704 aqb = SIMPLEQ_FIRST(q); 3705 if (aqb != NULL) { 3706 SIMPLEQ_REMOVE(q, aqb, ixl_aq_buf, aqb_entry); 3707 } 3708 3709 return aqb; 3710 } 3711 3712 static struct ixl_aq_buf * 3713 iavf_aqb_get(struct iavf_softc *sc, struct ixl_aq_bufs *q) 3714 { 3715 struct ixl_aq_buf *aqb; 3716 3717 if (q != NULL) { 3718 mutex_enter(&sc->sc_adminq_lock); 3719 aqb = iavf_aqb_get_locked(q); 3720 mutex_exit(&sc->sc_adminq_lock); 3721 } else { 3722 aqb = NULL; 3723 } 3724 3725 if (aqb == NULL) { 3726 aqb = iavf_aqb_alloc(sc->sc_dmat, IAVF_AQ_BUFLEN); 3727 } 3728 3729 return aqb; 3730 } 3731 3732 static void 3733 iavf_aqb_put_locked(struct ixl_aq_bufs *q, struct ixl_aq_buf *aqb) 3734 { 3735 3736 SIMPLEQ_INSERT_TAIL(q, aqb, aqb_entry); 3737 } 3738 3739 static void 3740 iavf_aqb_clean(struct ixl_aq_bufs *q, bus_dma_tag_t dmat) 3741 { 3742 struct ixl_aq_buf *aqb; 3743 3744 while ((aqb = SIMPLEQ_FIRST(q)) != NULL) { 3745 SIMPLEQ_REMOVE(q, aqb, ixl_aq_buf, aqb_entry); 3746 iavf_aqb_free(dmat, aqb); 3747 } 3748 } 3749 3750 static const char * 3751 iavf_aq_vc_opcode_str(const struct ixl_aq_desc *iaq) 3752 { 3753 3754 switch (iavf_aq_vc_get_opcode(iaq)) { 3755 case IAVF_VC_OP_VERSION: 3756 return "GET_VERSION"; 3757 case IAVF_VC_OP_RESET_VF: 3758 return "RESET_VF"; 3759 case IAVF_VC_OP_GET_VF_RESOURCES: 3760 return "GET_VF_RESOURCES"; 3761 case IAVF_VC_OP_CONFIG_TX_QUEUE: 3762 return "CONFIG_TX_QUEUE"; 3763 case IAVF_VC_OP_CONFIG_RX_QUEUE: 3764 return "CONFIG_RX_QUEUE"; 3765 case IAVF_VC_OP_CONFIG_VSI_QUEUES: 3766 return "CONFIG_VSI_QUEUES"; 3767 case IAVF_VC_OP_CONFIG_IRQ_MAP: 3768 return "CONFIG_IRQ_MAP"; 3769 case IAVF_VC_OP_ENABLE_QUEUES: 3770 return "ENABLE_QUEUES"; 3771 case IAVF_VC_OP_DISABLE_QUEUES: 3772 return "DISABLE_QUEUES"; 3773 case IAVF_VC_OP_ADD_ETH_ADDR: 3774 return "ADD_ETH_ADDR"; 3775 case IAVF_VC_OP_DEL_ETH_ADDR: 3776 return "DEL_ETH_ADDR"; 3777 case IAVF_VC_OP_CONFIG_PROMISC: 3778 return "CONFIG_PROMISC"; 3779 case IAVF_VC_OP_GET_STATS: 3780 return "GET_STATS"; 3781 case IAVF_VC_OP_EVENT: 3782 return "EVENT"; 3783 case IAVF_VC_OP_CONFIG_RSS_KEY: 3784 return "CONFIG_RSS_KEY"; 3785 case IAVF_VC_OP_CONFIG_RSS_LUT: 3786 return "CONFIG_RSS_LUT"; 3787 case IAVF_VC_OP_GET_RSS_HENA_CAPS: 3788 return "GET_RS_HENA_CAPS"; 3789 case IAVF_VC_OP_SET_RSS_HENA: 3790 return "SET_RSS_HENA"; 3791 case IAVF_VC_OP_ENABLE_VLAN_STRIP: 3792 return "ENABLE_VLAN_STRIPPING"; 3793 case IAVF_VC_OP_DISABLE_VLAN_STRIP: 3794 return "DISABLE_VLAN_STRIPPING"; 3795 case IAVF_VC_OP_REQUEST_QUEUES: 3796 return "REQUEST_QUEUES"; 3797 } 3798 3799 return "unknown"; 3800 } 3801 3802 static void 3803 iavf_aq_dump(const struct iavf_softc *sc, const struct ixl_aq_desc *iaq, 3804 const char *msg) 3805 { 3806 char buf[512]; 3807 size_t len; 3808 3809 len = sizeof(buf); 3810 buf[--len] = '\0'; 3811 3812 device_printf(sc->sc_dev, "%s\n", msg); 3813 snprintb(buf, len, IXL_AQ_FLAGS_FMT, le16toh(iaq->iaq_flags)); 3814 device_printf(sc->sc_dev, "flags %s opcode %04x\n", 3815 buf, le16toh(iaq->iaq_opcode)); 3816 device_printf(sc->sc_dev, "datalen %u retval %u\n", 3817 le16toh(iaq->iaq_datalen), le16toh(iaq->iaq_retval)); 3818 device_printf(sc->sc_dev, "vc-opcode %u (%s)\n", 3819 iavf_aq_vc_get_opcode(iaq), 3820 iavf_aq_vc_opcode_str(iaq)); 3821 device_printf(sc->sc_dev, "vc-retval %u\n", 3822 iavf_aq_vc_get_retval(iaq)); 3823 device_printf(sc->sc_dev, "cookie %016" PRIx64 "\n", iaq->iaq_cookie); 3824 device_printf(sc->sc_dev, "%08x %08x %08x %08x\n", 3825 le32toh(iaq->iaq_param[0]), le32toh(iaq->iaq_param[1]), 3826 le32toh(iaq->iaq_param[2]), le32toh(iaq->iaq_param[3])); 3827 } 3828 3829 static int 3830 iavf_arq_fill(struct iavf_softc *sc) 3831 { 3832 struct ixl_aq_buf *aqb; 3833 struct ixl_aq_desc *arq, *iaq; 3834 unsigned int prod = sc->sc_arq_prod; 3835 unsigned int n; 3836 int filled; 3837 3838 n = ixl_rxr_unrefreshed(sc->sc_arq_prod, sc->sc_arq_cons, 3839 IAVF_AQ_NUM); 3840 3841 if (__predict_false(n <= 0)) 3842 return 0; 3843 3844 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_arq), 3845 0, IXL_DMA_LEN(&sc->sc_arq), 3846 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3847 3848 arq = IXL_DMA_KVA(&sc->sc_arq); 3849 3850 do { 3851 iaq = &arq[prod]; 3852 3853 if (ixl_aq_has_dva(iaq)) { 3854 /* already filled */ 3855 break; 3856 } 3857 3858 aqb = iavf_aqb_get_locked(&sc->sc_arq_idle); 3859 if (aqb == NULL) 3860 break; 3861 3862 memset(aqb->aqb_data, 0, aqb->aqb_size); 3863 3864 bus_dmamap_sync(sc->sc_dmat, aqb->aqb_map, 0, 3865 aqb->aqb_size, BUS_DMASYNC_PREREAD); 3866 3867 iaq->iaq_flags = htole16(IXL_AQ_BUF | 3868 (aqb->aqb_size > I40E_AQ_LARGE_BUF ? 3869 IXL_AQ_LB : 0)); 3870 iaq->iaq_opcode = 0; 3871 iaq->iaq_datalen = htole16(aqb->aqb_size); 3872 iaq->iaq_retval = 0; 3873 iaq->iaq_cookie = 0; 3874 iaq->iaq_param[0] = 0; 3875 iaq->iaq_param[1] = 0; 3876 ixl_aq_dva(iaq, IXL_AQB_DVA(aqb)); 3877 iavf_aqb_put_locked(&sc->sc_arq_live, aqb); 3878 3879 prod++; 3880 prod &= IAVF_AQ_MASK; 3881 filled = 1; 3882 } while (--n); 3883 3884 sc->sc_arq_prod = prod; 3885 3886 if (filled) { 3887 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_arq), 3888 0, IXL_DMA_LEN(&sc->sc_arq), 3889 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3890 iavf_wr(sc, sc->sc_aq_regs->arq_tail, sc->sc_arq_prod); 3891 } 3892 3893 return filled; 3894 } 3895 3896 static int 3897 iavf_arq_wait(struct iavf_softc *sc, uint32_t opcode) 3898 { 3899 int error; 3900 3901 KASSERT(mutex_owned(&sc->sc_adminq_lock)); 3902 3903 while ((error = cv_timedwait(&sc->sc_adminq_cv, 3904 &sc->sc_adminq_lock, mstohz(IAVF_EXEC_TIMEOUT))) == 0) { 3905 if (opcode == sc->sc_arq_opcode) 3906 break; 3907 } 3908 3909 if (error != 0 && 3910 atomic_load_relaxed(&sc->sc_debuglevel) >= 2) 3911 device_printf(sc->sc_dev, "cv_timedwait error=%d\n", error); 3912 3913 return error; 3914 } 3915 3916 static void 3917 iavf_arq_refill(void *xsc) 3918 { 3919 struct iavf_softc *sc = xsc; 3920 struct ixl_aq_bufs aqbs; 3921 struct ixl_aq_buf *aqb; 3922 unsigned int n, i; 3923 3924 mutex_enter(&sc->sc_adminq_lock); 3925 iavf_arq_fill(sc); 3926 n = ixl_rxr_unrefreshed(sc->sc_arq_prod, sc->sc_arq_cons, 3927 IAVF_AQ_NUM); 3928 mutex_exit(&sc->sc_adminq_lock); 3929 3930 if (n == 0) 3931 return; 3932 3933 if (atomic_load_relaxed(&sc->sc_debuglevel) >= 1) 3934 device_printf(sc->sc_dev, "Allocate %d bufs for arq\n", n); 3935 3936 SIMPLEQ_INIT(&aqbs); 3937 for (i = 0; i < n; i++) { 3938 aqb = iavf_aqb_get(sc, NULL); 3939 if (aqb == NULL) 3940 continue; 3941 SIMPLEQ_INSERT_TAIL(&aqbs, aqb, aqb_entry); 3942 } 3943 3944 mutex_enter(&sc->sc_adminq_lock); 3945 while ((aqb = SIMPLEQ_FIRST(&aqbs)) != NULL) { 3946 SIMPLEQ_REMOVE(&aqbs, aqb, ixl_aq_buf, aqb_entry); 3947 iavf_aqb_put_locked(&sc->sc_arq_idle, aqb); 3948 } 3949 iavf_arq_fill(sc); 3950 mutex_exit(&sc->sc_adminq_lock); 3951 } 3952 3953 static uint32_t 3954 iavf_process_arq(struct iavf_softc *sc, struct ixl_aq_desc *iaq, 3955 struct ixl_aq_buf *aqb) 3956 { 3957 uint32_t vc_retval, vc_opcode; 3958 int dbg; 3959 3960 dbg = atomic_load_relaxed(&sc->sc_debuglevel); 3961 if (dbg >= 3) 3962 iavf_aq_dump(sc, iaq, "arq proc"); 3963 3964 if (dbg >= 2) { 3965 vc_retval = iavf_aq_vc_get_retval(iaq); 3966 if (vc_retval != IAVF_VC_RC_SUCCESS) { 3967 device_printf(sc->sc_dev, "%s failed=%d(arq)\n", 3968 iavf_aq_vc_opcode_str(iaq), vc_retval); 3969 } 3970 } 3971 3972 vc_opcode = iavf_aq_vc_get_opcode(iaq); 3973 switch (vc_opcode) { 3974 case IAVF_VC_OP_VERSION: 3975 iavf_process_version(sc, iaq, aqb); 3976 break; 3977 case IAVF_VC_OP_GET_VF_RESOURCES: 3978 iavf_process_vf_resources(sc, iaq, aqb); 3979 break; 3980 case IAVF_VC_OP_CONFIG_IRQ_MAP: 3981 iavf_process_irq_map(sc, iaq); 3982 break; 3983 case IAVF_VC_OP_EVENT: 3984 iavf_process_vc_event(sc, iaq, aqb); 3985 break; 3986 case IAVF_VC_OP_GET_STATS: 3987 iavf_process_stats(sc, iaq, aqb); 3988 break; 3989 case IAVF_VC_OP_REQUEST_QUEUES: 3990 iavf_process_req_queues(sc, iaq, aqb); 3991 break; 3992 } 3993 3994 return vc_opcode; 3995 } 3996 3997 static int 3998 iavf_arq_poll(struct iavf_softc *sc, uint32_t wait_opcode, int retry) 3999 { 4000 struct ixl_aq_desc *arq, *iaq; 4001 struct ixl_aq_buf *aqb; 4002 unsigned int cons = sc->sc_arq_cons; 4003 unsigned int prod; 4004 uint32_t vc_opcode; 4005 bool received; 4006 int i; 4007 4008 for (i = 0, received = false; i < retry && !received; i++) { 4009 prod = iavf_rd(sc, sc->sc_aq_regs->arq_head); 4010 prod &= sc->sc_aq_regs->arq_head_mask; 4011 4012 if (prod == cons) { 4013 delaymsec(1); 4014 continue; 4015 } 4016 4017 if (prod >= IAVF_AQ_NUM) { 4018 return EIO; 4019 } 4020 4021 arq = IXL_DMA_KVA(&sc->sc_arq); 4022 4023 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_arq), 4024 0, IXL_DMA_LEN(&sc->sc_arq), 4025 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4026 4027 do { 4028 iaq = &arq[cons]; 4029 aqb = iavf_aqb_get_locked(&sc->sc_arq_live); 4030 KASSERT(aqb != NULL); 4031 4032 bus_dmamap_sync(sc->sc_dmat, aqb->aqb_map, 0, 4033 IAVF_AQ_BUFLEN, BUS_DMASYNC_POSTREAD); 4034 4035 vc_opcode = iavf_process_arq(sc, iaq, aqb); 4036 4037 if (vc_opcode == wait_opcode) 4038 received = true; 4039 4040 memset(iaq, 0, sizeof(*iaq)); 4041 iavf_aqb_put_locked(&sc->sc_arq_idle, aqb); 4042 4043 cons++; 4044 cons &= IAVF_AQ_MASK; 4045 4046 } while (cons != prod); 4047 4048 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_arq), 4049 0, IXL_DMA_LEN(&sc->sc_arq), 4050 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 4051 4052 sc->sc_arq_cons = cons; 4053 iavf_arq_fill(sc); 4054 4055 } 4056 4057 if (!received) 4058 return ETIMEDOUT; 4059 4060 return 0; 4061 } 4062 4063 static int 4064 iavf_arq(struct iavf_softc *sc) 4065 { 4066 struct ixl_aq_desc *arq, *iaq; 4067 struct ixl_aq_buf *aqb; 4068 unsigned int cons = sc->sc_arq_cons; 4069 unsigned int prod; 4070 uint32_t vc_opcode; 4071 4072 KASSERT(mutex_owned(&sc->sc_adminq_lock)); 4073 4074 prod = iavf_rd(sc, sc->sc_aq_regs->arq_head); 4075 prod &= sc->sc_aq_regs->arq_head_mask; 4076 4077 /* broken value at resetting */ 4078 if (prod >= IAVF_AQ_NUM) { 4079 iavf_work_set(&sc->sc_reset_task, iavf_reset_start, sc); 4080 iavf_work_add(sc->sc_workq, &sc->sc_reset_task); 4081 return 0; 4082 } 4083 4084 if (cons == prod) 4085 return 0; 4086 4087 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_arq), 4088 0, IXL_DMA_LEN(&sc->sc_arq), 4089 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4090 4091 arq = IXL_DMA_KVA(&sc->sc_arq); 4092 4093 do { 4094 iaq = &arq[cons]; 4095 aqb = iavf_aqb_get_locked(&sc->sc_arq_live); 4096 4097 KASSERT(aqb != NULL); 4098 4099 bus_dmamap_sync(sc->sc_dmat, aqb->aqb_map, 0, IAVF_AQ_BUFLEN, 4100 BUS_DMASYNC_POSTREAD); 4101 4102 vc_opcode = iavf_process_arq(sc, iaq, aqb); 4103 4104 switch (vc_opcode) { 4105 case IAVF_VC_OP_CONFIG_TX_QUEUE: 4106 case IAVF_VC_OP_CONFIG_RX_QUEUE: 4107 case IAVF_VC_OP_CONFIG_VSI_QUEUES: 4108 case IAVF_VC_OP_ENABLE_QUEUES: 4109 case IAVF_VC_OP_DISABLE_QUEUES: 4110 case IAVF_VC_OP_GET_RSS_HENA_CAPS: 4111 case IAVF_VC_OP_SET_RSS_HENA: 4112 case IAVF_VC_OP_ADD_ETH_ADDR: 4113 case IAVF_VC_OP_DEL_ETH_ADDR: 4114 case IAVF_VC_OP_CONFIG_PROMISC: 4115 case IAVF_VC_OP_ADD_VLAN: 4116 case IAVF_VC_OP_DEL_VLAN: 4117 case IAVF_VC_OP_ENABLE_VLAN_STRIP: 4118 case IAVF_VC_OP_DISABLE_VLAN_STRIP: 4119 case IAVF_VC_OP_CONFIG_RSS_KEY: 4120 case IAVF_VC_OP_CONFIG_RSS_LUT: 4121 sc->sc_arq_retval = iavf_aq_vc_get_retval(iaq); 4122 sc->sc_arq_opcode = vc_opcode; 4123 cv_signal(&sc->sc_adminq_cv); 4124 break; 4125 } 4126 4127 memset(iaq, 0, sizeof(*iaq)); 4128 iavf_aqb_put_locked(&sc->sc_arq_idle, aqb); 4129 4130 cons++; 4131 cons &= IAVF_AQ_MASK; 4132 } while (cons != prod); 4133 4134 sc->sc_arq_cons = cons; 4135 iavf_work_add(sc->sc_workq, &sc->sc_arq_refill); 4136 4137 return 1; 4138 } 4139 4140 static int 4141 iavf_atq_post(struct iavf_softc *sc, struct ixl_aq_desc *iaq, 4142 struct ixl_aq_buf *aqb) 4143 { 4144 struct ixl_aq_desc *atq, *slot; 4145 unsigned int prod; 4146 4147 atq = IXL_DMA_KVA(&sc->sc_atq); 4148 prod = sc->sc_atq_prod; 4149 slot = &atq[prod]; 4150 4151 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 4152 0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_POSTWRITE); 4153 4154 *slot = *iaq; 4155 slot->iaq_flags |= htole16(IXL_AQ_SI); 4156 if (aqb != NULL) { 4157 ixl_aq_dva(slot, IXL_AQB_DVA(aqb)); 4158 bus_dmamap_sync(sc->sc_dmat, IXL_AQB_MAP(aqb), 4159 0, IXL_AQB_LEN(aqb), BUS_DMASYNC_PREWRITE); 4160 iavf_aqb_put_locked(&sc->sc_atq_live, aqb); 4161 } else { 4162 ixl_aq_dva(slot, (bus_addr_t)0); 4163 } 4164 4165 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 4166 0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_PREWRITE); 4167 4168 if (atomic_load_relaxed(&sc->sc_debuglevel) >= 3) 4169 iavf_aq_dump(sc, slot, "post"); 4170 4171 prod++; 4172 prod &= IAVF_AQ_MASK; 4173 sc->sc_atq_prod = prod; 4174 iavf_wr(sc, sc->sc_aq_regs->atq_tail, prod); 4175 return prod; 4176 } 4177 4178 static int 4179 iavf_atq_poll(struct iavf_softc *sc, unsigned int tm) 4180 { 4181 struct ixl_aq_desc *atq, *slot; 4182 struct ixl_aq_desc iaq; 4183 unsigned int prod; 4184 unsigned int t; 4185 int dbg; 4186 4187 dbg = atomic_load_relaxed(&sc->sc_debuglevel); 4188 atq = IXL_DMA_KVA(&sc->sc_atq); 4189 prod = sc->sc_atq_prod; 4190 slot = &atq[prod]; 4191 t = 0; 4192 4193 while (iavf_rd(sc, sc->sc_aq_regs->atq_head) != prod) { 4194 delaymsec(1); 4195 4196 if (t++ > tm) { 4197 if (dbg >= 2) { 4198 device_printf(sc->sc_dev, 4199 "atq timedout\n"); 4200 } 4201 return ETIMEDOUT; 4202 } 4203 } 4204 4205 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 4206 0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_POSTREAD); 4207 iaq = *slot; 4208 memset(slot, 0, sizeof(*slot)); 4209 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 4210 0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_PREREAD); 4211 4212 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) { 4213 if (dbg >= 2) { 4214 device_printf(sc->sc_dev, 4215 "atq retcode=0x%04x\n", le16toh(iaq.iaq_retval)); 4216 } 4217 return EIO; 4218 } 4219 4220 return 0; 4221 } 4222 4223 static void 4224 iavf_atq_done(struct iavf_softc *sc) 4225 { 4226 struct ixl_aq_desc *atq, *slot; 4227 struct ixl_aq_buf *aqb; 4228 unsigned int cons; 4229 unsigned int prod; 4230 4231 KASSERT(mutex_owned(&sc->sc_adminq_lock)); 4232 4233 prod = sc->sc_atq_prod; 4234 cons = sc->sc_atq_cons; 4235 4236 if (prod == cons) 4237 return; 4238 4239 atq = IXL_DMA_KVA(&sc->sc_atq); 4240 4241 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 4242 0, IXL_DMA_LEN(&sc->sc_atq), 4243 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4244 4245 do { 4246 slot = &atq[cons]; 4247 if (!ISSET(slot->iaq_flags, htole16(IXL_AQ_DD))) 4248 break; 4249 4250 if (ixl_aq_has_dva(slot) && 4251 (aqb = iavf_aqb_get_locked(&sc->sc_atq_live)) != NULL) { 4252 bus_dmamap_sync(sc->sc_dmat, IXL_AQB_MAP(aqb), 4253 0, IXL_AQB_LEN(aqb), BUS_DMASYNC_POSTWRITE); 4254 iavf_aqb_put_locked(&sc->sc_atq_idle, aqb); 4255 } 4256 4257 memset(slot, 0, sizeof(*slot)); 4258 4259 cons++; 4260 cons &= IAVF_AQ_MASK; 4261 } while (cons != prod); 4262 4263 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 4264 0, IXL_DMA_LEN(&sc->sc_atq), 4265 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 4266 4267 sc->sc_atq_cons = cons; 4268 } 4269 4270 static int 4271 iavf_adminq_poll(struct iavf_softc *sc, struct ixl_aq_desc *iaq, 4272 struct ixl_aq_buf *aqb, int retry) 4273 { 4274 int error; 4275 4276 mutex_enter(&sc->sc_adminq_lock); 4277 error = iavf_adminq_poll_locked(sc, iaq, aqb, retry); 4278 mutex_exit(&sc->sc_adminq_lock); 4279 4280 return error; 4281 } 4282 4283 static int 4284 iavf_adminq_poll_locked(struct iavf_softc *sc, 4285 struct ixl_aq_desc *iaq, struct ixl_aq_buf *aqb, int retry) 4286 { 4287 uint32_t opcode; 4288 int error; 4289 4290 KASSERT(!sc->sc_attached || mutex_owned(&sc->sc_adminq_lock)); 4291 4292 opcode = iavf_aq_vc_get_opcode(iaq); 4293 4294 iavf_atq_post(sc, iaq, aqb); 4295 4296 error = iavf_atq_poll(sc, retry); 4297 4298 /* 4299 * collect the aqb used in the current command and 4300 * added to sc_atq_live at iavf_atq_post(), 4301 * whether or not the command succeeded. 4302 */ 4303 if (aqb != NULL) { 4304 (void)iavf_aqb_get_locked(&sc->sc_atq_live); 4305 bus_dmamap_sync(sc->sc_dmat, IXL_AQB_MAP(aqb), 4306 0, IXL_AQB_LEN(aqb), BUS_DMASYNC_POSTWRITE); 4307 } 4308 4309 if (error) 4310 return error; 4311 4312 error = iavf_arq_poll(sc, opcode, retry); 4313 4314 if (error != 0 && 4315 atomic_load_relaxed(&sc->sc_debuglevel) >= 1) { 4316 device_printf(sc->sc_dev, "%s failed=%d(polling)\n", 4317 iavf_aq_vc_opcode_str(iaq), error); 4318 } 4319 4320 return error; 4321 } 4322 4323 static int 4324 iavf_adminq_exec(struct iavf_softc *sc, struct ixl_aq_desc *iaq, 4325 struct ixl_aq_buf *aqb) 4326 { 4327 int error; 4328 uint32_t opcode; 4329 4330 opcode = iavf_aq_vc_get_opcode(iaq); 4331 4332 mutex_enter(&sc->sc_adminq_lock); 4333 iavf_atq_post(sc, iaq, aqb); 4334 4335 error = iavf_arq_wait(sc, opcode); 4336 if (error == 0) { 4337 error = sc->sc_arq_retval; 4338 if (error != IAVF_VC_RC_SUCCESS && 4339 atomic_load_relaxed(&sc->sc_debuglevel) >= 1) { 4340 device_printf(sc->sc_dev, "%s failed=%d\n", 4341 iavf_aq_vc_opcode_str(iaq), error); 4342 } 4343 } 4344 4345 mutex_exit(&sc->sc_adminq_lock); 4346 return error; 4347 } 4348 4349 static void 4350 iavf_process_version(struct iavf_softc *sc, struct ixl_aq_desc *iaq, 4351 struct ixl_aq_buf *aqb) 4352 { 4353 struct iavf_vc_version_info *ver; 4354 4355 ver = (struct iavf_vc_version_info *)aqb->aqb_data; 4356 sc->sc_major_ver = le32toh(ver->major); 4357 sc->sc_minor_ver = le32toh(ver->minor); 4358 } 4359 4360 static void 4361 iavf_process_vf_resources(struct iavf_softc *sc, struct ixl_aq_desc *iaq, 4362 struct ixl_aq_buf *aqb) 4363 { 4364 struct iavf_vc_vf_resource *vf_res; 4365 struct iavf_vc_vsi_resource *vsi_res; 4366 uint8_t *enaddr; 4367 int mtu, dbg; 4368 char buf[512]; 4369 4370 dbg = atomic_load_relaxed(&sc->sc_debuglevel); 4371 sc->sc_got_vf_resources = 1; 4372 4373 vf_res = aqb->aqb_data; 4374 sc->sc_max_vectors = le16toh(vf_res->max_vectors); 4375 if (le16toh(vf_res->num_vsis) == 0) { 4376 if (dbg >= 1) { 4377 device_printf(sc->sc_dev, "no vsi available\n"); 4378 } 4379 return; 4380 } 4381 sc->sc_vf_cap = le32toh(vf_res->offload_flags); 4382 if (dbg >= 2) { 4383 snprintb(buf, sizeof(buf), 4384 IAVF_VC_OFFLOAD_FMT, sc->sc_vf_cap); 4385 device_printf(sc->sc_dev, "VF cap=%s\n", buf); 4386 } 4387 4388 mtu = le16toh(vf_res->max_mtu); 4389 if (IAVF_MIN_MTU < mtu && mtu < IAVF_MAX_MTU) { 4390 sc->sc_max_mtu = MIN(IAVF_MAX_MTU, mtu); 4391 } 4392 4393 vsi_res = &vf_res->vsi_res[0]; 4394 sc->sc_vsi_id = le16toh(vsi_res->vsi_id); 4395 sc->sc_vf_id = le32toh(iaq->iaq_param[0]); 4396 sc->sc_qset_handle = le16toh(vsi_res->qset_handle); 4397 sc->sc_nqps_vsi = le16toh(vsi_res->num_queue_pairs); 4398 if (!iavf_is_etheranyaddr(vsi_res->default_mac)) { 4399 enaddr = vsi_res->default_mac; 4400 } else { 4401 enaddr = sc->sc_enaddr_fake; 4402 } 4403 memcpy(sc->sc_enaddr, enaddr, ETHER_ADDR_LEN); 4404 } 4405 4406 static void 4407 iavf_process_irq_map(struct iavf_softc *sc, struct ixl_aq_desc *iaq) 4408 { 4409 uint32_t retval; 4410 4411 retval = iavf_aq_vc_get_retval(iaq); 4412 if (retval != IAVF_VC_RC_SUCCESS) { 4413 return; 4414 } 4415 4416 sc->sc_got_irq_map = 1; 4417 } 4418 4419 static void 4420 iavf_process_vc_event(struct iavf_softc *sc, struct ixl_aq_desc *iaq, 4421 struct ixl_aq_buf *aqb) 4422 { 4423 struct iavf_vc_pf_event *event; 4424 struct ifnet *ifp = &sc->sc_ec.ec_if; 4425 const struct iavf_link_speed *speed; 4426 int link; 4427 4428 event = aqb->aqb_data; 4429 switch (event->event) { 4430 case IAVF_VC_EVENT_LINK_CHANGE: 4431 sc->sc_media_status = IFM_AVALID; 4432 sc->sc_media_active = IFM_ETHER; 4433 link = LINK_STATE_DOWN; 4434 if (event->link_status) { 4435 link = LINK_STATE_UP; 4436 sc->sc_media_status |= IFM_ACTIVE; 4437 sc->sc_media_active |= IFM_FDX; 4438 4439 ifp->if_baudrate = 0; 4440 speed = iavf_find_link_speed(sc, event->link_speed); 4441 if (speed != NULL) { 4442 sc->sc_media_active |= speed->media; 4443 ifp->if_baudrate = speed->baudrate; 4444 } 4445 } 4446 4447 if (sc->sc_link_state != link) { 4448 sc->sc_link_state = link; 4449 if (sc->sc_attached) { 4450 if_link_state_change(ifp, link); 4451 } 4452 } 4453 break; 4454 case IAVF_VC_EVENT_RESET_IMPENDING: 4455 log(LOG_INFO, "%s: Reset warning received from the PF\n", 4456 ifp->if_xname); 4457 iavf_work_set(&sc->sc_reset_task, iavf_reset_request, sc); 4458 iavf_work_add(sc->sc_workq, &sc->sc_reset_task); 4459 break; 4460 } 4461 } 4462 4463 static void 4464 iavf_process_stats(struct iavf_softc *sc, struct ixl_aq_desc *iaq, 4465 struct ixl_aq_buf *aqb) 4466 { 4467 struct iavf_stat_counters *isc; 4468 struct i40e_eth_stats *st; 4469 4470 KASSERT(mutex_owned(&sc->sc_adminq_lock)); 4471 4472 st = aqb->aqb_data; 4473 isc = &sc->sc_stat_counters; 4474 4475 isc->isc_rx_bytes.ev_count = st->rx_bytes; 4476 isc->isc_rx_unicast.ev_count = st->rx_unicast; 4477 isc->isc_rx_multicast.ev_count = st->rx_multicast; 4478 isc->isc_rx_broadcast.ev_count = st->rx_broadcast; 4479 isc->isc_rx_discards.ev_count = st->rx_discards; 4480 isc->isc_rx_unknown_protocol.ev_count = st->rx_unknown_protocol; 4481 4482 isc->isc_tx_bytes.ev_count = st->tx_bytes; 4483 isc->isc_tx_unicast.ev_count = st->tx_unicast; 4484 isc->isc_tx_multicast.ev_count = st->tx_multicast; 4485 isc->isc_tx_broadcast.ev_count = st->tx_broadcast; 4486 isc->isc_tx_discards.ev_count = st->tx_discards; 4487 isc->isc_tx_errors.ev_count = st->tx_errors; 4488 } 4489 4490 static void 4491 iavf_process_req_queues(struct iavf_softc *sc, struct ixl_aq_desc *iaq, 4492 struct ixl_aq_buf *aqb) 4493 { 4494 struct iavf_vc_res_request *req; 4495 struct ifnet *ifp; 4496 uint32_t vc_retval; 4497 4498 ifp = &sc->sc_ec.ec_if; 4499 req = aqb->aqb_data; 4500 4501 vc_retval = iavf_aq_vc_get_retval(iaq); 4502 if (vc_retval != IAVF_VC_RC_SUCCESS) { 4503 return; 4504 } 4505 4506 if (sc->sc_nqps_req < req->num_queue_pairs) { 4507 log(LOG_INFO, 4508 "%s: requested %d queues, but only %d left.\n", 4509 ifp->if_xname, 4510 sc->sc_nqps_req, req->num_queue_pairs); 4511 } 4512 4513 if (sc->sc_nqps_vsi < req->num_queue_pairs) { 4514 if (!sc->sc_req_queues_retried) { 4515 /* req->num_queue_pairs indicates max qps */ 4516 sc->sc_nqps_req = req->num_queue_pairs; 4517 4518 sc->sc_req_queues_retried = true; 4519 iavf_work_add(sc->sc_workq, &sc->sc_req_queues_task); 4520 } 4521 } 4522 } 4523 4524 static int 4525 iavf_get_version(struct iavf_softc *sc, struct ixl_aq_buf *aqb) 4526 { 4527 struct ixl_aq_desc iaq; 4528 struct iavf_vc_version_info *ver; 4529 int error; 4530 4531 memset(&iaq, 0, sizeof(iaq)); 4532 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD); 4533 iaq.iaq_opcode = htole16(IAVF_AQ_OP_SEND_TO_PF); 4534 iavf_aq_vc_set_opcode(&iaq, IAVF_VC_OP_VERSION); 4535 iaq.iaq_datalen = htole16(sizeof(struct iavf_vc_version_info)); 4536 4537 ver = IXL_AQB_KVA(aqb); 4538 ver->major = htole32(IAVF_VF_MAJOR); 4539 ver->minor = htole32(IAVF_VF_MINOR); 4540 4541 sc->sc_major_ver = UINT_MAX; 4542 sc->sc_minor_ver = UINT_MAX; 4543 4544 if (sc->sc_attached) { 4545 error = iavf_adminq_poll(sc, &iaq, aqb, 250); 4546 } else { 4547 error = iavf_adminq_poll_locked(sc, &iaq, aqb, 250); 4548 } 4549 4550 if (error) 4551 return -1; 4552 4553 return 0; 4554 } 4555 4556 static int 4557 iavf_get_vf_resources(struct iavf_softc *sc, struct ixl_aq_buf *aqb) 4558 { 4559 struct ixl_aq_desc iaq; 4560 uint32_t *cap, cap0; 4561 int error; 4562 4563 memset(&iaq, 0, sizeof(iaq)); 4564 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD); 4565 iaq.iaq_opcode = htole16(IAVF_AQ_OP_SEND_TO_PF); 4566 iavf_aq_vc_set_opcode(&iaq, IAVF_VC_OP_GET_VF_RESOURCES); 4567 4568 if (sc->sc_major_ver > 0) { 4569 cap0 = IAVF_VC_OFFLOAD_L2 | 4570 IAVF_VC_OFFLOAD_VLAN | 4571 IAVF_VC_OFFLOAD_RSS_PF | 4572 IAVF_VC_OFFLOAD_REQ_QUEUES; 4573 4574 cap = IXL_AQB_KVA(aqb); 4575 *cap = htole32(cap0); 4576 iaq.iaq_datalen = htole16(sizeof(*cap)); 4577 } 4578 4579 sc->sc_got_vf_resources = 0; 4580 if (sc->sc_attached) { 4581 error = iavf_adminq_poll(sc, &iaq, aqb, 250); 4582 } else { 4583 error = iavf_adminq_poll_locked(sc, &iaq, aqb, 250); 4584 } 4585 4586 if (error) 4587 return -1; 4588 return 0; 4589 } 4590 4591 static int 4592 iavf_get_stats(struct iavf_softc *sc) 4593 { 4594 struct ixl_aq_desc iaq; 4595 struct ixl_aq_buf *aqb; 4596 struct iavf_vc_queue_select *qsel; 4597 int error; 4598 4599 mutex_enter(&sc->sc_adminq_lock); 4600 aqb = iavf_aqb_get_locked(&sc->sc_atq_idle); 4601 mutex_exit(&sc->sc_adminq_lock); 4602 4603 if (aqb == NULL) 4604 return ENOMEM; 4605 4606 qsel = IXL_AQB_KVA(aqb); 4607 memset(qsel, 0, sizeof(*qsel)); 4608 qsel->vsi_id = htole16(sc->sc_vsi_id); 4609 4610 memset(&iaq, 0, sizeof(iaq)); 4611 4612 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD); 4613 iaq.iaq_opcode = htole16(IAVF_AQ_OP_SEND_TO_PF); 4614 iavf_aq_vc_set_opcode(&iaq, IAVF_VC_OP_GET_STATS); 4615 iaq.iaq_datalen = htole16(sizeof(*qsel)); 4616 4617 if (atomic_load_relaxed(&sc->sc_debuglevel) >= 3) { 4618 device_printf(sc->sc_dev, "post GET_STATS command\n"); 4619 } 4620 4621 mutex_enter(&sc->sc_adminq_lock); 4622 error = iavf_atq_post(sc, &iaq, aqb); 4623 mutex_exit(&sc->sc_adminq_lock); 4624 4625 return error; 4626 } 4627 4628 static int 4629 iavf_config_irq_map(struct iavf_softc *sc, struct ixl_aq_buf *aqb) 4630 { 4631 struct ixl_aq_desc iaq; 4632 struct iavf_vc_vector_map *vec; 4633 struct iavf_vc_irq_map_info *map; 4634 struct iavf_rx_ring *rxr; 4635 struct iavf_tx_ring *txr; 4636 unsigned int num_vec; 4637 int error; 4638 4639 map = IXL_AQB_KVA(aqb); 4640 vec = map->vecmap; 4641 num_vec = 0; 4642 4643 if (sc->sc_nintrs == 1) { 4644 vec[0].vsi_id = htole16(sc->sc_vsi_id); 4645 vec[0].vector_id = htole16(0); 4646 vec[0].rxq_map = htole16(iavf_allqueues(sc)); 4647 vec[0].txq_map = htole16(iavf_allqueues(sc)); 4648 vec[0].rxitr_idx = htole16(IAVF_NOITR); 4649 vec[0].rxitr_idx = htole16(IAVF_NOITR); 4650 num_vec = 1; 4651 } else if (sc->sc_nintrs > 1) { 4652 KASSERT(sc->sc_nqps_alloc >= (sc->sc_nintrs - 1)); 4653 for (; num_vec < (sc->sc_nintrs - 1); num_vec++) { 4654 rxr = sc->sc_qps[num_vec].qp_rxr; 4655 txr = sc->sc_qps[num_vec].qp_txr; 4656 4657 vec[num_vec].vsi_id = htole16(sc->sc_vsi_id); 4658 vec[num_vec].vector_id = htole16(num_vec + 1); 4659 vec[num_vec].rxq_map = htole16(__BIT(rxr->rxr_qid)); 4660 vec[num_vec].txq_map = htole16(__BIT(txr->txr_qid)); 4661 vec[num_vec].rxitr_idx = htole16(IAVF_ITR_RX); 4662 vec[num_vec].txitr_idx = htole16(IAVF_ITR_TX); 4663 } 4664 4665 vec[num_vec].vsi_id = htole16(sc->sc_vsi_id); 4666 vec[num_vec].vector_id = htole16(0); 4667 vec[num_vec].rxq_map = htole16(0); 4668 vec[num_vec].txq_map = htole16(0); 4669 num_vec++; 4670 } 4671 4672 map->num_vectors = htole16(num_vec); 4673 4674 memset(&iaq, 0, sizeof(iaq)); 4675 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD); 4676 iaq.iaq_opcode = htole16(IAVF_AQ_OP_SEND_TO_PF); 4677 iavf_aq_vc_set_opcode(&iaq, IAVF_VC_OP_CONFIG_IRQ_MAP); 4678 iaq.iaq_datalen = htole16(sizeof(*map) + sizeof(*vec) * num_vec); 4679 4680 if (sc->sc_attached) { 4681 error = iavf_adminq_poll(sc, &iaq, aqb, 250); 4682 } else { 4683 error = iavf_adminq_poll_locked(sc, &iaq, aqb, 250); 4684 } 4685 4686 if (error) 4687 return -1; 4688 4689 return 0; 4690 } 4691 4692 static int 4693 iavf_config_vsi_queues(struct iavf_softc *sc) 4694 { 4695 struct ifnet *ifp = &sc->sc_ec.ec_if; 4696 struct ixl_aq_desc iaq; 4697 struct ixl_aq_buf *aqb; 4698 struct iavf_vc_queue_config_info *config; 4699 struct iavf_vc_txq_info *txq; 4700 struct iavf_vc_rxq_info *rxq; 4701 struct iavf_rx_ring *rxr; 4702 struct iavf_tx_ring *txr; 4703 uint32_t rxmtu_max; 4704 unsigned int i; 4705 int error; 4706 4707 rxmtu_max = ifp->if_mtu + IAVF_MTU_ETHERLEN; 4708 4709 aqb = iavf_aqb_get(sc, &sc->sc_atq_idle); 4710 4711 if (aqb == NULL) 4712 return -1; 4713 4714 config = IXL_AQB_KVA(aqb); 4715 memset(config, 0, sizeof(*config)); 4716 config->vsi_id = htole16(sc->sc_vsi_id); 4717 config->num_queue_pairs = htole16(sc->sc_nqueue_pairs); 4718 4719 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 4720 rxr = sc->sc_qps[i].qp_rxr; 4721 txr = sc->sc_qps[i].qp_txr; 4722 4723 txq = &config->qpair[i].txq; 4724 txq->vsi_id = htole16(sc->sc_vsi_id); 4725 txq->queue_id = htole16(txr->txr_qid); 4726 txq->ring_len = htole16(sc->sc_tx_ring_ndescs); 4727 txq->headwb_ena = 0; 4728 txq->dma_ring_addr = htole64(IXL_DMA_DVA(&txr->txr_mem)); 4729 txq->dma_headwb_addr = 0; 4730 4731 rxq = &config->qpair[i].rxq; 4732 rxq->vsi_id = htole16(sc->sc_vsi_id); 4733 rxq->queue_id = htole16(rxr->rxr_qid); 4734 rxq->ring_len = htole16(sc->sc_rx_ring_ndescs); 4735 rxq->splithdr_ena = 0; 4736 rxq->databuf_size = htole32(IAVF_MCLBYTES); 4737 rxq->max_pkt_size = htole32(rxmtu_max); 4738 rxq->dma_ring_addr = htole64(IXL_DMA_DVA(&rxr->rxr_mem)); 4739 rxq->rx_split_pos = 0; 4740 } 4741 4742 memset(&iaq, 0, sizeof(iaq)); 4743 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD); 4744 iaq.iaq_opcode = htole16(IAVF_AQ_OP_SEND_TO_PF); 4745 iavf_aq_vc_set_opcode(&iaq, IAVF_VC_OP_CONFIG_VSI_QUEUES); 4746 iaq.iaq_datalen = htole16(sizeof(*config) + 4747 sizeof(config->qpair[0]) * sc->sc_nqueue_pairs); 4748 4749 error = iavf_adminq_exec(sc, &iaq, aqb); 4750 if (error != IAVF_VC_RC_SUCCESS) { 4751 return -1; 4752 } 4753 4754 return 0; 4755 } 4756 4757 static int 4758 iavf_config_hena(struct iavf_softc *sc) 4759 { 4760 struct ixl_aq_desc iaq; 4761 struct ixl_aq_buf *aqb; 4762 uint64_t *caps; 4763 int error; 4764 4765 aqb = iavf_aqb_get(sc, &sc->sc_atq_idle); 4766 4767 if (aqb == NULL) 4768 return -1; 4769 4770 caps = IXL_AQB_KVA(aqb); 4771 if (sc->sc_mac_type == I40E_MAC_X722_VF) 4772 *caps = IXL_RSS_HENA_DEFAULT_X722; 4773 else 4774 *caps = IXL_RSS_HENA_DEFAULT_XL710; 4775 4776 memset(&iaq, 0, sizeof(iaq)); 4777 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD); 4778 iaq.iaq_opcode = htole16(IAVF_AQ_OP_SEND_TO_PF); 4779 iavf_aq_vc_set_opcode(&iaq, IAVF_VC_OP_SET_RSS_HENA); 4780 iaq.iaq_datalen = htole16(sizeof(*caps)); 4781 4782 error = iavf_adminq_exec(sc, &iaq, aqb); 4783 if (error != IAVF_VC_RC_SUCCESS) { 4784 return -1; 4785 } 4786 4787 return 0; 4788 } 4789 4790 static inline void 4791 iavf_get_default_rss_key(uint8_t *buf, size_t len) 4792 { 4793 uint8_t rss_seed[RSS_KEYSIZE]; 4794 size_t cplen; 4795 4796 cplen = MIN(len, sizeof(rss_seed)); 4797 rss_getkey(rss_seed); 4798 4799 memcpy(buf, rss_seed, cplen); 4800 if (cplen < len) 4801 memset(buf + cplen, 0, len - cplen); 4802 } 4803 4804 static int 4805 iavf_config_rss_key(struct iavf_softc *sc) 4806 { 4807 struct ixl_aq_desc iaq; 4808 struct ixl_aq_buf *aqb; 4809 struct iavf_vc_rss_key *rss_key; 4810 size_t key_len; 4811 int rv; 4812 4813 aqb = iavf_aqb_get(sc, &sc->sc_atq_idle); 4814 if (aqb == NULL) 4815 return -1; 4816 4817 rss_key = IXL_AQB_KVA(aqb); 4818 rss_key->vsi_id = htole16(sc->sc_vsi_id); 4819 key_len = IXL_RSS_KEY_SIZE; 4820 iavf_get_default_rss_key(rss_key->key, key_len); 4821 rss_key->key_len = key_len; 4822 4823 memset(&iaq, 0, sizeof(iaq)); 4824 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD); 4825 iaq.iaq_opcode = htole16(IAVF_AQ_OP_SEND_TO_PF); 4826 iavf_aq_vc_set_opcode(&iaq, IAVF_VC_OP_CONFIG_RSS_KEY); 4827 iaq.iaq_datalen = htole16(sizeof(*rss_key) - sizeof(rss_key->pad) 4828 + (sizeof(rss_key->key[0]) * key_len)); 4829 4830 rv = iavf_adminq_exec(sc, &iaq, aqb); 4831 if (rv != IAVF_VC_RC_SUCCESS) { 4832 return -1; 4833 } 4834 4835 return 0; 4836 } 4837 4838 static int 4839 iavf_config_rss_lut(struct iavf_softc *sc) 4840 { 4841 struct ixl_aq_desc iaq; 4842 struct ixl_aq_buf *aqb; 4843 struct iavf_vc_rss_lut *rss_lut; 4844 uint8_t *lut, v; 4845 int rv, i; 4846 4847 aqb = iavf_aqb_get(sc, &sc->sc_atq_idle); 4848 if (aqb == NULL) 4849 return -1; 4850 4851 rss_lut = IXL_AQB_KVA(aqb); 4852 rss_lut->vsi_id = htole16(sc->sc_vsi_id); 4853 rss_lut->lut_entries = htole16(IXL_RSS_VSI_LUT_SIZE); 4854 4855 lut = rss_lut->lut; 4856 for (i = 0; i < IXL_RSS_VSI_LUT_SIZE; i++) { 4857 v = i % sc->sc_nqueue_pairs; 4858 v &= IAVF_RSS_VSI_LUT_ENTRY_MASK; 4859 lut[i] = v; 4860 } 4861 4862 memset(&iaq, 0, sizeof(iaq)); 4863 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD); 4864 iaq.iaq_opcode = htole16(IAVF_AQ_OP_SEND_TO_PF); 4865 iavf_aq_vc_set_opcode(&iaq, IAVF_VC_OP_CONFIG_RSS_LUT); 4866 iaq.iaq_datalen = htole16(sizeof(*rss_lut) - sizeof(rss_lut->pad) 4867 + (sizeof(rss_lut->lut[0]) * IXL_RSS_VSI_LUT_SIZE)); 4868 4869 rv = iavf_adminq_exec(sc, &iaq, aqb); 4870 if (rv != IAVF_VC_RC_SUCCESS) { 4871 return -1; 4872 } 4873 4874 return 0; 4875 } 4876 4877 static int 4878 iavf_queue_select(struct iavf_softc *sc, int opcode) 4879 { 4880 struct ixl_aq_desc iaq; 4881 struct ixl_aq_buf *aqb; 4882 struct iavf_vc_queue_select *qsel; 4883 int error; 4884 4885 aqb = iavf_aqb_get(sc, &sc->sc_atq_idle); 4886 if (aqb == NULL) 4887 return -1; 4888 4889 qsel = IXL_AQB_KVA(aqb); 4890 qsel->vsi_id = htole16(sc->sc_vsi_id); 4891 qsel->rx_queues = htole32(iavf_allqueues(sc)); 4892 qsel->tx_queues = htole32(iavf_allqueues(sc)); 4893 4894 memset(&iaq, 0, sizeof(iaq)); 4895 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD); 4896 iaq.iaq_opcode = htole16(IAVF_AQ_OP_SEND_TO_PF); 4897 iavf_aq_vc_set_opcode(&iaq, opcode); 4898 iaq.iaq_datalen = htole16(sizeof(*qsel)); 4899 4900 error = iavf_adminq_exec(sc, &iaq, aqb); 4901 if (error != IAVF_VC_RC_SUCCESS) { 4902 return -1; 4903 } 4904 4905 return 0; 4906 } 4907 4908 static int 4909 iavf_request_queues(struct iavf_softc *sc, unsigned int req_num) 4910 { 4911 struct ixl_aq_desc iaq; 4912 struct ixl_aq_buf *aqb; 4913 struct iavf_vc_res_request *req; 4914 int rv; 4915 4916 aqb = iavf_aqb_get(sc, &sc->sc_atq_idle); 4917 if (aqb == NULL) 4918 return ENOMEM; 4919 4920 req = IXL_AQB_KVA(aqb); 4921 req->num_queue_pairs = req_num; 4922 4923 memset(&iaq, 0, sizeof(iaq)); 4924 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD); 4925 iaq.iaq_opcode = htole16(IAVF_AQ_OP_SEND_TO_PF); 4926 iavf_aq_vc_set_opcode(&iaq, IAVF_VC_OP_REQUEST_QUEUES); 4927 iaq.iaq_datalen = htole16(sizeof(*req)); 4928 4929 mutex_enter(&sc->sc_adminq_lock); 4930 rv = iavf_atq_post(sc, &iaq, aqb); 4931 mutex_exit(&sc->sc_adminq_lock); 4932 4933 return rv; 4934 } 4935 4936 static int 4937 iavf_reset_vf(struct iavf_softc *sc) 4938 { 4939 struct ixl_aq_desc iaq; 4940 int error; 4941 4942 memset(&iaq, 0, sizeof(iaq)); 4943 iaq.iaq_flags = htole16(IXL_AQ_RD); 4944 iaq.iaq_opcode = htole16(IAVF_AQ_OP_SEND_TO_PF); 4945 iavf_aq_vc_set_opcode(&iaq, IAVF_VC_OP_RESET_VF); 4946 iaq.iaq_datalen = htole16(0); 4947 4948 iavf_wr(sc, I40E_VFGEN_RSTAT, IAVF_VFR_INPROGRESS); 4949 4950 mutex_enter(&sc->sc_adminq_lock); 4951 error = iavf_atq_post(sc, &iaq, NULL); 4952 mutex_exit(&sc->sc_adminq_lock); 4953 4954 return error; 4955 } 4956 4957 static int 4958 iavf_eth_addr(struct iavf_softc *sc, const uint8_t *addr, uint32_t opcode) 4959 { 4960 struct ixl_aq_desc iaq; 4961 struct ixl_aq_buf *aqb; 4962 struct iavf_vc_eth_addr_list *addrs; 4963 struct iavf_vc_eth_addr *vcaddr; 4964 int rv; 4965 4966 KASSERT(sc->sc_attached); 4967 KASSERT(opcode == IAVF_VC_OP_ADD_ETH_ADDR || 4968 opcode == IAVF_VC_OP_DEL_ETH_ADDR); 4969 4970 aqb = iavf_aqb_get(sc, &sc->sc_atq_idle); 4971 if (aqb == NULL) 4972 return -1; 4973 4974 addrs = IXL_AQB_KVA(aqb); 4975 addrs->vsi_id = htole16(sc->sc_vsi_id); 4976 addrs->num_elements = htole16(1); 4977 vcaddr = addrs->list; 4978 memcpy(vcaddr->addr, addr, ETHER_ADDR_LEN); 4979 4980 memset(&iaq, 0, sizeof(iaq)); 4981 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD); 4982 iaq.iaq_opcode = htole16(IAVF_AQ_OP_SEND_TO_PF); 4983 iavf_aq_vc_set_opcode(&iaq, opcode); 4984 iaq.iaq_datalen = htole16(sizeof(*addrs) + sizeof(*vcaddr)); 4985 4986 if (sc->sc_resetting) { 4987 mutex_enter(&sc->sc_adminq_lock); 4988 rv = iavf_adminq_poll_locked(sc, &iaq, aqb, 250); 4989 iavf_aqb_put_locked(&sc->sc_atq_idle, aqb); 4990 mutex_exit(&sc->sc_adminq_lock); 4991 } else { 4992 rv = iavf_adminq_exec(sc, &iaq, aqb); 4993 } 4994 4995 if (rv != IAVF_VC_RC_SUCCESS) { 4996 return -1; 4997 } 4998 4999 return 0; 5000 } 5001 5002 static int 5003 iavf_config_promisc_mode(struct iavf_softc *sc, int unicast, int multicast) 5004 { 5005 struct ixl_aq_desc iaq; 5006 struct ixl_aq_buf *aqb; 5007 struct iavf_vc_promisc_info *promisc; 5008 int flags; 5009 5010 KASSERT(sc->sc_attached); 5011 5012 aqb = iavf_aqb_get(sc, &sc->sc_atq_idle); 5013 if (aqb == NULL) 5014 return -1; 5015 5016 flags = 0; 5017 if (unicast) 5018 flags |= IAVF_FLAG_VF_UNICAST_PROMISC; 5019 if (multicast) 5020 flags |= IAVF_FLAG_VF_MULTICAST_PROMISC; 5021 5022 promisc = IXL_AQB_KVA(aqb); 5023 promisc->vsi_id = htole16(sc->sc_vsi_id); 5024 promisc->flags = htole16(flags); 5025 5026 memset(&iaq, 0, sizeof(iaq)); 5027 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD); 5028 iaq.iaq_opcode = htole16(IAVF_AQ_OP_SEND_TO_PF); 5029 iavf_aq_vc_set_opcode(&iaq, IAVF_VC_OP_CONFIG_PROMISC); 5030 iaq.iaq_datalen = htole16(sizeof(*promisc)); 5031 5032 if (iavf_adminq_exec(sc, &iaq, aqb) != IAVF_VC_RC_SUCCESS) { 5033 return -1; 5034 } 5035 5036 return 0; 5037 } 5038 5039 static int 5040 iavf_config_vlan_stripping(struct iavf_softc *sc, int eccap) 5041 { 5042 struct ixl_aq_desc iaq; 5043 uint32_t opcode; 5044 5045 opcode = ISSET(eccap, ETHERCAP_VLAN_HWTAGGING) ? 5046 IAVF_VC_OP_ENABLE_VLAN_STRIP : IAVF_VC_OP_DISABLE_VLAN_STRIP; 5047 5048 memset(&iaq, 0, sizeof(iaq)); 5049 iaq.iaq_flags = htole16(IXL_AQ_RD); 5050 iaq.iaq_opcode = htole16(IAVF_AQ_OP_SEND_TO_PF); 5051 iavf_aq_vc_set_opcode(&iaq, opcode); 5052 iaq.iaq_datalen = htole16(0); 5053 5054 if (iavf_adminq_exec(sc, &iaq, NULL) != IAVF_VC_RC_SUCCESS) { 5055 return -1; 5056 } 5057 5058 return 0; 5059 } 5060 5061 static int 5062 iavf_config_vlan_id(struct iavf_softc *sc, uint16_t vid, uint32_t opcode) 5063 { 5064 struct ixl_aq_desc iaq; 5065 struct ixl_aq_buf *aqb; 5066 struct iavf_vc_vlan_filter *vfilter; 5067 int rv; 5068 5069 KASSERT(opcode == IAVF_VC_OP_ADD_VLAN || opcode == IAVF_VC_OP_DEL_VLAN); 5070 5071 aqb = iavf_aqb_get(sc, &sc->sc_atq_idle); 5072 5073 if (aqb == NULL) 5074 return -1; 5075 5076 vfilter = IXL_AQB_KVA(aqb); 5077 vfilter->vsi_id = htole16(sc->sc_vsi_id); 5078 vfilter->num_vlan_id = htole16(1); 5079 vfilter->vlan_id[0] = vid; 5080 5081 memset(&iaq, 0, sizeof(iaq)); 5082 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD); 5083 iaq.iaq_opcode = htole16(IAVF_AQ_OP_SEND_TO_PF); 5084 iavf_aq_vc_set_opcode(&iaq, opcode); 5085 iaq.iaq_datalen = htole16(sizeof(*vfilter) + sizeof(vid)); 5086 5087 if (sc->sc_resetting) { 5088 mutex_enter(&sc->sc_adminq_lock); 5089 rv = iavf_adminq_poll_locked(sc, &iaq, aqb, 250); 5090 iavf_aqb_put_locked(&sc->sc_atq_idle, aqb); 5091 mutex_exit(&sc->sc_adminq_lock); 5092 } else { 5093 rv = iavf_adminq_exec(sc, &iaq, aqb); 5094 } 5095 5096 if (rv != IAVF_VC_RC_SUCCESS) { 5097 return -1; 5098 } 5099 5100 return 0; 5101 } 5102 5103 static void 5104 iavf_post_request_queues(void *xsc) 5105 { 5106 struct iavf_softc *sc; 5107 struct ifnet *ifp; 5108 5109 sc = xsc; 5110 ifp = &sc->sc_ec.ec_if; 5111 5112 if (!ISSET(sc->sc_vf_cap, IAVF_VC_OFFLOAD_REQ_QUEUES)) { 5113 log(LOG_DEBUG, "%s: the VF has no REQ_QUEUES capability\n", 5114 ifp->if_xname); 5115 return; 5116 } 5117 5118 log(LOG_INFO, "%s: try to change the number of queue pairs" 5119 " (vsi %u, %u allocated, request %u)\n", 5120 ifp->if_xname, 5121 sc->sc_nqps_vsi, sc->sc_nqps_alloc, sc->sc_nqps_req); 5122 iavf_request_queues(sc, sc->sc_nqps_req); 5123 } 5124 5125 static bool 5126 iavf_sysctlnode_is_rx(struct sysctlnode *node) 5127 { 5128 5129 if (strstr(node->sysctl_parent->sysctl_name, "rx") != NULL) 5130 return true; 5131 5132 return false; 5133 } 5134 5135 static int 5136 iavf_sysctl_itr_handler(SYSCTLFN_ARGS) 5137 { 5138 struct sysctlnode node = *rnode; 5139 struct iavf_softc *sc = (struct iavf_softc *)node.sysctl_data; 5140 uint32_t newitr, *itrptr; 5141 unsigned int i; 5142 int itr, error; 5143 5144 if (iavf_sysctlnode_is_rx(&node)) { 5145 itrptr = &sc->sc_rx_itr; 5146 itr = IAVF_ITR_RX; 5147 } else { 5148 itrptr = &sc->sc_tx_itr; 5149 itr = IAVF_ITR_TX; 5150 } 5151 5152 newitr = *itrptr; 5153 node.sysctl_data = &newitr; 5154 node.sysctl_size = sizeof(newitr); 5155 5156 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 5157 if (error || newp == NULL) 5158 return error; 5159 5160 if (newitr > 0x07FF) 5161 return EINVAL; 5162 5163 *itrptr = newitr; 5164 5165 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 5166 iavf_wr(sc, I40E_VFINT_ITRN1(itr, i), *itrptr); 5167 } 5168 iavf_wr(sc, I40E_VFINT_ITR01(itr), *itrptr); 5169 5170 return 0; 5171 } 5172 5173 static void 5174 iavf_workq_work(struct work *wk, void *context) 5175 { 5176 struct iavf_work *work; 5177 5178 work = container_of(wk, struct iavf_work, ixw_cookie); 5179 5180 atomic_swap_uint(&work->ixw_added, 0); 5181 work->ixw_func(work->ixw_arg); 5182 } 5183 5184 static struct workqueue * 5185 iavf_workq_create(const char *name, pri_t prio, int ipl, int flags) 5186 { 5187 struct workqueue *wq; 5188 int error; 5189 5190 error = workqueue_create(&wq, name, iavf_workq_work, NULL, 5191 prio, ipl, flags); 5192 5193 if (error) 5194 return NULL; 5195 5196 return wq; 5197 } 5198 5199 static void 5200 iavf_workq_destroy(struct workqueue *wq) 5201 { 5202 5203 workqueue_destroy(wq); 5204 } 5205 5206 static int 5207 iavf_work_set(struct iavf_work *work, void (*func)(void *), void *arg) 5208 { 5209 5210 if (work->ixw_added != 0) 5211 return -1; 5212 5213 memset(work, 0, sizeof(*work)); 5214 work->ixw_func = func; 5215 work->ixw_arg = arg; 5216 5217 return 0; 5218 } 5219 5220 static void 5221 iavf_work_add(struct workqueue *wq, struct iavf_work *work) 5222 { 5223 if (atomic_cas_uint(&work->ixw_added, 0, 1) != 0) 5224 return; 5225 5226 kpreempt_disable(); 5227 workqueue_enqueue(wq, &work->ixw_cookie, NULL); 5228 kpreempt_enable(); 5229 } 5230 5231 static void 5232 iavf_work_wait(struct workqueue *wq, struct iavf_work *work) 5233 { 5234 5235 workqueue_wait(wq, &work->ixw_cookie); 5236 } 5237 5238 static void 5239 iavf_evcnt_attach(struct evcnt *ec, 5240 const char *n0, const char *n1) 5241 { 5242 5243 evcnt_attach_dynamic(ec, EVCNT_TYPE_MISC, 5244 NULL, n0, n1); 5245 } 5246 5247 MODULE(MODULE_CLASS_DRIVER, if_iavf, "pci"); 5248 5249 #ifdef _MODULE 5250 #include "ioconf.c" 5251 #endif 5252 5253 #ifdef _MODULE 5254 static void 5255 iavf_parse_modprop(prop_dictionary_t dict) 5256 { 5257 prop_object_t obj; 5258 int64_t val; 5259 uint32_t n; 5260 5261 if (dict == NULL) 5262 return; 5263 5264 obj = prop_dictionary_get(dict, "debug_level"); 5265 if (obj != NULL && prop_object_type(obj) == PROP_TYPE_NUMBER) { 5266 val = prop_number_signed_value((prop_number_t)obj); 5267 5268 if (val > 0) { 5269 iavf_params.debug = val; 5270 printf("iavf: debug level=%d\n", iavf_params.debug); 5271 } 5272 } 5273 5274 obj = prop_dictionary_get(dict, "max_qps"); 5275 if (obj != NULL && prop_object_type(obj) == PROP_TYPE_NUMBER) { 5276 val = prop_number_signed_value((prop_number_t)obj); 5277 5278 if (val < 1 || val > I40E_MAX_VF_QUEUES) { 5279 printf("iavf: invalid queue size(1 <= n <= %d)", 5280 I40E_MAX_VF_QUEUES); 5281 } else { 5282 iavf_params.max_qps = val; 5283 printf("iavf: request queue pair = %u\n", 5284 iavf_params.max_qps); 5285 } 5286 } 5287 5288 obj = prop_dictionary_get(dict, "tx_itr"); 5289 if (obj != NULL && prop_object_type(obj) == PROP_TYPE_NUMBER) { 5290 val = prop_number_signed_value((prop_number_t)obj); 5291 if (val > 0x07FF) { 5292 printf("iavf: TX ITR too big (%" PRId64 " <= %d)", 5293 val, 0x7FF); 5294 } else { 5295 iavf_params.tx_itr = val; 5296 printf("iavf: TX ITR = 0x%" PRIx32, 5297 iavf_params.tx_itr); 5298 } 5299 } 5300 5301 obj = prop_dictionary_get(dict, "rx_itr"); 5302 if (obj != NULL && prop_object_type(obj) == PROP_TYPE_NUMBER) { 5303 val = prop_number_signed_value((prop_number_t)obj); 5304 if (val > 0x07FF) { 5305 printf("iavf: RX ITR too big (%" PRId64 " <= %d)", 5306 val, 0x7FF); 5307 } else { 5308 iavf_params.rx_itr = val; 5309 printf("iavf: RX ITR = 0x%" PRIx32, 5310 iavf_params.rx_itr); 5311 } 5312 } 5313 5314 obj = prop_dictionary_get(dict, "tx_ndescs"); 5315 if (obj != NULL && prop_object_type(obj) == PROP_TYPE_NUMBER) { 5316 val = prop_number_signed_value((prop_number_t)obj); 5317 n = 1U << (fls32(val) - 1); 5318 if (val != (int64_t) n) { 5319 printf("iavf: TX desc invalid size" 5320 "(%" PRId64 " != %" PRIu32 ")\n", val, n); 5321 } else if (val > (8192 - 32)) { 5322 printf("iavf: Tx desc too big (%" PRId64 " > %d)", 5323 val, (8192 - 32)); 5324 } else { 5325 iavf_params.tx_ndescs = val; 5326 printf("iavf: TX descriptors = 0x%04x", 5327 iavf_params.tx_ndescs); 5328 } 5329 } 5330 5331 obj = prop_dictionary_get(dict, "rx_ndescs"); 5332 if (obj != NULL && prop_object_type(obj) == PROP_TYPE_NUMBER) { 5333 val = prop_number_signed_value((prop_number_t)obj); 5334 n = 1U << (fls32(val) - 1); 5335 if (val != (int64_t) n) { 5336 printf("iavf: RX desc invalid size" 5337 "(%" PRId64 " != %" PRIu32 ")\n", val, n); 5338 } else if (val > (8192 - 32)) { 5339 printf("iavf: Rx desc too big (%" PRId64 " > %d)", 5340 val, (8192 - 32)); 5341 } else { 5342 iavf_params.rx_ndescs = val; 5343 printf("iavf: RX descriptors = 0x%04x", 5344 iavf_params.rx_ndescs); 5345 } 5346 } 5347 } 5348 #endif 5349 5350 static int 5351 if_iavf_modcmd(modcmd_t cmd, void *opaque) 5352 { 5353 int error = 0; 5354 5355 #ifdef _MODULE 5356 switch (cmd) { 5357 case MODULE_CMD_INIT: 5358 iavf_parse_modprop((prop_dictionary_t)opaque); 5359 error = config_init_component(cfdriver_ioconf_if_iavf, 5360 cfattach_ioconf_if_iavf, cfdata_ioconf_if_iavf); 5361 break; 5362 case MODULE_CMD_FINI: 5363 error = config_fini_component(cfdriver_ioconf_if_iavf, 5364 cfattach_ioconf_if_iavf, cfdata_ioconf_if_iavf); 5365 break; 5366 default: 5367 error = ENOTTY; 5368 break; 5369 } 5370 #endif 5371 5372 return error; 5373 } 5374
Indexes created Tue Sep 30 17:09:57 GMT 2025