if_iavf.c revision 1.4
1 /* $NetBSD: if_iavf.c,v 1.4 2020/09/09 00:56:17 yamaguchi Exp $ */ 2 3 /* 4 * Copyright (c) 2013-2015, Intel Corporation 5 * All rights reserved. 6 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * 3. Neither the name of the Intel Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived from 19 * this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Copyright (c) 2016,2017 David Gwynne <dlg (at) openbsd.org> 36 * Copyright (c) 2019 Jonathan Matthew <jmatthew (at) openbsd.org> 37 * 38 * Permission to use, copy, modify, and distribute this software for any 39 * purpose with or without fee is hereby granted, provided that the above 40 * copyright notice and this permission notice appear in all copies. 41 * 42 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 43 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 44 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 45 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 46 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 47 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 48 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 49 */ 50 51 /* 52 * Copyright (c) 2020 Internet Initiative Japan, Inc. 53 * All rights reserved. 54 * 55 * Redistribution and use in source and binary forms, with or without 56 * modification, are permitted provided that the following conditions 57 * are met: 58 * 1. Redistributions of source code must retain the above copyright 59 * notice, this list of conditions and the following disclaimer. 60 * 2. Redistributions in binary form must reproduce the above copyright 61 * notice, this list of conditions and the following disclaimer in the 62 * documentation and/or other materials provided with the distribution. 63 * 64 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 65 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 66 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 67 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 68 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 69 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 70 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 71 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 72 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 73 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 74 * POSSIBILITY OF SUCH DAMAGE. 75 */ 76 77 #include <sys/cdefs.h> 78 __KERNEL_RCSID(0, "$NetBSD: if_iavf.c,v 1.4 2020/09/09 00:56:17 yamaguchi Exp $"); 79 80 #include <sys/param.h> 81 #include <sys/types.h> 82 83 #include <sys/bitops.h> 84 #include <sys/bus.h> 85 #include <sys/cprng.h> 86 #include <sys/cpu.h> 87 #include <sys/device.h> 88 #include <sys/evcnt.h> 89 #include <sys/interrupt.h> 90 #include <sys/kmem.h> 91 #include <sys/module.h> 92 #include <sys/mutex.h> 93 #include <sys/pcq.h> 94 #include <sys/queue.h> 95 #include <sys/syslog.h> 96 #include <sys/workqueue.h> 97 98 #include <net/bpf.h> 99 #include <net/if.h> 100 #include <net/if_dl.h> 101 #include <net/if_media.h> 102 #include <net/if_ether.h> 103 #include <net/rss_config.h> 104 105 #include <netinet/tcp.h> /* for struct tcphdr */ 106 #include <netinet/udp.h> /* for struct udphdr */ 107 108 #include <dev/pci/pcivar.h> 109 #include <dev/pci/pcidevs.h> 110 111 #include <dev/pci/if_ixlreg.h> 112 #include <dev/pci/if_ixlvar.h> 113 #include <dev/pci/if_iavfvar.h> 114 115 #include <prop/proplib.h> 116 117 #define IAVF_PCIREG PCI_MAPREG_START 118 #define IAVF_AQ_NUM 256 119 #define IAVF_AQ_MASK (IAVF_AQ_NUM-1) 120 #define IAVF_AQ_ALIGN 64 121 #define IAVF_AQ_BUFLEN 4096 122 #define I40E_AQ_LARGE_BUF 512 123 #define IAVF_VF_MAJOR 1 124 #define IAVF_VF_MINOR 1 125 126 #define IAVF_VFR_INPROGRESS 0 127 #define IAVF_VFR_COMPLETED 1 128 #define IAVF_VFR_VFACTIVE 2 129 130 #define IAVF_REG_VFR 0xdeadbeef 131 132 #define IAVF_ITR_RX 0x0 133 #define IAVF_ITR_TX 0x1 134 #define IAVF_ITR_MISC 0x2 135 #define IAVF_NOITR 0x3 136 137 #define IAVF_MTU_ETHERLEN (ETHER_HDR_LEN \ 138 + ETHER_CRC_LEN) 139 #define IAVF_MAX_MTU (9600 - IAVF_MTU_ETHERLEN) 140 #define IAVF_MIN_MTU (ETHER_MIN_LEN - ETHER_CRC_LEN) 141 142 #define IAVF_WORKQUEUE_PRI PRI_SOFTNET 143 144 #define IAVF_TX_PKT_DESCS 8 145 #define IAVF_TX_QUEUE_ALIGN 128 146 #define IAVF_RX_QUEUE_ALIGN 128 147 #define IAVF_TX_PKT_MAXSIZE (MCLBYTES * IAVF_TX_PKT_DESCS) 148 #define IAVF_MCLBYTES (MCLBYTES - ETHER_ALIGN) 149 150 #define IAVF_TICK_INTERVAL (5 * hz) 151 #define IAVF_WATCHDOG_TICKS 3 152 #define IAVF_WATCHDOG_STOP 0 153 154 #define IAVF_TXRX_PROCESS_UNLIMIT UINT_MAX 155 #define IAVF_TX_PROCESS_LIMIT 256 156 #define IAVF_RX_PROCESS_LIMIT 256 157 #define IAVF_TX_INTR_PROCESS_LIMIT 256 158 #define IAVF_RX_INTR_PROCESS_LIMIT 0U 159 160 #define IAVF_EXEC_TIMEOUT 3000 161 162 #define IAVF_IFCAP_RXCSUM (IFCAP_CSUM_IPv4_Rx | \ 163 IFCAP_CSUM_TCPv4_Rx | \ 164 IFCAP_CSUM_UDPv4_Rx | \ 165 IFCAP_CSUM_TCPv6_Rx | \ 166 IFCAP_CSUM_UDPv6_Rx) 167 #define IAVF_IFCAP_TXCSUM (IFCAP_CSUM_IPv4_Tx | \ 168 IFCAP_CSUM_TCPv4_Tx | \ 169 IFCAP_CSUM_UDPv4_Tx | \ 170 IFCAP_CSUM_TCPv6_Tx | \ 171 IFCAP_CSUM_UDPv6_Tx) 172 #define IAVF_CSUM_ALL_OFFLOAD (M_CSUM_IPv4 | \ 173 M_CSUM_TCPv4 | M_CSUM_TCPv6 | \ 174 M_CSUM_UDPv4 | M_CSUM_UDPv6) 175 176 struct iavf_softc; /* defined */ 177 178 struct iavf_module_params { 179 int debug; 180 uint32_t rx_itr; 181 uint32_t tx_itr; 182 unsigned int rx_ndescs; 183 unsigned int tx_ndescs; 184 int max_qps; 185 }; 186 187 struct iavf_product { 188 unsigned int vendor_id; 189 unsigned int product_id; 190 }; 191 192 struct iavf_link_speed { 193 uint64_t baudrate; 194 uint64_t media; 195 }; 196 197 struct iavf_aq_regs { 198 bus_size_t atq_tail; 199 bus_size_t atq_head; 200 bus_size_t atq_len; 201 bus_size_t atq_bal; 202 bus_size_t atq_bah; 203 204 bus_size_t arq_tail; 205 bus_size_t arq_head; 206 bus_size_t arq_len; 207 bus_size_t arq_bal; 208 bus_size_t arq_bah; 209 210 uint32_t atq_len_enable; 211 uint32_t atq_tail_mask; 212 uint32_t atq_head_mask; 213 214 uint32_t arq_len_enable; 215 uint32_t arq_tail_mask; 216 uint32_t arq_head_mask; 217 }; 218 219 struct iavf_work { 220 struct work ixw_cookie; 221 void (*ixw_func)(void *); 222 void *ixw_arg; 223 unsigned int ixw_added; 224 }; 225 226 struct iavf_tx_map { 227 struct mbuf *txm_m; 228 bus_dmamap_t txm_map; 229 unsigned int txm_eop; 230 }; 231 232 struct iavf_tx_ring { 233 unsigned int txr_qid; 234 char txr_name[16]; 235 236 struct iavf_softc *txr_sc; 237 kmutex_t txr_lock; 238 pcq_t *txr_intrq; 239 void *txr_si; 240 unsigned int txr_prod; 241 unsigned int txr_cons; 242 243 struct iavf_tx_map *txr_maps; 244 struct ixl_dmamem txr_mem; 245 bus_size_t txr_tail; 246 247 int txr_watchdog; 248 249 struct evcnt txr_defragged; 250 struct evcnt txr_defrag_failed; 251 struct evcnt txr_pcqdrop; 252 struct evcnt txr_transmitdef; 253 struct evcnt txr_defer; 254 struct evcnt txr_watchdogto; 255 struct evcnt txr_intr; 256 }; 257 258 struct iavf_rx_map { 259 struct mbuf *rxm_m; 260 bus_dmamap_t rxm_map; 261 }; 262 263 struct iavf_rx_ring { 264 unsigned int rxr_qid; 265 char rxr_name[16]; 266 267 struct iavf_softc *rxr_sc; 268 kmutex_t rxr_lock; 269 270 unsigned int rxr_prod; 271 unsigned int rxr_cons; 272 273 struct iavf_rx_map *rxr_maps; 274 struct ixl_dmamem rxr_mem; 275 bus_size_t rxr_tail; 276 277 struct mbuf *rxr_m_head; 278 struct mbuf **rxr_m_tail; 279 280 struct evcnt rxr_mgethdr_failed; 281 struct evcnt rxr_mgetcl_failed; 282 struct evcnt rxr_mbuf_load_failed; 283 struct evcnt rxr_defer; 284 struct evcnt rxr_intr; 285 }; 286 287 struct iavf_queue_pair { 288 struct iavf_tx_ring *qp_txr; 289 struct iavf_rx_ring *qp_rxr; 290 struct work qp_work; 291 void *qp_si; 292 bool qp_workqueue; 293 }; 294 295 struct iavf_stat_counters { 296 struct evcnt isc_rx_bytes; 297 struct evcnt isc_rx_unicast; 298 struct evcnt isc_rx_multicast; 299 struct evcnt isc_rx_broadcast; 300 struct evcnt isc_rx_discards; 301 struct evcnt isc_rx_unknown_protocol; 302 struct evcnt isc_tx_bytes; 303 struct evcnt isc_tx_unicast; 304 struct evcnt isc_tx_multicast; 305 struct evcnt isc_tx_broadcast; 306 struct evcnt isc_tx_discards; 307 struct evcnt isc_tx_errors; 308 }; 309 310 /* 311 * Locking notes: 312 * + A field in iavf_tx_ring is protected by txr_lock (a spin mutex), and 313 * A field in iavf_rx_ring is protected by rxr_lock (a spin mutex). 314 * - more than one lock must not be held at once. 315 * + fields named sc_atq_*, sc_arq_*, and sc_adminq_* are protected by 316 * sc_adminq_lock(a spin mutex). 317 * - The lock is held while accessing sc_aq_regs 318 * and is not held with txr_lock and rxr_lock together. 319 * + Other fields in iavf_softc is protected by sc_cfg_lock 320 * (an adaptive mutex). 321 * - The lock must be held before acquiring another lock. 322 * 323 * Locking order: 324 * - IFNET_LOCK => sc_cfg_lock => sc_adminq_lock 325 * - sc_cfg_lock => ETHER_LOCK => sc_adminq_lock 326 * - sc_cfg_lock => txr_lock 327 * - sc_cfg_lock => rxr_lock 328 */ 329 330 struct iavf_softc { 331 device_t sc_dev; 332 enum i40e_mac_type sc_mac_type; 333 int sc_debuglevel; 334 bool sc_attached; 335 bool sc_dead; 336 kmutex_t sc_cfg_lock; 337 callout_t sc_tick; 338 struct ifmedia sc_media; 339 uint64_t sc_media_status; 340 uint64_t sc_media_active; 341 int sc_link_state; 342 343 const struct iavf_aq_regs * 344 sc_aq_regs; 345 346 struct ethercom sc_ec; 347 uint8_t sc_enaddr[ETHER_ADDR_LEN]; 348 uint8_t sc_enaddr_fake[ETHER_ADDR_LEN]; 349 uint8_t sc_enaddr_added[ETHER_ADDR_LEN]; 350 uint8_t sc_enaddr_reset[ETHER_ADDR_LEN]; 351 struct if_percpuq *sc_ipq; 352 353 struct pci_attach_args sc_pa; 354 bus_dma_tag_t sc_dmat; 355 bus_space_tag_t sc_memt; 356 bus_space_handle_t sc_memh; 357 bus_size_t sc_mems; 358 pci_intr_handle_t *sc_ihp; 359 void **sc_ihs; 360 unsigned int sc_nintrs; 361 362 uint32_t sc_major_ver; 363 uint32_t sc_minor_ver; 364 uint32_t sc_vf_id; 365 uint32_t sc_vf_cap; 366 uint16_t sc_vsi_id; 367 uint16_t sc_qset_handle; 368 uint16_t sc_max_mtu; 369 bool sc_got_vf_resources; 370 bool sc_got_irq_map; 371 unsigned int sc_max_vectors; 372 373 kmutex_t sc_adminq_lock; 374 kcondvar_t sc_adminq_cv; 375 struct ixl_dmamem sc_atq; 376 unsigned int sc_atq_prod; 377 unsigned int sc_atq_cons; 378 struct ixl_aq_bufs sc_atq_idle; 379 struct ixl_aq_bufs sc_atq_live; 380 struct ixl_dmamem sc_arq; 381 struct ixl_aq_bufs sc_arq_idle; 382 struct ixl_aq_bufs sc_arq_live; 383 unsigned int sc_arq_prod; 384 unsigned int sc_arq_cons; 385 struct iavf_work sc_arq_refill; 386 uint32_t sc_arq_opcode; 387 uint32_t sc_arq_retval; 388 389 uint32_t sc_tx_itr; 390 uint32_t sc_rx_itr; 391 unsigned int sc_tx_ring_ndescs; 392 unsigned int sc_rx_ring_ndescs; 393 unsigned int sc_nqueue_pairs; 394 unsigned int sc_nqps_alloc; 395 unsigned int sc_nqps_vsi; 396 unsigned int sc_nqps_req; 397 struct iavf_queue_pair *sc_qps; 398 bool sc_txrx_workqueue; 399 u_int sc_tx_intr_process_limit; 400 u_int sc_tx_process_limit; 401 u_int sc_rx_intr_process_limit; 402 u_int sc_rx_process_limit; 403 404 struct workqueue *sc_workq; 405 struct workqueue *sc_workq_txrx; 406 struct iavf_work sc_reset_task; 407 struct iavf_work sc_wdto_task; 408 struct iavf_work sc_req_queues_task; 409 bool sc_req_queues_retried; 410 bool sc_resetting; 411 bool sc_reset_up; 412 413 struct sysctllog *sc_sysctllog; 414 struct iavf_stat_counters 415 sc_stat_counters; 416 }; 417 418 #define IAVF_LOG(_sc, _lvl, _fmt, _args...) \ 419 do { \ 420 if (!(_sc)->sc_attached) { \ 421 switch (_lvl) { \ 422 case LOG_ERR: \ 423 case LOG_WARNING: \ 424 aprint_error_dev((_sc)->sc_dev, _fmt, ##_args); \ 425 break; \ 426 case LOG_INFO: \ 427 aprint_normal_dev((_sc)->sc_dev,_fmt, ##_args); \ 428 break; \ 429 case LOG_DEBUG: \ 430 default: \ 431 aprint_debug_dev((_sc)->sc_dev, _fmt, ##_args); \ 432 } \ 433 } else { \ 434 struct ifnet *_ifp = &(_sc)->sc_ec.ec_if; \ 435 log((_lvl), "%s: " _fmt, _ifp->if_xname, ##_args); \ 436 } \ 437 } while (0) 438 439 static int iavf_dmamem_alloc(bus_dma_tag_t, struct ixl_dmamem *, 440 bus_size_t, bus_size_t); 441 static void iavf_dmamem_free(bus_dma_tag_t, struct ixl_dmamem *); 442 static struct ixl_aq_buf * 443 iavf_aqb_get(struct iavf_softc *, struct ixl_aq_bufs *); 444 static struct ixl_aq_buf * 445 iavf_aqb_get_locked(struct ixl_aq_bufs *); 446 static void iavf_aqb_put_locked(struct ixl_aq_bufs *, struct ixl_aq_buf *); 447 static void iavf_aqb_clean(struct ixl_aq_bufs *, bus_dma_tag_t); 448 449 static const struct iavf_product * 450 iavf_lookup(const struct pci_attach_args *); 451 static enum i40e_mac_type 452 iavf_mactype(pci_product_id_t); 453 static void iavf_pci_csr_setup(pci_chipset_tag_t, pcitag_t); 454 static int iavf_wait_active(struct iavf_softc *); 455 static bool iavf_is_etheranyaddr(const uint8_t *); 456 static void iavf_prepare_fakeaddr(struct iavf_softc *); 457 static int iavf_replace_lla(struct ifnet *, 458 const uint8_t *, const uint8_t *); 459 static void iavf_evcnt_attach(struct evcnt *, 460 const char *, const char *); 461 static int iavf_setup_interrupts(struct iavf_softc *); 462 static void iavf_teardown_interrupts(struct iavf_softc *); 463 static int iavf_setup_sysctls(struct iavf_softc *); 464 static void iavf_teardown_sysctls(struct iavf_softc *); 465 static int iavf_setup_stats(struct iavf_softc *); 466 static void iavf_teardown_stats(struct iavf_softc *); 467 static struct workqueue * 468 iavf_workq_create(const char *, pri_t, int, int); 469 static void iavf_workq_destroy(struct workqueue *); 470 static int iavf_work_set(struct iavf_work *, void (*)(void *), void *); 471 static void iavf_work_add(struct workqueue *, struct iavf_work *); 472 static void iavf_work_wait(struct workqueue *, struct iavf_work *); 473 static unsigned int 474 iavf_calc_msix_count(struct iavf_softc *); 475 static unsigned int 476 iavf_calc_queue_pair_size(struct iavf_softc *); 477 static int iavf_queue_pairs_alloc(struct iavf_softc *); 478 static void iavf_queue_pairs_free(struct iavf_softc *); 479 static int iavf_arq_fill(struct iavf_softc *); 480 static void iavf_arq_refill(void *); 481 static int iavf_arq_poll(struct iavf_softc *, uint32_t, int); 482 static void iavf_atq_done(struct iavf_softc *); 483 static int iavf_init_admin_queue(struct iavf_softc *); 484 static void iavf_cleanup_admin_queue(struct iavf_softc *); 485 static int iavf_arq(struct iavf_softc *); 486 static int iavf_adminq_exec(struct iavf_softc *, 487 struct ixl_aq_desc *, struct ixl_aq_buf *); 488 static int iavf_adminq_poll(struct iavf_softc *, 489 struct ixl_aq_desc *, struct ixl_aq_buf *, int); 490 static int iavf_adminq_poll_locked(struct iavf_softc *, 491 struct ixl_aq_desc *, struct ixl_aq_buf *, int); 492 static int iavf_add_multi(struct iavf_softc *, uint8_t *, uint8_t *); 493 static int iavf_del_multi(struct iavf_softc *, uint8_t *, uint8_t *); 494 static void iavf_del_all_multi(struct iavf_softc *); 495 496 static int iavf_get_version(struct iavf_softc *, struct ixl_aq_buf *); 497 static int iavf_get_vf_resources(struct iavf_softc *, struct ixl_aq_buf *); 498 static int iavf_get_stats(struct iavf_softc *); 499 static int iavf_config_irq_map(struct iavf_softc *, struct ixl_aq_buf *); 500 static int iavf_config_vsi_queues(struct iavf_softc *); 501 static int iavf_config_hena(struct iavf_softc *); 502 static int iavf_config_rss_key(struct iavf_softc *); 503 static int iavf_config_rss_lut(struct iavf_softc *); 504 static int iavf_config_promisc_mode(struct iavf_softc *, int, int); 505 static int iavf_config_vlan_stripping(struct iavf_softc *, int); 506 static int iavf_config_vlan_id(struct iavf_softc *, uint16_t, uint32_t); 507 static int iavf_queue_select(struct iavf_softc *, int); 508 static int iavf_request_queues(struct iavf_softc *, unsigned int); 509 static int iavf_reset_vf(struct iavf_softc *); 510 static int iavf_eth_addr(struct iavf_softc *, const uint8_t *, uint32_t); 511 static void iavf_process_version(struct iavf_softc *, 512 struct ixl_aq_desc *, struct ixl_aq_buf *); 513 static void iavf_process_vf_resources(struct iavf_softc *, 514 struct ixl_aq_desc *, struct ixl_aq_buf *); 515 static void iavf_process_irq_map(struct iavf_softc *, 516 struct ixl_aq_desc *); 517 static void iavf_process_vc_event(struct iavf_softc *, 518 struct ixl_aq_desc *, struct ixl_aq_buf *); 519 static void iavf_process_stats(struct iavf_softc *, 520 struct ixl_aq_desc *, struct ixl_aq_buf *); 521 static void iavf_process_req_queues(struct iavf_softc *, 522 struct ixl_aq_desc *, struct ixl_aq_buf *); 523 524 static int iavf_intr(void *); 525 static int iavf_queue_intr(void *); 526 static void iavf_tick(void *); 527 static void iavf_tick_halt(void *); 528 static void iavf_reset_request(void *); 529 static void iavf_reset_start(void *); 530 static void iavf_reset(void *); 531 static void iavf_reset_finish(struct iavf_softc *); 532 static int iavf_init(struct ifnet *); 533 static int iavf_init_locked(struct iavf_softc *); 534 static void iavf_stop(struct ifnet *, int); 535 static void iavf_stop_locked(struct iavf_softc *); 536 static int iavf_ioctl(struct ifnet *, u_long, void *); 537 static void iavf_start(struct ifnet *); 538 static int iavf_transmit(struct ifnet *, struct mbuf*); 539 static int iavf_watchdog(struct iavf_tx_ring *); 540 static void iavf_watchdog_timeout(void *); 541 static int iavf_media_change(struct ifnet *); 542 static void iavf_media_status(struct ifnet *, struct ifmediareq *); 543 static int iavf_ifflags_cb(struct ethercom *); 544 static int iavf_vlan_cb(struct ethercom *, uint16_t, bool); 545 static void iavf_deferred_transmit(void *); 546 static void iavf_handle_queue(void *); 547 static void iavf_handle_queue_wk(struct work *, void *); 548 static int iavf_reinit(struct iavf_softc *); 549 static int iavf_rxfill(struct iavf_softc *, struct iavf_rx_ring *); 550 static void iavf_txr_clean(struct iavf_softc *, struct iavf_tx_ring *); 551 static void iavf_rxr_clean(struct iavf_softc *, struct iavf_rx_ring *); 552 static int iavf_txeof(struct iavf_softc *, struct iavf_tx_ring *, 553 u_int, struct evcnt *); 554 static int iavf_rxeof(struct iavf_softc *, struct iavf_rx_ring *, 555 u_int, struct evcnt *); 556 static int iavf_iff(struct iavf_softc *); 557 static int iavf_iff_locked(struct iavf_softc *); 558 static void iavf_post_request_queues(void *); 559 static int iavf_sysctl_itr_handler(SYSCTLFN_PROTO); 560 561 static int iavf_match(device_t, cfdata_t, void *); 562 static void iavf_attach(device_t, device_t, void*); 563 static int iavf_detach(device_t, int); 564 static int iavf_finalize_teardown(device_t); 565 566 CFATTACH_DECL3_NEW(iavf, sizeof(struct iavf_softc), 567 iavf_match, iavf_attach, iavf_detach, NULL, NULL, NULL, 568 DVF_DETACH_SHUTDOWN); 569 570 static const struct iavf_product iavf_products[] = { 571 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XL710_VF }, 572 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XL710_VF_HV }, 573 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X722_VF }, 574 /* required last entry */ 575 {0, 0} 576 }; 577 578 static const struct iavf_link_speed iavf_link_speeds[] = { 579 { 0, 0 }, 580 { IF_Mbps(100), IFM_100_TX }, 581 { IF_Mbps(1000), IFM_1000_T }, 582 { IF_Gbps(10), IFM_10G_T }, 583 { IF_Gbps(40), IFM_40G_CR4 }, 584 { IF_Gbps(20), IFM_20G_KR2 }, 585 { IF_Gbps(25), IFM_25G_CR } 586 }; 587 588 static const struct iavf_aq_regs iavf_aq_regs = { 589 .atq_tail = I40E_VF_ATQT1, 590 .atq_tail_mask = I40E_VF_ATQT1_ATQT_MASK, 591 .atq_head = I40E_VF_ATQH1, 592 .atq_head_mask = I40E_VF_ARQH1_ARQH_MASK, 593 .atq_len = I40E_VF_ATQLEN1, 594 .atq_bal = I40E_VF_ATQBAL1, 595 .atq_bah = I40E_VF_ATQBAH1, 596 .atq_len_enable = I40E_VF_ATQLEN1_ATQENABLE_MASK, 597 598 .arq_tail = I40E_VF_ARQT1, 599 .arq_tail_mask = I40E_VF_ARQT1_ARQT_MASK, 600 .arq_head = I40E_VF_ARQH1, 601 .arq_head_mask = I40E_VF_ARQH1_ARQH_MASK, 602 .arq_len = I40E_VF_ARQLEN1, 603 .arq_bal = I40E_VF_ARQBAL1, 604 .arq_bah = I40E_VF_ARQBAH1, 605 .arq_len_enable = I40E_VF_ARQLEN1_ARQENABLE_MASK, 606 }; 607 608 static struct iavf_module_params iavf_params = { 609 .debug = 0, 610 .rx_itr = 0x07a, /* 4K intrs/sec */ 611 .tx_itr = 0x07a, /* 4K intrs/sec */ 612 .tx_ndescs = 512, 613 .rx_ndescs = 256, 614 .max_qps = INT_MAX, 615 }; 616 617 #define delaymsec(_x) DELAY(1000 * (_x)) 618 #define iavf_rd(_s, _r) \ 619 bus_space_read_4((_s)->sc_memt, (_s)->sc_memh, (_r)) 620 #define iavf_wr(_s, _r, _v) \ 621 bus_space_write_4((_s)->sc_memt, (_s)->sc_memh, (_r), (_v)) 622 #define iavf_barrier(_s, _r, _l, _o) \ 623 bus_space_barrier((_s)->sc_memt, (_s)->sc_memh, (_r), (_l), (_o)) 624 #define iavf_flush(_s) (void)iavf_rd((_s), I40E_VFGEN_RSTAT) 625 #define iavf_nqueues(_sc) (1 << ((_sc)->sc_nqueue_pairs - 1)) 626 #define iavf_allqueues(_sc) ((1 << ((_sc)->sc_nqueue_pairs)) - 1) 627 628 static inline void 629 iavf_intr_enable(struct iavf_softc *sc) 630 { 631 632 iavf_wr(sc, I40E_VFINT_DYN_CTL01, I40E_VFINT_DYN_CTL0_INTENA_MASK | 633 I40E_VFINT_DYN_CTL0_CLEARPBA_MASK | 634 (IAVF_NOITR << I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT)); 635 iavf_wr(sc, I40E_VFINT_ICR0_ENA1, I40E_VFINT_ICR0_ENA1_ADMINQ_MASK); 636 iavf_flush(sc); 637 } 638 639 static inline void 640 iavf_intr_disable(struct iavf_softc *sc) 641 { 642 643 iavf_wr(sc, I40E_VFINT_DYN_CTL01, 644 (IAVF_NOITR << I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT)); 645 iavf_wr(sc, I40E_VFINT_ICR0_ENA1, 0); 646 iavf_flush(sc); 647 } 648 649 static inline void 650 iavf_queue_intr_enable(struct iavf_softc *sc, unsigned int qid) 651 { 652 653 iavf_wr(sc, I40E_VFINT_DYN_CTLN1(qid), 654 I40E_VFINT_DYN_CTLN1_INTENA_MASK | 655 I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK | 656 (IAVF_NOITR << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT)); 657 iavf_flush(sc); 658 } 659 660 static inline void 661 iavf_queue_intr_disable(struct iavf_softc *sc, unsigned int qid) 662 { 663 664 iavf_wr(sc, I40E_VFINT_DYN_CTLN1(qid), 665 (IAVF_NOITR << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT)); 666 iavf_flush(sc); 667 } 668 669 static inline void 670 iavf_aq_vc_set_opcode(struct ixl_aq_desc *iaq, uint32_t opcode) 671 { 672 struct iavf_aq_vc *vc; 673 674 vc = (struct iavf_aq_vc *)&iaq->iaq_cookie; 675 vc->iaq_vc_opcode = htole32(opcode); 676 } 677 678 static inline uint32_t 679 iavf_aq_vc_get_opcode(const struct ixl_aq_desc *iaq) 680 { 681 const struct iavf_aq_vc *vc; 682 683 vc = (const struct iavf_aq_vc *)&iaq->iaq_cookie; 684 return le32toh(vc->iaq_vc_opcode); 685 } 686 687 static inline uint32_t 688 iavf_aq_vc_get_retval(const struct ixl_aq_desc *iaq) 689 { 690 const struct iavf_aq_vc *vc; 691 692 vc = (const struct iavf_aq_vc *)&iaq->iaq_cookie; 693 return le32toh(vc->iaq_vc_retval); 694 } 695 696 static int 697 iavf_match(device_t parent, cfdata_t match, void *aux) 698 { 699 const struct pci_attach_args *pa = aux; 700 701 return (iavf_lookup(pa) != NULL) ? 1 : 0; 702 } 703 704 static void 705 iavf_attach(device_t parent, device_t self, void *aux) 706 { 707 struct iavf_softc *sc; 708 struct pci_attach_args *pa = aux; 709 struct ifnet *ifp; 710 struct ixl_aq_buf *aqb; 711 pcireg_t memtype; 712 char xnamebuf[MAXCOMLEN]; 713 int error, i; 714 715 sc = device_private(self); 716 sc->sc_dev = self; 717 ifp = &sc->sc_ec.ec_if; 718 719 sc->sc_pa = *pa; 720 sc->sc_dmat = (pci_dma64_available(pa)) ? pa->pa_dmat64 : pa->pa_dmat; 721 sc->sc_aq_regs = &iavf_aq_regs; 722 sc->sc_debuglevel = iavf_params.debug; 723 sc->sc_tx_ring_ndescs = iavf_params.tx_ndescs; 724 sc->sc_rx_ring_ndescs = iavf_params.rx_ndescs; 725 sc->sc_tx_itr = iavf_params.tx_itr; 726 sc->sc_rx_itr = iavf_params.rx_itr; 727 sc->sc_nqps_req = MIN(ncpu, iavf_params.max_qps); 728 iavf_prepare_fakeaddr(sc); 729 730 sc->sc_mac_type = iavf_mactype(PCI_PRODUCT(pa->pa_id)); 731 iavf_pci_csr_setup(pa->pa_pc, pa->pa_tag); 732 733 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, IAVF_PCIREG); 734 if (pci_mapreg_map(pa, IAVF_PCIREG, memtype, 0, 735 &sc->sc_memt, &sc->sc_memh, NULL, &sc->sc_mems)) { 736 aprint_error(": unable to map registers\n"); 737 return; 738 } 739 740 if (iavf_wait_active(sc) != 0) { 741 aprint_error(": VF reset timed out\n"); 742 goto unmap; 743 } 744 745 mutex_init(&sc->sc_cfg_lock, MUTEX_DEFAULT, IPL_SOFTNET); 746 mutex_init(&sc->sc_adminq_lock, MUTEX_DEFAULT, IPL_NET); 747 SIMPLEQ_INIT(&sc->sc_atq_idle); 748 SIMPLEQ_INIT(&sc->sc_atq_live); 749 SIMPLEQ_INIT(&sc->sc_arq_idle); 750 SIMPLEQ_INIT(&sc->sc_arq_live); 751 sc->sc_arq_cons = 0; 752 sc->sc_arq_prod = 0; 753 aqb = NULL; 754 755 if (iavf_dmamem_alloc(sc->sc_dmat, &sc->sc_atq, 756 sizeof(struct ixl_aq_desc) * IAVF_AQ_NUM, IAVF_AQ_ALIGN) != 0) { 757 aprint_error(": unable to allocate atq\n"); 758 goto free_mutex; 759 } 760 761 if (iavf_dmamem_alloc(sc->sc_dmat, &sc->sc_arq, 762 sizeof(struct ixl_aq_desc) * IAVF_AQ_NUM, IAVF_AQ_ALIGN) != 0) { 763 aprint_error(": unable to allocate arq\n"); 764 goto free_atq; 765 } 766 767 for (i = 0; i < IAVF_AQ_NUM; i++) { 768 aqb = iavf_aqb_get(sc, NULL); 769 if (aqb != NULL) { 770 iavf_aqb_put_locked(&sc->sc_arq_idle, aqb); 771 } 772 } 773 aqb = NULL; 774 775 if (!iavf_arq_fill(sc)) { 776 aprint_error(": unable to fill arq descriptors\n"); 777 goto free_arq; 778 } 779 780 if (iavf_init_admin_queue(sc) != 0) { 781 aprint_error(": unable to initialize admin queue\n"); 782 goto shutdown; 783 } 784 785 aqb = iavf_aqb_get(sc, NULL); 786 if (aqb == NULL) { 787 aprint_error(": unable to allocate buffer for ATQ\n"); 788 goto shutdown; 789 } 790 791 error = iavf_get_version(sc, aqb); 792 switch (error) { 793 case 0: 794 break; 795 case ETIMEDOUT: 796 aprint_error(": timeout waiting for VF version\n"); 797 goto shutdown; 798 case ENOTSUP: 799 aprint_error(": unsupported VF version %d\n", sc->sc_major_ver); 800 goto shutdown; 801 default: 802 aprint_error(":unable to get VF interface version\n"); 803 goto shutdown; 804 } 805 806 if (iavf_get_vf_resources(sc, aqb) != 0) { 807 aprint_error(": timeout waiting for VF resources\n"); 808 goto shutdown; 809 } 810 811 aprint_normal(", VF version %d.%d%s", 812 sc->sc_major_ver, sc->sc_minor_ver, 813 (sc->sc_minor_ver > IAVF_VF_MINOR) ? "(minor mismatch)" : ""); 814 aprint_normal(", VF %d, VSI %d", sc->sc_vf_id, sc->sc_vsi_id); 815 aprint_normal("\n"); 816 aprint_naive("\n"); 817 818 aprint_normal_dev(self, "Ethernet address %s\n", 819 ether_sprintf(sc->sc_enaddr)); 820 821 if (iavf_queue_pairs_alloc(sc) != 0) { 822 goto shutdown; 823 } 824 825 if (iavf_setup_interrupts(sc) != 0) { 826 goto free_queue_pairs; 827 } 828 829 if (iavf_config_irq_map(sc, aqb) != 0) { 830 aprint_error(", timed out waiting for IRQ map response\n"); 831 goto teardown_intrs; 832 } 833 834 if (iavf_setup_sysctls(sc) != 0) { 835 goto teardown_intrs; 836 } 837 838 if (iavf_setup_stats(sc) != 0) { 839 goto teardown_sysctls; 840 } 841 842 iavf_aqb_put_locked(&sc->sc_atq_idle, aqb); 843 aqb = NULL; 844 845 snprintf(xnamebuf, sizeof(xnamebuf), 846 "%s_adminq_cv", device_xname(self)); 847 cv_init(&sc->sc_adminq_cv, xnamebuf); 848 849 callout_init(&sc->sc_tick, CALLOUT_MPSAFE); 850 callout_setfunc(&sc->sc_tick, iavf_tick, sc); 851 852 iavf_work_set(&sc->sc_reset_task, iavf_reset_start, sc); 853 iavf_work_set(&sc->sc_arq_refill, iavf_arq_refill, sc); 854 iavf_work_set(&sc->sc_wdto_task, iavf_watchdog_timeout, sc); 855 iavf_work_set(&sc->sc_req_queues_task, iavf_post_request_queues, sc); 856 snprintf(xnamebuf, sizeof(xnamebuf), "%s_wq_cfg", device_xname(self)); 857 sc->sc_workq = iavf_workq_create(xnamebuf, IAVF_WORKQUEUE_PRI, 858 IPL_NET, WQ_MPSAFE); 859 if (sc->sc_workq == NULL) 860 goto destroy_cv; 861 862 snprintf(xnamebuf, sizeof(xnamebuf), "%s_wq_txrx", device_xname(self)); 863 error = workqueue_create(&sc->sc_workq_txrx, xnamebuf, 864 iavf_handle_queue_wk, sc, IAVF_WORKQUEUE_PRI, IPL_NET, 865 WQ_PERCPU|WQ_MPSAFE); 866 if (error != 0) { 867 sc->sc_workq_txrx = NULL; 868 goto teardown_wqs; 869 } 870 871 error = if_initialize(ifp); 872 if (error != 0) { 873 aprint_error_dev(self, "if_initialize failed=%d\n", error); 874 goto teardown_wqs; 875 } 876 877 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 878 879 ifp->if_softc = sc; 880 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 881 ifp->if_extflags = IFEF_MPSAFE; 882 ifp->if_ioctl = iavf_ioctl; 883 ifp->if_start = iavf_start; 884 ifp->if_transmit = iavf_transmit; 885 ifp->if_watchdog = NULL; 886 ifp->if_init = iavf_init; 887 ifp->if_stop = iavf_stop; 888 889 IFQ_SET_MAXLEN(&ifp->if_snd, sc->sc_tx_ring_ndescs); 890 IFQ_SET_READY(&ifp->if_snd); 891 sc->sc_ipq = if_percpuq_create(ifp); 892 893 ifp->if_capabilities |= IAVF_IFCAP_RXCSUM; 894 ifp->if_capabilities |= IAVF_IFCAP_TXCSUM; 895 896 ether_set_vlan_cb(&sc->sc_ec, iavf_vlan_cb); 897 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 898 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_HWFILTER; 899 sc->sc_ec.ec_capenable = sc->sc_ec.ec_capabilities; 900 901 ether_set_ifflags_cb(&sc->sc_ec, iavf_ifflags_cb); 902 903 sc->sc_ec.ec_ifmedia = &sc->sc_media; 904 ifmedia_init_with_lock(&sc->sc_media, IFM_IMASK, iavf_media_change, 905 iavf_media_status, &sc->sc_cfg_lock); 906 907 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_AUTO, 0, NULL); 908 ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_AUTO); 909 910 if_deferred_start_init(ifp, NULL); 911 ether_ifattach(ifp, sc->sc_enaddr); 912 913 sc->sc_txrx_workqueue = true; 914 sc->sc_tx_process_limit = IAVF_TX_PROCESS_LIMIT; 915 sc->sc_rx_process_limit = IAVF_RX_PROCESS_LIMIT; 916 sc->sc_tx_intr_process_limit = IAVF_TX_INTR_PROCESS_LIMIT; 917 sc->sc_rx_intr_process_limit = IAVF_RX_INTR_PROCESS_LIMIT; 918 919 if_register(ifp); 920 if_link_state_change(ifp, sc->sc_link_state); 921 iavf_intr_enable(sc); 922 if (sc->sc_nqps_vsi < sc->sc_nqps_req) 923 iavf_work_add(sc->sc_workq, &sc->sc_req_queues_task); 924 sc->sc_attached = true; 925 return; 926 927 teardown_wqs: 928 config_finalize_register(self, iavf_finalize_teardown); 929 destroy_cv: 930 cv_destroy(&sc->sc_adminq_cv); 931 callout_destroy(&sc->sc_tick); 932 iavf_teardown_stats(sc); 933 teardown_sysctls: 934 iavf_teardown_sysctls(sc); 935 teardown_intrs: 936 iavf_teardown_interrupts(sc); 937 free_queue_pairs: 938 iavf_queue_pairs_free(sc); 939 shutdown: 940 if (aqb != NULL) 941 iavf_aqb_put_locked(&sc->sc_atq_idle, aqb); 942 iavf_cleanup_admin_queue(sc); 943 iavf_aqb_clean(&sc->sc_atq_idle, sc->sc_dmat); 944 iavf_aqb_clean(&sc->sc_arq_idle, sc->sc_dmat); 945 free_arq: 946 iavf_dmamem_free(sc->sc_dmat, &sc->sc_arq); 947 free_atq: 948 iavf_dmamem_free(sc->sc_dmat, &sc->sc_atq); 949 free_mutex: 950 mutex_destroy(&sc->sc_cfg_lock); 951 mutex_destroy(&sc->sc_adminq_lock); 952 unmap: 953 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems); 954 sc->sc_mems = 0; 955 sc->sc_attached = false; 956 } 957 958 static int 959 iavf_detach(device_t self, int flags) 960 { 961 struct iavf_softc *sc = device_private(self); 962 struct ifnet *ifp = &sc->sc_ec.ec_if; 963 964 if (!sc->sc_attached) 965 return 0; 966 967 iavf_stop(ifp, 1); 968 ether_ifdetach(ifp); 969 if_detach(ifp); 970 ifmedia_fini(&sc->sc_media); 971 if_percpuq_destroy(sc->sc_ipq); 972 973 iavf_intr_disable(sc); 974 975 mutex_enter(&sc->sc_adminq_lock); 976 mutex_exit(&sc->sc_adminq_lock); 977 978 /* 979 * set a dummy function to halt callout safely 980 * even if a workqueue entry calls callout_schedule() 981 */ 982 callout_setfunc(&sc->sc_tick, iavf_tick_halt, sc); 983 984 iavf_work_wait(sc->sc_workq, &sc->sc_reset_task); 985 iavf_work_wait(sc->sc_workq, &sc->sc_arq_refill); 986 iavf_work_wait(sc->sc_workq, &sc->sc_wdto_task); 987 iavf_workq_destroy(sc->sc_workq); 988 sc->sc_workq = NULL; 989 990 callout_halt(&sc->sc_tick, NULL); 991 callout_destroy(&sc->sc_tick); 992 993 iavf_cleanup_admin_queue(sc); 994 iavf_aqb_clean(&sc->sc_atq_idle, sc->sc_dmat); 995 iavf_aqb_clean(&sc->sc_arq_idle, sc->sc_dmat); 996 iavf_dmamem_free(sc->sc_dmat, &sc->sc_arq); 997 iavf_dmamem_free(sc->sc_dmat, &sc->sc_atq); 998 cv_destroy(&sc->sc_adminq_cv); 999 1000 iavf_queue_pairs_free(sc); 1001 iavf_teardown_interrupts(sc); 1002 iavf_teardown_sysctls(sc); 1003 iavf_teardown_stats(sc); 1004 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems); 1005 1006 mutex_destroy(&sc->sc_adminq_lock); 1007 mutex_destroy(&sc->sc_cfg_lock); 1008 1009 return 0; 1010 } 1011 1012 static int 1013 iavf_finalize_teardown(device_t self) 1014 { 1015 struct iavf_softc *sc = device_private(self); 1016 1017 if (sc->sc_workq != NULL) { 1018 iavf_workq_destroy(sc->sc_workq); 1019 sc->sc_workq = NULL; 1020 } 1021 1022 if (sc->sc_workq_txrx != NULL) { 1023 workqueue_destroy(sc->sc_workq_txrx); 1024 sc->sc_workq_txrx = NULL; 1025 } 1026 1027 return 0; 1028 } 1029 1030 static int 1031 iavf_init(struct ifnet *ifp) 1032 { 1033 struct iavf_softc *sc; 1034 int rv; 1035 1036 sc = ifp->if_softc; 1037 mutex_enter(&sc->sc_cfg_lock); 1038 rv = iavf_init_locked(sc); 1039 mutex_exit(&sc->sc_cfg_lock); 1040 1041 return rv; 1042 } 1043 1044 static int 1045 iavf_init_locked(struct iavf_softc *sc) 1046 { 1047 struct ifnet *ifp = &sc->sc_ec.ec_if; 1048 unsigned int i; 1049 int error; 1050 1051 KASSERT(mutex_owned(&sc->sc_cfg_lock)); 1052 1053 if (ISSET(ifp->if_flags, IFF_RUNNING)) 1054 iavf_stop_locked(sc); 1055 1056 if (sc->sc_resetting) 1057 return ENXIO; 1058 1059 error = iavf_reinit(sc); 1060 if (error) { 1061 iavf_stop_locked(sc); 1062 return error; 1063 } 1064 1065 SET(ifp->if_flags, IFF_RUNNING); 1066 CLR(ifp->if_flags, IFF_OACTIVE); 1067 1068 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 1069 iavf_wr(sc, I40E_VFINT_ITRN1(IAVF_ITR_RX, i), sc->sc_rx_itr); 1070 iavf_wr(sc, I40E_VFINT_ITRN1(IAVF_ITR_TX, i), sc->sc_tx_itr); 1071 } 1072 iavf_wr(sc, I40E_VFINT_ITR01(IAVF_ITR_RX), sc->sc_rx_itr); 1073 iavf_wr(sc, I40E_VFINT_ITR01(IAVF_ITR_TX), sc->sc_tx_itr); 1074 iavf_wr(sc, I40E_VFINT_ITR01(IAVF_ITR_MISC), 0); 1075 1076 error = iavf_iff_locked(sc); 1077 if (error) { 1078 iavf_stop_locked(sc); 1079 return error; 1080 }; 1081 1082 /* ETHERCAP_VLAN_HWFILTER can not be disabled */ 1083 SET(sc->sc_ec.ec_capenable, ETHERCAP_VLAN_HWFILTER); 1084 1085 callout_schedule(&sc->sc_tick, IAVF_TICK_INTERVAL); 1086 return 0; 1087 } 1088 1089 static int 1090 iavf_reinit(struct iavf_softc *sc) 1091 { 1092 struct iavf_rx_ring *rxr; 1093 struct iavf_tx_ring *txr; 1094 unsigned int i; 1095 uint32_t reg; 1096 1097 KASSERT(mutex_owned(&sc->sc_cfg_lock)); 1098 1099 sc->sc_reset_up = true; 1100 sc->sc_nqueue_pairs = MIN(sc->sc_nqps_alloc, sc->sc_nintrs - 1); 1101 1102 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 1103 rxr = sc->sc_qps[i].qp_rxr; 1104 txr = sc->sc_qps[i].qp_txr; 1105 1106 iavf_rxfill(sc, rxr); 1107 txr->txr_watchdog = IAVF_WATCHDOG_STOP; 1108 } 1109 1110 if (iavf_config_vsi_queues(sc) != 0) 1111 return EIO; 1112 1113 if (iavf_config_hena(sc) != 0) 1114 return EIO; 1115 1116 iavf_config_rss_key(sc); 1117 iavf_config_rss_lut(sc); 1118 1119 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 1120 iavf_queue_intr_enable(sc, i); 1121 } 1122 /* unmask */ 1123 reg = iavf_rd(sc, I40E_VFINT_DYN_CTL01); 1124 reg |= (IAVF_NOITR << I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT); 1125 iavf_wr(sc, I40E_VFINT_DYN_CTL01, reg); 1126 1127 if (iavf_queue_select(sc, IAVF_VC_OP_ENABLE_QUEUES) != 0) 1128 return EIO; 1129 1130 return 0; 1131 } 1132 1133 static void 1134 iavf_stop(struct ifnet *ifp, int disable) 1135 { 1136 struct iavf_softc *sc; 1137 1138 sc = ifp->if_softc; 1139 mutex_enter(&sc->sc_cfg_lock); 1140 iavf_stop_locked(sc); 1141 mutex_exit(&sc->sc_cfg_lock); 1142 } 1143 1144 static void 1145 iavf_stop_locked(struct iavf_softc *sc) 1146 { 1147 struct ifnet *ifp = &sc->sc_ec.ec_if; 1148 struct iavf_rx_ring *rxr; 1149 struct iavf_tx_ring *txr; 1150 uint32_t reg; 1151 unsigned int i; 1152 1153 KASSERT(mutex_owned(&sc->sc_cfg_lock)); 1154 1155 CLR(ifp->if_flags, IFF_RUNNING); 1156 sc->sc_reset_up = false; 1157 callout_stop(&sc->sc_tick); 1158 1159 if (!sc->sc_resetting) { 1160 /* disable queues*/ 1161 if (iavf_queue_select(sc, IAVF_VC_OP_DISABLE_QUEUES) != 0) { 1162 goto die; 1163 } 1164 } 1165 1166 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 1167 iavf_queue_intr_disable(sc, i); 1168 } 1169 1170 /* mask interrupts */ 1171 reg = iavf_rd(sc, I40E_VFINT_DYN_CTL01); 1172 reg |= I40E_VFINT_DYN_CTL0_INTENA_MSK_MASK | 1173 (IAVF_NOITR << I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT); 1174 iavf_wr(sc, I40E_VFINT_DYN_CTL01, reg); 1175 1176 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 1177 rxr = sc->sc_qps[i].qp_rxr; 1178 txr = sc->sc_qps[i].qp_txr; 1179 1180 mutex_enter(&rxr->rxr_lock); 1181 iavf_rxr_clean(sc, rxr); 1182 mutex_exit(&rxr->rxr_lock); 1183 1184 mutex_enter(&txr->txr_lock); 1185 iavf_txr_clean(sc, txr); 1186 mutex_exit(&txr->txr_lock); 1187 1188 workqueue_wait(sc->sc_workq_txrx, 1189 &sc->sc_qps[i].qp_work); 1190 } 1191 1192 return; 1193 die: 1194 if (!sc->sc_dead) { 1195 sc->sc_dead = true; 1196 log(LOG_INFO, "%s: Request VF reset\n", ifp->if_xname); 1197 1198 iavf_work_set(&sc->sc_reset_task, iavf_reset_request, sc); 1199 iavf_work_add(sc->sc_workq, &sc->sc_reset_task); 1200 } 1201 log(LOG_CRIT, "%s: failed to shut down rings\n", ifp->if_xname); 1202 } 1203 1204 static int 1205 iavf_watchdog(struct iavf_tx_ring *txr) 1206 { 1207 struct iavf_softc *sc; 1208 1209 sc = txr->txr_sc; 1210 1211 mutex_enter(&txr->txr_lock); 1212 1213 if (txr->txr_watchdog == IAVF_WATCHDOG_STOP 1214 || --txr->txr_watchdog > 0) { 1215 mutex_exit(&txr->txr_lock); 1216 return 0; 1217 } 1218 1219 txr->txr_watchdog = IAVF_WATCHDOG_STOP; 1220 txr->txr_watchdogto.ev_count++; 1221 mutex_exit(&txr->txr_lock); 1222 1223 device_printf(sc->sc_dev, "watchdog timeout on queue %d\n", 1224 txr->txr_qid); 1225 return 1; 1226 } 1227 1228 static void 1229 iavf_watchdog_timeout(void *xsc) 1230 { 1231 struct iavf_softc *sc; 1232 struct ifnet *ifp; 1233 1234 sc = xsc; 1235 ifp = &sc->sc_ec.ec_if; 1236 1237 mutex_enter(&sc->sc_cfg_lock); 1238 if (ISSET(ifp->if_flags, IFF_RUNNING)) 1239 iavf_init_locked(sc); 1240 mutex_exit(&sc->sc_cfg_lock); 1241 } 1242 1243 static int 1244 iavf_media_change(struct ifnet *ifp) 1245 { 1246 struct iavf_softc *sc; 1247 struct ifmedia *ifm; 1248 1249 sc = ifp->if_softc; 1250 ifm = &sc->sc_media; 1251 1252 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1253 return EINVAL; 1254 1255 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1256 case IFM_AUTO: 1257 break; 1258 default: 1259 return EINVAL; 1260 } 1261 1262 return 0; 1263 } 1264 1265 static void 1266 iavf_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 1267 { 1268 struct iavf_softc *sc = ifp->if_softc; 1269 1270 KASSERT(mutex_owned(&sc->sc_cfg_lock)); 1271 1272 ifmr->ifm_status = sc->sc_media_status; 1273 ifmr->ifm_active = sc->sc_media_active; 1274 } 1275 1276 static int 1277 iavf_ifflags_cb(struct ethercom *ec) 1278 { 1279 struct ifnet *ifp = &ec->ec_if; 1280 struct iavf_softc *sc = ifp->if_softc; 1281 1282 /* vlan hwfilter can not be disabled */ 1283 SET(ec->ec_capenable, ETHERCAP_VLAN_HWFILTER); 1284 1285 return iavf_iff(sc); 1286 } 1287 1288 static int 1289 iavf_vlan_cb(struct ethercom *ec, uint16_t vid, bool set) 1290 { 1291 struct ifnet *ifp = &ec->ec_if; 1292 struct iavf_softc *sc = ifp->if_softc; 1293 int rv; 1294 1295 mutex_enter(&sc->sc_cfg_lock); 1296 1297 if (sc->sc_resetting) { 1298 mutex_exit(&sc->sc_cfg_lock); 1299 1300 /* all vlan id was already removed */ 1301 if (!set) 1302 return 0; 1303 1304 return ENXIO; 1305 } 1306 1307 /* ETHERCAP_VLAN_HWFILTER can not be disabled */ 1308 SET(sc->sc_ec.ec_capenable, ETHERCAP_VLAN_HWFILTER); 1309 1310 if (set) { 1311 rv = iavf_config_vlan_id(sc, vid, IAVF_VC_OP_ADD_VLAN); 1312 if (!ISSET(sc->sc_ec.ec_capenable, ETHERCAP_VLAN_HWTAGGING)) { 1313 iavf_config_vlan_stripping(sc, 1314 sc->sc_ec.ec_capenable); 1315 } 1316 } else { 1317 rv = iavf_config_vlan_id(sc, vid, IAVF_VC_OP_DEL_VLAN); 1318 } 1319 1320 mutex_exit(&sc->sc_cfg_lock); 1321 1322 if (rv != 0) 1323 return EIO; 1324 1325 return 0; 1326 } 1327 1328 static int 1329 iavf_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1330 { 1331 struct ifreq *ifr = (struct ifreq *)data; 1332 struct iavf_softc *sc = (struct iavf_softc *)ifp->if_softc; 1333 const struct sockaddr *sa; 1334 uint8_t addrhi[ETHER_ADDR_LEN], addrlo[ETHER_ADDR_LEN]; 1335 int s, error = 0; 1336 unsigned int nmtu; 1337 1338 switch (cmd) { 1339 case SIOCSIFMTU: 1340 nmtu = ifr->ifr_mtu; 1341 1342 if (nmtu < IAVF_MIN_MTU || nmtu > IAVF_MAX_MTU) { 1343 error = EINVAL; 1344 break; 1345 } 1346 if (ifp->if_mtu != nmtu) { 1347 s = splnet(); 1348 error = ether_ioctl(ifp, cmd, data); 1349 splx(s); 1350 if (error == ENETRESET) 1351 error = iavf_init(ifp); 1352 } 1353 break; 1354 case SIOCADDMULTI: 1355 sa = ifreq_getaddr(SIOCADDMULTI, ifr); 1356 if (ether_addmulti(sa, &sc->sc_ec) == ENETRESET) { 1357 error = ether_multiaddr(sa, addrlo, addrhi); 1358 if (error != 0) 1359 return error; 1360 1361 error = iavf_add_multi(sc, addrlo, addrhi); 1362 if (error != 0 && error != ENETRESET) { 1363 ether_delmulti(sa, &sc->sc_ec); 1364 error = EIO; 1365 } 1366 } 1367 break; 1368 1369 case SIOCDELMULTI: 1370 sa = ifreq_getaddr(SIOCDELMULTI, ifr); 1371 if (ether_delmulti(sa, &sc->sc_ec) == ENETRESET) { 1372 error = ether_multiaddr(sa, addrlo, addrhi); 1373 if (error != 0) 1374 return error; 1375 1376 error = iavf_del_multi(sc, addrlo, addrhi); 1377 } 1378 break; 1379 1380 default: 1381 s = splnet(); 1382 error = ether_ioctl(ifp, cmd, data); 1383 splx(s); 1384 } 1385 1386 if (error == ENETRESET) 1387 error = iavf_iff(sc); 1388 1389 return error; 1390 } 1391 1392 static int 1393 iavf_iff(struct iavf_softc *sc) 1394 { 1395 int error; 1396 1397 mutex_enter(&sc->sc_cfg_lock); 1398 error = iavf_iff_locked(sc); 1399 mutex_exit(&sc->sc_cfg_lock); 1400 1401 return error; 1402 } 1403 1404 static int 1405 iavf_iff_locked(struct iavf_softc *sc) 1406 { 1407 struct ifnet *ifp = &sc->sc_ec.ec_if; 1408 int unicast, multicast; 1409 const uint8_t *enaddr; 1410 1411 KASSERT(mutex_owned(&sc->sc_cfg_lock)); 1412 1413 if (!ISSET(ifp->if_flags, IFF_RUNNING)) 1414 return 0; 1415 1416 unicast = 0; 1417 multicast = 0; 1418 if (ISSET(ifp->if_flags, IFF_PROMISC)) { 1419 unicast = 1; 1420 multicast = 1; 1421 } else if (ISSET(ifp->if_flags, IFF_ALLMULTI)) { 1422 multicast = 1; 1423 } 1424 1425 iavf_config_promisc_mode(sc, unicast, multicast); 1426 1427 iavf_config_vlan_stripping(sc, sc->sc_ec.ec_capenable); 1428 1429 enaddr = CLLADDR(ifp->if_sadl); 1430 if (memcmp(enaddr, sc->sc_enaddr_added, ETHER_ADDR_LEN) != 0) { 1431 if (!iavf_is_etheranyaddr(sc->sc_enaddr_added)) { 1432 iavf_eth_addr(sc, sc->sc_enaddr_added, 1433 IAVF_VC_OP_DEL_ETH_ADDR); 1434 } 1435 memcpy(sc->sc_enaddr_added, enaddr, ETHER_ADDR_LEN); 1436 iavf_eth_addr(sc, enaddr, IAVF_VC_OP_ADD_ETH_ADDR); 1437 } 1438 1439 return 0; 1440 } 1441 1442 static const struct iavf_product * 1443 iavf_lookup(const struct pci_attach_args *pa) 1444 { 1445 const struct iavf_product *iavfp; 1446 1447 for (iavfp = iavf_products; iavfp->vendor_id != 0; iavfp++) { 1448 if (PCI_VENDOR(pa->pa_id) == iavfp->vendor_id && 1449 PCI_PRODUCT(pa->pa_id) == iavfp->product_id) 1450 return iavfp; 1451 } 1452 1453 return NULL; 1454 } 1455 1456 static enum i40e_mac_type 1457 iavf_mactype(pci_product_id_t id) 1458 { 1459 1460 switch (id) { 1461 case PCI_PRODUCT_INTEL_XL710_VF: 1462 case PCI_PRODUCT_INTEL_XL710_VF_HV: 1463 return I40E_MAC_VF; 1464 case PCI_PRODUCT_INTEL_X722_VF: 1465 return I40E_MAC_X722_VF; 1466 } 1467 1468 return I40E_MAC_GENERIC; 1469 } 1470 1471 static const struct iavf_link_speed * 1472 iavf_find_link_speed(struct iavf_softc *sc, uint32_t link_speed) 1473 { 1474 size_t i; 1475 1476 for (i = 0; i < __arraycount(iavf_link_speeds); i++) { 1477 if (link_speed & (1 << i)) 1478 return (&iavf_link_speeds[i]); 1479 } 1480 1481 return NULL; 1482 } 1483 1484 static void 1485 iavf_pci_csr_setup(pci_chipset_tag_t pc, pcitag_t tag) 1486 { 1487 pcireg_t csr; 1488 1489 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 1490 csr |= (PCI_COMMAND_MASTER_ENABLE | 1491 PCI_COMMAND_MEM_ENABLE); 1492 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 1493 } 1494 1495 static int 1496 iavf_wait_active(struct iavf_softc *sc) 1497 { 1498 int tries; 1499 uint32_t reg; 1500 1501 for (tries = 0; tries < 100; tries++) { 1502 reg = iavf_rd(sc, I40E_VFGEN_RSTAT) & 1503 I40E_VFGEN_RSTAT_VFR_STATE_MASK; 1504 if (reg == IAVF_VFR_VFACTIVE || 1505 reg == IAVF_VFR_COMPLETED) 1506 return 0; 1507 1508 delaymsec(10); 1509 } 1510 1511 return -1; 1512 } 1513 1514 static bool 1515 iavf_is_etheranyaddr(const uint8_t *enaddr) 1516 { 1517 static const uint8_t etheranyaddr[ETHER_ADDR_LEN] = { 1518 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1519 }; 1520 1521 if (memcmp(enaddr, etheranyaddr, ETHER_ADDR_LEN) != 0) 1522 return false; 1523 1524 return true; 1525 } 1526 1527 static void 1528 iavf_prepare_fakeaddr(struct iavf_softc *sc) 1529 { 1530 uint64_t rndval; 1531 1532 if (!iavf_is_etheranyaddr(sc->sc_enaddr_fake)) 1533 return; 1534 1535 rndval = cprng_strong64(); 1536 1537 memcpy(sc->sc_enaddr_fake, &rndval, sizeof(sc->sc_enaddr_fake)); 1538 sc->sc_enaddr_fake[0] &= 0xFE; 1539 sc->sc_enaddr_fake[0] |= 0x02; 1540 } 1541 1542 static int 1543 iavf_replace_lla(struct ifnet *ifp, const uint8_t *prev, const uint8_t *next) 1544 { 1545 union { 1546 struct sockaddr sa; 1547 struct sockaddr_dl sdl; 1548 struct sockaddr_storage ss; 1549 } u; 1550 struct psref psref_prev, psref_next; 1551 struct ifaddr *ifa_prev, *ifa_next; 1552 const struct sockaddr_dl *nsdl; 1553 int s, error; 1554 1555 KASSERT(IFNET_LOCKED(ifp)); 1556 1557 error = 0; 1558 ifa_prev = ifa_next = NULL; 1559 1560 if (memcmp(prev, next, ETHER_ADDR_LEN) == 0) { 1561 goto done; 1562 } 1563 1564 if (sockaddr_dl_init(&u.sdl, sizeof(u.ss), ifp->if_index, 1565 ifp->if_type, ifp->if_xname, strlen(ifp->if_xname), 1566 prev, ETHER_ADDR_LEN) == NULL) { 1567 error = EINVAL; 1568 goto done; 1569 } 1570 1571 s = pserialize_read_enter(); 1572 IFADDR_READER_FOREACH(ifa_prev, ifp) { 1573 if (sockaddr_cmp(&u.sa, ifa_prev->ifa_addr) == 0) { 1574 ifa_acquire(ifa_prev, &psref_prev); 1575 break; 1576 } 1577 } 1578 pserialize_read_exit(s); 1579 1580 if (sockaddr_dl_init(&u.sdl, sizeof(u.ss), ifp->if_index, 1581 ifp->if_type, ifp->if_xname, strlen(ifp->if_xname), 1582 next, ETHER_ADDR_LEN) == NULL) { 1583 error = EINVAL; 1584 goto done; 1585 } 1586 1587 s = pserialize_read_enter(); 1588 IFADDR_READER_FOREACH(ifa_next, ifp) { 1589 if (sockaddr_cmp(&u.sa, ifa_next->ifa_addr) == 0) { 1590 ifa_acquire(ifa_next, &psref_next); 1591 break; 1592 } 1593 } 1594 pserialize_read_exit(s); 1595 1596 if (ifa_next == NULL) { 1597 nsdl = &u.sdl; 1598 ifa_next = if_dl_create(ifp, &nsdl); 1599 if (ifa_next == NULL) { 1600 error = ENOMEM; 1601 goto done; 1602 } 1603 1604 s = pserialize_read_enter(); 1605 ifa_acquire(ifa_next, &psref_next); 1606 pserialize_read_exit(s); 1607 1608 sockaddr_copy(ifa_next->ifa_addr, 1609 ifa_next->ifa_addr->sa_len, &u.sa); 1610 ifa_insert(ifp, ifa_next); 1611 } else { 1612 nsdl = NULL; 1613 } 1614 1615 if (ifa_prev != NULL && ifa_prev == ifp->if_dl) { 1616 if_activate_sadl(ifp, ifa_next, nsdl); 1617 } 1618 1619 ifa_release(ifa_next, &psref_next); 1620 ifa_next = NULL; 1621 1622 if (ifa_prev != NULL && ifa_prev != ifp->if_hwdl) { 1623 ifaref(ifa_prev); 1624 ifa_release(ifa_prev, &psref_prev); 1625 ifa_remove(ifp, ifa_prev); 1626 KASSERTMSG(ifa_prev->ifa_refcnt == 1, "ifa_refcnt=%d", 1627 ifa_prev->ifa_refcnt); 1628 ifafree(ifa_prev); 1629 ifa_prev = NULL; 1630 } 1631 1632 if (ISSET(ifp->if_flags, IFF_RUNNING)) 1633 error = ENETRESET; 1634 1635 done: 1636 if (ifa_prev != NULL) 1637 ifa_release(ifa_prev, &psref_prev); 1638 if (ifa_next != NULL) 1639 ifa_release(ifa_next, &psref_next); 1640 1641 return error; 1642 } 1643 static int 1644 iavf_add_multi(struct iavf_softc *sc, uint8_t *addrlo, uint8_t *addrhi) 1645 { 1646 struct ifnet *ifp = &sc->sc_ec.ec_if; 1647 int rv; 1648 1649 if (ISSET(ifp->if_flags, IFF_ALLMULTI)) 1650 return 0; 1651 1652 if (memcmp(addrlo, addrhi, ETHER_ADDR_LEN) != 0) { 1653 iavf_del_all_multi(sc); 1654 SET(ifp->if_flags, IFF_ALLMULTI); 1655 return ENETRESET; 1656 } 1657 1658 rv = iavf_eth_addr(sc, addrlo, IAVF_VC_OP_ADD_ETH_ADDR); 1659 1660 if (rv == ENOSPC) { 1661 iavf_del_all_multi(sc); 1662 SET(ifp->if_flags, IFF_ALLMULTI); 1663 return ENETRESET; 1664 } 1665 1666 return rv; 1667 } 1668 1669 static int 1670 iavf_del_multi(struct iavf_softc *sc, uint8_t *addrlo, uint8_t *addrhi) 1671 { 1672 struct ifnet *ifp = &sc->sc_ec.ec_if; 1673 struct ethercom *ec = &sc->sc_ec; 1674 struct ether_multi *enm, *enm_last; 1675 struct ether_multistep step; 1676 int error, rv = 0; 1677 1678 if (!ISSET(ifp->if_flags, IFF_ALLMULTI)) { 1679 if (memcmp(addrlo, addrhi, ETHER_ADDR_LEN) != 0) 1680 return 0; 1681 1682 iavf_eth_addr(sc, addrlo, IAVF_VC_OP_DEL_ETH_ADDR); 1683 return 0; 1684 } 1685 1686 ETHER_LOCK(ec); 1687 for (ETHER_FIRST_MULTI(step, ec, enm); enm != NULL; 1688 ETHER_NEXT_MULTI(step, enm)) { 1689 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1690 ETHER_ADDR_LEN) != 0) { 1691 goto out; 1692 } 1693 } 1694 1695 for (ETHER_FIRST_MULTI(step, ec, enm); enm != NULL; 1696 ETHER_NEXT_MULTI(step, enm)) { 1697 error = iavf_eth_addr(sc, enm->enm_addrlo, 1698 IAVF_VC_OP_ADD_ETH_ADDR); 1699 if (error != 0) 1700 break; 1701 } 1702 1703 if (enm != NULL) { 1704 enm_last = enm; 1705 for (ETHER_FIRST_MULTI(step, ec, enm); enm != NULL; 1706 ETHER_NEXT_MULTI(step, enm)) { 1707 if (enm == enm_last) 1708 break; 1709 1710 iavf_eth_addr(sc, enm->enm_addrlo, 1711 IAVF_VC_OP_DEL_ETH_ADDR); 1712 } 1713 } else { 1714 CLR(ifp->if_flags, IFF_ALLMULTI); 1715 rv = ENETRESET; 1716 } 1717 1718 out: 1719 ETHER_UNLOCK(ec); 1720 return rv; 1721 } 1722 1723 static void 1724 iavf_del_all_multi(struct iavf_softc *sc) 1725 { 1726 struct ethercom *ec = &sc->sc_ec; 1727 struct ether_multi *enm; 1728 struct ether_multistep step; 1729 1730 ETHER_LOCK(ec); 1731 for (ETHER_FIRST_MULTI(step, ec, enm); enm != NULL; 1732 ETHER_NEXT_MULTI(step, enm)) { 1733 iavf_eth_addr(sc, enm->enm_addrlo, 1734 IAVF_VC_OP_DEL_ETH_ADDR); 1735 } 1736 ETHER_UNLOCK(ec); 1737 } 1738 1739 static int 1740 iavf_setup_interrupts(struct iavf_softc *sc) 1741 { 1742 struct pci_attach_args *pa; 1743 kcpuset_t *affinity = NULL; 1744 char intrbuf[PCI_INTRSTR_LEN], xnamebuf[32]; 1745 char const *intrstr; 1746 int counts[PCI_INTR_TYPE_SIZE]; 1747 int error, affinity_to; 1748 unsigned int vector, qid, num; 1749 1750 /* queue pairs + misc interrupt */ 1751 num = sc->sc_nqps_alloc + 1; 1752 1753 num = MIN(num, iavf_calc_msix_count(sc)); 1754 if (num <= 0) { 1755 return -1; 1756 } 1757 1758 KASSERT(sc->sc_nqps_alloc > 0); 1759 num = MIN(num, sc->sc_nqps_alloc + 1); 1760 1761 pa = &sc->sc_pa; 1762 memset(counts, 0, sizeof(counts)); 1763 counts[PCI_INTR_TYPE_MSIX] = num; 1764 1765 error = pci_intr_alloc(pa, &sc->sc_ihp, counts, PCI_INTR_TYPE_MSIX); 1766 if (error != 0) { 1767 IAVF_LOG(sc, LOG_WARNING, "couldn't allocate interrupts\n"); 1768 return -1; 1769 } 1770 1771 KASSERT(pci_intr_type(pa->pa_pc, sc->sc_ihp[0]) == PCI_INTR_TYPE_MSIX); 1772 1773 if (counts[PCI_INTR_TYPE_MSIX] < 1) { 1774 IAVF_LOG(sc, LOG_ERR, "couldn't allocate interrupts\n"); 1775 } else if (counts[PCI_INTR_TYPE_MSIX] != (int)num) { 1776 IAVF_LOG(sc, LOG_DEBUG, 1777 "request %u intruppts, but allocate %d interrupts\n", 1778 num, counts[PCI_INTR_TYPE_MSIX]); 1779 num = counts[PCI_INTR_TYPE_MSIX]; 1780 } 1781 1782 sc->sc_ihs = kmem_alloc(sizeof(sc->sc_ihs[0]) * num, KM_NOSLEEP); 1783 if (sc->sc_ihs == NULL) { 1784 IAVF_LOG(sc, LOG_ERR, 1785 "couldn't allocate memory for interrupts\n"); 1786 goto fail; 1787 } 1788 1789 /* vector #0 is Misc interrupt */ 1790 vector = 0; 1791 pci_intr_setattr(pa->pa_pc, &sc->sc_ihp[vector], PCI_INTR_MPSAFE, true); 1792 intrstr = pci_intr_string(pa->pa_pc, sc->sc_ihp[vector], 1793 intrbuf, sizeof(intrbuf)); 1794 snprintf(xnamebuf, sizeof(xnamebuf), "%s-Misc", 1795 device_xname(sc->sc_dev)); 1796 1797 sc->sc_ihs[vector] = pci_intr_establish_xname(pa->pa_pc, 1798 sc->sc_ihp[vector], IPL_NET, iavf_intr, sc, xnamebuf); 1799 if (sc->sc_ihs[vector] == NULL) { 1800 IAVF_LOG(sc, LOG_WARNING, 1801 "unable to establish interrupt at %s", intrstr); 1802 goto fail; 1803 } 1804 1805 kcpuset_create(&affinity, false); 1806 affinity_to = ((int)num <= ncpu) ? 1 : 0; 1807 qid = 0; 1808 for (vector = 1; vector < num; vector++) { 1809 pci_intr_setattr(pa->pa_pc, &sc->sc_ihp[vector], 1810 PCI_INTR_MPSAFE, true); 1811 intrstr = pci_intr_string(pa->pa_pc, sc->sc_ihp[vector], 1812 intrbuf, sizeof(intrbuf)); 1813 snprintf(xnamebuf, sizeof(xnamebuf), "%s-TXRX%u", 1814 device_xname(sc->sc_dev), qid); 1815 1816 sc->sc_ihs[vector] = pci_intr_establish_xname(pa->pa_pc, 1817 sc->sc_ihp[vector], IPL_NET, iavf_queue_intr, 1818 (void *)&sc->sc_qps[qid], xnamebuf); 1819 if (sc->sc_ihs[vector] == NULL) { 1820 IAVF_LOG(sc, LOG_WARNING, 1821 "unable to establish interrupt at %s\n", intrstr); 1822 goto fail; 1823 } 1824 1825 kcpuset_zero(affinity); 1826 kcpuset_set(affinity, affinity_to); 1827 error = interrupt_distribute(sc->sc_ihs[vector], 1828 affinity, NULL); 1829 1830 if (error == 0) { 1831 IAVF_LOG(sc, LOG_INFO, 1832 "for TXRX%d interrupt at %s, affinity to %d\n", 1833 qid, intrstr, affinity_to); 1834 } else { 1835 IAVF_LOG(sc, LOG_INFO, 1836 "for TXRX%d interrupt at %s\n", 1837 qid, intrstr); 1838 } 1839 1840 qid++; 1841 affinity_to = (affinity_to + 1) % ncpu; 1842 } 1843 1844 kcpuset_destroy(affinity); 1845 1846 sc->sc_nintrs = num; 1847 return 0; 1848 1849 fail: 1850 if (affinity != NULL) 1851 kcpuset_destroy(affinity); 1852 for (vector = 0; vector < num; vector++) { 1853 if (sc->sc_ihs[vector] == NULL) 1854 continue; 1855 pci_intr_disestablish(pa->pa_pc, sc->sc_ihs[vector]); 1856 } 1857 kmem_free(sc->sc_ihs, sizeof(sc->sc_ihs[0]) * num); 1858 pci_intr_release(pa->pa_pc, sc->sc_ihp, num); 1859 1860 return -1; 1861 } 1862 1863 static void 1864 iavf_teardown_interrupts(struct iavf_softc *sc) 1865 { 1866 struct pci_attach_args *pa; 1867 unsigned int i; 1868 1869 if (sc->sc_ihs == NULL) 1870 return; 1871 1872 pa = &sc->sc_pa; 1873 1874 for (i = 0; i < sc->sc_nintrs; i++) { 1875 pci_intr_disestablish(pa->pa_pc, sc->sc_ihs[i]); 1876 } 1877 1878 kmem_free(sc->sc_ihs, sizeof(sc->sc_ihs[0]) * sc->sc_nintrs); 1879 sc->sc_ihs = NULL; 1880 1881 pci_intr_release(pa->pa_pc, sc->sc_ihp, sc->sc_nintrs); 1882 sc->sc_nintrs = 0; 1883 } 1884 1885 static int 1886 iavf_setup_sysctls(struct iavf_softc *sc) 1887 { 1888 const char *devname; 1889 struct sysctllog **log; 1890 const struct sysctlnode *rnode, *rxnode, *txnode; 1891 int error; 1892 1893 log = &sc->sc_sysctllog; 1894 devname = device_xname(sc->sc_dev); 1895 1896 error = sysctl_createv(log, 0, NULL, &rnode, 1897 0, CTLTYPE_NODE, devname, 1898 SYSCTL_DESCR("iavf information and settings"), 1899 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 1900 if (error) 1901 goto out; 1902 1903 error = sysctl_createv(log, 0, &rnode, NULL, 1904 CTLFLAG_READWRITE, CTLTYPE_BOOL, "txrx_workqueue", 1905 SYSCTL_DESCR("Use workqueue for packet processing"), 1906 NULL, 0, &sc->sc_txrx_workqueue, 0, CTL_CREATE, CTL_EOL); 1907 if (error) 1908 goto out; 1909 1910 error = sysctl_createv(log, 0, &rnode, NULL, 1911 CTLFLAG_READWRITE, CTLTYPE_INT, "debug_level", 1912 SYSCTL_DESCR("Debug level"), 1913 NULL, 0, &sc->sc_debuglevel, 0, CTL_CREATE, CTL_EOL); 1914 if (error) 1915 goto out; 1916 1917 error = sysctl_createv(log, 0, &rnode, &rxnode, 1918 0, CTLTYPE_NODE, "rx", 1919 SYSCTL_DESCR("iavf information and settings for Rx"), 1920 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL); 1921 if (error) 1922 goto out; 1923 1924 error = sysctl_createv(log, 0, &rxnode, NULL, 1925 CTLFLAG_READWRITE, CTLTYPE_INT, "itr", 1926 SYSCTL_DESCR("Interrupt Throttling"), 1927 iavf_sysctl_itr_handler, 0, 1928 (void *)sc, 0, CTL_CREATE, CTL_EOL); 1929 if (error) 1930 goto out; 1931 1932 error = sysctl_createv(log, 0, &rxnode, NULL, 1933 CTLFLAG_READONLY, CTLTYPE_INT, "descriptor_num", 1934 SYSCTL_DESCR("descriptor size"), 1935 NULL, 0, &sc->sc_rx_ring_ndescs, 0, CTL_CREATE, CTL_EOL); 1936 if (error) 1937 goto out; 1938 1939 error = sysctl_createv(log, 0, &rxnode, NULL, 1940 CTLFLAG_READWRITE, CTLTYPE_INT, "intr_process_limit", 1941 SYSCTL_DESCR("max number of Rx packets" 1942 " to process for interrupt processing"), 1943 NULL, 0, &sc->sc_rx_intr_process_limit, 0, CTL_CREATE, CTL_EOL); 1944 if (error) 1945 goto out; 1946 1947 error = sysctl_createv(log, 0, &rxnode, NULL, 1948 CTLFLAG_READWRITE, CTLTYPE_INT, "process_limit", 1949 SYSCTL_DESCR("max number of Rx packets" 1950 " to process for deferred processing"), 1951 NULL, 0, &sc->sc_rx_process_limit, 0, CTL_CREATE, CTL_EOL); 1952 if (error) 1953 goto out; 1954 1955 error = sysctl_createv(log, 0, &rnode, &txnode, 1956 0, CTLTYPE_NODE, "tx", 1957 SYSCTL_DESCR("iavf information and settings for Tx"), 1958 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL); 1959 if (error) 1960 goto out; 1961 1962 error = sysctl_createv(log, 0, &txnode, NULL, 1963 CTLFLAG_READWRITE, CTLTYPE_INT, "itr", 1964 SYSCTL_DESCR("Interrupt Throttling"), 1965 iavf_sysctl_itr_handler, 0, 1966 (void *)sc, 0, CTL_CREATE, CTL_EOL); 1967 if (error) 1968 goto out; 1969 1970 error = sysctl_createv(log, 0, &txnode, NULL, 1971 CTLFLAG_READONLY, CTLTYPE_INT, "descriptor_num", 1972 SYSCTL_DESCR("the number of Tx descriptors"), 1973 NULL, 0, &sc->sc_tx_ring_ndescs, 0, CTL_CREATE, CTL_EOL); 1974 if (error) 1975 goto out; 1976 1977 error = sysctl_createv(log, 0, &txnode, NULL, 1978 CTLFLAG_READWRITE, CTLTYPE_INT, "intr_process_limit", 1979 SYSCTL_DESCR("max number of Tx packets" 1980 " to process for interrupt processing"), 1981 NULL, 0, &sc->sc_tx_intr_process_limit, 0, CTL_CREATE, CTL_EOL); 1982 if (error) 1983 goto out; 1984 1985 error = sysctl_createv(log, 0, &txnode, NULL, 1986 CTLFLAG_READWRITE, CTLTYPE_INT, "process_limit", 1987 SYSCTL_DESCR("max number of Tx packets" 1988 " to process for deferred processing"), 1989 NULL, 0, &sc->sc_tx_process_limit, 0, CTL_CREATE, CTL_EOL); 1990 if (error) 1991 goto out; 1992 out: 1993 return error; 1994 } 1995 1996 static void 1997 iavf_teardown_sysctls(struct iavf_softc *sc) 1998 { 1999 2000 sysctl_teardown(&sc->sc_sysctllog); 2001 } 2002 2003 static int 2004 iavf_setup_stats(struct iavf_softc *sc) 2005 { 2006 struct iavf_stat_counters *isc; 2007 const char *dn; 2008 2009 dn = device_xname(sc->sc_dev); 2010 isc = &sc->sc_stat_counters; 2011 2012 iavf_evcnt_attach(&isc->isc_rx_bytes, dn, "Rx bytes"); 2013 iavf_evcnt_attach(&isc->isc_rx_unicast, dn, "Rx unicast"); 2014 iavf_evcnt_attach(&isc->isc_rx_multicast, dn, "Rx multicast"); 2015 iavf_evcnt_attach(&isc->isc_rx_broadcast, dn, "Rx broadcast"); 2016 iavf_evcnt_attach(&isc->isc_rx_discards, dn, "Rx discards"); 2017 iavf_evcnt_attach(&isc->isc_rx_unknown_protocol, 2018 dn, "Rx unknown protocol"); 2019 2020 iavf_evcnt_attach(&isc->isc_tx_bytes, dn, "Tx bytes"); 2021 iavf_evcnt_attach(&isc->isc_tx_unicast, dn, "Tx unicast"); 2022 iavf_evcnt_attach(&isc->isc_tx_multicast, dn, "Tx multicast"); 2023 iavf_evcnt_attach(&isc->isc_tx_broadcast, dn, "Tx broadcast"); 2024 iavf_evcnt_attach(&isc->isc_tx_discards, dn, "Tx discards"); 2025 iavf_evcnt_attach(&isc->isc_tx_errors, dn, "Tx errors"); 2026 2027 return 0; 2028 } 2029 2030 static void 2031 iavf_teardown_stats(struct iavf_softc *sc) 2032 { 2033 struct iavf_stat_counters *isc; 2034 2035 isc = &sc->sc_stat_counters; 2036 2037 evcnt_detach(&isc->isc_rx_bytes); 2038 evcnt_detach(&isc->isc_rx_unicast); 2039 evcnt_detach(&isc->isc_rx_multicast); 2040 evcnt_detach(&isc->isc_rx_broadcast); 2041 evcnt_detach(&isc->isc_rx_discards); 2042 evcnt_detach(&isc->isc_rx_unknown_protocol); 2043 2044 evcnt_detach(&isc->isc_tx_bytes); 2045 evcnt_detach(&isc->isc_tx_unicast); 2046 evcnt_detach(&isc->isc_tx_multicast); 2047 evcnt_detach(&isc->isc_tx_broadcast); 2048 evcnt_detach(&isc->isc_tx_discards); 2049 evcnt_detach(&isc->isc_tx_errors); 2050 2051 } 2052 2053 static int 2054 iavf_init_admin_queue(struct iavf_softc *sc) 2055 { 2056 uint32_t reg; 2057 2058 sc->sc_atq_cons = 0; 2059 sc->sc_atq_prod = 0; 2060 2061 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 2062 0, IXL_DMA_LEN(&sc->sc_atq), 2063 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2064 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_arq), 2065 0, IXL_DMA_LEN(&sc->sc_arq), 2066 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2067 2068 iavf_wr(sc, sc->sc_aq_regs->atq_head, 0); 2069 iavf_wr(sc, sc->sc_aq_regs->arq_head, 0); 2070 iavf_wr(sc, sc->sc_aq_regs->atq_tail, 0); 2071 iavf_wr(sc, sc->sc_aq_regs->arq_tail, 0); 2072 2073 iavf_barrier(sc, 0, sc->sc_mems, BUS_SPACE_BARRIER_WRITE); 2074 2075 iavf_wr(sc, sc->sc_aq_regs->atq_bal, 2076 ixl_dmamem_lo(&sc->sc_atq)); 2077 iavf_wr(sc, sc->sc_aq_regs->atq_bah, 2078 ixl_dmamem_hi(&sc->sc_atq)); 2079 iavf_wr(sc, sc->sc_aq_regs->atq_len, 2080 sc->sc_aq_regs->atq_len_enable | IAVF_AQ_NUM); 2081 2082 iavf_wr(sc, sc->sc_aq_regs->arq_bal, 2083 ixl_dmamem_lo(&sc->sc_arq)); 2084 iavf_wr(sc, sc->sc_aq_regs->arq_bah, 2085 ixl_dmamem_hi(&sc->sc_arq)); 2086 iavf_wr(sc, sc->sc_aq_regs->arq_len, 2087 sc->sc_aq_regs->arq_len_enable | IAVF_AQ_NUM); 2088 2089 iavf_wr(sc, sc->sc_aq_regs->arq_tail, sc->sc_arq_prod); 2090 2091 reg = iavf_rd(sc, sc->sc_aq_regs->atq_bal); 2092 if (reg != ixl_dmamem_lo(&sc->sc_atq)) 2093 goto fail; 2094 2095 reg = iavf_rd(sc, sc->sc_aq_regs->arq_bal); 2096 if (reg != ixl_dmamem_lo(&sc->sc_arq)) 2097 goto fail; 2098 2099 sc->sc_dead = false; 2100 return 0; 2101 2102 fail: 2103 iavf_wr(sc, sc->sc_aq_regs->atq_len, 0); 2104 iavf_wr(sc, sc->sc_aq_regs->arq_len, 0); 2105 return -1; 2106 } 2107 2108 static void 2109 iavf_cleanup_admin_queue(struct iavf_softc *sc) 2110 { 2111 struct ixl_aq_buf *aqb; 2112 2113 iavf_wr(sc, sc->sc_aq_regs->atq_head, 0); 2114 iavf_wr(sc, sc->sc_aq_regs->arq_head, 0); 2115 iavf_wr(sc, sc->sc_aq_regs->atq_tail, 0); 2116 iavf_wr(sc, sc->sc_aq_regs->arq_tail, 0); 2117 2118 iavf_wr(sc, sc->sc_aq_regs->atq_bal, 0); 2119 iavf_wr(sc, sc->sc_aq_regs->atq_bah, 0); 2120 iavf_wr(sc, sc->sc_aq_regs->atq_len, 0); 2121 2122 iavf_wr(sc, sc->sc_aq_regs->arq_bal, 0); 2123 iavf_wr(sc, sc->sc_aq_regs->arq_bah, 0); 2124 iavf_wr(sc, sc->sc_aq_regs->arq_len, 0); 2125 iavf_flush(sc); 2126 2127 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_arq), 2128 0, IXL_DMA_LEN(&sc->sc_arq), 2129 BUS_DMASYNC_POSTREAD); 2130 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 2131 0, IXL_DMA_LEN(&sc->sc_atq), 2132 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2133 2134 sc->sc_atq_cons = 0; 2135 sc->sc_atq_prod = 0; 2136 sc->sc_arq_cons = 0; 2137 sc->sc_arq_prod = 0; 2138 2139 memset(IXL_DMA_KVA(&sc->sc_arq), 0, IXL_DMA_LEN(&sc->sc_arq)); 2140 memset(IXL_DMA_KVA(&sc->sc_atq), 0, IXL_DMA_LEN(&sc->sc_atq)); 2141 2142 while ((aqb = iavf_aqb_get_locked(&sc->sc_arq_live)) != NULL) { 2143 bus_dmamap_sync(sc->sc_dmat, aqb->aqb_map, 0, aqb->aqb_size, 2144 BUS_DMASYNC_POSTREAD); 2145 iavf_aqb_put_locked(&sc->sc_arq_idle, aqb); 2146 } 2147 2148 while ((aqb = iavf_aqb_get_locked(&sc->sc_atq_live)) != NULL) { 2149 bus_dmamap_sync(sc->sc_dmat, aqb->aqb_map, 0, aqb->aqb_size, 2150 BUS_DMASYNC_POSTREAD); 2151 iavf_aqb_put_locked(&sc->sc_atq_idle, aqb); 2152 } 2153 } 2154 2155 static unsigned int 2156 iavf_calc_msix_count(struct iavf_softc *sc) 2157 { 2158 struct pci_attach_args *pa; 2159 int count; 2160 2161 pa = &sc->sc_pa; 2162 count = pci_msix_count(pa->pa_pc, pa->pa_tag); 2163 if (count < 0) { 2164 IAVF_LOG(sc, LOG_DEBUG,"MSIX config error\n"); 2165 count = 0; 2166 } 2167 2168 return MIN(sc->sc_max_vectors, (unsigned int)count); 2169 } 2170 2171 static unsigned int 2172 iavf_calc_queue_pair_size(struct iavf_softc *sc) 2173 { 2174 unsigned int nqp, nvec; 2175 2176 nvec = iavf_calc_msix_count(sc); 2177 if (sc->sc_max_vectors > 1) { 2178 /* decrease the number of misc interrupt */ 2179 nvec -= 1; 2180 } 2181 2182 nqp = ncpu; 2183 nqp = MIN(nqp, sc->sc_nqps_vsi); 2184 nqp = MIN(nqp, nvec); 2185 nqp = MIN(nqp, (unsigned int)iavf_params.max_qps); 2186 2187 return nqp; 2188 } 2189 2190 static struct iavf_tx_ring * 2191 iavf_txr_alloc(struct iavf_softc *sc, unsigned int qid) 2192 { 2193 struct iavf_tx_ring *txr; 2194 struct iavf_tx_map *maps; 2195 unsigned int i; 2196 int error; 2197 2198 txr = kmem_zalloc(sizeof(*txr), KM_NOSLEEP); 2199 if (txr == NULL) 2200 return NULL; 2201 2202 maps = kmem_zalloc(sizeof(maps[0]) * sc->sc_tx_ring_ndescs, 2203 KM_NOSLEEP); 2204 if (maps == NULL) 2205 goto free_txr; 2206 2207 if (iavf_dmamem_alloc(sc->sc_dmat, &txr->txr_mem, 2208 sizeof(struct ixl_tx_desc) * sc->sc_tx_ring_ndescs, 2209 IAVF_TX_QUEUE_ALIGN) != 0) { 2210 goto free_maps; 2211 } 2212 2213 for (i = 0; i < sc->sc_tx_ring_ndescs; i++) { 2214 error = bus_dmamap_create(sc->sc_dmat, IAVF_TX_PKT_MAXSIZE, 2215 IAVF_TX_PKT_DESCS, IAVF_TX_PKT_MAXSIZE, 0, 2216 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &maps[i].txm_map); 2217 if (error) 2218 goto destroy_maps; 2219 } 2220 2221 txr->txr_intrq = pcq_create(sc->sc_tx_ring_ndescs, KM_NOSLEEP); 2222 if (txr->txr_intrq == NULL) 2223 goto destroy_maps; 2224 2225 txr->txr_si = softint_establish(SOFTINT_NET|SOFTINT_MPSAFE, 2226 iavf_deferred_transmit, txr); 2227 if (txr->txr_si == NULL) 2228 goto destroy_pcq; 2229 2230 snprintf(txr->txr_name, sizeof(txr->txr_name), "%s-tx%d", 2231 device_xname(sc->sc_dev), qid); 2232 2233 iavf_evcnt_attach(&txr->txr_defragged, 2234 txr->txr_name, "m_defrag successed"); 2235 iavf_evcnt_attach(&txr->txr_defrag_failed, 2236 txr->txr_name, "m_defrag failed"); 2237 iavf_evcnt_attach(&txr->txr_pcqdrop, 2238 txr->txr_name, "Dropped in pcq"); 2239 iavf_evcnt_attach(&txr->txr_transmitdef, 2240 txr->txr_name, "Deferred transmit"); 2241 iavf_evcnt_attach(&txr->txr_watchdogto, 2242 txr->txr_name, "Watchdog timedout on queue"); 2243 iavf_evcnt_attach(&txr->txr_defer, 2244 txr->txr_name, "Handled queue in softint/workqueue"); 2245 2246 evcnt_attach_dynamic(&txr->txr_intr, EVCNT_TYPE_INTR, NULL, 2247 txr->txr_name, "Interrupt on queue"); 2248 2249 txr->txr_qid = qid; 2250 txr->txr_sc = sc; 2251 txr->txr_maps = maps; 2252 txr->txr_prod = txr->txr_cons = 0; 2253 txr->txr_tail = I40E_QTX_TAIL1(qid); 2254 mutex_init(&txr->txr_lock, MUTEX_DEFAULT, IPL_NET); 2255 2256 return txr; 2257 destroy_pcq: 2258 pcq_destroy(txr->txr_intrq); 2259 destroy_maps: 2260 for (i = 0; i < sc->sc_tx_ring_ndescs; i++) { 2261 if (maps[i].txm_map == NULL) 2262 continue; 2263 bus_dmamap_destroy(sc->sc_dmat, maps[i].txm_map); 2264 } 2265 2266 iavf_dmamem_free(sc->sc_dmat, &txr->txr_mem); 2267 free_maps: 2268 kmem_free(maps, sizeof(maps[0]) * sc->sc_tx_ring_ndescs); 2269 free_txr: 2270 kmem_free(txr, sizeof(*txr)); 2271 return NULL; 2272 } 2273 2274 static void 2275 iavf_txr_free(struct iavf_softc *sc, struct iavf_tx_ring *txr) 2276 { 2277 struct iavf_tx_map *maps; 2278 unsigned int i; 2279 2280 maps = txr->txr_maps; 2281 if (maps != NULL) { 2282 for (i = 0; i < sc->sc_tx_ring_ndescs; i++) { 2283 if (maps[i].txm_map == NULL) 2284 continue; 2285 bus_dmamap_destroy(sc->sc_dmat, maps[i].txm_map); 2286 } 2287 kmem_free(txr->txr_maps, 2288 sizeof(maps[0]) * sc->sc_tx_ring_ndescs); 2289 txr->txr_maps = NULL; 2290 } 2291 2292 evcnt_detach(&txr->txr_defragged); 2293 evcnt_detach(&txr->txr_defrag_failed); 2294 evcnt_detach(&txr->txr_pcqdrop); 2295 evcnt_detach(&txr->txr_transmitdef); 2296 evcnt_detach(&txr->txr_watchdogto); 2297 evcnt_detach(&txr->txr_defer); 2298 evcnt_detach(&txr->txr_intr); 2299 2300 iavf_dmamem_free(sc->sc_dmat, &txr->txr_mem); 2301 softint_disestablish(txr->txr_si); 2302 pcq_destroy(txr->txr_intrq); 2303 mutex_destroy(&txr->txr_lock); 2304 kmem_free(txr, sizeof(*txr)); 2305 } 2306 2307 static struct iavf_rx_ring * 2308 iavf_rxr_alloc(struct iavf_softc *sc, unsigned int qid) 2309 { 2310 struct iavf_rx_ring *rxr; 2311 struct iavf_rx_map *maps; 2312 unsigned int i; 2313 int error; 2314 2315 rxr = kmem_zalloc(sizeof(*rxr), KM_NOSLEEP); 2316 if (rxr == NULL) 2317 return NULL; 2318 2319 maps = kmem_zalloc(sizeof(maps[0]) * sc->sc_rx_ring_ndescs, 2320 KM_NOSLEEP); 2321 if (maps == NULL) 2322 goto free_rxr; 2323 2324 if (iavf_dmamem_alloc(sc->sc_dmat, &rxr->rxr_mem, 2325 sizeof(struct ixl_rx_rd_desc_32) * sc->sc_rx_ring_ndescs, 2326 IAVF_RX_QUEUE_ALIGN) != 0) 2327 goto free_maps; 2328 2329 for (i = 0; i < sc->sc_rx_ring_ndescs; i++) { 2330 error = bus_dmamap_create(sc->sc_dmat, IAVF_MCLBYTES, 2331 1, IAVF_MCLBYTES, 0, 2332 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &maps[i].rxm_map); 2333 if (error) 2334 goto destroy_maps; 2335 } 2336 2337 snprintf(rxr->rxr_name, sizeof(rxr->rxr_name), "%s-rx%d", 2338 device_xname(sc->sc_dev), qid); 2339 2340 iavf_evcnt_attach(&rxr->rxr_mgethdr_failed, 2341 rxr->rxr_name, "MGETHDR failed"); 2342 iavf_evcnt_attach(&rxr->rxr_mgetcl_failed, 2343 rxr->rxr_name, "MCLGET failed"); 2344 iavf_evcnt_attach(&rxr->rxr_mbuf_load_failed, 2345 rxr->rxr_name, "bus_dmamap_load_mbuf failed"); 2346 iavf_evcnt_attach(&rxr->rxr_defer, 2347 rxr->rxr_name, "Handled queue in softint/workqueue"); 2348 2349 evcnt_attach_dynamic(&rxr->rxr_intr, EVCNT_TYPE_INTR, NULL, 2350 rxr->rxr_name, "Interrupt on queue"); 2351 2352 rxr->rxr_qid = qid; 2353 rxr->rxr_sc = sc; 2354 rxr->rxr_cons = rxr->rxr_prod = 0; 2355 rxr->rxr_m_head = NULL; 2356 rxr->rxr_m_tail = &rxr->rxr_m_head; 2357 rxr->rxr_maps = maps; 2358 rxr->rxr_tail = I40E_QRX_TAIL1(qid); 2359 mutex_init(&rxr->rxr_lock, MUTEX_DEFAULT, IPL_NET); 2360 2361 return rxr; 2362 2363 destroy_maps: 2364 for (i = 0; i < sc->sc_rx_ring_ndescs; i++) { 2365 if (maps[i].rxm_map == NULL) 2366 continue; 2367 bus_dmamap_destroy(sc->sc_dmat, maps[i].rxm_map); 2368 } 2369 iavf_dmamem_free(sc->sc_dmat, &rxr->rxr_mem); 2370 free_maps: 2371 kmem_free(maps, sizeof(maps[0]) * sc->sc_rx_ring_ndescs); 2372 free_rxr: 2373 kmem_free(rxr, sizeof(*rxr)); 2374 2375 return NULL; 2376 } 2377 2378 static void 2379 iavf_rxr_free(struct iavf_softc *sc, struct iavf_rx_ring *rxr) 2380 { 2381 struct iavf_rx_map *maps; 2382 unsigned int i; 2383 2384 maps = rxr->rxr_maps; 2385 if (maps != NULL) { 2386 for (i = 0; i < sc->sc_rx_ring_ndescs; i++) { 2387 if (maps[i].rxm_map == NULL) 2388 continue; 2389 bus_dmamap_destroy(sc->sc_dmat, maps[i].rxm_map); 2390 } 2391 kmem_free(maps, sizeof(maps[0]) * sc->sc_rx_ring_ndescs); 2392 rxr->rxr_maps = NULL; 2393 } 2394 2395 evcnt_detach(&rxr->rxr_mgethdr_failed); 2396 evcnt_detach(&rxr->rxr_mgetcl_failed); 2397 evcnt_detach(&rxr->rxr_mbuf_load_failed); 2398 evcnt_detach(&rxr->rxr_defer); 2399 evcnt_detach(&rxr->rxr_intr); 2400 2401 iavf_dmamem_free(sc->sc_dmat, &rxr->rxr_mem); 2402 mutex_destroy(&rxr->rxr_lock); 2403 kmem_free(rxr, sizeof(*rxr)); 2404 } 2405 2406 static int 2407 iavf_queue_pairs_alloc(struct iavf_softc *sc) 2408 { 2409 struct iavf_queue_pair *qp; 2410 unsigned int i, num; 2411 2412 num = iavf_calc_queue_pair_size(sc); 2413 if (num <= 0) { 2414 return -1; 2415 } 2416 2417 sc->sc_qps = kmem_zalloc(sizeof(sc->sc_qps[0]) * num, KM_NOSLEEP); 2418 if (sc->sc_qps == NULL) { 2419 return -1; 2420 } 2421 2422 for (i = 0; i < num; i++) { 2423 qp = &sc->sc_qps[i]; 2424 2425 qp->qp_rxr = iavf_rxr_alloc(sc, i); 2426 qp->qp_txr = iavf_txr_alloc(sc, i); 2427 2428 if (qp->qp_rxr == NULL || qp->qp_txr == NULL) 2429 goto free; 2430 2431 qp->qp_si = softint_establish(SOFTINT_NET|SOFTINT_MPSAFE, 2432 iavf_handle_queue, qp); 2433 if (qp->qp_si == NULL) 2434 goto free; 2435 } 2436 2437 sc->sc_nqps_alloc = num; 2438 return 0; 2439 free: 2440 for (i = 0; i < num; i++) { 2441 qp = &sc->sc_qps[i]; 2442 2443 if (qp->qp_si != NULL) 2444 softint_disestablish(qp->qp_si); 2445 if (qp->qp_rxr != NULL) 2446 iavf_rxr_free(sc, qp->qp_rxr); 2447 if (qp->qp_txr != NULL) 2448 iavf_txr_free(sc, qp->qp_txr); 2449 } 2450 2451 kmem_free(sc->sc_qps, sizeof(sc->sc_qps[0]) * num); 2452 sc->sc_qps = NULL; 2453 2454 return -1; 2455 } 2456 2457 static void 2458 iavf_queue_pairs_free(struct iavf_softc *sc) 2459 { 2460 struct iavf_queue_pair *qp; 2461 unsigned int i; 2462 size_t sz; 2463 2464 if (sc->sc_qps == NULL) 2465 return; 2466 2467 for (i = 0; i < sc->sc_nqps_alloc; i++) { 2468 qp = &sc->sc_qps[i]; 2469 2470 if (qp->qp_si != NULL) 2471 softint_disestablish(qp->qp_si); 2472 if (qp->qp_rxr != NULL) 2473 iavf_rxr_free(sc, qp->qp_rxr); 2474 if (qp->qp_txr != NULL) 2475 iavf_txr_free(sc, qp->qp_txr); 2476 } 2477 2478 sz = sizeof(sc->sc_qps[0]) * sc->sc_nqps_alloc; 2479 kmem_free(sc->sc_qps, sz); 2480 sc->sc_qps = NULL; 2481 sc->sc_nqps_alloc = 0; 2482 } 2483 2484 static int 2485 iavf_rxfill(struct iavf_softc *sc, struct iavf_rx_ring *rxr) 2486 { 2487 struct ixl_rx_rd_desc_32 *ring, *rxd; 2488 struct iavf_rx_map *rxm; 2489 bus_dmamap_t map; 2490 struct mbuf *m; 2491 unsigned int slots, prod, mask; 2492 int error, post; 2493 2494 slots = ixl_rxr_unrefreshed(rxr->rxr_prod, rxr->rxr_cons, 2495 sc->sc_rx_ring_ndescs); 2496 2497 if (slots == 0) 2498 return 0; 2499 2500 error = 0; 2501 prod = rxr->rxr_prod; 2502 2503 ring = IXL_DMA_KVA(&rxr->rxr_mem); 2504 mask = sc->sc_rx_ring_ndescs - 1; 2505 2506 do { 2507 rxm = &rxr->rxr_maps[prod]; 2508 2509 MGETHDR(m, M_DONTWAIT, MT_DATA); 2510 if (m == NULL) { 2511 rxr->rxr_mgethdr_failed.ev_count++; 2512 error = -1; 2513 break; 2514 } 2515 2516 MCLGET(m, M_DONTWAIT); 2517 if (!ISSET(m->m_flags, M_EXT)) { 2518 rxr->rxr_mgetcl_failed.ev_count++; 2519 error = -1; 2520 m_freem(m); 2521 break; 2522 } 2523 2524 m->m_len = m->m_pkthdr.len = MCLBYTES; 2525 m_adj(m, ETHER_ALIGN); 2526 2527 map = rxm->rxm_map; 2528 2529 if (bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 2530 BUS_DMA_READ|BUS_DMA_NOWAIT) != 0) { 2531 rxr->rxr_mbuf_load_failed.ev_count++; 2532 error = -1; 2533 m_freem(m); 2534 break; 2535 } 2536 2537 rxm->rxm_m = m; 2538 2539 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 2540 BUS_DMASYNC_PREREAD); 2541 2542 rxd = &ring[prod]; 2543 rxd->paddr = htole64(map->dm_segs[0].ds_addr); 2544 rxd->haddr = htole64(0); 2545 2546 prod++; 2547 prod &= mask; 2548 post = 1; 2549 } while (--slots); 2550 2551 if (post) { 2552 rxr->rxr_prod = prod; 2553 iavf_wr(sc, rxr->rxr_tail, prod); 2554 } 2555 2556 return error; 2557 } 2558 2559 static inline void 2560 iavf_rx_csum(struct mbuf *m, uint64_t qword) 2561 { 2562 int flags_mask; 2563 2564 if (!ISSET(qword, IXL_RX_DESC_L3L4P)) { 2565 /* No L3 or L4 checksum was calculated */ 2566 return; 2567 } 2568 2569 switch (__SHIFTOUT(qword, IXL_RX_DESC_PTYPE_MASK)) { 2570 case IXL_RX_DESC_PTYPE_IPV4FRAG: 2571 case IXL_RX_DESC_PTYPE_IPV4: 2572 case IXL_RX_DESC_PTYPE_SCTPV4: 2573 case IXL_RX_DESC_PTYPE_ICMPV4: 2574 flags_mask = M_CSUM_IPv4 | M_CSUM_IPv4_BAD; 2575 break; 2576 case IXL_RX_DESC_PTYPE_TCPV4: 2577 flags_mask = M_CSUM_IPv4 | M_CSUM_IPv4_BAD; 2578 flags_mask |= M_CSUM_TCPv4 | M_CSUM_TCP_UDP_BAD; 2579 break; 2580 case IXL_RX_DESC_PTYPE_UDPV4: 2581 flags_mask = M_CSUM_IPv4 | M_CSUM_IPv4_BAD; 2582 flags_mask |= M_CSUM_UDPv4 | M_CSUM_TCP_UDP_BAD; 2583 break; 2584 case IXL_RX_DESC_PTYPE_TCPV6: 2585 flags_mask = M_CSUM_TCPv6 | M_CSUM_TCP_UDP_BAD; 2586 break; 2587 case IXL_RX_DESC_PTYPE_UDPV6: 2588 flags_mask = M_CSUM_UDPv6 | M_CSUM_TCP_UDP_BAD; 2589 break; 2590 default: 2591 flags_mask = 0; 2592 } 2593 2594 m->m_pkthdr.csum_flags |= (flags_mask & (M_CSUM_IPv4 | 2595 M_CSUM_TCPv4 | M_CSUM_TCPv6 | M_CSUM_UDPv4 | M_CSUM_UDPv6)); 2596 2597 if (ISSET(qword, IXL_RX_DESC_IPE)) { 2598 m->m_pkthdr.csum_flags |= (flags_mask & M_CSUM_IPv4_BAD); 2599 } 2600 2601 if (ISSET(qword, IXL_RX_DESC_L4E)) { 2602 m->m_pkthdr.csum_flags |= (flags_mask & M_CSUM_TCP_UDP_BAD); 2603 } 2604 } 2605 2606 static int 2607 iavf_rxeof(struct iavf_softc *sc, struct iavf_rx_ring *rxr, u_int rxlimit, 2608 struct evcnt *ecnt) 2609 { 2610 struct ifnet *ifp = &sc->sc_ec.ec_if; 2611 struct ixl_rx_wb_desc_32 *ring, *rxd; 2612 struct iavf_rx_map *rxm; 2613 bus_dmamap_t map; 2614 unsigned int cons, prod; 2615 struct mbuf *m; 2616 uint64_t word, word0; 2617 unsigned int len; 2618 unsigned int mask; 2619 int done = 0, more = 0; 2620 2621 KASSERT(mutex_owned(&rxr->rxr_lock)); 2622 2623 if (!ISSET(ifp->if_flags, IFF_RUNNING)) 2624 return 0; 2625 2626 prod = rxr->rxr_prod; 2627 cons = rxr->rxr_cons; 2628 2629 if (cons == prod) 2630 return 0; 2631 2632 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&rxr->rxr_mem), 2633 0, IXL_DMA_LEN(&rxr->rxr_mem), 2634 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2635 2636 ring = IXL_DMA_KVA(&rxr->rxr_mem); 2637 mask = sc->sc_rx_ring_ndescs - 1; 2638 2639 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 2640 2641 do { 2642 if (rxlimit-- <= 0) { 2643 more = 1; 2644 break; 2645 } 2646 2647 rxd = &ring[cons]; 2648 2649 word = le64toh(rxd->qword1); 2650 2651 if (!ISSET(word, IXL_RX_DESC_DD)) 2652 break; 2653 2654 rxm = &rxr->rxr_maps[cons]; 2655 2656 map = rxm->rxm_map; 2657 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 2658 BUS_DMASYNC_POSTREAD); 2659 bus_dmamap_unload(sc->sc_dmat, map); 2660 2661 m = rxm->rxm_m; 2662 rxm->rxm_m = NULL; 2663 2664 KASSERT(m != NULL); 2665 2666 len = (word & IXL_RX_DESC_PLEN_MASK) >> IXL_RX_DESC_PLEN_SHIFT; 2667 m->m_len = len; 2668 m->m_pkthdr.len = 0; 2669 2670 m->m_next = NULL; 2671 *rxr->rxr_m_tail = m; 2672 rxr->rxr_m_tail = &m->m_next; 2673 2674 m = rxr->rxr_m_head; 2675 m->m_pkthdr.len += len; 2676 2677 if (ISSET(word, IXL_RX_DESC_EOP)) { 2678 word0 = le64toh(rxd->qword0); 2679 2680 if (ISSET(word, IXL_RX_DESC_L2TAG1P)) { 2681 vlan_set_tag(m, 2682 __SHIFTOUT(word0, IXL_RX_DESC_L2TAG1_MASK)); 2683 } 2684 2685 if ((ifp->if_capenable & IAVF_IFCAP_RXCSUM) != 0) 2686 iavf_rx_csum(m, word); 2687 2688 if (!ISSET(word, 2689 IXL_RX_DESC_RXE | IXL_RX_DESC_OVERSIZE)) { 2690 m_set_rcvif(m, ifp); 2691 if_statinc_ref(nsr, if_ipackets); 2692 if_statadd_ref(nsr, if_ibytes, 2693 m->m_pkthdr.len); 2694 if_percpuq_enqueue(sc->sc_ipq, m); 2695 } else { 2696 if_statinc_ref(nsr, if_ierrors); 2697 m_freem(m); 2698 } 2699 2700 rxr->rxr_m_head = NULL; 2701 rxr->rxr_m_tail = &rxr->rxr_m_head; 2702 } 2703 2704 cons++; 2705 cons &= mask; 2706 2707 done = 1; 2708 } while (cons != prod); 2709 2710 if (done) { 2711 ecnt->ev_count++; 2712 rxr->rxr_cons = cons; 2713 if (iavf_rxfill(sc, rxr) == -1) 2714 if_statinc_ref(nsr, if_iqdrops); 2715 } 2716 2717 IF_STAT_PUTREF(ifp); 2718 2719 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&rxr->rxr_mem), 2720 0, IXL_DMA_LEN(&rxr->rxr_mem), 2721 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2722 2723 return more; 2724 } 2725 2726 static void 2727 iavf_rxr_clean(struct iavf_softc *sc, struct iavf_rx_ring *rxr) 2728 { 2729 struct iavf_rx_map *maps, *rxm; 2730 bus_dmamap_t map; 2731 unsigned int i; 2732 2733 KASSERT(mutex_owned(&rxr->rxr_lock)); 2734 2735 maps = rxr->rxr_maps; 2736 for (i = 0; i < sc->sc_rx_ring_ndescs; i++) { 2737 rxm = &maps[i]; 2738 2739 if (rxm->rxm_m == NULL) 2740 continue; 2741 2742 map = rxm->rxm_map; 2743 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 2744 BUS_DMASYNC_POSTWRITE); 2745 bus_dmamap_unload(sc->sc_dmat, map); 2746 2747 m_freem(rxm->rxm_m); 2748 rxm->rxm_m = NULL; 2749 } 2750 2751 m_freem(rxr->rxr_m_head); 2752 rxr->rxr_m_head = NULL; 2753 rxr->rxr_m_tail = &rxr->rxr_m_head; 2754 2755 memset(IXL_DMA_KVA(&rxr->rxr_mem), 0, IXL_DMA_LEN(&rxr->rxr_mem)); 2756 rxr->rxr_prod = rxr->rxr_cons = 0; 2757 } 2758 2759 static int 2760 iavf_txeof(struct iavf_softc *sc, struct iavf_tx_ring *txr, u_int txlimit, 2761 struct evcnt *ecnt) 2762 { 2763 struct ifnet *ifp = &sc->sc_ec.ec_if; 2764 struct ixl_tx_desc *ring, *txd; 2765 struct iavf_tx_map *txm; 2766 struct mbuf *m; 2767 bus_dmamap_t map; 2768 unsigned int cons, prod, last; 2769 unsigned int mask; 2770 uint64_t dtype; 2771 int done = 0, more = 0; 2772 2773 KASSERT(mutex_owned(&txr->txr_lock)); 2774 2775 prod = txr->txr_prod; 2776 cons = txr->txr_cons; 2777 2778 if (cons == prod) 2779 return 0; 2780 2781 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&txr->txr_mem), 2782 0, IXL_DMA_LEN(&txr->txr_mem), BUS_DMASYNC_POSTREAD); 2783 2784 ring = IXL_DMA_KVA(&txr->txr_mem); 2785 mask = sc->sc_tx_ring_ndescs - 1; 2786 2787 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 2788 2789 do { 2790 if (txlimit-- <= 0) { 2791 more = 1; 2792 break; 2793 } 2794 2795 txm = &txr->txr_maps[cons]; 2796 last = txm->txm_eop; 2797 txd = &ring[last]; 2798 2799 dtype = txd->cmd & htole64(IXL_TX_DESC_DTYPE_MASK); 2800 if (dtype != htole64(IXL_TX_DESC_DTYPE_DONE)) 2801 break; 2802 2803 map = txm->txm_map; 2804 2805 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 2806 BUS_DMASYNC_POSTWRITE); 2807 bus_dmamap_unload(sc->sc_dmat, map); 2808 2809 m = txm->txm_m; 2810 if (m != NULL) { 2811 if_statinc_ref(nsr, if_opackets); 2812 if_statadd_ref(nsr, if_obytes, m->m_pkthdr.len); 2813 if (ISSET(m->m_flags, M_MCAST)) 2814 if_statinc_ref(nsr, if_omcasts); 2815 m_freem(m); 2816 } 2817 2818 txm->txm_m = NULL; 2819 txm->txm_eop = -1; 2820 2821 cons = last + 1; 2822 cons &= mask; 2823 done = 1; 2824 } while (cons != prod); 2825 2826 IF_STAT_PUTREF(ifp); 2827 2828 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&txr->txr_mem), 2829 0, IXL_DMA_LEN(&txr->txr_mem), BUS_DMASYNC_PREREAD); 2830 2831 txr->txr_cons = cons; 2832 2833 if (done) { 2834 ecnt->ev_count++; 2835 softint_schedule(txr->txr_si); 2836 if (txr->txr_qid == 0) { 2837 CLR(ifp->if_flags, IFF_OACTIVE); 2838 if_schedule_deferred_start(ifp); 2839 } 2840 } 2841 2842 if (txr->txr_cons == txr->txr_prod) { 2843 txr->txr_watchdog = IAVF_WATCHDOG_STOP; 2844 } 2845 2846 return more; 2847 } 2848 2849 static inline int 2850 iavf_load_mbuf(bus_dma_tag_t dmat, bus_dmamap_t map, struct mbuf **m0, 2851 struct iavf_tx_ring *txr) 2852 { 2853 struct mbuf *m; 2854 int error; 2855 2856 KASSERT(mutex_owned(&txr->txr_lock)); 2857 2858 m = *m0; 2859 2860 error = bus_dmamap_load_mbuf(dmat, map, m, 2861 BUS_DMA_STREAMING|BUS_DMA_WRITE|BUS_DMA_NOWAIT); 2862 if (error != EFBIG) 2863 return error; 2864 2865 m = m_defrag(m, M_DONTWAIT); 2866 if (m != NULL) { 2867 *m0 = m; 2868 txr->txr_defragged.ev_count++; 2869 error = bus_dmamap_load_mbuf(dmat, map, m, 2870 BUS_DMA_STREAMING|BUS_DMA_WRITE|BUS_DMA_NOWAIT); 2871 } else { 2872 txr->txr_defrag_failed.ev_count++; 2873 error = ENOBUFS; 2874 } 2875 2876 return error; 2877 } 2878 2879 static inline int 2880 iavf_tx_setup_offloads(struct mbuf *m, uint64_t *cmd_txd) 2881 { 2882 struct ether_header *eh; 2883 size_t len; 2884 uint64_t cmd; 2885 2886 cmd = 0; 2887 2888 eh = mtod(m, struct ether_header *); 2889 switch (htons(eh->ether_type)) { 2890 case ETHERTYPE_IP: 2891 case ETHERTYPE_IPV6: 2892 len = ETHER_HDR_LEN; 2893 break; 2894 case ETHERTYPE_VLAN: 2895 len = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2896 break; 2897 default: 2898 len = 0; 2899 } 2900 cmd |= ((len >> 1) << IXL_TX_DESC_MACLEN_SHIFT); 2901 2902 if (m->m_pkthdr.csum_flags & 2903 (M_CSUM_TSOv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 2904 cmd |= IXL_TX_DESC_CMD_IIPT_IPV4; 2905 } 2906 if (m->m_pkthdr.csum_flags & M_CSUM_IPv4) { 2907 cmd |= IXL_TX_DESC_CMD_IIPT_IPV4_CSUM; 2908 } 2909 2910 if (m->m_pkthdr.csum_flags & 2911 (M_CSUM_TSOv6 | M_CSUM_TCPv6 | M_CSUM_UDPv6)) { 2912 cmd |= IXL_TX_DESC_CMD_IIPT_IPV6; 2913 } 2914 2915 switch (cmd & IXL_TX_DESC_CMD_IIPT_MASK) { 2916 case IXL_TX_DESC_CMD_IIPT_IPV4: 2917 case IXL_TX_DESC_CMD_IIPT_IPV4_CSUM: 2918 len = M_CSUM_DATA_IPv4_IPHL(m->m_pkthdr.csum_data); 2919 break; 2920 case IXL_TX_DESC_CMD_IIPT_IPV6: 2921 len = M_CSUM_DATA_IPv6_IPHL(m->m_pkthdr.csum_data); 2922 break; 2923 default: 2924 len = 0; 2925 } 2926 cmd |= ((len >> 2) << IXL_TX_DESC_IPLEN_SHIFT); 2927 2928 if (m->m_pkthdr.csum_flags & 2929 (M_CSUM_TSOv4 | M_CSUM_TSOv6 | M_CSUM_TCPv4 | M_CSUM_TCPv6)) { 2930 len = sizeof(struct tcphdr); 2931 cmd |= IXL_TX_DESC_CMD_L4T_EOFT_TCP; 2932 } else if (m->m_pkthdr.csum_flags & (M_CSUM_UDPv4 | M_CSUM_UDPv6)) { 2933 len = sizeof(struct udphdr); 2934 cmd |= IXL_TX_DESC_CMD_L4T_EOFT_UDP; 2935 } else { 2936 len = 0; 2937 } 2938 cmd |= ((len >> 2) << IXL_TX_DESC_L4LEN_SHIFT); 2939 2940 *cmd_txd |= cmd; 2941 return 0; 2942 } 2943 2944 static void 2945 iavf_tx_common_locked(struct ifnet *ifp, struct iavf_tx_ring *txr, 2946 bool is_transmit) 2947 { 2948 struct iavf_softc *sc; 2949 struct ixl_tx_desc *ring, *txd; 2950 struct iavf_tx_map *txm; 2951 bus_dmamap_t map; 2952 struct mbuf *m; 2953 unsigned int prod, free, last, i; 2954 unsigned int mask; 2955 uint64_t cmd, cmd_txd; 2956 int post = 0; 2957 2958 KASSERT(mutex_owned(&txr->txr_lock)); 2959 2960 sc = ifp->if_softc; 2961 2962 if (!ISSET(ifp->if_flags, IFF_RUNNING) 2963 || (!is_transmit && ISSET(ifp->if_flags, IFF_OACTIVE))) { 2964 if (!is_transmit) 2965 IFQ_PURGE(&ifp->if_snd); 2966 return; 2967 } 2968 2969 prod = txr->txr_prod; 2970 free = txr->txr_cons; 2971 2972 if (free <= prod) 2973 free += sc->sc_tx_ring_ndescs; 2974 free -= prod; 2975 2976 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&txr->txr_mem), 2977 0, IXL_DMA_LEN(&txr->txr_mem), BUS_DMASYNC_POSTWRITE); 2978 2979 ring = IXL_DMA_KVA(&txr->txr_mem); 2980 mask = sc->sc_tx_ring_ndescs - 1; 2981 last = prod; 2982 cmd = 0; 2983 txd = NULL; 2984 2985 for (;;) { 2986 if (free < IAVF_TX_PKT_DESCS) { 2987 if (!is_transmit) 2988 SET(ifp->if_flags, IFF_OACTIVE); 2989 break; 2990 } 2991 2992 if (is_transmit) 2993 m = pcq_get(txr->txr_intrq); 2994 else 2995 IFQ_DEQUEUE(&ifp->if_snd, m); 2996 2997 if (m == NULL) 2998 break; 2999 3000 txm = &txr->txr_maps[prod]; 3001 map = txm->txm_map; 3002 3003 if (iavf_load_mbuf(sc->sc_dmat, map, &m, txr) != 0) { 3004 if_statinc(ifp, if_oerrors); 3005 m_freem(m); 3006 continue; 3007 } 3008 3009 cmd_txd = 0; 3010 if (m->m_pkthdr.csum_flags & IAVF_CSUM_ALL_OFFLOAD) { 3011 iavf_tx_setup_offloads(m, &cmd_txd); 3012 } 3013 if (vlan_has_tag(m)) { 3014 cmd_txd |= IXL_TX_DESC_CMD_IL2TAG1 | 3015 ((uint64_t)vlan_get_tag(m) 3016 << IXL_TX_DESC_L2TAG1_SHIFT); 3017 } 3018 3019 bus_dmamap_sync(sc->sc_dmat, map, 0, 3020 map->dm_mapsize, BUS_DMASYNC_PREWRITE); 3021 3022 for (i = 0; i < (unsigned int)map->dm_nsegs; i++) { 3023 txd = &ring[prod]; 3024 3025 cmd = (uint64_t)map->dm_segs[i].ds_len << 3026 IXL_TX_DESC_BSIZE_SHIFT; 3027 cmd |= IXL_TX_DESC_DTYPE_DATA|IXL_TX_DESC_CMD_ICRC| 3028 cmd_txd; 3029 3030 txd->addr = htole64(map->dm_segs[i].ds_addr); 3031 txd->cmd = htole64(cmd); 3032 3033 last = prod; 3034 prod++; 3035 prod &= mask; 3036 } 3037 3038 cmd |= IXL_TX_DESC_CMD_EOP|IXL_TX_DESC_CMD_RS; 3039 txd->cmd = htole64(cmd); 3040 txm->txm_m = m; 3041 txm->txm_eop = last; 3042 3043 bpf_mtap(ifp, m, BPF_D_OUT); 3044 free -= i; 3045 post = 1; 3046 } 3047 3048 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&txr->txr_mem), 3049 0, IXL_DMA_LEN(&txr->txr_mem), BUS_DMASYNC_PREWRITE); 3050 3051 if (post) { 3052 txr->txr_prod = prod; 3053 iavf_wr(sc, txr->txr_tail, prod); 3054 txr->txr_watchdog = IAVF_WATCHDOG_TICKS; 3055 } 3056 } 3057 3058 static inline int 3059 iavf_handle_queue_common(struct iavf_softc *sc, struct iavf_queue_pair *qp, 3060 u_int txlimit, struct evcnt *txevcnt, 3061 u_int rxlimit, struct evcnt *rxevcnt) 3062 { 3063 struct iavf_tx_ring *txr; 3064 struct iavf_rx_ring *rxr; 3065 int txmore, rxmore; 3066 int rv; 3067 3068 txr = qp->qp_txr; 3069 rxr = qp->qp_rxr; 3070 3071 mutex_enter(&txr->txr_lock); 3072 txmore = iavf_txeof(sc, txr, txlimit, txevcnt); 3073 mutex_exit(&txr->txr_lock); 3074 3075 mutex_enter(&rxr->rxr_lock); 3076 rxmore = iavf_rxeof(sc, rxr, rxlimit, rxevcnt); 3077 mutex_exit(&rxr->rxr_lock); 3078 3079 rv = txmore | (rxmore << 1); 3080 3081 return rv; 3082 } 3083 3084 static void 3085 iavf_sched_handle_queue(struct iavf_softc *sc, struct iavf_queue_pair *qp) 3086 { 3087 3088 if (qp->qp_workqueue) 3089 workqueue_enqueue(sc->sc_workq_txrx, &qp->qp_work, NULL); 3090 else 3091 softint_schedule(qp->qp_si); 3092 } 3093 3094 static void 3095 iavf_start(struct ifnet *ifp) 3096 { 3097 struct iavf_softc *sc; 3098 struct iavf_tx_ring *txr; 3099 3100 sc = ifp->if_softc; 3101 txr = sc->sc_qps[0].qp_txr; 3102 3103 mutex_enter(&txr->txr_lock); 3104 iavf_tx_common_locked(ifp, txr, false); 3105 mutex_exit(&txr->txr_lock); 3106 3107 } 3108 3109 static inline unsigned int 3110 iavf_select_txqueue(struct iavf_softc *sc, struct mbuf *m) 3111 { 3112 u_int cpuid; 3113 3114 cpuid = cpu_index(curcpu()); 3115 3116 return (unsigned int)(cpuid % sc->sc_nqueue_pairs); 3117 } 3118 3119 static int 3120 iavf_transmit(struct ifnet *ifp, struct mbuf *m) 3121 { 3122 struct iavf_softc *sc; 3123 struct iavf_tx_ring *txr; 3124 unsigned int qid; 3125 3126 sc = ifp->if_softc; 3127 qid = iavf_select_txqueue(sc, m); 3128 3129 txr = sc->sc_qps[qid].qp_txr; 3130 3131 if (__predict_false(!pcq_put(txr->txr_intrq, m))) { 3132 mutex_enter(&txr->txr_lock); 3133 txr->txr_pcqdrop.ev_count++; 3134 mutex_exit(&txr->txr_lock); 3135 3136 m_freem(m); 3137 return ENOBUFS; 3138 } 3139 3140 if (mutex_tryenter(&txr->txr_lock)) { 3141 iavf_tx_common_locked(ifp, txr, true); 3142 mutex_exit(&txr->txr_lock); 3143 } else { 3144 kpreempt_disable(); 3145 softint_schedule(txr->txr_si); 3146 kpreempt_enable(); 3147 } 3148 return 0; 3149 } 3150 3151 static void 3152 iavf_deferred_transmit(void *xtxr) 3153 { 3154 struct iavf_tx_ring *txr; 3155 struct iavf_softc *sc; 3156 struct ifnet *ifp; 3157 3158 txr = xtxr; 3159 sc = txr->txr_sc; 3160 ifp = &sc->sc_ec.ec_if; 3161 3162 mutex_enter(&txr->txr_lock); 3163 txr->txr_transmitdef.ev_count++; 3164 if (pcq_peek(txr->txr_intrq) != NULL) 3165 iavf_tx_common_locked(ifp, txr, true); 3166 mutex_exit(&txr->txr_lock); 3167 } 3168 3169 static void 3170 iavf_txr_clean(struct iavf_softc *sc, struct iavf_tx_ring *txr) 3171 { 3172 struct iavf_tx_map *maps, *txm; 3173 bus_dmamap_t map; 3174 unsigned int i; 3175 3176 KASSERT(mutex_owned(&txr->txr_lock)); 3177 3178 maps = txr->txr_maps; 3179 for (i = 0; i < sc->sc_tx_ring_ndescs; i++) { 3180 txm = &maps[i]; 3181 3182 if (txm->txm_m == NULL) 3183 continue; 3184 3185 map = txm->txm_map; 3186 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 3187 BUS_DMASYNC_POSTWRITE); 3188 bus_dmamap_unload(sc->sc_dmat, map); 3189 3190 m_freem(txm->txm_m); 3191 txm->txm_m = NULL; 3192 } 3193 3194 memset(IXL_DMA_KVA(&txr->txr_mem), 0, IXL_DMA_LEN(&txr->txr_mem)); 3195 txr->txr_prod = txr->txr_cons = 0; 3196 } 3197 3198 static int 3199 iavf_intr(void *xsc) 3200 { 3201 struct iavf_softc *sc = xsc; 3202 struct ifnet *ifp = &sc->sc_ec.ec_if; 3203 struct iavf_rx_ring *rxr; 3204 struct iavf_tx_ring *txr; 3205 uint32_t icr; 3206 unsigned int i; 3207 3208 /* read I40E_VFINT_ICR_ENA1 to clear status */ 3209 (void)iavf_rd(sc, I40E_VFINT_ICR0_ENA1); 3210 3211 iavf_intr_enable(sc); 3212 icr = iavf_rd(sc, I40E_VFINT_ICR01); 3213 3214 if (icr == IAVF_REG_VFR) { 3215 log(LOG_INFO, "%s: VF reset in progress\n", 3216 ifp->if_xname); 3217 iavf_work_set(&sc->sc_reset_task, iavf_reset_start, sc); 3218 iavf_work_add(sc->sc_workq, &sc->sc_reset_task); 3219 return 1; 3220 } 3221 3222 if (ISSET(icr, I40E_VFINT_ICR01_ADMINQ_MASK)) { 3223 mutex_enter(&sc->sc_adminq_lock); 3224 iavf_atq_done(sc); 3225 iavf_arq(sc); 3226 mutex_exit(&sc->sc_adminq_lock); 3227 } 3228 3229 if (ISSET(icr, I40E_VFINT_ICR01_QUEUE_0_MASK)) { 3230 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 3231 rxr = sc->sc_qps[i].qp_rxr; 3232 txr = sc->sc_qps[i].qp_txr; 3233 3234 mutex_enter(&rxr->rxr_lock); 3235 while (iavf_rxeof(sc, rxr, UINT_MAX, 3236 &rxr->rxr_intr) != 0) { 3237 /* do nothing */ 3238 } 3239 mutex_exit(&rxr->rxr_lock); 3240 3241 mutex_enter(&txr->txr_lock); 3242 while (iavf_txeof(sc, txr, UINT_MAX, 3243 &txr->txr_intr) != 0) { 3244 /* do nothing */ 3245 } 3246 mutex_exit(&txr->txr_lock); 3247 } 3248 } 3249 3250 return 0; 3251 } 3252 3253 static int 3254 iavf_queue_intr(void *xqp) 3255 { 3256 struct iavf_queue_pair *qp = xqp; 3257 struct iavf_tx_ring *txr; 3258 struct iavf_rx_ring *rxr; 3259 struct iavf_softc *sc; 3260 unsigned int qid; 3261 u_int txlimit, rxlimit; 3262 int more; 3263 3264 txr = qp->qp_txr; 3265 rxr = qp->qp_rxr; 3266 sc = txr->txr_sc; 3267 qid = txr->txr_qid; 3268 3269 txlimit = sc->sc_tx_intr_process_limit; 3270 rxlimit = sc->sc_rx_intr_process_limit; 3271 qp->qp_workqueue = sc->sc_txrx_workqueue; 3272 3273 more = iavf_handle_queue_common(sc, qp, 3274 txlimit, &txr->txr_intr, rxlimit, &rxr->rxr_intr); 3275 3276 if (more != 0) { 3277 iavf_sched_handle_queue(sc, qp); 3278 } else { 3279 /* for ALTQ */ 3280 if (txr->txr_qid == 0) 3281 if_schedule_deferred_start(&sc->sc_ec.ec_if); 3282 softint_schedule(txr->txr_si); 3283 3284 iavf_queue_intr_enable(sc, qid); 3285 } 3286 3287 return 0; 3288 } 3289 3290 static void 3291 iavf_handle_queue_wk(struct work *wk, void *xsc __unused) 3292 { 3293 struct iavf_queue_pair *qp; 3294 3295 qp = container_of(wk, struct iavf_queue_pair, qp_work); 3296 iavf_handle_queue(qp); 3297 } 3298 3299 static void 3300 iavf_handle_queue(void *xqp) 3301 { 3302 struct iavf_queue_pair *qp = xqp; 3303 struct iavf_tx_ring *txr; 3304 struct iavf_rx_ring *rxr; 3305 struct iavf_softc *sc; 3306 unsigned int qid; 3307 u_int txlimit, rxlimit; 3308 int more; 3309 3310 txr = qp->qp_txr; 3311 rxr = qp->qp_rxr; 3312 sc = txr->txr_sc; 3313 qid = txr->txr_qid; 3314 3315 txlimit = sc->sc_tx_process_limit; 3316 rxlimit = sc->sc_rx_process_limit; 3317 3318 more = iavf_handle_queue_common(sc, qp, 3319 txlimit, &txr->txr_defer, rxlimit, &rxr->rxr_defer); 3320 3321 if (more != 0) 3322 iavf_sched_handle_queue(sc, qp); 3323 else 3324 iavf_queue_intr_enable(sc, qid); 3325 } 3326 3327 static void 3328 iavf_tick(void *xsc) 3329 { 3330 struct iavf_softc *sc; 3331 unsigned int i; 3332 int timedout; 3333 3334 sc = xsc; 3335 timedout = 0; 3336 3337 mutex_enter(&sc->sc_cfg_lock); 3338 3339 if (sc->sc_resetting) { 3340 iavf_work_add(sc->sc_workq, &sc->sc_reset_task); 3341 mutex_exit(&sc->sc_cfg_lock); 3342 return; 3343 } 3344 3345 iavf_get_stats(sc); 3346 3347 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 3348 timedout |= iavf_watchdog(sc->sc_qps[i].qp_txr); 3349 } 3350 3351 if (timedout != 0) { 3352 iavf_work_add(sc->sc_workq, &sc->sc_wdto_task); 3353 } else { 3354 callout_schedule(&sc->sc_tick, IAVF_TICK_INTERVAL); 3355 } 3356 3357 mutex_exit(&sc->sc_cfg_lock); 3358 } 3359 3360 static void 3361 iavf_tick_halt(void *unused __unused) 3362 { 3363 3364 /* do nothing */ 3365 } 3366 3367 static void 3368 iavf_reset_request(void *xsc) 3369 { 3370 struct iavf_softc *sc = xsc; 3371 3372 iavf_reset_vf(sc); 3373 iavf_reset_start(sc); 3374 } 3375 3376 static void 3377 iavf_reset_start(void *xsc) 3378 { 3379 struct iavf_softc *sc = xsc; 3380 struct ifnet *ifp = &sc->sc_ec.ec_if; 3381 3382 mutex_enter(&sc->sc_cfg_lock); 3383 3384 if (sc->sc_resetting) 3385 goto do_reset; 3386 3387 sc->sc_resetting = true; 3388 if_link_state_change(ifp, LINK_STATE_DOWN); 3389 3390 if (ISSET(ifp->if_flags, IFF_RUNNING)) { 3391 iavf_stop_locked(sc); 3392 sc->sc_reset_up = true; 3393 } 3394 3395 memcpy(sc->sc_enaddr_reset, sc->sc_enaddr, ETHER_ADDR_LEN); 3396 3397 do_reset: 3398 iavf_work_set(&sc->sc_reset_task, iavf_reset, sc); 3399 3400 mutex_exit(&sc->sc_cfg_lock); 3401 3402 iavf_reset((void *)sc); 3403 } 3404 3405 static void 3406 iavf_reset(void *xsc) 3407 { 3408 struct iavf_softc *sc = xsc; 3409 struct ifnet *ifp = &sc->sc_ec.ec_if; 3410 struct ixl_aq_buf *aqb; 3411 bool realloc_qps, realloc_intrs; 3412 3413 mutex_enter(&sc->sc_cfg_lock); 3414 3415 mutex_enter(&sc->sc_adminq_lock); 3416 iavf_cleanup_admin_queue(sc); 3417 mutex_exit(&sc->sc_adminq_lock); 3418 3419 sc->sc_major_ver = UINT_MAX; 3420 sc->sc_minor_ver = UINT_MAX; 3421 sc->sc_got_vf_resources = 0; 3422 sc->sc_got_irq_map = 0; 3423 3424 aqb = iavf_aqb_get(sc, &sc->sc_atq_idle); 3425 if (aqb == NULL) 3426 goto failed; 3427 3428 if (iavf_wait_active(sc) != 0) { 3429 log(LOG_WARNING, "%s: VF reset timed out\n", 3430 ifp->if_xname); 3431 goto failed; 3432 } 3433 3434 if (!iavf_arq_fill(sc)) { 3435 log(LOG_ERR, "%s: unable to fill arq descriptors\n", 3436 ifp->if_xname); 3437 goto failed; 3438 } 3439 3440 if (iavf_init_admin_queue(sc) != 0) { 3441 log(LOG_ERR, "%s: unable to initialize admin queue\n", 3442 ifp->if_xname); 3443 goto failed; 3444 } 3445 3446 if (iavf_get_version(sc, aqb) != 0) { 3447 log(LOG_ERR, "%s: unable to get VF interface version\n", 3448 ifp->if_xname); 3449 goto failed; 3450 } 3451 3452 if (iavf_get_vf_resources(sc, aqb) != 0) { 3453 log(LOG_ERR, "%s: timed out waiting for VF resources\n", 3454 ifp->if_xname); 3455 goto failed; 3456 } 3457 3458 if (sc->sc_nqps_alloc < iavf_calc_queue_pair_size(sc)) { 3459 realloc_qps = true; 3460 } else { 3461 realloc_qps = false; 3462 } 3463 3464 if (sc->sc_nintrs < iavf_calc_msix_count(sc)) { 3465 realloc_intrs = true; 3466 } else { 3467 realloc_intrs = false; 3468 } 3469 3470 if (realloc_qps || realloc_intrs) 3471 iavf_teardown_interrupts(sc); 3472 3473 if (realloc_qps) { 3474 iavf_queue_pairs_free(sc); 3475 if (iavf_queue_pairs_alloc(sc) != 0) { 3476 log(LOG_ERR, "%s: failed to allocate queue pairs\n", 3477 ifp->if_xname); 3478 goto failed; 3479 } 3480 } 3481 3482 if (realloc_qps || realloc_intrs) { 3483 if (iavf_setup_interrupts(sc) != 0) { 3484 sc->sc_nintrs = 0; 3485 log(LOG_ERR, "%s: failed to allocate interrupts\n", 3486 ifp->if_xname); 3487 goto failed; 3488 } 3489 log(LOG_INFO, "%s: reallocated queues\n", ifp->if_xname); 3490 } 3491 3492 if (iavf_config_irq_map(sc, aqb) != 0) { 3493 log(LOG_ERR, "%s: timed out configuring IRQ map\n", 3494 ifp->if_xname); 3495 goto failed; 3496 } 3497 3498 mutex_enter(&sc->sc_adminq_lock); 3499 iavf_aqb_put_locked(&sc->sc_atq_idle, aqb); 3500 mutex_exit(&sc->sc_adminq_lock); 3501 3502 iavf_reset_finish(sc); 3503 3504 mutex_exit(&sc->sc_cfg_lock); 3505 return; 3506 3507 failed: 3508 mutex_enter(&sc->sc_adminq_lock); 3509 iavf_cleanup_admin_queue(sc); 3510 if (aqb != NULL) { 3511 iavf_aqb_put_locked(&sc->sc_atq_idle, aqb); 3512 } 3513 mutex_exit(&sc->sc_adminq_lock); 3514 callout_schedule(&sc->sc_tick, IAVF_TICK_INTERVAL); 3515 mutex_exit(&sc->sc_cfg_lock); 3516 } 3517 3518 static void 3519 iavf_reset_finish(struct iavf_softc *sc) 3520 { 3521 struct ethercom *ec = &sc->sc_ec; 3522 struct ether_multi *enm; 3523 struct ether_multistep step; 3524 struct ifnet *ifp = &ec->ec_if; 3525 struct vlanid_list *vlanidp; 3526 3527 KASSERT(mutex_owned(&sc->sc_cfg_lock)); 3528 3529 callout_stop(&sc->sc_tick); 3530 3531 iavf_intr_enable(sc); 3532 3533 if (!iavf_is_etheranyaddr(sc->sc_enaddr_added)) { 3534 iavf_eth_addr(sc, sc->sc_enaddr_added, IAVF_VC_OP_ADD_ETH_ADDR); 3535 } 3536 3537 ETHER_LOCK(ec); 3538 if (!ISSET(ifp->if_flags, IFF_ALLMULTI)) { 3539 for (ETHER_FIRST_MULTI(step, ec, enm); enm != NULL; 3540 ETHER_NEXT_MULTI(step, enm)) { 3541 iavf_add_multi(sc, enm->enm_addrlo, enm->enm_addrhi); 3542 } 3543 } 3544 3545 SIMPLEQ_FOREACH(vlanidp, &ec->ec_vids, vid_list) { 3546 ETHER_UNLOCK(ec); 3547 iavf_config_vlan_id(sc, vlanidp->vid, IAVF_VC_OP_ADD_VLAN); 3548 ETHER_LOCK(ec); 3549 } 3550 ETHER_UNLOCK(ec); 3551 3552 if (memcmp(sc->sc_enaddr, sc->sc_enaddr_reset, ETHER_ADDR_LEN) != 0) { 3553 log(LOG_INFO, "%s: Ethernet address changed to %s\n", 3554 ifp->if_xname, ether_sprintf(sc->sc_enaddr)); 3555 IFNET_LOCK(ifp); 3556 kpreempt_disable(); 3557 /*XXX we need an API to change ethernet address. */ 3558 iavf_replace_lla(ifp, sc->sc_enaddr_reset, sc->sc_enaddr); 3559 kpreempt_enable(); 3560 IFNET_UNLOCK(ifp); 3561 } 3562 3563 sc->sc_resetting = false; 3564 3565 if (sc->sc_reset_up) { 3566 iavf_init_locked(sc); 3567 } 3568 3569 if (sc->sc_link_state != LINK_STATE_DOWN) { 3570 if_link_state_change(ifp, sc->sc_link_state); 3571 } 3572 3573 } 3574 3575 static int 3576 iavf_dmamem_alloc(bus_dma_tag_t dmat, struct ixl_dmamem *ixm, 3577 bus_size_t size, bus_size_t align) 3578 { 3579 ixm->ixm_size = size; 3580 3581 if (bus_dmamap_create(dmat, ixm->ixm_size, 1, 3582 ixm->ixm_size, 0, 3583 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 3584 &ixm->ixm_map) != 0) 3585 return 1; 3586 if (bus_dmamem_alloc(dmat, ixm->ixm_size, 3587 align, 0, &ixm->ixm_seg, 1, &ixm->ixm_nsegs, 3588 BUS_DMA_WAITOK) != 0) 3589 goto destroy; 3590 if (bus_dmamem_map(dmat, &ixm->ixm_seg, ixm->ixm_nsegs, 3591 ixm->ixm_size, &ixm->ixm_kva, BUS_DMA_WAITOK) != 0) 3592 goto free; 3593 if (bus_dmamap_load(dmat, ixm->ixm_map, ixm->ixm_kva, 3594 ixm->ixm_size, NULL, BUS_DMA_WAITOK) != 0) 3595 goto unmap; 3596 3597 memset(ixm->ixm_kva, 0, ixm->ixm_size); 3598 3599 return 0; 3600 unmap: 3601 bus_dmamem_unmap(dmat, ixm->ixm_kva, ixm->ixm_size); 3602 free: 3603 bus_dmamem_free(dmat, &ixm->ixm_seg, 1); 3604 destroy: 3605 bus_dmamap_destroy(dmat, ixm->ixm_map); 3606 return 1; 3607 } 3608 3609 static void 3610 iavf_dmamem_free(bus_dma_tag_t dmat, struct ixl_dmamem *ixm) 3611 { 3612 3613 bus_dmamap_unload(dmat, ixm->ixm_map); 3614 bus_dmamem_unmap(dmat, ixm->ixm_kva, ixm->ixm_size); 3615 bus_dmamem_free(dmat, &ixm->ixm_seg, 1); 3616 bus_dmamap_destroy(dmat, ixm->ixm_map); 3617 } 3618 3619 static struct ixl_aq_buf * 3620 iavf_aqb_alloc(bus_dma_tag_t dmat, size_t buflen) 3621 { 3622 struct ixl_aq_buf *aqb; 3623 3624 aqb = kmem_alloc(sizeof(*aqb), KM_NOSLEEP); 3625 if (aqb == NULL) 3626 return NULL; 3627 3628 aqb->aqb_size = buflen; 3629 3630 if (bus_dmamap_create(dmat, aqb->aqb_size, 1, 3631 aqb->aqb_size, 0, 3632 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, &aqb->aqb_map) != 0) 3633 goto free; 3634 if (bus_dmamem_alloc(dmat, aqb->aqb_size, 3635 IAVF_AQ_ALIGN, 0, &aqb->aqb_seg, 1, &aqb->aqb_nsegs, 3636 BUS_DMA_WAITOK) != 0) 3637 goto destroy; 3638 if (bus_dmamem_map(dmat, &aqb->aqb_seg, aqb->aqb_nsegs, 3639 aqb->aqb_size, &aqb->aqb_data, BUS_DMA_WAITOK) != 0) 3640 goto dma_free; 3641 if (bus_dmamap_load(dmat, aqb->aqb_map, aqb->aqb_data, 3642 aqb->aqb_size, NULL, BUS_DMA_WAITOK) != 0) 3643 goto unmap; 3644 3645 return aqb; 3646 unmap: 3647 bus_dmamem_unmap(dmat, aqb->aqb_data, aqb->aqb_size); 3648 dma_free: 3649 bus_dmamem_free(dmat, &aqb->aqb_seg, 1); 3650 destroy: 3651 bus_dmamap_destroy(dmat, aqb->aqb_map); 3652 free: 3653 kmem_free(aqb, sizeof(*aqb)); 3654 3655 return NULL; 3656 } 3657 3658 static void 3659 iavf_aqb_free(bus_dma_tag_t dmat, struct ixl_aq_buf *aqb) 3660 { 3661 3662 bus_dmamap_unload(dmat, aqb->aqb_map); 3663 bus_dmamem_unmap(dmat, aqb->aqb_data, aqb->aqb_size); 3664 bus_dmamem_free(dmat, &aqb->aqb_seg, 1); 3665 bus_dmamap_destroy(dmat, aqb->aqb_map); 3666 kmem_free(aqb, sizeof(*aqb)); 3667 } 3668 3669 static struct ixl_aq_buf * 3670 iavf_aqb_get_locked(struct ixl_aq_bufs *q) 3671 { 3672 struct ixl_aq_buf *aqb; 3673 3674 aqb = SIMPLEQ_FIRST(q); 3675 if (aqb != NULL) { 3676 SIMPLEQ_REMOVE(q, aqb, ixl_aq_buf, aqb_entry); 3677 } 3678 3679 return aqb; 3680 } 3681 3682 static struct ixl_aq_buf * 3683 iavf_aqb_get(struct iavf_softc *sc, struct ixl_aq_bufs *q) 3684 { 3685 struct ixl_aq_buf *aqb; 3686 3687 if (q != NULL) { 3688 mutex_enter(&sc->sc_adminq_lock); 3689 aqb = iavf_aqb_get_locked(q); 3690 mutex_exit(&sc->sc_adminq_lock); 3691 } else { 3692 aqb = NULL; 3693 } 3694 3695 if (aqb == NULL) { 3696 aqb = iavf_aqb_alloc(sc->sc_dmat, IAVF_AQ_BUFLEN); 3697 } 3698 3699 return aqb; 3700 } 3701 3702 static void 3703 iavf_aqb_put_locked(struct ixl_aq_bufs *q, struct ixl_aq_buf *aqb) 3704 { 3705 3706 SIMPLEQ_INSERT_TAIL(q, aqb, aqb_entry); 3707 } 3708 3709 static void 3710 iavf_aqb_clean(struct ixl_aq_bufs *q, bus_dma_tag_t dmat) 3711 { 3712 struct ixl_aq_buf *aqb; 3713 3714 while ((aqb = SIMPLEQ_FIRST(q)) != NULL) { 3715 SIMPLEQ_REMOVE(q, aqb, ixl_aq_buf, aqb_entry); 3716 iavf_aqb_free(dmat, aqb); 3717 } 3718 } 3719 3720 static const char * 3721 iavf_aq_vc_opcode_str(const struct ixl_aq_desc *iaq) 3722 { 3723 3724 switch (iavf_aq_vc_get_opcode(iaq)) { 3725 case IAVF_VC_OP_VERSION: 3726 return "GET_VERSION"; 3727 case IAVF_VC_OP_RESET_VF: 3728 return "RESET_VF"; 3729 case IAVF_VC_OP_GET_VF_RESOURCES: 3730 return "GET_VF_RESOURCES"; 3731 case IAVF_VC_OP_CONFIG_TX_QUEUE: 3732 return "CONFIG_TX_QUEUE"; 3733 case IAVF_VC_OP_CONFIG_RX_QUEUE: 3734 return "CONFIG_RX_QUEUE"; 3735 case IAVF_VC_OP_CONFIG_VSI_QUEUES: 3736 return "CONFIG_VSI_QUEUES"; 3737 case IAVF_VC_OP_CONFIG_IRQ_MAP: 3738 return "CONFIG_IRQ_MAP"; 3739 case IAVF_VC_OP_ENABLE_QUEUES: 3740 return "ENABLE_QUEUES"; 3741 case IAVF_VC_OP_DISABLE_QUEUES: 3742 return "DISABLE_QUEUES"; 3743 case IAVF_VC_OP_ADD_ETH_ADDR: 3744 return "ADD_ETH_ADDR"; 3745 case IAVF_VC_OP_DEL_ETH_ADDR: 3746 return "DEL_ETH_ADDR"; 3747 case IAVF_VC_OP_CONFIG_PROMISC: 3748 return "CONFIG_PROMISC"; 3749 case IAVF_VC_OP_GET_STATS: 3750 return "GET_STATS"; 3751 case IAVF_VC_OP_EVENT: 3752 return "EVENT"; 3753 case IAVF_VC_OP_CONFIG_RSS_KEY: 3754 return "CONFIG_RSS_KEY"; 3755 case IAVF_VC_OP_GET_RSS_HENA_CAPS: 3756 return "GET_RS_HENA_CAPS"; 3757 case IAVF_VC_OP_SET_RSS_HENA: 3758 return "SET_RSS_HENA"; 3759 case IAVF_VC_OP_ENABLE_VLAN_STRIP: 3760 return "ENABLE_VLAN_STRIPPING"; 3761 case IAVF_VC_OP_DISABLE_VLAN_STRIP: 3762 return "DISABLE_VLAN_STRIPPING"; 3763 case IAVF_VC_OP_REQUEST_QUEUES: 3764 return "REQUEST_QUEUES"; 3765 } 3766 3767 return "unknown"; 3768 } 3769 3770 static void 3771 iavf_aq_dump(const struct iavf_softc *sc, const struct ixl_aq_desc *iaq, 3772 const char *msg) 3773 { 3774 char buf[512]; 3775 size_t len; 3776 3777 len = sizeof(buf); 3778 buf[--len] = '\0'; 3779 3780 device_printf(sc->sc_dev, "%s\n", msg); 3781 snprintb(buf, len, IXL_AQ_FLAGS_FMT, le16toh(iaq->iaq_flags)); 3782 device_printf(sc->sc_dev, "flags %s opcode %04x\n", 3783 buf, le16toh(iaq->iaq_opcode)); 3784 device_printf(sc->sc_dev, "datalen %u retval %u\n", 3785 le16toh(iaq->iaq_datalen), le16toh(iaq->iaq_retval)); 3786 device_printf(sc->sc_dev, "vc-opcode %u (%s)\n", 3787 iavf_aq_vc_get_opcode(iaq), 3788 iavf_aq_vc_opcode_str(iaq)); 3789 device_printf(sc->sc_dev, "vc-retval %u\n", 3790 iavf_aq_vc_get_retval(iaq)); 3791 device_printf(sc->sc_dev, "cookie %016" PRIx64 "\n", iaq->iaq_cookie); 3792 device_printf(sc->sc_dev, "%08x %08x %08x %08x\n", 3793 le32toh(iaq->iaq_param[0]), le32toh(iaq->iaq_param[1]), 3794 le32toh(iaq->iaq_param[2]), le32toh(iaq->iaq_param[3])); 3795 } 3796 3797 static int 3798 iavf_arq_fill(struct iavf_softc *sc) 3799 { 3800 struct ixl_aq_buf *aqb; 3801 struct ixl_aq_desc *arq, *iaq; 3802 unsigned int prod = sc->sc_arq_prod; 3803 unsigned int n; 3804 int filled; 3805 3806 n = ixl_rxr_unrefreshed(sc->sc_arq_prod, sc->sc_arq_cons, 3807 IAVF_AQ_NUM); 3808 3809 if (__predict_false(n <= 0)) 3810 return 0; 3811 3812 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_arq), 3813 0, IXL_DMA_LEN(&sc->sc_arq), 3814 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3815 3816 arq = IXL_DMA_KVA(&sc->sc_arq); 3817 3818 do { 3819 iaq = &arq[prod]; 3820 3821 if (ixl_aq_has_dva(iaq)) { 3822 /* already filled */ 3823 break; 3824 } 3825 3826 aqb = iavf_aqb_get_locked(&sc->sc_arq_idle); 3827 if (aqb == NULL) 3828 break; 3829 3830 memset(aqb->aqb_data, 0, aqb->aqb_size); 3831 3832 bus_dmamap_sync(sc->sc_dmat, aqb->aqb_map, 0, 3833 aqb->aqb_size, BUS_DMASYNC_PREREAD); 3834 3835 iaq->iaq_flags = htole16(IXL_AQ_BUF | 3836 (aqb->aqb_size > I40E_AQ_LARGE_BUF ? 3837 IXL_AQ_LB : 0)); 3838 iaq->iaq_opcode = 0; 3839 iaq->iaq_datalen = htole16(aqb->aqb_size); 3840 iaq->iaq_retval = 0; 3841 iaq->iaq_cookie = 0; 3842 iaq->iaq_param[0] = 0; 3843 iaq->iaq_param[1] = 0; 3844 ixl_aq_dva(iaq, IXL_AQB_DVA(aqb)); 3845 iavf_aqb_put_locked(&sc->sc_arq_live, aqb); 3846 3847 prod++; 3848 prod &= IAVF_AQ_MASK; 3849 filled = 1; 3850 } while (--n); 3851 3852 sc->sc_arq_prod = prod; 3853 3854 if (filled) { 3855 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_arq), 3856 0, IXL_DMA_LEN(&sc->sc_arq), 3857 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3858 iavf_wr(sc, sc->sc_aq_regs->arq_tail, sc->sc_arq_prod); 3859 } 3860 3861 return filled; 3862 } 3863 3864 static int 3865 iavf_arq_wait(struct iavf_softc *sc, uint32_t opcode) 3866 { 3867 int error; 3868 3869 KASSERT(mutex_owned(&sc->sc_adminq_lock)); 3870 3871 while ((error = cv_timedwait(&sc->sc_adminq_cv, 3872 &sc->sc_adminq_lock, mstohz(IAVF_EXEC_TIMEOUT))) == 0) { 3873 if (opcode == sc->sc_arq_opcode) 3874 break; 3875 } 3876 3877 if (error != 0 && 3878 atomic_load_relaxed(&sc->sc_debuglevel) >= 2) 3879 device_printf(sc->sc_dev, "cv_timedwait error=%d\n", error); 3880 3881 return error; 3882 } 3883 3884 static void 3885 iavf_arq_refill(void *xsc) 3886 { 3887 struct iavf_softc *sc = xsc; 3888 struct ixl_aq_bufs aqbs; 3889 struct ixl_aq_buf *aqb; 3890 unsigned int n, i; 3891 3892 mutex_enter(&sc->sc_adminq_lock); 3893 iavf_arq_fill(sc); 3894 n = ixl_rxr_unrefreshed(sc->sc_arq_prod, sc->sc_arq_cons, 3895 IAVF_AQ_NUM); 3896 mutex_exit(&sc->sc_adminq_lock); 3897 3898 if (n == 0) 3899 return; 3900 3901 if (atomic_load_relaxed(&sc->sc_debuglevel) >= 1) 3902 device_printf(sc->sc_dev, "Allocate %d bufs for arq\n", n); 3903 3904 SIMPLEQ_INIT(&aqbs); 3905 for (i = 0; i < n; i++) { 3906 aqb = iavf_aqb_get(sc, NULL); 3907 if (aqb == NULL) 3908 continue; 3909 SIMPLEQ_INSERT_TAIL(&aqbs, aqb, aqb_entry); 3910 } 3911 3912 mutex_enter(&sc->sc_adminq_lock); 3913 while ((aqb = SIMPLEQ_FIRST(&aqbs)) != NULL) { 3914 SIMPLEQ_REMOVE(&aqbs, aqb, ixl_aq_buf, aqb_entry); 3915 iavf_aqb_put_locked(&sc->sc_arq_idle, aqb); 3916 } 3917 iavf_arq_fill(sc); 3918 mutex_exit(&sc->sc_adminq_lock); 3919 } 3920 3921 static uint32_t 3922 iavf_process_arq(struct iavf_softc *sc, struct ixl_aq_desc *iaq, 3923 struct ixl_aq_buf *aqb) 3924 { 3925 uint32_t vc_retval, vc_opcode; 3926 int dbg; 3927 3928 dbg = atomic_load_relaxed(&sc->sc_debuglevel); 3929 if (dbg >= 3) 3930 iavf_aq_dump(sc, iaq, "arq proc"); 3931 3932 if (dbg >= 2) { 3933 vc_retval = iavf_aq_vc_get_retval(iaq); 3934 if (vc_retval != IAVF_VC_RC_SUCCESS) { 3935 device_printf(sc->sc_dev, "%s failed=%d(arq)\n", 3936 iavf_aq_vc_opcode_str(iaq), vc_retval); 3937 } 3938 } 3939 3940 vc_opcode = iavf_aq_vc_get_opcode(iaq); 3941 switch (vc_opcode) { 3942 case IAVF_VC_OP_VERSION: 3943 iavf_process_version(sc, iaq, aqb); 3944 break; 3945 case IAVF_VC_OP_GET_VF_RESOURCES: 3946 iavf_process_vf_resources(sc, iaq, aqb); 3947 break; 3948 case IAVF_VC_OP_CONFIG_IRQ_MAP: 3949 iavf_process_irq_map(sc, iaq); 3950 break; 3951 case IAVF_VC_OP_EVENT: 3952 iavf_process_vc_event(sc, iaq, aqb); 3953 break; 3954 case IAVF_VC_OP_GET_STATS: 3955 iavf_process_stats(sc, iaq, aqb); 3956 break; 3957 case IAVF_VC_OP_REQUEST_QUEUES: 3958 iavf_process_req_queues(sc, iaq, aqb); 3959 break; 3960 } 3961 3962 return vc_opcode; 3963 } 3964 3965 static int 3966 iavf_arq_poll(struct iavf_softc *sc, uint32_t wait_opcode, int retry) 3967 { 3968 struct ixl_aq_desc *arq, *iaq; 3969 struct ixl_aq_buf *aqb; 3970 unsigned int cons = sc->sc_arq_cons; 3971 unsigned int prod; 3972 uint32_t vc_opcode; 3973 bool received; 3974 int i; 3975 3976 for (i = 0, received = false; i < retry && !received; i++) { 3977 prod = iavf_rd(sc, sc->sc_aq_regs->arq_head); 3978 prod &= sc->sc_aq_regs->arq_head_mask; 3979 3980 if (prod == cons) { 3981 delaymsec(1); 3982 continue; 3983 } 3984 3985 if (prod >= IAVF_AQ_NUM) { 3986 return EIO; 3987 } 3988 3989 arq = IXL_DMA_KVA(&sc->sc_arq); 3990 3991 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_arq), 3992 0, IXL_DMA_LEN(&sc->sc_arq), 3993 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3994 3995 do { 3996 iaq = &arq[cons]; 3997 aqb = iavf_aqb_get_locked(&sc->sc_arq_live); 3998 KASSERT(aqb != NULL); 3999 4000 bus_dmamap_sync(sc->sc_dmat, aqb->aqb_map, 0, 4001 IAVF_AQ_BUFLEN, BUS_DMASYNC_POSTREAD); 4002 4003 vc_opcode = iavf_process_arq(sc, iaq, aqb); 4004 4005 if (vc_opcode == wait_opcode) 4006 received = true; 4007 4008 memset(iaq, 0, sizeof(*iaq)); 4009 iavf_aqb_put_locked(&sc->sc_arq_idle, aqb); 4010 4011 cons++; 4012 cons &= IAVF_AQ_MASK; 4013 4014 } while (cons != prod); 4015 4016 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_arq), 4017 0, IXL_DMA_LEN(&sc->sc_arq), 4018 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 4019 4020 sc->sc_arq_cons = cons; 4021 iavf_arq_fill(sc); 4022 4023 } 4024 4025 if (!received) 4026 return ETIMEDOUT; 4027 4028 return 0; 4029 } 4030 4031 static int 4032 iavf_arq(struct iavf_softc *sc) 4033 { 4034 struct ixl_aq_desc *arq, *iaq; 4035 struct ixl_aq_buf *aqb; 4036 unsigned int cons = sc->sc_arq_cons; 4037 unsigned int prod; 4038 uint32_t vc_opcode; 4039 4040 KASSERT(mutex_owned(&sc->sc_adminq_lock)); 4041 4042 prod = iavf_rd(sc, sc->sc_aq_regs->arq_head); 4043 prod &= sc->sc_aq_regs->arq_head_mask; 4044 4045 /* broken value at resetting */ 4046 if (prod >= IAVF_AQ_NUM) { 4047 iavf_work_set(&sc->sc_reset_task, iavf_reset_start, sc); 4048 iavf_work_add(sc->sc_workq, &sc->sc_reset_task); 4049 return 0; 4050 } 4051 4052 if (cons == prod) 4053 return 0; 4054 4055 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_arq), 4056 0, IXL_DMA_LEN(&sc->sc_arq), 4057 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4058 4059 arq = IXL_DMA_KVA(&sc->sc_arq); 4060 4061 do { 4062 iaq = &arq[cons]; 4063 aqb = iavf_aqb_get_locked(&sc->sc_arq_live); 4064 4065 KASSERT(aqb != NULL); 4066 4067 bus_dmamap_sync(sc->sc_dmat, aqb->aqb_map, 0, IAVF_AQ_BUFLEN, 4068 BUS_DMASYNC_POSTREAD); 4069 4070 vc_opcode = iavf_process_arq(sc, iaq, aqb); 4071 4072 switch (vc_opcode) { 4073 case IAVF_VC_OP_CONFIG_TX_QUEUE: 4074 case IAVF_VC_OP_CONFIG_RX_QUEUE: 4075 case IAVF_VC_OP_CONFIG_VSI_QUEUES: 4076 case IAVF_VC_OP_ENABLE_QUEUES: 4077 case IAVF_VC_OP_DISABLE_QUEUES: 4078 case IAVF_VC_OP_GET_RSS_HENA_CAPS: 4079 case IAVF_VC_OP_SET_RSS_HENA: 4080 case IAVF_VC_OP_ADD_ETH_ADDR: 4081 case IAVF_VC_OP_DEL_ETH_ADDR: 4082 case IAVF_VC_OP_CONFIG_PROMISC: 4083 case IAVF_VC_OP_ADD_VLAN: 4084 case IAVF_VC_OP_DEL_VLAN: 4085 case IAVF_VC_OP_ENABLE_VLAN_STRIP: 4086 case IAVF_VC_OP_DISABLE_VLAN_STRIP: 4087 case IAVF_VC_OP_CONFIG_RSS_KEY: 4088 case IAVF_VC_OP_CONFIG_RSS_LUT: 4089 sc->sc_arq_retval = iavf_aq_vc_get_retval(iaq); 4090 sc->sc_arq_opcode = vc_opcode; 4091 cv_signal(&sc->sc_adminq_cv); 4092 break; 4093 } 4094 4095 memset(iaq, 0, sizeof(*iaq)); 4096 iavf_aqb_put_locked(&sc->sc_arq_idle, aqb); 4097 4098 cons++; 4099 cons &= IAVF_AQ_MASK; 4100 } while (cons != prod); 4101 4102 sc->sc_arq_cons = cons; 4103 iavf_work_add(sc->sc_workq, &sc->sc_arq_refill); 4104 4105 return 1; 4106 } 4107 4108 static int 4109 iavf_atq_post(struct iavf_softc *sc, struct ixl_aq_desc *iaq, 4110 struct ixl_aq_buf *aqb) 4111 { 4112 struct ixl_aq_desc *atq, *slot; 4113 unsigned int prod; 4114 4115 atq = IXL_DMA_KVA(&sc->sc_atq); 4116 prod = sc->sc_atq_prod; 4117 slot = &atq[prod]; 4118 4119 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 4120 0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_POSTWRITE); 4121 4122 *slot = *iaq; 4123 slot->iaq_flags |= htole16(IXL_AQ_SI); 4124 if (aqb != NULL) { 4125 ixl_aq_dva(slot, IXL_AQB_DVA(aqb)); 4126 bus_dmamap_sync(sc->sc_dmat, IXL_AQB_MAP(aqb), 4127 0, IXL_AQB_LEN(aqb), BUS_DMASYNC_PREWRITE); 4128 iavf_aqb_put_locked(&sc->sc_atq_live, aqb); 4129 } else { 4130 ixl_aq_dva(slot, (bus_addr_t)0); 4131 } 4132 4133 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 4134 0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_PREWRITE); 4135 4136 if (atomic_load_relaxed(&sc->sc_debuglevel) >= 3) 4137 iavf_aq_dump(sc, slot, "post"); 4138 4139 prod++; 4140 prod &= IAVF_AQ_MASK; 4141 sc->sc_atq_prod = prod; 4142 iavf_wr(sc, sc->sc_aq_regs->atq_tail, prod); 4143 return prod; 4144 } 4145 4146 static int 4147 iavf_atq_poll(struct iavf_softc *sc, unsigned int tm) 4148 { 4149 struct ixl_aq_desc *atq, *slot; 4150 struct ixl_aq_desc iaq; 4151 struct ixl_aq_buf *aqb; 4152 unsigned int prod; 4153 unsigned int t; 4154 int dbg; 4155 4156 dbg = atomic_load_relaxed(&sc->sc_debuglevel); 4157 atq = IXL_DMA_KVA(&sc->sc_atq); 4158 prod = sc->sc_atq_prod; 4159 slot = &atq[prod]; 4160 t = 0; 4161 4162 while (iavf_rd(sc, sc->sc_aq_regs->atq_head) != prod) { 4163 delaymsec(1); 4164 4165 if (t++ > tm) { 4166 if (dbg >= 2) { 4167 device_printf(sc->sc_dev, 4168 "atq timedout\n"); 4169 } 4170 return ETIMEDOUT; 4171 } 4172 } 4173 4174 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 4175 0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_POSTREAD); 4176 iaq = *slot; 4177 memset(slot, 0, sizeof(*slot)); 4178 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 4179 0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_PREREAD); 4180 4181 aqb = iavf_aqb_get_locked(&sc->sc_atq_live); 4182 if (aqb != NULL) { 4183 bus_dmamap_sync(sc->sc_dmat, IXL_AQB_MAP(aqb), 4184 0, IXL_AQB_LEN(aqb), BUS_DMASYNC_POSTWRITE); 4185 /* no need to do iavf_aqb_put(&sc->sc_atq_idle, aqb) */ 4186 } 4187 4188 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) { 4189 if (dbg >= 2) { 4190 device_printf(sc->sc_dev, 4191 "atq retcode=0x%04x\n", le16toh(iaq.iaq_retval)); 4192 } 4193 return EIO; 4194 } 4195 4196 return 0; 4197 } 4198 4199 static void 4200 iavf_atq_done(struct iavf_softc *sc) 4201 { 4202 struct ixl_aq_desc *atq, *slot; 4203 struct ixl_aq_buf *aqb; 4204 unsigned int cons; 4205 unsigned int prod; 4206 4207 KASSERT(mutex_owned(&sc->sc_adminq_lock)); 4208 4209 prod = sc->sc_atq_prod; 4210 cons = sc->sc_atq_cons; 4211 4212 if (prod == cons) 4213 return; 4214 4215 atq = IXL_DMA_KVA(&sc->sc_atq); 4216 4217 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 4218 0, IXL_DMA_LEN(&sc->sc_atq), 4219 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4220 4221 do { 4222 slot = &atq[cons]; 4223 if (!ISSET(slot->iaq_flags, htole16(IXL_AQ_DD))) 4224 break; 4225 4226 if (ixl_aq_has_dva(slot) && 4227 (aqb = iavf_aqb_get_locked(&sc->sc_atq_live)) != NULL) { 4228 bus_dmamap_sync(sc->sc_dmat, IXL_AQB_MAP(aqb), 4229 0, IXL_AQB_LEN(aqb), BUS_DMASYNC_POSTWRITE); 4230 iavf_aqb_put_locked(&sc->sc_atq_idle, aqb); 4231 } 4232 4233 memset(slot, 0, sizeof(*slot)); 4234 4235 cons++; 4236 cons &= IAVF_AQ_MASK; 4237 } while (cons != prod); 4238 4239 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 4240 0, IXL_DMA_LEN(&sc->sc_atq), 4241 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 4242 4243 sc->sc_atq_cons = cons; 4244 } 4245 4246 static int 4247 iavf_adminq_poll(struct iavf_softc *sc, struct ixl_aq_desc *iaq, 4248 struct ixl_aq_buf *aqb, int retry) 4249 { 4250 int error; 4251 4252 mutex_enter(&sc->sc_adminq_lock); 4253 error = iavf_adminq_poll_locked(sc, iaq, aqb, retry); 4254 mutex_exit(&sc->sc_adminq_lock); 4255 4256 return error; 4257 } 4258 4259 static int 4260 iavf_adminq_poll_locked(struct iavf_softc *sc, 4261 struct ixl_aq_desc *iaq, struct ixl_aq_buf *aqb, int retry) 4262 { 4263 uint32_t opcode; 4264 int error; 4265 4266 KASSERT(!sc->sc_attached || mutex_owned(&sc->sc_adminq_lock)); 4267 4268 opcode = iavf_aq_vc_get_opcode(iaq); 4269 4270 iavf_atq_post(sc, iaq, aqb); 4271 4272 error = iavf_atq_poll(sc, retry); 4273 if (error) 4274 return error; 4275 4276 error = iavf_arq_poll(sc, opcode, retry); 4277 4278 if (error != 0 && 4279 atomic_load_relaxed(&sc->sc_debuglevel) >= 1) { 4280 device_printf(sc->sc_dev, "%s failed=%d(polling)\n", 4281 iavf_aq_vc_opcode_str(iaq), error); 4282 } 4283 4284 return error; 4285 } 4286 4287 static int 4288 iavf_adminq_exec(struct iavf_softc *sc, struct ixl_aq_desc *iaq, 4289 struct ixl_aq_buf *aqb) 4290 { 4291 int error; 4292 uint32_t opcode; 4293 4294 opcode = iavf_aq_vc_get_opcode(iaq); 4295 4296 mutex_enter(&sc->sc_adminq_lock); 4297 iavf_atq_post(sc, iaq, aqb); 4298 4299 error = iavf_arq_wait(sc, opcode); 4300 if (error == 0) { 4301 error = sc->sc_arq_retval; 4302 if (error != IAVF_VC_RC_SUCCESS && 4303 atomic_load_relaxed(&sc->sc_debuglevel) >= 1) { 4304 device_printf(sc->sc_dev, "%s failed=%d\n", 4305 iavf_aq_vc_opcode_str(iaq), error); 4306 } 4307 } 4308 4309 mutex_exit(&sc->sc_adminq_lock); 4310 return error; 4311 } 4312 4313 static void 4314 iavf_process_version(struct iavf_softc *sc, struct ixl_aq_desc *iaq, 4315 struct ixl_aq_buf *aqb) 4316 { 4317 struct iavf_vc_version_info *ver; 4318 4319 ver = (struct iavf_vc_version_info *)aqb->aqb_data; 4320 sc->sc_major_ver = le32toh(ver->major); 4321 sc->sc_minor_ver = le32toh(ver->minor); 4322 } 4323 4324 static void 4325 iavf_process_vf_resources(struct iavf_softc *sc, struct ixl_aq_desc *iaq, 4326 struct ixl_aq_buf *aqb) 4327 { 4328 struct iavf_vc_vf_resource *vf_res; 4329 struct iavf_vc_vsi_resource *vsi_res; 4330 uint8_t *enaddr; 4331 int mtu, dbg; 4332 char buf[512]; 4333 4334 dbg = atomic_load_relaxed(&sc->sc_debuglevel); 4335 sc->sc_got_vf_resources = 1; 4336 4337 vf_res = aqb->aqb_data; 4338 sc->sc_max_vectors = le16toh(vf_res->max_vectors); 4339 if (le16toh(vf_res->num_vsis) == 0) { 4340 if (dbg >= 1) { 4341 device_printf(sc->sc_dev, "no vsi available\n"); 4342 } 4343 return; 4344 } 4345 sc->sc_vf_cap = le32toh(vf_res->offload_flags); 4346 if (dbg >= 2) { 4347 snprintb(buf, sizeof(buf), 4348 IAVF_VC_OFFLOAD_FMT, sc->sc_vf_cap); 4349 device_printf(sc->sc_dev, "VF cap=%s\n", buf); 4350 } 4351 4352 mtu = le16toh(vf_res->max_mtu); 4353 if (IAVF_MIN_MTU < mtu && mtu < IAVF_MAX_MTU) { 4354 sc->sc_max_mtu = MIN(IAVF_MAX_MTU, mtu); 4355 } 4356 4357 vsi_res = &vf_res->vsi_res[0]; 4358 sc->sc_vsi_id = le16toh(vsi_res->vsi_id); 4359 sc->sc_vf_id = le32toh(iaq->iaq_param[0]); 4360 sc->sc_qset_handle = le16toh(vsi_res->qset_handle); 4361 sc->sc_nqps_vsi = le16toh(vsi_res->num_queue_pairs); 4362 if (!iavf_is_etheranyaddr(vsi_res->default_mac)) { 4363 enaddr = vsi_res->default_mac; 4364 } else { 4365 enaddr = sc->sc_enaddr_fake; 4366 } 4367 memcpy(sc->sc_enaddr, enaddr, ETHER_ADDR_LEN); 4368 } 4369 4370 static void 4371 iavf_process_irq_map(struct iavf_softc *sc, struct ixl_aq_desc *iaq) 4372 { 4373 uint32_t retval; 4374 4375 retval = iavf_aq_vc_get_retval(iaq); 4376 if (retval != IAVF_VC_RC_SUCCESS) { 4377 return; 4378 } 4379 4380 sc->sc_got_irq_map = 1; 4381 } 4382 4383 static void 4384 iavf_process_vc_event(struct iavf_softc *sc, struct ixl_aq_desc *iaq, 4385 struct ixl_aq_buf *aqb) 4386 { 4387 struct iavf_vc_pf_event *event; 4388 struct ifnet *ifp = &sc->sc_ec.ec_if; 4389 const struct iavf_link_speed *speed; 4390 int link; 4391 4392 event = aqb->aqb_data; 4393 switch (event->event) { 4394 case IAVF_VC_EVENT_LINK_CHANGE: 4395 sc->sc_media_status = IFM_AVALID; 4396 sc->sc_media_active = IFM_ETHER; 4397 link = LINK_STATE_DOWN; 4398 if (event->link_status) { 4399 link = LINK_STATE_UP; 4400 sc->sc_media_status |= IFM_ACTIVE; 4401 4402 ifp->if_baudrate = 0; 4403 speed = iavf_find_link_speed(sc, event->link_speed); 4404 if (speed != NULL) { 4405 sc->sc_media_active |= speed->media; 4406 ifp->if_baudrate = speed->baudrate; 4407 } 4408 } 4409 4410 if (sc->sc_link_state != link) { 4411 sc->sc_link_state = link; 4412 if (sc->sc_attached) { 4413 if_link_state_change(ifp, link); 4414 } 4415 } 4416 break; 4417 case IAVF_VC_EVENT_RESET_IMPENDING: 4418 log(LOG_INFO, "%s: Reset warning received from the PF\n", 4419 ifp->if_xname); 4420 iavf_work_set(&sc->sc_reset_task, iavf_reset_request, sc); 4421 iavf_work_add(sc->sc_workq, &sc->sc_reset_task); 4422 break; 4423 } 4424 } 4425 4426 static void 4427 iavf_process_stats(struct iavf_softc *sc, struct ixl_aq_desc *iaq, 4428 struct ixl_aq_buf *aqb) 4429 { 4430 struct iavf_stat_counters *isc; 4431 struct i40e_eth_stats *st; 4432 4433 KASSERT(mutex_owned(&sc->sc_adminq_lock)); 4434 4435 st = aqb->aqb_data; 4436 isc = &sc->sc_stat_counters; 4437 4438 isc->isc_rx_bytes.ev_count = st->rx_bytes; 4439 isc->isc_rx_unicast.ev_count = st->rx_unicast; 4440 isc->isc_rx_multicast.ev_count = st->rx_multicast; 4441 isc->isc_rx_broadcast.ev_count = st->rx_broadcast; 4442 isc->isc_rx_discards.ev_count = st->rx_discards; 4443 isc->isc_rx_unknown_protocol.ev_count = st->rx_unknown_protocol; 4444 4445 isc->isc_tx_bytes.ev_count = st->tx_bytes; 4446 isc->isc_tx_unicast.ev_count = st->tx_unicast; 4447 isc->isc_tx_multicast.ev_count = st->tx_multicast; 4448 isc->isc_tx_broadcast.ev_count = st->tx_broadcast; 4449 isc->isc_tx_discards.ev_count = st->tx_discards; 4450 isc->isc_tx_errors.ev_count = st->tx_errors; 4451 } 4452 4453 static void 4454 iavf_process_req_queues(struct iavf_softc *sc, struct ixl_aq_desc *iaq, 4455 struct ixl_aq_buf *aqb) 4456 { 4457 struct iavf_vc_res_request *req; 4458 struct ifnet *ifp; 4459 uint32_t vc_retval; 4460 4461 ifp = &sc->sc_ec.ec_if; 4462 req = aqb->aqb_data; 4463 4464 vc_retval = iavf_aq_vc_get_retval(iaq); 4465 if (vc_retval != IAVF_VC_RC_SUCCESS) { 4466 return; 4467 } 4468 4469 if (sc->sc_nqps_req < req->num_queue_pairs) { 4470 log(LOG_INFO, 4471 "%s: requested %d queues, but only %d left.\n", 4472 ifp->if_xname, 4473 sc->sc_nqps_req, req->num_queue_pairs); 4474 } 4475 4476 if (sc->sc_nqps_vsi < req->num_queue_pairs) { 4477 if (!sc->sc_req_queues_retried) { 4478 /* req->num_queue_pairs indicates max qps */ 4479 sc->sc_nqps_req = req->num_queue_pairs; 4480 4481 sc->sc_req_queues_retried = true; 4482 iavf_work_add(sc->sc_workq, &sc->sc_req_queues_task); 4483 } 4484 } 4485 } 4486 4487 static int 4488 iavf_get_version(struct iavf_softc *sc, struct ixl_aq_buf *aqb) 4489 { 4490 struct ixl_aq_desc iaq; 4491 struct iavf_vc_version_info *ver; 4492 int error; 4493 4494 memset(&iaq, 0, sizeof(iaq)); 4495 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD); 4496 iaq.iaq_opcode = htole16(IAVF_AQ_OP_SEND_TO_PF); 4497 iavf_aq_vc_set_opcode(&iaq, IAVF_VC_OP_VERSION); 4498 iaq.iaq_datalen = htole16(sizeof(struct iavf_vc_version_info)); 4499 4500 ver = IXL_AQB_KVA(aqb); 4501 ver->major = htole32(IAVF_VF_MAJOR); 4502 ver->minor = htole32(IAVF_VF_MINOR); 4503 4504 sc->sc_major_ver = UINT_MAX; 4505 sc->sc_minor_ver = UINT_MAX; 4506 4507 if (sc->sc_attached) { 4508 error = iavf_adminq_poll(sc, &iaq, aqb, 250); 4509 } else { 4510 error = iavf_adminq_poll_locked(sc, &iaq, aqb, 250); 4511 } 4512 4513 if (error) 4514 return -1; 4515 4516 return 0; 4517 } 4518 4519 static int 4520 iavf_get_vf_resources(struct iavf_softc *sc, struct ixl_aq_buf *aqb) 4521 { 4522 struct ixl_aq_desc iaq; 4523 uint32_t *cap, cap0; 4524 int error; 4525 4526 memset(&iaq, 0, sizeof(iaq)); 4527 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD); 4528 iaq.iaq_opcode = htole16(IAVF_AQ_OP_SEND_TO_PF); 4529 iavf_aq_vc_set_opcode(&iaq, IAVF_VC_OP_GET_VF_RESOURCES); 4530 4531 if (sc->sc_major_ver > 0) { 4532 cap0 = IAVF_VC_OFFLOAD_L2 | 4533 IAVF_VC_OFFLOAD_VLAN | 4534 IAVF_VC_OFFLOAD_RSS_PF | 4535 IAVF_VC_OFFLOAD_REQ_QUEUES; 4536 4537 cap = IXL_AQB_KVA(aqb); 4538 *cap = htole32(cap0); 4539 iaq.iaq_datalen = htole16(sizeof(*cap)); 4540 } 4541 4542 sc->sc_got_vf_resources = 0; 4543 if (sc->sc_attached) { 4544 error = iavf_adminq_poll(sc, &iaq, aqb, 250); 4545 } else { 4546 error = iavf_adminq_poll_locked(sc, &iaq, aqb, 250); 4547 } 4548 4549 if (error) 4550 return -1; 4551 return 0; 4552 } 4553 4554 static int 4555 iavf_get_stats(struct iavf_softc *sc) 4556 { 4557 struct ixl_aq_desc iaq; 4558 struct ixl_aq_buf *aqb; 4559 struct iavf_vc_queue_select *qsel; 4560 int error; 4561 4562 mutex_enter(&sc->sc_adminq_lock); 4563 aqb = iavf_aqb_get_locked(&sc->sc_atq_idle); 4564 mutex_exit(&sc->sc_adminq_lock); 4565 4566 if (aqb == NULL) 4567 return ENOMEM; 4568 4569 qsel = IXL_AQB_KVA(aqb); 4570 memset(qsel, 0, sizeof(*qsel)); 4571 qsel->vsi_id = htole16(sc->sc_vsi_id); 4572 4573 memset(&iaq, 0, sizeof(iaq)); 4574 4575 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD); 4576 iaq.iaq_opcode = htole16(IAVF_AQ_OP_SEND_TO_PF); 4577 iavf_aq_vc_set_opcode(&iaq, IAVF_VC_OP_GET_STATS); 4578 iaq.iaq_datalen = htole16(sizeof(*qsel)); 4579 4580 if (atomic_load_relaxed(&sc->sc_debuglevel) >= 3) { 4581 device_printf(sc->sc_dev, "post GET_STATS command\n"); 4582 } 4583 4584 mutex_enter(&sc->sc_adminq_lock); 4585 error = iavf_atq_post(sc, &iaq, aqb); 4586 mutex_exit(&sc->sc_adminq_lock); 4587 4588 return error; 4589 } 4590 4591 static int 4592 iavf_config_irq_map(struct iavf_softc *sc, struct ixl_aq_buf *aqb) 4593 { 4594 struct ixl_aq_desc iaq; 4595 struct iavf_vc_vector_map *vec; 4596 struct iavf_vc_irq_map_info *map; 4597 struct iavf_rx_ring *rxr; 4598 struct iavf_tx_ring *txr; 4599 unsigned int num_vec; 4600 int error; 4601 4602 map = IXL_AQB_KVA(aqb); 4603 vec = map->vecmap; 4604 num_vec = 0; 4605 4606 if (sc->sc_nintrs == 1) { 4607 vec[0].vsi_id = htole16(sc->sc_vsi_id); 4608 vec[0].vector_id = htole16(0); 4609 vec[0].rxq_map = htole16(iavf_allqueues(sc)); 4610 vec[0].txq_map = htole16(iavf_allqueues(sc)); 4611 vec[0].rxitr_idx = htole16(IAVF_NOITR); 4612 vec[0].rxitr_idx = htole16(IAVF_NOITR); 4613 num_vec = 1; 4614 } else if (sc->sc_nintrs > 1) { 4615 KASSERT(sc->sc_nqps_alloc >= (sc->sc_nintrs - 1)); 4616 for (; num_vec < (sc->sc_nintrs - 1); num_vec++) { 4617 rxr = sc->sc_qps[num_vec].qp_rxr; 4618 txr = sc->sc_qps[num_vec].qp_txr; 4619 4620 vec[num_vec].vsi_id = htole16(sc->sc_vsi_id); 4621 vec[num_vec].vector_id = htole16(num_vec + 1); 4622 vec[num_vec].rxq_map = htole16(__BIT(rxr->rxr_qid)); 4623 vec[num_vec].txq_map = htole16(__BIT(txr->txr_qid)); 4624 vec[num_vec].rxitr_idx = htole16(IAVF_ITR_RX); 4625 vec[num_vec].txitr_idx = htole16(IAVF_ITR_TX); 4626 } 4627 4628 vec[num_vec].vsi_id = htole16(sc->sc_vsi_id); 4629 vec[num_vec].vector_id = htole16(0); 4630 vec[num_vec].rxq_map = htole16(0); 4631 vec[num_vec].txq_map = htole16(0); 4632 num_vec++; 4633 } 4634 4635 map->num_vectors = htole16(num_vec); 4636 4637 memset(&iaq, 0, sizeof(iaq)); 4638 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD); 4639 iaq.iaq_opcode = htole16(IAVF_AQ_OP_SEND_TO_PF); 4640 iavf_aq_vc_set_opcode(&iaq, IAVF_VC_OP_CONFIG_IRQ_MAP); 4641 iaq.iaq_datalen = htole16(sizeof(*map) + sizeof(*vec) * num_vec); 4642 4643 if (sc->sc_attached) { 4644 error = iavf_adminq_poll(sc, &iaq, aqb, 250); 4645 } else { 4646 error = iavf_adminq_poll_locked(sc, &iaq, aqb, 250); 4647 } 4648 4649 if (error) 4650 return -1; 4651 4652 return 0; 4653 } 4654 4655 static int 4656 iavf_config_vsi_queues(struct iavf_softc *sc) 4657 { 4658 struct ifnet *ifp = &sc->sc_ec.ec_if; 4659 struct ixl_aq_desc iaq; 4660 struct ixl_aq_buf *aqb; 4661 struct iavf_vc_queue_config_info *config; 4662 struct iavf_vc_txq_info *txq; 4663 struct iavf_vc_rxq_info *rxq; 4664 struct iavf_rx_ring *rxr; 4665 struct iavf_tx_ring *txr; 4666 uint32_t rxmtu_max; 4667 unsigned int i; 4668 int error; 4669 4670 rxmtu_max = ifp->if_mtu + IAVF_MTU_ETHERLEN; 4671 4672 aqb = iavf_aqb_get(sc, &sc->sc_atq_idle); 4673 4674 if (aqb == NULL) 4675 return -1; 4676 4677 config = IXL_AQB_KVA(aqb); 4678 memset(config, 0, sizeof(*config)); 4679 config->vsi_id = htole16(sc->sc_vsi_id); 4680 config->num_queue_pairs = htole16(sc->sc_nqueue_pairs); 4681 4682 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 4683 rxr = sc->sc_qps[i].qp_rxr; 4684 txr = sc->sc_qps[i].qp_txr; 4685 4686 txq = &config->qpair[i].txq; 4687 txq->vsi_id = htole16(sc->sc_vsi_id); 4688 txq->queue_id = htole16(txr->txr_qid); 4689 txq->ring_len = htole16(sc->sc_tx_ring_ndescs); 4690 txq->headwb_ena = 0; 4691 txq->dma_ring_addr = htole64(IXL_DMA_DVA(&txr->txr_mem)); 4692 txq->dma_headwb_addr = 0; 4693 4694 rxq = &config->qpair[i].rxq; 4695 rxq->vsi_id = htole16(sc->sc_vsi_id); 4696 rxq->queue_id = htole16(rxr->rxr_qid); 4697 rxq->ring_len = htole16(sc->sc_rx_ring_ndescs); 4698 rxq->splithdr_ena = 0; 4699 rxq->databuf_size = htole32(IAVF_MCLBYTES); 4700 rxq->max_pkt_size = htole32(rxmtu_max); 4701 rxq->dma_ring_addr = htole64(IXL_DMA_DVA(&rxr->rxr_mem)); 4702 rxq->rx_split_pos = 0; 4703 } 4704 4705 memset(&iaq, 0, sizeof(iaq)); 4706 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD); 4707 iaq.iaq_opcode = htole16(IAVF_AQ_OP_SEND_TO_PF); 4708 iavf_aq_vc_set_opcode(&iaq, IAVF_VC_OP_CONFIG_VSI_QUEUES); 4709 iaq.iaq_datalen = htole16(sizeof(*config) + 4710 sizeof(config->qpair[0]) * sc->sc_nqueue_pairs); 4711 4712 error = iavf_adminq_exec(sc, &iaq, aqb); 4713 if (error != IAVF_VC_RC_SUCCESS) { 4714 return -1; 4715 } 4716 4717 return 0; 4718 } 4719 4720 static int 4721 iavf_config_hena(struct iavf_softc *sc) 4722 { 4723 struct ixl_aq_desc iaq; 4724 struct ixl_aq_buf *aqb; 4725 uint64_t *caps; 4726 int error; 4727 4728 aqb = iavf_aqb_get(sc, &sc->sc_atq_idle); 4729 4730 if (aqb == NULL) 4731 return -1; 4732 4733 caps = IXL_AQB_KVA(aqb); 4734 if (sc->sc_mac_type == I40E_MAC_X722_VF) 4735 *caps = IXL_RSS_HENA_DEFAULT_XL710; 4736 else 4737 *caps = IXL_RSS_HENA_DEFAULT_X722; 4738 4739 memset(&iaq, 0, sizeof(iaq)); 4740 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD); 4741 iaq.iaq_opcode = htole16(IAVF_AQ_OP_SEND_TO_PF); 4742 iavf_aq_vc_set_opcode(&iaq, IAVF_VC_OP_SET_RSS_HENA); 4743 iaq.iaq_datalen = htole16(sizeof(*caps)); 4744 4745 error = iavf_adminq_exec(sc, &iaq, aqb); 4746 if (error != IAVF_VC_RC_SUCCESS) { 4747 return -1; 4748 } 4749 4750 return 0; 4751 } 4752 4753 static inline void 4754 iavf_get_default_rss_key(uint8_t *buf, size_t len) 4755 { 4756 uint8_t rss_seed[RSS_KEYSIZE]; 4757 size_t cplen; 4758 4759 cplen = MIN(len, sizeof(rss_seed)); 4760 rss_getkey(rss_seed); 4761 4762 memcpy(buf, rss_seed, cplen); 4763 if (cplen < len) 4764 memset(buf + cplen, 0, len - cplen); 4765 } 4766 4767 static int 4768 iavf_config_rss_key(struct iavf_softc *sc) 4769 { 4770 struct ixl_aq_desc iaq; 4771 struct ixl_aq_buf *aqb; 4772 struct iavf_vc_rss_key *rss_key; 4773 size_t key_len; 4774 int rv; 4775 4776 aqb = iavf_aqb_get(sc, &sc->sc_atq_idle); 4777 if (aqb == NULL) 4778 return -1; 4779 4780 rss_key = IXL_AQB_KVA(aqb); 4781 rss_key->vsi_id = htole16(sc->sc_vsi_id); 4782 key_len = IXL_RSS_KEY_SIZE; 4783 iavf_get_default_rss_key(rss_key->key, key_len); 4784 rss_key->key_len = key_len; 4785 4786 memset(&iaq, 0, sizeof(iaq)); 4787 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD); 4788 iaq.iaq_opcode = htole16(IAVF_AQ_OP_SEND_TO_PF); 4789 iavf_aq_vc_set_opcode(&iaq, IAVF_VC_OP_CONFIG_RSS_KEY); 4790 iaq.iaq_datalen = htole16(sizeof(*rss_key) - sizeof(rss_key->pad) 4791 + (sizeof(rss_key->key[0]) * key_len)); 4792 4793 rv = iavf_adminq_exec(sc, &iaq, aqb); 4794 if (rv != IAVF_VC_RC_SUCCESS) { 4795 return -1; 4796 } 4797 4798 return 0; 4799 } 4800 4801 static int 4802 iavf_config_rss_lut(struct iavf_softc *sc) 4803 { 4804 struct ixl_aq_desc iaq; 4805 struct ixl_aq_buf *aqb; 4806 struct iavf_vc_rss_lut *rss_lut; 4807 uint8_t *lut, v; 4808 int rv, i; 4809 4810 mutex_enter(&sc->sc_adminq_lock); 4811 mutex_exit(&sc->sc_adminq_lock); 4812 4813 aqb = iavf_aqb_get(sc, &sc->sc_atq_idle); 4814 if (aqb == NULL) 4815 return -1; 4816 4817 rss_lut = IXL_AQB_KVA(aqb); 4818 rss_lut->vsi_id = htole16(sc->sc_vsi_id); 4819 rss_lut->lut_entries = htole16(IXL_RSS_VSI_LUT_SIZE); 4820 4821 lut = rss_lut->lut; 4822 for (i = 0; i < IXL_RSS_VSI_LUT_SIZE; i++) { 4823 v = i % sc->sc_nqueue_pairs; 4824 v &= IAVF_RSS_VSI_LUT_ENTRY_MASK; 4825 lut[i] = v; 4826 } 4827 4828 memset(&iaq, 0, sizeof(iaq)); 4829 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD); 4830 iaq.iaq_opcode = htole16(IAVF_AQ_OP_SEND_TO_PF); 4831 iavf_aq_vc_set_opcode(&iaq, IAVF_VC_OP_CONFIG_RSS_LUT); 4832 iaq.iaq_datalen = htole16(sizeof(*rss_lut) - sizeof(rss_lut->pad) 4833 + (sizeof(rss_lut->lut[0]) * IXL_RSS_VSI_LUT_SIZE)); 4834 4835 rv = iavf_adminq_exec(sc, &iaq, aqb); 4836 if (rv != IAVF_VC_RC_SUCCESS) { 4837 return -1; 4838 } 4839 4840 return 0; 4841 } 4842 4843 static int 4844 iavf_queue_select(struct iavf_softc *sc, int opcode) 4845 { 4846 struct ixl_aq_desc iaq; 4847 struct ixl_aq_buf *aqb; 4848 struct iavf_vc_queue_select *qsel; 4849 int error; 4850 4851 aqb = iavf_aqb_get(sc, &sc->sc_atq_idle); 4852 if (aqb == NULL) 4853 return -1; 4854 4855 qsel = IXL_AQB_KVA(aqb); 4856 qsel->vsi_id = htole16(sc->sc_vsi_id); 4857 qsel->rx_queues = htole32(iavf_allqueues(sc)); 4858 qsel->tx_queues = htole32(iavf_allqueues(sc)); 4859 4860 memset(&iaq, 0, sizeof(iaq)); 4861 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD); 4862 iaq.iaq_opcode = htole16(IAVF_AQ_OP_SEND_TO_PF); 4863 iavf_aq_vc_set_opcode(&iaq, opcode); 4864 iaq.iaq_datalen = htole16(sizeof(*qsel)); 4865 4866 error = iavf_adminq_exec(sc, &iaq, aqb); 4867 if (error != IAVF_VC_RC_SUCCESS) { 4868 return -1; 4869 } 4870 4871 return 0; 4872 } 4873 4874 static int 4875 iavf_request_queues(struct iavf_softc *sc, unsigned int req_num) 4876 { 4877 struct ixl_aq_desc iaq; 4878 struct ixl_aq_buf *aqb; 4879 struct iavf_vc_res_request *req; 4880 int rv; 4881 4882 aqb = iavf_aqb_get(sc, &sc->sc_atq_idle); 4883 if (aqb == NULL) 4884 return ENOMEM; 4885 4886 req = IXL_AQB_KVA(aqb); 4887 req->num_queue_pairs = req_num; 4888 4889 memset(&iaq, 0, sizeof(iaq)); 4890 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD); 4891 iaq.iaq_opcode = htole16(IAVF_AQ_OP_SEND_TO_PF); 4892 iavf_aq_vc_set_opcode(&iaq, IAVF_VC_OP_REQUEST_QUEUES); 4893 iaq.iaq_datalen = htole16(sizeof(*req)); 4894 4895 mutex_enter(&sc->sc_adminq_lock); 4896 rv = iavf_atq_post(sc, &iaq, aqb); 4897 mutex_exit(&sc->sc_adminq_lock); 4898 4899 return rv; 4900 } 4901 4902 static int 4903 iavf_reset_vf(struct iavf_softc *sc) 4904 { 4905 struct ixl_aq_desc iaq; 4906 int error; 4907 4908 memset(&iaq, 0, sizeof(iaq)); 4909 iaq.iaq_flags = htole16(IXL_AQ_RD); 4910 iaq.iaq_opcode = htole16(IAVF_AQ_OP_SEND_TO_PF); 4911 iavf_aq_vc_set_opcode(&iaq, IAVF_VC_OP_RESET_VF); 4912 iaq.iaq_datalen = htole16(0); 4913 4914 iavf_wr(sc, I40E_VFGEN_RSTAT, IAVF_VFR_INPROGRESS); 4915 4916 mutex_enter(&sc->sc_adminq_lock); 4917 error = iavf_atq_post(sc, &iaq, NULL); 4918 mutex_exit(&sc->sc_adminq_lock); 4919 4920 return error; 4921 } 4922 4923 static int 4924 iavf_eth_addr(struct iavf_softc *sc, const uint8_t *addr, uint32_t opcode) 4925 { 4926 struct ixl_aq_desc iaq; 4927 struct ixl_aq_buf *aqb; 4928 struct iavf_vc_eth_addr_list *addrs; 4929 struct iavf_vc_eth_addr *vcaddr; 4930 int rv; 4931 4932 KASSERT(sc->sc_attached); 4933 KASSERT(opcode == IAVF_VC_OP_ADD_ETH_ADDR || 4934 opcode == IAVF_VC_OP_DEL_ETH_ADDR); 4935 4936 aqb = iavf_aqb_get(sc, &sc->sc_atq_idle); 4937 if (aqb == NULL) 4938 return -1; 4939 4940 addrs = IXL_AQB_KVA(aqb); 4941 addrs->vsi_id = htole16(sc->sc_vsi_id); 4942 addrs->num_elements = htole16(1); 4943 vcaddr = addrs->list; 4944 memcpy(vcaddr->addr, addr, ETHER_ADDR_LEN); 4945 4946 memset(&iaq, 0, sizeof(iaq)); 4947 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD); 4948 iaq.iaq_opcode = htole16(IAVF_AQ_OP_SEND_TO_PF); 4949 iavf_aq_vc_set_opcode(&iaq, opcode); 4950 iaq.iaq_datalen = htole16(sizeof(*addrs) + sizeof(*vcaddr)); 4951 4952 if (sc->sc_resetting) { 4953 mutex_enter(&sc->sc_adminq_lock); 4954 rv = iavf_adminq_poll_locked(sc, &iaq, aqb, 250); 4955 iavf_aqb_put_locked(&sc->sc_atq_idle, aqb); 4956 mutex_exit(&sc->sc_adminq_lock); 4957 } else { 4958 rv = iavf_adminq_exec(sc, &iaq, aqb); 4959 } 4960 4961 if (rv != IAVF_VC_RC_SUCCESS) { 4962 return -1; 4963 } 4964 4965 return 0; 4966 } 4967 4968 static int 4969 iavf_config_promisc_mode(struct iavf_softc *sc, int unicast, int multicast) 4970 { 4971 struct ixl_aq_desc iaq; 4972 struct ixl_aq_buf *aqb; 4973 struct iavf_vc_promisc_info *promisc; 4974 int flags; 4975 4976 KASSERT(sc->sc_attached); 4977 4978 aqb = iavf_aqb_get(sc, &sc->sc_atq_idle); 4979 if (aqb == NULL) 4980 return -1; 4981 4982 flags = 0; 4983 if (unicast) 4984 flags |= IAVF_FLAG_VF_UNICAST_PROMISC; 4985 if (multicast) 4986 flags |= IAVF_FLAG_VF_MULTICAST_PROMISC; 4987 4988 promisc = IXL_AQB_KVA(aqb); 4989 promisc->vsi_id = htole16(sc->sc_vsi_id); 4990 promisc->flags = htole16(flags); 4991 4992 memset(&iaq, 0, sizeof(iaq)); 4993 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD); 4994 iaq.iaq_opcode = htole16(IAVF_AQ_OP_SEND_TO_PF); 4995 iavf_aq_vc_set_opcode(&iaq, IAVF_VC_OP_CONFIG_PROMISC); 4996 iaq.iaq_datalen = htole16(sizeof(*promisc)); 4997 4998 if (iavf_adminq_exec(sc, &iaq, aqb) != IAVF_VC_RC_SUCCESS) { 4999 return -1; 5000 } 5001 5002 return 0; 5003 } 5004 5005 static int 5006 iavf_config_vlan_stripping(struct iavf_softc *sc, int eccap) 5007 { 5008 struct ixl_aq_desc iaq; 5009 uint32_t opcode; 5010 5011 opcode = ISSET(eccap, ETHERCAP_VLAN_HWTAGGING) ? 5012 IAVF_VC_OP_ENABLE_VLAN_STRIP : IAVF_VC_OP_DISABLE_VLAN_STRIP; 5013 5014 memset(&iaq, 0, sizeof(iaq)); 5015 iaq.iaq_flags = htole16(IXL_AQ_RD); 5016 iaq.iaq_opcode = htole16(IAVF_AQ_OP_SEND_TO_PF); 5017 iavf_aq_vc_set_opcode(&iaq, opcode); 5018 iaq.iaq_datalen = htole16(0); 5019 5020 if (iavf_adminq_exec(sc, &iaq, NULL) != IAVF_VC_RC_SUCCESS) { 5021 return -1; 5022 } 5023 5024 return 0; 5025 } 5026 5027 static int 5028 iavf_config_vlan_id(struct iavf_softc *sc, uint16_t vid, uint32_t opcode) 5029 { 5030 struct ixl_aq_desc iaq; 5031 struct ixl_aq_buf *aqb; 5032 struct iavf_vc_vlan_filter *vfilter; 5033 int rv; 5034 5035 KASSERT(opcode == IAVF_VC_OP_ADD_VLAN || opcode == IAVF_VC_OP_DEL_VLAN); 5036 5037 aqb = iavf_aqb_get(sc, &sc->sc_atq_idle); 5038 5039 if (aqb == NULL) 5040 return -1; 5041 5042 vfilter = IXL_AQB_KVA(aqb); 5043 vfilter->vsi_id = htole16(sc->sc_vsi_id); 5044 vfilter->num_vlan_id = htole16(1); 5045 vfilter->vlan_id[0] = vid; 5046 5047 memset(&iaq, 0, sizeof(iaq)); 5048 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD); 5049 iaq.iaq_opcode = htole16(IAVF_AQ_OP_SEND_TO_PF); 5050 iavf_aq_vc_set_opcode(&iaq, opcode); 5051 iaq.iaq_datalen = htole16(sizeof(*vfilter) + sizeof(vid)); 5052 5053 if (sc->sc_resetting) { 5054 mutex_enter(&sc->sc_adminq_lock); 5055 rv = iavf_adminq_poll_locked(sc, &iaq, aqb, 250); 5056 iavf_aqb_put_locked(&sc->sc_atq_idle, aqb); 5057 mutex_exit(&sc->sc_adminq_lock); 5058 } else { 5059 rv = iavf_adminq_exec(sc, &iaq, aqb); 5060 } 5061 5062 if (rv != IAVF_VC_RC_SUCCESS) { 5063 return -1; 5064 } 5065 5066 return 0; 5067 } 5068 5069 static void 5070 iavf_post_request_queues(void *xsc) 5071 { 5072 struct iavf_softc *sc; 5073 struct ifnet *ifp; 5074 5075 sc = xsc; 5076 ifp = &sc->sc_ec.ec_if; 5077 5078 if (!ISSET(sc->sc_vf_cap, IAVF_VC_OFFLOAD_REQ_QUEUES)) { 5079 log(LOG_DEBUG, "%s: the VF has no REQ_QUEUES capability\n", 5080 ifp->if_xname); 5081 return; 5082 } 5083 5084 log(LOG_INFO, "%s: try to change the number of queue pairs" 5085 " (vsi %u, %u allocated, request %u)\n", 5086 ifp->if_xname, 5087 sc->sc_nqps_vsi, sc->sc_nqps_alloc, sc->sc_nqps_req); 5088 iavf_request_queues(sc, sc->sc_nqps_req); 5089 } 5090 5091 static bool 5092 iavf_sysctlnode_is_rx(struct sysctlnode *node) 5093 { 5094 5095 if (strstr(node->sysctl_parent->sysctl_name, "rx") != NULL) 5096 return true; 5097 5098 return false; 5099 } 5100 5101 static int 5102 iavf_sysctl_itr_handler(SYSCTLFN_ARGS) 5103 { 5104 struct sysctlnode node = *rnode; 5105 struct iavf_softc *sc = (struct iavf_softc *)node.sysctl_data; 5106 uint32_t newitr, *itrptr; 5107 unsigned int i; 5108 int itr, error; 5109 5110 if (iavf_sysctlnode_is_rx(&node)) { 5111 itrptr = &sc->sc_rx_itr; 5112 itr = IAVF_ITR_RX; 5113 } else { 5114 itrptr = &sc->sc_tx_itr; 5115 itr = IAVF_ITR_TX; 5116 } 5117 5118 newitr = *itrptr; 5119 node.sysctl_data = &newitr; 5120 node.sysctl_size = sizeof(newitr); 5121 5122 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 5123 if (error || newp == NULL) 5124 return error; 5125 5126 if (newitr > 0x07FF) 5127 return EINVAL; 5128 5129 *itrptr = newitr; 5130 5131 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 5132 iavf_wr(sc, I40E_VFINT_ITRN1(itr, i), *itrptr); 5133 } 5134 iavf_wr(sc, I40E_VFINT_ITR01(itr), *itrptr); 5135 5136 return 0; 5137 } 5138 5139 static void 5140 iavf_workq_work(struct work *wk, void *context) 5141 { 5142 struct iavf_work *work; 5143 5144 work = container_of(wk, struct iavf_work, ixw_cookie); 5145 5146 atomic_swap_uint(&work->ixw_added, 0); 5147 work->ixw_func(work->ixw_arg); 5148 } 5149 5150 static struct workqueue * 5151 iavf_workq_create(const char *name, pri_t prio, int ipl, int flags) 5152 { 5153 struct workqueue *wq; 5154 int error; 5155 5156 error = workqueue_create(&wq, name, iavf_workq_work, NULL, 5157 prio, ipl, flags); 5158 5159 if (error) 5160 return NULL; 5161 5162 return wq; 5163 } 5164 5165 static void 5166 iavf_workq_destroy(struct workqueue *wq) 5167 { 5168 5169 workqueue_destroy(wq); 5170 } 5171 5172 static int 5173 iavf_work_set(struct iavf_work *work, void (*func)(void *), void *arg) 5174 { 5175 5176 if (work->ixw_added != 0) 5177 return -1; 5178 5179 memset(work, 0, sizeof(*work)); 5180 work->ixw_func = func; 5181 work->ixw_arg = arg; 5182 5183 return 0; 5184 } 5185 5186 static void 5187 iavf_work_add(struct workqueue *wq, struct iavf_work *work) 5188 { 5189 if (atomic_cas_uint(&work->ixw_added, 0, 1) != 0) 5190 return; 5191 5192 kpreempt_disable(); 5193 workqueue_enqueue(wq, &work->ixw_cookie, NULL); 5194 kpreempt_enable(); 5195 } 5196 5197 static void 5198 iavf_work_wait(struct workqueue *wq, struct iavf_work *work) 5199 { 5200 5201 workqueue_wait(wq, &work->ixw_cookie); 5202 } 5203 5204 static void 5205 iavf_evcnt_attach(struct evcnt *ec, 5206 const char *n0, const char *n1) 5207 { 5208 5209 evcnt_attach_dynamic(ec, EVCNT_TYPE_MISC, 5210 NULL, n0, n1); 5211 } 5212 5213 MODULE(MODULE_CLASS_DRIVER, if_iavf, "pci"); 5214 5215 #ifdef _MODULE 5216 #include "ioconf.c" 5217 #endif 5218 5219 #ifdef _MODULE 5220 static void 5221 iavf_parse_modprop(prop_dictionary_t dict) 5222 { 5223 prop_object_t obj; 5224 int64_t val; 5225 uint32_t n; 5226 5227 if (dict == NULL) 5228 return; 5229 5230 obj = prop_dictionary_get(dict, "debug_level"); 5231 if (obj != NULL && prop_object_type(obj) == PROP_TYPE_NUMBER) { 5232 val = prop_number_signed_value((prop_number_t)obj); 5233 5234 if (val > 0) { 5235 iavf_params.debug = val; 5236 printf("iavf: debug level=%d\n", iavf_params.debug); 5237 } 5238 } 5239 5240 obj = prop_dictionary_get(dict, "max_qps"); 5241 if (obj != NULL && prop_object_type(obj) == PROP_TYPE_NUMBER) { 5242 val = prop_number_signed_value((prop_number_t)obj); 5243 5244 if (val < 1 || val > I40E_MAX_VF_QUEUES) { 5245 printf("iavf: invalid queue size(1 <= n <= %d)", 5246 I40E_MAX_VF_QUEUES); 5247 } else { 5248 iavf_params.max_qps = val; 5249 printf("iavf: request queue pair = %u\n", 5250 iavf_params.max_qps); 5251 } 5252 } 5253 5254 obj = prop_dictionary_get(dict, "tx_itr"); 5255 if (obj != NULL && prop_object_type(obj) == PROP_TYPE_NUMBER) { 5256 val = prop_number_signed_value((prop_number_t)obj); 5257 if (val > 0x07FF) { 5258 printf("iavf: TX ITR too big (%" PRId64 " <= %d)", 5259 val, 0x7FF); 5260 } else { 5261 iavf_params.tx_itr = val; 5262 printf("iavf: TX ITR = 0x%" PRIx32, 5263 iavf_params.tx_itr); 5264 } 5265 } 5266 5267 obj = prop_dictionary_get(dict, "rx_itr"); 5268 if (obj != NULL && prop_object_type(obj) == PROP_TYPE_NUMBER) { 5269 val = prop_number_signed_value((prop_number_t)obj); 5270 if (val > 0x07FF) { 5271 printf("iavf: RX ITR too big (%" PRId64 " <= %d)", 5272 val, 0x7FF); 5273 } else { 5274 iavf_params.rx_itr = val; 5275 printf("iavf: RX ITR = 0x%" PRIx32, 5276 iavf_params.rx_itr); 5277 } 5278 } 5279 5280 obj = prop_dictionary_get(dict, "tx_ndescs"); 5281 if (obj != NULL && prop_object_type(obj) == PROP_TYPE_NUMBER) { 5282 val = prop_number_signed_value((prop_number_t)obj); 5283 n = 1U << (fls32(val) - 1); 5284 if (val != (int64_t) n) { 5285 printf("iavf: TX desc invlaid size" 5286 "(%" PRId64 " != %" PRIu32 ")\n", val, n); 5287 } else if (val > (8192 - 32)) { 5288 printf("iavf: Tx desc too big (%" PRId64 " > %d)", 5289 val, (8192 - 32)); 5290 } else { 5291 iavf_params.tx_ndescs = val; 5292 printf("iavf: TX descriptors = 0x%04x", 5293 iavf_params.tx_ndescs); 5294 } 5295 } 5296 5297 obj = prop_dictionary_get(dict, "rx_ndescs"); 5298 if (obj != NULL && prop_object_type(obj) == PROP_TYPE_NUMBER) { 5299 val = prop_number_signed_value((prop_number_t)obj); 5300 n = 1U << (fls32(val) - 1); 5301 if (val != (int64_t) n) { 5302 printf("iavf: RX desc invlaid size" 5303 "(%" PRId64 " != %" PRIu32 ")\n", val, n); 5304 } else if (val > (8192 - 32)) { 5305 printf("iavf: Rx desc too big (%" PRId64 " > %d)", 5306 val, (8192 - 32)); 5307 } else { 5308 iavf_params.rx_ndescs = val; 5309 printf("iavf: RX descriptors = 0x%04x", 5310 iavf_params.rx_ndescs); 5311 } 5312 } 5313 } 5314 #endif 5315 5316 static int 5317 if_iavf_modcmd(modcmd_t cmd, void *opaque) 5318 { 5319 int error = 0; 5320 5321 #ifdef _MODULE 5322 switch (cmd) { 5323 case MODULE_CMD_INIT: 5324 iavf_parse_modprop((prop_dictionary_t)opaque); 5325 error = config_init_component(cfdriver_ioconf_if_iavf, 5326 cfattach_ioconf_if_iavf, cfdata_ioconf_if_iavf); 5327 break; 5328 case MODULE_CMD_FINI: 5329 error = config_fini_component(cfdriver_ioconf_if_iavf, 5330 cfattach_ioconf_if_iavf, cfdata_ioconf_if_iavf); 5331 break; 5332 default: 5333 error = ENOTTY; 5334 break; 5335 } 5336 #endif 5337 5338 return error; 5339 } 5340
Indexes created Tue Sep 30 10:09:55 GMT 2025