if_ipw.c revision 1.2.2.2
1 1.2.2.2 skrll /* $NetBSD: if_ipw.c,v 1.2.2.2 2004/08/25 06:58:05 skrll Exp $ */ 2 1.2.2.2 skrll /* Id: if_ipw.c,v 1.1.2.7 2004/08/20 11:20:11 damien Exp */ 3 1.2.2.2 skrll 4 1.2.2.2 skrll /*- 5 1.2.2.2 skrll * Copyright (c) 2004 6 1.2.2.2 skrll * Damien Bergamini <damien.bergamini (at) free.fr>. All rights reserved. 7 1.2.2.2 skrll * 8 1.2.2.2 skrll * Redistribution and use in source and binary forms, with or without 9 1.2.2.2 skrll * modification, are permitted provided that the following conditions 10 1.2.2.2 skrll * are met: 11 1.2.2.2 skrll * 1. Redistributions of source code must retain the above copyright 12 1.2.2.2 skrll * notice unmodified, this list of conditions, and the following 13 1.2.2.2 skrll * disclaimer. 14 1.2.2.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 15 1.2.2.2 skrll * notice, this list of conditions and the following disclaimer in the 16 1.2.2.2 skrll * documentation and/or other materials provided with the distribution. 17 1.2.2.2 skrll * 18 1.2.2.2 skrll * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 1.2.2.2 skrll * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 1.2.2.2 skrll * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 1.2.2.2 skrll * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 1.2.2.2 skrll * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 1.2.2.2 skrll * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 1.2.2.2 skrll * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 1.2.2.2 skrll * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 1.2.2.2 skrll * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 1.2.2.2 skrll * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 1.2.2.2 skrll * SUCH DAMAGE. 29 1.2.2.2 skrll */ 30 1.2.2.2 skrll 31 1.2.2.2 skrll #include <sys/cdefs.h> 32 1.2.2.2 skrll __KERNEL_RCSID(0, "$NetBSD: if_ipw.c,v 1.2.2.2 2004/08/25 06:58:05 skrll Exp $"); 33 1.2.2.2 skrll 34 1.2.2.2 skrll /*- 35 1.2.2.2 skrll * Intel(R) PRO/Wireless 2100 MiniPCI driver 36 1.2.2.2 skrll * http://www.intel.com/products/mobiletechnology/prowireless.htm 37 1.2.2.2 skrll */ 38 1.2.2.2 skrll 39 1.2.2.2 skrll #include "bpfilter.h" 40 1.2.2.2 skrll 41 1.2.2.2 skrll #include <sys/param.h> 42 1.2.2.2 skrll #include <sys/sockio.h> 43 1.2.2.2 skrll #include <sys/sysctl.h> 44 1.2.2.2 skrll #include <sys/mbuf.h> 45 1.2.2.2 skrll #include <sys/kernel.h> 46 1.2.2.2 skrll #include <sys/socket.h> 47 1.2.2.2 skrll #include <sys/systm.h> 48 1.2.2.2 skrll #include <sys/malloc.h> 49 1.2.2.2 skrll #include <sys/conf.h> 50 1.2.2.2 skrll 51 1.2.2.2 skrll #include <machine/bus.h> 52 1.2.2.2 skrll #include <machine/endian.h> 53 1.2.2.2 skrll #include <machine/intr.h> 54 1.2.2.2 skrll 55 1.2.2.2 skrll #include <dev/pci/pcireg.h> 56 1.2.2.2 skrll #include <dev/pci/pcivar.h> 57 1.2.2.2 skrll #include <dev/pci/pcidevs.h> 58 1.2.2.2 skrll 59 1.2.2.2 skrll #if NBPFILTER > 0 60 1.2.2.2 skrll #include <net/bpf.h> 61 1.2.2.2 skrll #endif 62 1.2.2.2 skrll #include <net/if.h> 63 1.2.2.2 skrll #include <net/if_arp.h> 64 1.2.2.2 skrll #include <net/if_dl.h> 65 1.2.2.2 skrll #include <net/if_ether.h> 66 1.2.2.2 skrll #include <net/if_media.h> 67 1.2.2.2 skrll #include <net/if_types.h> 68 1.2.2.2 skrll 69 1.2.2.2 skrll #include <net80211/ieee80211_var.h> 70 1.2.2.2 skrll 71 1.2.2.2 skrll #include <netinet/in.h> 72 1.2.2.2 skrll #include <netinet/in_systm.h> 73 1.2.2.2 skrll #include <netinet/in_var.h> 74 1.2.2.2 skrll #include <netinet/ip.h> 75 1.2.2.2 skrll 76 1.2.2.2 skrll #include "if_ipwreg.h" 77 1.2.2.2 skrll #include "if_ipwvar.h" 78 1.2.2.2 skrll 79 1.2.2.2 skrll static int ipw_match(struct device *, struct cfdata *, void *); 80 1.2.2.2 skrll static void ipw_attach(struct device *, struct device *, void *); 81 1.2.2.2 skrll static int ipw_detach(struct device *, int); 82 1.2.2.2 skrll static int ipw_media_change(struct ifnet *); 83 1.2.2.2 skrll static int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 84 1.2.2.2 skrll static void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 85 1.2.2.2 skrll static void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 86 1.2.2.2 skrll static void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 87 1.2.2.2 skrll struct ipw_soft_bd *, struct ipw_soft_buf *); 88 1.2.2.2 skrll static void ipw_notification_intr(struct ipw_softc *, struct ipw_soft_buf *); 89 1.2.2.2 skrll static void ipw_rx_intr(struct ipw_softc *); 90 1.2.2.2 skrll static void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 91 1.2.2.2 skrll static void ipw_tx_intr(struct ipw_softc *); 92 1.2.2.2 skrll static int ipw_intr(void *); 93 1.2.2.2 skrll static int ipw_cmd(struct ipw_softc *, u_int32_t, void *, u_int32_t); 94 1.2.2.2 skrll static int ipw_tx_start(struct ifnet *, struct mbuf *, struct ieee80211_node *); 95 1.2.2.2 skrll static void ipw_start(struct ifnet *); 96 1.2.2.2 skrll static void ipw_watchdog(struct ifnet *); 97 1.2.2.2 skrll static int ipw_get_table1(struct ipw_softc *, u_int32_t *); 98 1.2.2.2 skrll static int ipw_get_radio(struct ipw_softc *, int *); 99 1.2.2.2 skrll static int ipw_ioctl(struct ifnet *, u_long, caddr_t); 100 1.2.2.2 skrll static u_int32_t ipw_read_table1(struct ipw_softc *, u_int32_t); 101 1.2.2.2 skrll static void ipw_write_table1(struct ipw_softc *, u_int32_t, u_int32_t); 102 1.2.2.2 skrll static int ipw_read_table2(struct ipw_softc *, u_int32_t, void *, u_int32_t *); 103 1.2.2.2 skrll static int ipw_tx_init(struct ipw_softc *); 104 1.2.2.2 skrll static void ipw_tx_stop(struct ipw_softc *); 105 1.2.2.2 skrll static int ipw_rx_init(struct ipw_softc *); 106 1.2.2.2 skrll static void ipw_rx_stop(struct ipw_softc *); 107 1.2.2.2 skrll static void ipw_reset(struct ipw_softc *); 108 1.2.2.2 skrll static int ipw_clock_sync(struct ipw_softc *); 109 1.2.2.2 skrll static int ipw_load_ucode(struct ipw_softc *, u_char *, int); 110 1.2.2.2 skrll static int ipw_load_firmware(struct ipw_softc *, u_char *, int); 111 1.2.2.2 skrll static int ipw_firmware_init(struct ipw_softc *, u_char *); 112 1.2.2.2 skrll static int ipw_config(struct ipw_softc *); 113 1.2.2.2 skrll static int ipw_init(struct ifnet *); 114 1.2.2.2 skrll static void ipw_stop(struct ifnet *, int); 115 1.2.2.2 skrll static void ipw_read_mem_1(struct ipw_softc *, bus_size_t, u_int8_t *, 116 1.2.2.2 skrll bus_size_t); 117 1.2.2.2 skrll static void ipw_write_mem_1(struct ipw_softc *, bus_size_t, u_int8_t *, 118 1.2.2.2 skrll bus_size_t); 119 1.2.2.2 skrll static void ipw_zero_mem_4(struct ipw_softc *, bus_size_t, bus_size_t); 120 1.2.2.2 skrll 121 1.2.2.2 skrll static inline u_int8_t MEM_READ_1(struct ipw_softc *sc, u_int32_t addr) 122 1.2.2.2 skrll { 123 1.2.2.2 skrll CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 124 1.2.2.2 skrll return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); 125 1.2.2.2 skrll } 126 1.2.2.2 skrll 127 1.2.2.2 skrll static inline u_int16_t MEM_READ_2(struct ipw_softc *sc, u_int32_t addr) 128 1.2.2.2 skrll { 129 1.2.2.2 skrll CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 130 1.2.2.2 skrll return CSR_READ_2(sc, IPW_CSR_INDIRECT_DATA); 131 1.2.2.2 skrll } 132 1.2.2.2 skrll 133 1.2.2.2 skrll static inline u_int32_t MEM_READ_4(struct ipw_softc *sc, u_int32_t addr) 134 1.2.2.2 skrll { 135 1.2.2.2 skrll CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 136 1.2.2.2 skrll return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); 137 1.2.2.2 skrll } 138 1.2.2.2 skrll 139 1.2.2.2 skrll #ifdef IPW_DEBUG 140 1.2.2.2 skrll #define DPRINTF(x) if (ipw_debug > 0) printf x 141 1.2.2.2 skrll #define DPRINTFN(n, x) if (ipw_debug >= (n)) printf x 142 1.2.2.2 skrll int ipw_debug = 0; 143 1.2.2.2 skrll #else 144 1.2.2.2 skrll #define DPRINTF(x) 145 1.2.2.2 skrll #define DPRINTFN(n, x) 146 1.2.2.2 skrll #endif 147 1.2.2.2 skrll 148 1.2.2.2 skrll CFATTACH_DECL(ipw, sizeof (struct ipw_softc), ipw_match, ipw_attach, 149 1.2.2.2 skrll ipw_detach, NULL); 150 1.2.2.2 skrll 151 1.2.2.2 skrll static int 152 1.2.2.2 skrll ipw_match(struct device *parent, struct cfdata *match, void *aux) 153 1.2.2.2 skrll { 154 1.2.2.2 skrll struct pci_attach_args *pa = aux; 155 1.2.2.2 skrll 156 1.2.2.2 skrll if (PCI_VENDOR (pa->pa_id) == PCI_VENDOR_INTEL && 157 1.2.2.2 skrll PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_PRO_WL_2100) 158 1.2.2.2 skrll return 1; 159 1.2.2.2 skrll 160 1.2.2.2 skrll return 0; 161 1.2.2.2 skrll } 162 1.2.2.2 skrll 163 1.2.2.2 skrll /* Base Address Register */ 164 1.2.2.2 skrll #define IPW_PCI_BAR0 0x10 165 1.2.2.2 skrll 166 1.2.2.2 skrll static void 167 1.2.2.2 skrll ipw_attach(struct device *parent, struct device *self, void *aux) 168 1.2.2.2 skrll { 169 1.2.2.2 skrll struct ipw_softc *sc = (struct ipw_softc *)self; 170 1.2.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 171 1.2.2.2 skrll struct ifnet *ifp = &ic->ic_if; 172 1.2.2.2 skrll struct ieee80211_rateset *rs; 173 1.2.2.2 skrll struct pci_attach_args *pa = aux; 174 1.2.2.2 skrll const char *intrstr; 175 1.2.2.2 skrll char devinfo[256]; 176 1.2.2.2 skrll bus_space_tag_t memt; 177 1.2.2.2 skrll bus_space_handle_t memh; 178 1.2.2.2 skrll bus_addr_t base; 179 1.2.2.2 skrll pci_intr_handle_t ih; 180 1.2.2.2 skrll u_int32_t data; 181 1.2.2.2 skrll int i, revision, error; 182 1.2.2.2 skrll 183 1.2.2.2 skrll sc->sc_pct = pa->pa_pc; 184 1.2.2.2 skrll 185 1.2.2.2 skrll pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof devinfo); 186 1.2.2.2 skrll revision = PCI_REVISION(pa->pa_class); 187 1.2.2.2 skrll aprint_normal(": %s (rev. 0x%02x)\n", devinfo, revision); 188 1.2.2.2 skrll 189 1.2.2.2 skrll /* enable bus-mastering */ 190 1.2.2.2 skrll data = pci_conf_read(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG); 191 1.2.2.2 skrll data |= PCI_COMMAND_MASTER_ENABLE; 192 1.2.2.2 skrll pci_conf_write(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG, data); 193 1.2.2.2 skrll 194 1.2.2.2 skrll /* map the register window */ 195 1.2.2.2 skrll error = pci_mapreg_map(pa, IPW_PCI_BAR0, PCI_MAPREG_TYPE_MEM | 196 1.2.2.2 skrll PCI_MAPREG_MEM_TYPE_32BIT, 0, &memt, &memh, &base, &sc->sc_sz); 197 1.2.2.2 skrll if (error != 0) { 198 1.2.2.2 skrll aprint_error("%s: could not map memory space\n", 199 1.2.2.2 skrll sc->sc_dev.dv_xname); 200 1.2.2.2 skrll return; 201 1.2.2.2 skrll } 202 1.2.2.2 skrll 203 1.2.2.2 skrll sc->sc_st = memt; 204 1.2.2.2 skrll sc->sc_sh = memh; 205 1.2.2.2 skrll sc->sc_dmat = pa->pa_dmat; 206 1.2.2.2 skrll 207 1.2.2.2 skrll /* disable interrupts */ 208 1.2.2.2 skrll CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 209 1.2.2.2 skrll 210 1.2.2.2 skrll if (pci_intr_map(pa, &ih) != 0) { 211 1.2.2.2 skrll aprint_error("%s: could not map interrupt\n", 212 1.2.2.2 skrll sc->sc_dev.dv_xname); 213 1.2.2.2 skrll return; 214 1.2.2.2 skrll } 215 1.2.2.2 skrll 216 1.2.2.2 skrll intrstr = pci_intr_string(sc->sc_pct, ih); 217 1.2.2.2 skrll sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, ipw_intr, sc); 218 1.2.2.2 skrll if (sc->sc_ih == NULL) { 219 1.2.2.2 skrll aprint_error("%s: could not establish interrupt", 220 1.2.2.2 skrll sc->sc_dev.dv_xname); 221 1.2.2.2 skrll if (intrstr != NULL) 222 1.2.2.2 skrll aprint_error(" at %s", intrstr); 223 1.2.2.2 skrll aprint_error("\n"); 224 1.2.2.2 skrll return; 225 1.2.2.2 skrll } 226 1.2.2.2 skrll aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 227 1.2.2.2 skrll 228 1.2.2.2 skrll ic->ic_phytype = IEEE80211_T_DS; 229 1.2.2.2 skrll ic->ic_opmode = IEEE80211_M_STA; 230 1.2.2.2 skrll ic->ic_state = IEEE80211_S_INIT; 231 1.2.2.2 skrll 232 1.2.2.2 skrll /* set device capabilities */ 233 1.2.2.2 skrll ic->ic_caps = IEEE80211_C_IBSS | IEEE80211_C_MONITOR | 234 1.2.2.2 skrll IEEE80211_C_PMGT | IEEE80211_C_TXPMGT | IEEE80211_C_WEP; 235 1.2.2.2 skrll 236 1.2.2.2 skrll /* set supported 11.b rates */ 237 1.2.2.2 skrll rs = &ic->ic_sup_rates[IEEE80211_MODE_11B]; 238 1.2.2.2 skrll rs->rs_nrates = 4; 239 1.2.2.2 skrll rs->rs_rates[0] = 2; /* 1Mbps */ 240 1.2.2.2 skrll rs->rs_rates[1] = 4; /* 2Mbps */ 241 1.2.2.2 skrll rs->rs_rates[2] = 11; /* 5.5Mbps */ 242 1.2.2.2 skrll rs->rs_rates[3] = 22; /* 11Mbps */ 243 1.2.2.2 skrll 244 1.2.2.2 skrll /* set supported 11.b channels (1 through 14) */ 245 1.2.2.2 skrll for (i = 1; i <= 14; i++) { 246 1.2.2.2 skrll ic->ic_channels[i].ic_freq = 247 1.2.2.2 skrll ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 248 1.2.2.2 skrll ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 249 1.2.2.2 skrll } 250 1.2.2.2 skrll 251 1.2.2.2 skrll ic->ic_ibss_chan = &ic->ic_channels[0]; 252 1.2.2.2 skrll 253 1.2.2.2 skrll ifp->if_softc = sc; 254 1.2.2.2 skrll ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 255 1.2.2.2 skrll ifp->if_init = ipw_init; 256 1.2.2.2 skrll ifp->if_stop = ipw_stop; 257 1.2.2.2 skrll ifp->if_ioctl = ipw_ioctl; 258 1.2.2.2 skrll ifp->if_start = ipw_start; 259 1.2.2.2 skrll ifp->if_watchdog = ipw_watchdog; 260 1.2.2.2 skrll IFQ_SET_READY(&ifp->if_snd); 261 1.2.2.2 skrll bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 262 1.2.2.2 skrll 263 1.2.2.2 skrll if_attach(ifp); 264 1.2.2.2 skrll ieee80211_ifattach(ifp); 265 1.2.2.2 skrll /* override state transition machine */ 266 1.2.2.2 skrll sc->sc_newstate = ic->ic_newstate; 267 1.2.2.2 skrll ic->ic_newstate = ipw_newstate; 268 1.2.2.2 skrll 269 1.2.2.2 skrll ieee80211_media_init(ifp, ipw_media_change, ieee80211_media_status); 270 1.2.2.2 skrll } 271 1.2.2.2 skrll 272 1.2.2.2 skrll static int 273 1.2.2.2 skrll ipw_detach(struct device* self, int flags) 274 1.2.2.2 skrll { 275 1.2.2.2 skrll struct ipw_softc *sc = (struct ipw_softc *)self; 276 1.2.2.2 skrll struct ifnet *ifp = &sc->sc_ic.ic_if; 277 1.2.2.2 skrll 278 1.2.2.2 skrll ipw_reset(sc); 279 1.2.2.2 skrll 280 1.2.2.2 skrll ieee80211_ifdetach(ifp); 281 1.2.2.2 skrll if_detach(ifp); 282 1.2.2.2 skrll 283 1.2.2.2 skrll if (sc->sc_ih != NULL) { 284 1.2.2.2 skrll pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 285 1.2.2.2 skrll sc->sc_ih = NULL; 286 1.2.2.2 skrll } 287 1.2.2.2 skrll 288 1.2.2.2 skrll bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 289 1.2.2.2 skrll 290 1.2.2.2 skrll return 0; 291 1.2.2.2 skrll } 292 1.2.2.2 skrll 293 1.2.2.2 skrll static int 294 1.2.2.2 skrll ipw_media_change(struct ifnet *ifp) 295 1.2.2.2 skrll { 296 1.2.2.2 skrll int error; 297 1.2.2.2 skrll 298 1.2.2.2 skrll error = ieee80211_media_change(ifp); 299 1.2.2.2 skrll if (error != ENETRESET) 300 1.2.2.2 skrll return error; 301 1.2.2.2 skrll 302 1.2.2.2 skrll if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 303 1.2.2.2 skrll ipw_init(ifp); 304 1.2.2.2 skrll 305 1.2.2.2 skrll return 0; 306 1.2.2.2 skrll } 307 1.2.2.2 skrll 308 1.2.2.2 skrll static int 309 1.2.2.2 skrll ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 310 1.2.2.2 skrll { 311 1.2.2.2 skrll struct ifnet *ifp = &ic->ic_if; 312 1.2.2.2 skrll struct ipw_softc *sc = ifp->if_softc; 313 1.2.2.2 skrll struct ieee80211_node *ni = ic->ic_bss; 314 1.2.2.2 skrll u_int32_t val, len; 315 1.2.2.2 skrll 316 1.2.2.2 skrll switch (nstate) { 317 1.2.2.2 skrll case IEEE80211_S_INIT: 318 1.2.2.2 skrll break; 319 1.2.2.2 skrll 320 1.2.2.2 skrll case IEEE80211_S_RUN: 321 1.2.2.2 skrll len = IEEE80211_NWID_LEN; 322 1.2.2.2 skrll ipw_read_table2(sc, IPW_INFO_CURRENT_SSID, ni->ni_essid, &len); 323 1.2.2.2 skrll ni->ni_esslen = len; 324 1.2.2.2 skrll 325 1.2.2.2 skrll val = ipw_read_table1(sc, IPW_INFO_CURRENT_CHANNEL); 326 1.2.2.2 skrll ni->ni_chan = &ic->ic_channels[val]; 327 1.2.2.2 skrll 328 1.2.2.2 skrll DELAY(100); /* firmware needs a short delay here */ 329 1.2.2.2 skrll 330 1.2.2.2 skrll len = IEEE80211_ADDR_LEN; 331 1.2.2.2 skrll ipw_read_table2(sc, IPW_INFO_CURRENT_BSSID, ni->ni_bssid, &len); 332 1.2.2.2 skrll break; 333 1.2.2.2 skrll 334 1.2.2.2 skrll case IEEE80211_S_SCAN: 335 1.2.2.2 skrll case IEEE80211_S_AUTH: 336 1.2.2.2 skrll case IEEE80211_S_ASSOC: 337 1.2.2.2 skrll break; 338 1.2.2.2 skrll } 339 1.2.2.2 skrll 340 1.2.2.2 skrll ic->ic_state = nstate; 341 1.2.2.2 skrll return 0; 342 1.2.2.2 skrll } 343 1.2.2.2 skrll 344 1.2.2.2 skrll static void 345 1.2.2.2 skrll ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 346 1.2.2.2 skrll { 347 1.2.2.2 skrll struct ipw_cmd *cmd; 348 1.2.2.2 skrll 349 1.2.2.2 skrll bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof (struct ipw_cmd), 350 1.2.2.2 skrll BUS_DMASYNC_POSTREAD); 351 1.2.2.2 skrll 352 1.2.2.2 skrll cmd = mtod(sbuf->m, struct ipw_cmd *); 353 1.2.2.2 skrll 354 1.2.2.2 skrll DPRINTFN(2, ("RX!CMD!%u!%u!%u!%u!%u\n", 355 1.2.2.2 skrll le32toh(cmd->type), le32toh(cmd->subtype), le32toh(cmd->seq), 356 1.2.2.2 skrll le32toh(cmd->len), le32toh(cmd->status))); 357 1.2.2.2 skrll 358 1.2.2.2 skrll /* 359 1.2.2.2 skrll * Wake up processes waiting for command ack. In the case of the 360 1.2.2.2 skrll * IPW_CMD_DISABLE command, wake up the process only when the adapter 361 1.2.2.2 skrll * enters the IPW_STATE_DISABLED state. This is notified in 362 1.2.2.2 skrll * ipw_newstate_intr(). 363 1.2.2.2 skrll */ 364 1.2.2.2 skrll if (le32toh(cmd->type) != IPW_CMD_DISABLE) 365 1.2.2.2 skrll wakeup(sc->cmd); 366 1.2.2.2 skrll } 367 1.2.2.2 skrll 368 1.2.2.2 skrll static void 369 1.2.2.2 skrll ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 370 1.2.2.2 skrll { 371 1.2.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 372 1.2.2.2 skrll u_int32_t state; 373 1.2.2.2 skrll 374 1.2.2.2 skrll bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof state, 375 1.2.2.2 skrll BUS_DMASYNC_POSTREAD); 376 1.2.2.2 skrll 377 1.2.2.2 skrll state = le32toh(*mtod(sbuf->m, u_int32_t *)); 378 1.2.2.2 skrll 379 1.2.2.2 skrll DPRINTFN(2, ("RX!NEWSTATE!%u\n", state)); 380 1.2.2.2 skrll 381 1.2.2.2 skrll switch (state) { 382 1.2.2.2 skrll case IPW_STATE_ASSOCIATED: 383 1.2.2.2 skrll ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 384 1.2.2.2 skrll break; 385 1.2.2.2 skrll 386 1.2.2.2 skrll case IPW_STATE_SCANNING: 387 1.2.2.2 skrll ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 388 1.2.2.2 skrll break; 389 1.2.2.2 skrll 390 1.2.2.2 skrll case IPW_STATE_ASSOCIATION_LOST: 391 1.2.2.2 skrll ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 392 1.2.2.2 skrll break; 393 1.2.2.2 skrll 394 1.2.2.2 skrll case IPW_STATE_DISABLED: 395 1.2.2.2 skrll wakeup(sc->cmd); 396 1.2.2.2 skrll break; 397 1.2.2.2 skrll 398 1.2.2.2 skrll case IPW_STATE_RADIO_DISABLED: 399 1.2.2.2 skrll /* XXX should turn the interface down */ 400 1.2.2.2 skrll break; 401 1.2.2.2 skrll } 402 1.2.2.2 skrll } 403 1.2.2.2 skrll 404 1.2.2.2 skrll static void 405 1.2.2.2 skrll ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 406 1.2.2.2 skrll struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 407 1.2.2.2 skrll { 408 1.2.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 409 1.2.2.2 skrll struct ifnet *ifp = &ic->ic_if; 410 1.2.2.2 skrll struct mbuf *m; 411 1.2.2.2 skrll struct ieee80211_frame *wh; 412 1.2.2.2 skrll struct ieee80211_node *ni; 413 1.2.2.2 skrll int error; 414 1.2.2.2 skrll 415 1.2.2.2 skrll DPRINTFN(5, ("RX!DATA!%u!%u\n", le32toh(status->len), status->rssi)); 416 1.2.2.2 skrll 417 1.2.2.2 skrll bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, le32toh(status->len), 418 1.2.2.2 skrll BUS_DMASYNC_POSTREAD); 419 1.2.2.2 skrll 420 1.2.2.2 skrll bus_dmamap_unload(sc->sc_dmat, sbuf->map); 421 1.2.2.2 skrll 422 1.2.2.2 skrll /* Finalize mbuf */ 423 1.2.2.2 skrll m = sbuf->m; 424 1.2.2.2 skrll m->m_pkthdr.rcvif = ifp; 425 1.2.2.2 skrll m->m_pkthdr.len = m->m_len = le32toh(status->len); 426 1.2.2.2 skrll 427 1.2.2.2 skrll wh = mtod(m, struct ieee80211_frame *); 428 1.2.2.2 skrll 429 1.2.2.2 skrll if (ic->ic_opmode != IEEE80211_M_STA) { 430 1.2.2.2 skrll ni = ieee80211_find_node(ic, wh->i_addr2); 431 1.2.2.2 skrll if (ni == NULL) 432 1.2.2.2 skrll ni = ieee80211_ref_node(ic->ic_bss); 433 1.2.2.2 skrll } else 434 1.2.2.2 skrll ni = ieee80211_ref_node(ic->ic_bss); 435 1.2.2.2 skrll 436 1.2.2.2 skrll /* Send it up to the upper layer */ 437 1.2.2.2 skrll ieee80211_input(ifp, m, ni, status->rssi, 0/*rstamp*/); 438 1.2.2.2 skrll 439 1.2.2.2 skrll ieee80211_release_node(ic, ni); 440 1.2.2.2 skrll 441 1.2.2.2 skrll MGETHDR(m, M_DONTWAIT, MT_DATA); 442 1.2.2.2 skrll if (m == NULL) { 443 1.2.2.2 skrll aprint_error("%s: could not allocate rx mbuf\n", 444 1.2.2.2 skrll sc->sc_dev.dv_xname); 445 1.2.2.2 skrll return; 446 1.2.2.2 skrll } 447 1.2.2.2 skrll MCLGET(m, M_DONTWAIT); 448 1.2.2.2 skrll if (!(m->m_flags & M_EXT)) { 449 1.2.2.2 skrll m_freem(m); 450 1.2.2.2 skrll aprint_error("%s: could not allocate rx mbuf cluster\n", 451 1.2.2.2 skrll sc->sc_dev.dv_xname); 452 1.2.2.2 skrll return; 453 1.2.2.2 skrll } 454 1.2.2.2 skrll 455 1.2.2.2 skrll error = bus_dmamap_load(sc->sc_dmat, sbuf->map, mtod(m, void *), 456 1.2.2.2 skrll MCLBYTES, NULL, BUS_DMA_NOWAIT); 457 1.2.2.2 skrll if (error != 0) { 458 1.2.2.2 skrll aprint_error("%s: could not map rxbuf dma memory\n", 459 1.2.2.2 skrll sc->sc_dev.dv_xname); 460 1.2.2.2 skrll m_freem(m); 461 1.2.2.2 skrll return; 462 1.2.2.2 skrll } 463 1.2.2.2 skrll 464 1.2.2.2 skrll sbuf->m = m; 465 1.2.2.2 skrll sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 466 1.2.2.2 skrll } 467 1.2.2.2 skrll 468 1.2.2.2 skrll static void 469 1.2.2.2 skrll ipw_notification_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 470 1.2.2.2 skrll { 471 1.2.2.2 skrll DPRINTFN(2, ("RX!NOTIFICATION\n")); 472 1.2.2.2 skrll } 473 1.2.2.2 skrll 474 1.2.2.2 skrll static void 475 1.2.2.2 skrll ipw_rx_intr(struct ipw_softc *sc) 476 1.2.2.2 skrll { 477 1.2.2.2 skrll struct ipw_status *status; 478 1.2.2.2 skrll struct ipw_soft_bd *sbd; 479 1.2.2.2 skrll struct ipw_soft_buf *sbuf; 480 1.2.2.2 skrll u_int32_t r, i; 481 1.2.2.2 skrll 482 1.2.2.2 skrll r = CSR_READ_4(sc, IPW_CSR_RX_READ_INDEX); 483 1.2.2.2 skrll 484 1.2.2.2 skrll for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 485 1.2.2.2 skrll 486 1.2.2.2 skrll bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 487 1.2.2.2 skrll i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 488 1.2.2.2 skrll BUS_DMASYNC_POSTREAD); 489 1.2.2.2 skrll 490 1.2.2.2 skrll bus_dmamap_sync(sc->sc_dmat, sc->status_map, 491 1.2.2.2 skrll i * sizeof (struct ipw_status), sizeof (struct ipw_status), 492 1.2.2.2 skrll BUS_DMASYNC_POSTREAD); 493 1.2.2.2 skrll 494 1.2.2.2 skrll status = &sc->status_list[i]; 495 1.2.2.2 skrll sbd = &sc->srbd_list[i]; 496 1.2.2.2 skrll sbuf = sbd->priv; 497 1.2.2.2 skrll 498 1.2.2.2 skrll switch (le16toh(status->code) & 0xf) { 499 1.2.2.2 skrll case IPW_STATUS_CODE_COMMAND: 500 1.2.2.2 skrll ipw_command_intr(sc, sbuf); 501 1.2.2.2 skrll break; 502 1.2.2.2 skrll 503 1.2.2.2 skrll case IPW_STATUS_CODE_NEWSTATE: 504 1.2.2.2 skrll ipw_newstate_intr(sc, sbuf); 505 1.2.2.2 skrll break; 506 1.2.2.2 skrll 507 1.2.2.2 skrll case IPW_STATUS_CODE_DATA_802_3: 508 1.2.2.2 skrll case IPW_STATUS_CODE_DATA_802_11: 509 1.2.2.2 skrll ipw_data_intr(sc, status, sbd, sbuf); 510 1.2.2.2 skrll break; 511 1.2.2.2 skrll 512 1.2.2.2 skrll case IPW_STATUS_CODE_NOTIFICATION: 513 1.2.2.2 skrll ipw_notification_intr(sc, sbuf); 514 1.2.2.2 skrll break; 515 1.2.2.2 skrll 516 1.2.2.2 skrll default: 517 1.2.2.2 skrll aprint_debug("%s: unknown status code %u\n", 518 1.2.2.2 skrll sc->sc_dev.dv_xname, le16toh(status->code)); 519 1.2.2.2 skrll } 520 1.2.2.2 skrll sbd->bd->flags = 0; 521 1.2.2.2 skrll 522 1.2.2.2 skrll bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 523 1.2.2.2 skrll i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 524 1.2.2.2 skrll BUS_DMASYNC_PREWRITE); 525 1.2.2.2 skrll } 526 1.2.2.2 skrll 527 1.2.2.2 skrll /* Tell the firmware what we have processed */ 528 1.2.2.2 skrll sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 529 1.2.2.2 skrll CSR_WRITE_4(sc, IPW_CSR_RX_WRITE_INDEX, sc->rxcur); 530 1.2.2.2 skrll } 531 1.2.2.2 skrll 532 1.2.2.2 skrll static void 533 1.2.2.2 skrll ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 534 1.2.2.2 skrll { 535 1.2.2.2 skrll struct ieee80211com *ic; 536 1.2.2.2 skrll struct ipw_soft_hdr *shdr; 537 1.2.2.2 skrll struct ipw_soft_buf *sbuf; 538 1.2.2.2 skrll 539 1.2.2.2 skrll switch (sbd->type) { 540 1.2.2.2 skrll case IPW_SBD_TYPE_COMMAND: 541 1.2.2.2 skrll bus_dmamap_unload(sc->sc_dmat, sc->cmd_map); 542 1.2.2.2 skrll break; 543 1.2.2.2 skrll 544 1.2.2.2 skrll case IPW_SBD_TYPE_HEADER: 545 1.2.2.2 skrll shdr = sbd->priv; 546 1.2.2.2 skrll bus_dmamap_unload(sc->sc_dmat, shdr->map); 547 1.2.2.2 skrll TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 548 1.2.2.2 skrll break; 549 1.2.2.2 skrll 550 1.2.2.2 skrll case IPW_SBD_TYPE_DATA: 551 1.2.2.2 skrll ic = &sc->sc_ic; 552 1.2.2.2 skrll sbuf = sbd->priv; 553 1.2.2.2 skrll bus_dmamap_unload(sc->sc_dmat, sbuf->map); 554 1.2.2.2 skrll m_freem(sbuf->m); 555 1.2.2.2 skrll if (sbuf->ni != NULL) 556 1.2.2.2 skrll ieee80211_release_node(ic, sbuf->ni); 557 1.2.2.2 skrll /* kill watchdog timer */ 558 1.2.2.2 skrll sc->sc_tx_timer = 0; 559 1.2.2.2 skrll TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 560 1.2.2.2 skrll break; 561 1.2.2.2 skrll } 562 1.2.2.2 skrll sbd->type = IPW_SBD_TYPE_NOASSOC; 563 1.2.2.2 skrll } 564 1.2.2.2 skrll 565 1.2.2.2 skrll static void 566 1.2.2.2 skrll ipw_tx_intr(struct ipw_softc *sc) 567 1.2.2.2 skrll { 568 1.2.2.2 skrll struct ifnet *ifp = &sc->sc_ic.ic_if; 569 1.2.2.2 skrll u_int32_t r, i; 570 1.2.2.2 skrll 571 1.2.2.2 skrll r = CSR_READ_4(sc, IPW_CSR_TX_READ_INDEX); 572 1.2.2.2 skrll 573 1.2.2.2 skrll for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) 574 1.2.2.2 skrll ipw_release_sbd(sc, &sc->stbd_list[i]); 575 1.2.2.2 skrll 576 1.2.2.2 skrll /* Remember what the firmware has processed */ 577 1.2.2.2 skrll sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 578 1.2.2.2 skrll 579 1.2.2.2 skrll /* Call start() since some buffer descriptors have been released */ 580 1.2.2.2 skrll ifp->if_flags &= ~IFF_OACTIVE; 581 1.2.2.2 skrll (*ifp->if_start)(ifp); 582 1.2.2.2 skrll } 583 1.2.2.2 skrll 584 1.2.2.2 skrll static int 585 1.2.2.2 skrll ipw_intr(void *arg) 586 1.2.2.2 skrll { 587 1.2.2.2 skrll struct ipw_softc *sc = arg; 588 1.2.2.2 skrll u_int32_t r; 589 1.2.2.2 skrll 590 1.2.2.2 skrll if ((r = CSR_READ_4(sc, IPW_CSR_INTR)) == 0) 591 1.2.2.2 skrll return 0; 592 1.2.2.2 skrll 593 1.2.2.2 skrll /* Disable interrupts */ 594 1.2.2.2 skrll CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 595 1.2.2.2 skrll 596 1.2.2.2 skrll DPRINTFN(8, ("INTR!0x%08x\n", r)); 597 1.2.2.2 skrll 598 1.2.2.2 skrll if (r & IPW_INTR_RX_TRANSFER) 599 1.2.2.2 skrll ipw_rx_intr(sc); 600 1.2.2.2 skrll 601 1.2.2.2 skrll if (r & IPW_INTR_TX_TRANSFER) 602 1.2.2.2 skrll ipw_tx_intr(sc); 603 1.2.2.2 skrll 604 1.2.2.2 skrll if (r & IPW_INTR_FW_INIT_DONE) { 605 1.2.2.2 skrll if (!(r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR))) 606 1.2.2.2 skrll wakeup(sc); 607 1.2.2.2 skrll } 608 1.2.2.2 skrll 609 1.2.2.2 skrll /* Acknowledge interrupts */ 610 1.2.2.2 skrll CSR_WRITE_4(sc, IPW_CSR_INTR, r); 611 1.2.2.2 skrll 612 1.2.2.2 skrll /* Re-enable interrupts */ 613 1.2.2.2 skrll CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 614 1.2.2.2 skrll 615 1.2.2.2 skrll return 0; 616 1.2.2.2 skrll } 617 1.2.2.2 skrll 618 1.2.2.2 skrll static int 619 1.2.2.2 skrll ipw_cmd(struct ipw_softc *sc, u_int32_t type, void *data, u_int32_t len) 620 1.2.2.2 skrll { 621 1.2.2.2 skrll struct ipw_soft_bd *sbd; 622 1.2.2.2 skrll int error; 623 1.2.2.2 skrll 624 1.2.2.2 skrll sbd = &sc->stbd_list[sc->txcur]; 625 1.2.2.2 skrll 626 1.2.2.2 skrll error = bus_dmamap_load(sc->sc_dmat, sc->cmd_map, sc->cmd, 627 1.2.2.2 skrll sizeof (struct ipw_cmd), NULL, BUS_DMA_NOWAIT); 628 1.2.2.2 skrll if (error != 0) { 629 1.2.2.2 skrll aprint_error("%s: could not map cmd dma memory\n", 630 1.2.2.2 skrll sc->sc_dev.dv_xname); 631 1.2.2.2 skrll return error; 632 1.2.2.2 skrll } 633 1.2.2.2 skrll 634 1.2.2.2 skrll sc->cmd->type = htole32(type); 635 1.2.2.2 skrll sc->cmd->subtype = htole32(0); 636 1.2.2.2 skrll sc->cmd->len = htole32(len); 637 1.2.2.2 skrll sc->cmd->seq = htole32(0); 638 1.2.2.2 skrll if (data != NULL) 639 1.2.2.2 skrll bcopy(data, sc->cmd->data, len); 640 1.2.2.2 skrll 641 1.2.2.2 skrll sbd->type = IPW_SBD_TYPE_COMMAND; 642 1.2.2.2 skrll sbd->bd->physaddr = htole32(sc->cmd_map->dm_segs[0].ds_addr); 643 1.2.2.2 skrll sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 644 1.2.2.2 skrll sbd->bd->nfrag = 1; 645 1.2.2.2 skrll sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 646 1.2.2.2 skrll IPW_BD_FLAG_TX_LAST_FRAGMENT; 647 1.2.2.2 skrll 648 1.2.2.2 skrll bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 0, sizeof (struct ipw_cmd), 649 1.2.2.2 skrll BUS_DMASYNC_PREWRITE); 650 1.2.2.2 skrll 651 1.2.2.2 skrll bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 652 1.2.2.2 skrll sc->txcur * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 653 1.2.2.2 skrll BUS_DMASYNC_PREWRITE); 654 1.2.2.2 skrll 655 1.2.2.2 skrll sc->txcur = (sc->txcur + 1) % IPW_NTBD; 656 1.2.2.2 skrll CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, sc->txcur); 657 1.2.2.2 skrll 658 1.2.2.2 skrll DPRINTFN(2, ("TX!CMD!%u!%u!%u!%u\n", type, 0, 0, len)); 659 1.2.2.2 skrll 660 1.2.2.2 skrll /* Wait at most two seconds for command to complete */ 661 1.2.2.2 skrll return tsleep(sc->cmd, 0, "ipwcmd", 2 * hz); 662 1.2.2.2 skrll } 663 1.2.2.2 skrll 664 1.2.2.2 skrll static int 665 1.2.2.2 skrll ipw_tx_start(struct ifnet *ifp, struct mbuf *m, struct ieee80211_node *ni) 666 1.2.2.2 skrll { 667 1.2.2.2 skrll struct ipw_softc *sc = ifp->if_softc; 668 1.2.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 669 1.2.2.2 skrll struct ieee80211_frame *wh; 670 1.2.2.2 skrll struct ipw_soft_bd *sbd; 671 1.2.2.2 skrll struct ipw_soft_hdr *shdr; 672 1.2.2.2 skrll struct ipw_soft_buf *sbuf; 673 1.2.2.2 skrll int error, i; 674 1.2.2.2 skrll 675 1.2.2.2 skrll if (ic->ic_flags & IEEE80211_F_PRIVACY) { 676 1.2.2.2 skrll m = ieee80211_wep_crypt(ifp, m, 1); 677 1.2.2.2 skrll if (m == NULL) 678 1.2.2.2 skrll return ENOBUFS; 679 1.2.2.2 skrll } 680 1.2.2.2 skrll 681 1.2.2.2 skrll wh = mtod(m, struct ieee80211_frame *); 682 1.2.2.2 skrll 683 1.2.2.2 skrll shdr = TAILQ_FIRST(&sc->sc_free_shdr); 684 1.2.2.2 skrll sbuf = TAILQ_FIRST(&sc->sc_free_sbuf); 685 1.2.2.2 skrll 686 1.2.2.2 skrll shdr->hdr.type = htole32(IPW_HDR_TYPE_SEND); 687 1.2.2.2 skrll shdr->hdr.subtype = htole32(0); 688 1.2.2.2 skrll shdr->hdr.encrypted = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0; 689 1.2.2.2 skrll shdr->hdr.encrypt = 0; 690 1.2.2.2 skrll shdr->hdr.keyidx = 0; 691 1.2.2.2 skrll shdr->hdr.keysz = 0; 692 1.2.2.2 skrll shdr->hdr.fragmentsz = htole16(0); 693 1.2.2.2 skrll IEEE80211_ADDR_COPY(shdr->hdr.src_addr, wh->i_addr2); 694 1.2.2.2 skrll if (ic->ic_opmode == IEEE80211_M_STA) 695 1.2.2.2 skrll IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr3); 696 1.2.2.2 skrll else 697 1.2.2.2 skrll IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr1); 698 1.2.2.2 skrll 699 1.2.2.2 skrll /* trim IEEE802.11 header */ 700 1.2.2.2 skrll m_adj(m, sizeof (struct ieee80211_frame)); 701 1.2.2.2 skrll 702 1.2.2.2 skrll /* 703 1.2.2.2 skrll * We need to map the mbuf first to know how many buffer descriptors 704 1.2.2.2 skrll * are needed for this transfer. 705 1.2.2.2 skrll */ 706 1.2.2.2 skrll error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m, BUS_DMA_NOWAIT); 707 1.2.2.2 skrll if (error != 0) { 708 1.2.2.2 skrll aprint_error("%s: could not map mbuf (error %d)\n", 709 1.2.2.2 skrll sc->sc_dev.dv_xname, error); 710 1.2.2.2 skrll m_freem(m); 711 1.2.2.2 skrll return error; 712 1.2.2.2 skrll } 713 1.2.2.2 skrll 714 1.2.2.2 skrll error = bus_dmamap_load(sc->sc_dmat, shdr->map, &shdr->hdr, 715 1.2.2.2 skrll sizeof (struct ipw_hdr), NULL, BUS_DMA_NOWAIT); 716 1.2.2.2 skrll if (error != 0) { 717 1.2.2.2 skrll aprint_error("%s: could not map hdr (error %d)\n", 718 1.2.2.2 skrll sc->sc_dev.dv_xname, error); 719 1.2.2.2 skrll bus_dmamap_unload(sc->sc_dmat, sbuf->map); 720 1.2.2.2 skrll m_freem(m); 721 1.2.2.2 skrll return error; 722 1.2.2.2 skrll } 723 1.2.2.2 skrll 724 1.2.2.2 skrll TAILQ_REMOVE(&sc->sc_free_sbuf, sbuf, next); 725 1.2.2.2 skrll TAILQ_REMOVE(&sc->sc_free_shdr, shdr, next); 726 1.2.2.2 skrll 727 1.2.2.2 skrll sbd = &sc->stbd_list[sc->txcur]; 728 1.2.2.2 skrll sbd->type = IPW_SBD_TYPE_HEADER; 729 1.2.2.2 skrll sbd->priv = shdr; 730 1.2.2.2 skrll sbd->bd->physaddr = htole32(shdr->map->dm_segs[0].ds_addr); 731 1.2.2.2 skrll sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 732 1.2.2.2 skrll sbd->bd->nfrag = 1 + sbuf->map->dm_nsegs; 733 1.2.2.2 skrll sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 734 1.2.2.2 skrll IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 735 1.2.2.2 skrll 736 1.2.2.2 skrll DPRINTFN(5, ("TX!HDR!%u!%u!%u!%u\n", shdr->hdr.type, shdr->hdr.subtype, 737 1.2.2.2 skrll shdr->hdr.encrypted, shdr->hdr.encrypt)); 738 1.2.2.2 skrll DPRINTFN(5, ("!%s", ether_sprintf(shdr->hdr.src_addr))); 739 1.2.2.2 skrll DPRINTFN(5, ("!%s\n", ether_sprintf(shdr->hdr.dst_addr))); 740 1.2.2.2 skrll sc->txcur = (sc->txcur + 1) % IPW_NTBD; 741 1.2.2.2 skrll 742 1.2.2.2 skrll sbuf->m = m; 743 1.2.2.2 skrll sbuf->ni = ni; 744 1.2.2.2 skrll 745 1.2.2.2 skrll for (i = 0; i < sbuf->map->dm_nsegs; i++) { 746 1.2.2.2 skrll sbd = &sc->stbd_list[sc->txcur]; 747 1.2.2.2 skrll sbd->bd->physaddr = htole32(sbuf->map->dm_segs[i].ds_addr); 748 1.2.2.2 skrll sbd->bd->len = htole32(sbuf->map->dm_segs[i].ds_len); 749 1.2.2.2 skrll sbd->bd->nfrag = 0; /* used only in first bd */ 750 1.2.2.2 skrll sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 751 1.2.2.2 skrll if (i == sbuf->map->dm_nsegs - 1) { 752 1.2.2.2 skrll sbd->type = IPW_SBD_TYPE_DATA; 753 1.2.2.2 skrll sbd->priv = sbuf; 754 1.2.2.2 skrll sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 755 1.2.2.2 skrll } else { 756 1.2.2.2 skrll sbd->type = IPW_SBD_TYPE_NOASSOC; 757 1.2.2.2 skrll sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 758 1.2.2.2 skrll } 759 1.2.2.2 skrll 760 1.2.2.2 skrll DPRINTFN(5, ("TX!FRAG!%d!%ld\n", i, 761 1.2.2.2 skrll sbuf->map->dm_segs[i].ds_len)); 762 1.2.2.2 skrll 763 1.2.2.2 skrll bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 764 1.2.2.2 skrll sc->txcur * sizeof (struct ipw_bd), 765 1.2.2.2 skrll sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 766 1.2.2.2 skrll 767 1.2.2.2 skrll sc->txcur = (sc->txcur + 1) % IPW_NTBD; 768 1.2.2.2 skrll } 769 1.2.2.2 skrll 770 1.2.2.2 skrll bus_dmamap_sync(sc->sc_dmat, shdr->map, 0, sizeof (struct ipw_hdr), 771 1.2.2.2 skrll BUS_DMASYNC_PREWRITE); 772 1.2.2.2 skrll 773 1.2.2.2 skrll bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, MCLBYTES, 774 1.2.2.2 skrll BUS_DMASYNC_PREWRITE); 775 1.2.2.2 skrll 776 1.2.2.2 skrll /* Inform firmware about this new packet */ 777 1.2.2.2 skrll CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, sc->txcur); 778 1.2.2.2 skrll 779 1.2.2.2 skrll return 0; 780 1.2.2.2 skrll } 781 1.2.2.2 skrll 782 1.2.2.2 skrll static void 783 1.2.2.2 skrll ipw_start(struct ifnet *ifp) 784 1.2.2.2 skrll { 785 1.2.2.2 skrll struct ipw_softc *sc = ifp->if_softc; 786 1.2.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 787 1.2.2.2 skrll struct mbuf *m; 788 1.2.2.2 skrll struct ieee80211_node *ni; 789 1.2.2.2 skrll 790 1.2.2.2 skrll for (;;) { 791 1.2.2.2 skrll IF_DEQUEUE(&ifp->if_snd, m); 792 1.2.2.2 skrll if (m == NULL) 793 1.2.2.2 skrll break; 794 1.2.2.2 skrll 795 1.2.2.2 skrll #if NBPFILTER > 0 796 1.2.2.2 skrll if (ifp->if_bpf != NULL) 797 1.2.2.2 skrll bpf_mtap(ifp->if_bpf, m); 798 1.2.2.2 skrll #endif 799 1.2.2.2 skrll 800 1.2.2.2 skrll m = ieee80211_encap(ifp, m, &ni); 801 1.2.2.2 skrll if (m == NULL) 802 1.2.2.2 skrll continue; 803 1.2.2.2 skrll 804 1.2.2.2 skrll #if NBPFILTER > 0 805 1.2.2.2 skrll if (ic->ic_rawbpf != NULL) 806 1.2.2.2 skrll bpf_mtap(ic->ic_rawbpf, m); 807 1.2.2.2 skrll #endif 808 1.2.2.2 skrll 809 1.2.2.2 skrll if (ipw_tx_start(ifp, m, ni) != 0) { 810 1.2.2.2 skrll if (ni != NULL) 811 1.2.2.2 skrll ieee80211_release_node(ic, ni); 812 1.2.2.2 skrll break; 813 1.2.2.2 skrll } 814 1.2.2.2 skrll 815 1.2.2.2 skrll /* start watchdog timer */ 816 1.2.2.2 skrll sc->sc_tx_timer = 5; 817 1.2.2.2 skrll ifp->if_timer = 1; 818 1.2.2.2 skrll } 819 1.2.2.2 skrll } 820 1.2.2.2 skrll 821 1.2.2.2 skrll static void 822 1.2.2.2 skrll ipw_watchdog(struct ifnet *ifp) 823 1.2.2.2 skrll { 824 1.2.2.2 skrll struct ipw_softc *sc = ifp->if_softc; 825 1.2.2.2 skrll 826 1.2.2.2 skrll ifp->if_timer = 0; 827 1.2.2.2 skrll 828 1.2.2.2 skrll if (sc->sc_tx_timer > 0) { 829 1.2.2.2 skrll if (--sc->sc_tx_timer == 0) { 830 1.2.2.2 skrll aprint_error("%s: device timeout\n", 831 1.2.2.2 skrll sc->sc_dev.dv_xname); 832 1.2.2.2 skrll #ifdef notyet 833 1.2.2.2 skrll ipw_init(ifp); 834 1.2.2.2 skrll #endif 835 1.2.2.2 skrll return; 836 1.2.2.2 skrll } 837 1.2.2.2 skrll ifp->if_timer = 1; 838 1.2.2.2 skrll } 839 1.2.2.2 skrll 840 1.2.2.2 skrll ieee80211_watchdog(ifp); 841 1.2.2.2 skrll } 842 1.2.2.2 skrll 843 1.2.2.2 skrll static int 844 1.2.2.2 skrll ipw_get_table1(struct ipw_softc *sc, u_int32_t *tbl) 845 1.2.2.2 skrll { 846 1.2.2.2 skrll u_int32_t addr, size, i; 847 1.2.2.2 skrll 848 1.2.2.2 skrll if (!(sc->flags & IPW_FLAG_FW_INITED)) 849 1.2.2.2 skrll return ENOTTY; 850 1.2.2.2 skrll 851 1.2.2.2 skrll CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, sc->table1_base); 852 1.2.2.2 skrll 853 1.2.2.2 skrll size = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 854 1.2.2.2 skrll if (suword(tbl, size) != 0) 855 1.2.2.2 skrll return EFAULT; 856 1.2.2.2 skrll 857 1.2.2.2 skrll for (i = 1, ++tbl; i < size; i++, tbl++) { 858 1.2.2.2 skrll addr = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 859 1.2.2.2 skrll if (suword(tbl, MEM_READ_4(sc, addr)) != 0) 860 1.2.2.2 skrll return EFAULT; 861 1.2.2.2 skrll } 862 1.2.2.2 skrll return 0; 863 1.2.2.2 skrll } 864 1.2.2.2 skrll 865 1.2.2.2 skrll static int 866 1.2.2.2 skrll ipw_get_radio(struct ipw_softc *sc, int *ret) 867 1.2.2.2 skrll { 868 1.2.2.2 skrll u_int32_t addr; 869 1.2.2.2 skrll 870 1.2.2.2 skrll if (!(sc->flags & IPW_FLAG_FW_INITED)) 871 1.2.2.2 skrll return ENOTTY; 872 1.2.2.2 skrll 873 1.2.2.2 skrll addr = ipw_read_table1(sc, IPW_INFO_EEPROM_ADDRESS); 874 1.2.2.2 skrll if ((MEM_READ_4(sc, addr + 32) >> 24) & 1) { 875 1.2.2.2 skrll suword(ret, -1); 876 1.2.2.2 skrll return 0; 877 1.2.2.2 skrll } 878 1.2.2.2 skrll 879 1.2.2.2 skrll if (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED) 880 1.2.2.2 skrll suword(ret, 0); 881 1.2.2.2 skrll else 882 1.2.2.2 skrll suword(ret, 1); 883 1.2.2.2 skrll 884 1.2.2.2 skrll return 0; 885 1.2.2.2 skrll } 886 1.2.2.2 skrll 887 1.2.2.2 skrll static int 888 1.2.2.2 skrll ipw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 889 1.2.2.2 skrll { 890 1.2.2.2 skrll struct ipw_softc *sc = ifp->if_softc; 891 1.2.2.2 skrll struct ifreq *ifr; 892 1.2.2.2 skrll int s, error = 0; 893 1.2.2.2 skrll 894 1.2.2.2 skrll s = splnet(); 895 1.2.2.2 skrll 896 1.2.2.2 skrll switch (cmd) { 897 1.2.2.2 skrll case SIOCSIFFLAGS: 898 1.2.2.2 skrll if (ifp->if_flags & IFF_UP) { 899 1.2.2.2 skrll if (!(ifp->if_flags & IFF_RUNNING)) 900 1.2.2.2 skrll ipw_init(ifp); 901 1.2.2.2 skrll } else { 902 1.2.2.2 skrll if (ifp->if_flags & IFF_RUNNING) 903 1.2.2.2 skrll ipw_stop(ifp, 1); 904 1.2.2.2 skrll } 905 1.2.2.2 skrll break; 906 1.2.2.2 skrll 907 1.2.2.2 skrll case SIOCGTABLE1: 908 1.2.2.2 skrll ifr = (struct ifreq *)data; 909 1.2.2.2 skrll error = ipw_get_table1(sc, (u_int32_t *)ifr->ifr_data); 910 1.2.2.2 skrll break; 911 1.2.2.2 skrll 912 1.2.2.2 skrll case SIOCGRADIO: 913 1.2.2.2 skrll ifr = (struct ifreq *)data; 914 1.2.2.2 skrll error = ipw_get_radio(sc, (int *)ifr->ifr_data); 915 1.2.2.2 skrll break; 916 1.2.2.2 skrll 917 1.2.2.2 skrll case SIOCSLOADFW: 918 1.2.2.2 skrll /* only super-user can do that! */ 919 1.2.2.2 skrll if ((error = suser(curproc->p_ucred, &curproc->p_acflag)) != 0) 920 1.2.2.2 skrll break; 921 1.2.2.2 skrll 922 1.2.2.2 skrll ifr = (struct ifreq *)data; 923 1.2.2.2 skrll error = ipw_firmware_init(sc, (u_char *)ifr->ifr_data); 924 1.2.2.2 skrll break; 925 1.2.2.2 skrll 926 1.2.2.2 skrll case SIOCSKILLFW: 927 1.2.2.2 skrll /* only super-user can do that! */ 928 1.2.2.2 skrll if ((error = suser(curproc->p_ucred, &curproc->p_acflag)) != 0) 929 1.2.2.2 skrll break; 930 1.2.2.2 skrll 931 1.2.2.2 skrll ipw_reset(sc); 932 1.2.2.2 skrll break; 933 1.2.2.2 skrll 934 1.2.2.2 skrll default: 935 1.2.2.2 skrll error = ieee80211_ioctl(ifp, cmd, data); 936 1.2.2.2 skrll if (error != ENETRESET) 937 1.2.2.2 skrll break; 938 1.2.2.2 skrll 939 1.2.2.2 skrll if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 940 1.2.2.2 skrll (IFF_UP | IFF_RUNNING)) 941 1.2.2.2 skrll ipw_init(ifp); 942 1.2.2.2 skrll error = 0; 943 1.2.2.2 skrll } 944 1.2.2.2 skrll 945 1.2.2.2 skrll splx(s); 946 1.2.2.2 skrll return error; 947 1.2.2.2 skrll } 948 1.2.2.2 skrll 949 1.2.2.2 skrll static u_int32_t 950 1.2.2.2 skrll ipw_read_table1(struct ipw_softc *sc, u_int32_t off) 951 1.2.2.2 skrll { 952 1.2.2.2 skrll return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 953 1.2.2.2 skrll } 954 1.2.2.2 skrll 955 1.2.2.2 skrll static void 956 1.2.2.2 skrll ipw_write_table1(struct ipw_softc *sc, u_int32_t off, u_int32_t info) 957 1.2.2.2 skrll { 958 1.2.2.2 skrll MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 959 1.2.2.2 skrll } 960 1.2.2.2 skrll 961 1.2.2.2 skrll static int 962 1.2.2.2 skrll ipw_read_table2(struct ipw_softc *sc, u_int32_t off, void *buf, u_int32_t *len) 963 1.2.2.2 skrll { 964 1.2.2.2 skrll u_int32_t addr, info; 965 1.2.2.2 skrll u_int16_t count, size; 966 1.2.2.2 skrll u_int32_t total; 967 1.2.2.2 skrll 968 1.2.2.2 skrll /* addr[4] + count[2] + size[2] */ 969 1.2.2.2 skrll addr = MEM_READ_4(sc, sc->table2_base + off); 970 1.2.2.2 skrll info = MEM_READ_4(sc, sc->table2_base + off + 4); 971 1.2.2.2 skrll 972 1.2.2.2 skrll count = info >> 16; 973 1.2.2.2 skrll size = info & 0xffff; 974 1.2.2.2 skrll total = count * size; 975 1.2.2.2 skrll 976 1.2.2.2 skrll if (total > *len) { 977 1.2.2.2 skrll *len = total; 978 1.2.2.2 skrll return EINVAL; 979 1.2.2.2 skrll } 980 1.2.2.2 skrll 981 1.2.2.2 skrll *len = total; 982 1.2.2.2 skrll ipw_read_mem_1(sc, addr, buf, total); 983 1.2.2.2 skrll 984 1.2.2.2 skrll return 0; 985 1.2.2.2 skrll } 986 1.2.2.2 skrll 987 1.2.2.2 skrll static int 988 1.2.2.2 skrll ipw_tx_init(struct ipw_softc *sc) 989 1.2.2.2 skrll { 990 1.2.2.2 skrll char *errmsg; 991 1.2.2.2 skrll struct ipw_bd *bd; 992 1.2.2.2 skrll struct ipw_soft_bd *sbd; 993 1.2.2.2 skrll struct ipw_soft_hdr *shdr; 994 1.2.2.2 skrll struct ipw_soft_buf *sbuf; 995 1.2.2.2 skrll int error, i, nsegs; 996 1.2.2.2 skrll 997 1.2.2.2 skrll /* Allocate transmission buffer descriptors */ 998 1.2.2.2 skrll error = bus_dmamap_create(sc->sc_dmat, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, 999 1.2.2.2 skrll BUS_DMA_NOWAIT, &sc->tbd_map); 1000 1.2.2.2 skrll if (error != 0) { 1001 1.2.2.2 skrll errmsg = "could not create tbd dma map"; 1002 1.2.2.2 skrll goto fail; 1003 1.2.2.2 skrll } 1004 1.2.2.2 skrll 1005 1.2.2.2 skrll error = bus_dmamem_alloc(sc->sc_dmat, IPW_TBD_SZ, PAGE_SIZE, 0, 1006 1.2.2.2 skrll &sc->tbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 1007 1.2.2.2 skrll if (error != 0) { 1008 1.2.2.2 skrll errmsg = "could not allocate tbd dma memory"; 1009 1.2.2.2 skrll goto fail; 1010 1.2.2.2 skrll } 1011 1.2.2.2 skrll 1012 1.2.2.2 skrll error = bus_dmamem_map(sc->sc_dmat, &sc->tbd_seg, nsegs, IPW_TBD_SZ, 1013 1.2.2.2 skrll (caddr_t *)&sc->tbd_list, BUS_DMA_NOWAIT); 1014 1.2.2.2 skrll if (error != 0) { 1015 1.2.2.2 skrll errmsg = "could not map tbd dma memory"; 1016 1.2.2.2 skrll goto fail; 1017 1.2.2.2 skrll } 1018 1.2.2.2 skrll 1019 1.2.2.2 skrll error = bus_dmamap_load(sc->sc_dmat, sc->tbd_map, sc->tbd_list, 1020 1.2.2.2 skrll IPW_TBD_SZ, NULL, BUS_DMA_NOWAIT); 1021 1.2.2.2 skrll if (error != 0) { 1022 1.2.2.2 skrll errmsg = "could not load tbd dma memory"; 1023 1.2.2.2 skrll goto fail; 1024 1.2.2.2 skrll } 1025 1.2.2.2 skrll 1026 1.2.2.2 skrll sc->stbd_list = malloc(IPW_NTBD * sizeof (struct ipw_soft_bd), 1027 1.2.2.2 skrll M_DEVBUF, M_NOWAIT); 1028 1.2.2.2 skrll if (sc->stbd_list == NULL) { 1029 1.2.2.2 skrll errmsg = "could not allocate soft tbd"; 1030 1.2.2.2 skrll error = ENOMEM; 1031 1.2.2.2 skrll goto fail; 1032 1.2.2.2 skrll } 1033 1.2.2.2 skrll sbd = sc->stbd_list; 1034 1.2.2.2 skrll bd = sc->tbd_list; 1035 1.2.2.2 skrll for (i = 0; i < IPW_NTBD; i++, sbd++, bd++) { 1036 1.2.2.2 skrll sbd->type = IPW_SBD_TYPE_NOASSOC; 1037 1.2.2.2 skrll sbd->bd = bd; 1038 1.2.2.2 skrll } 1039 1.2.2.2 skrll 1040 1.2.2.2 skrll CSR_WRITE_4(sc, IPW_CSR_TX_BD_BASE, sc->tbd_map->dm_segs[0].ds_addr); 1041 1.2.2.2 skrll CSR_WRITE_4(sc, IPW_CSR_TX_BD_SIZE, IPW_NTBD); 1042 1.2.2.2 skrll CSR_WRITE_4(sc, IPW_CSR_TX_READ_INDEX, 0); 1043 1.2.2.2 skrll CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, 0); 1044 1.2.2.2 skrll sc->txold = IPW_NTBD - 1; /* latest bd index ack'ed by firmware */ 1045 1.2.2.2 skrll sc->txcur = 0; /* bd index to write to */ 1046 1.2.2.2 skrll 1047 1.2.2.2 skrll /* Allocate a DMA-able command */ 1048 1.2.2.2 skrll error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_cmd), 1, 1049 1.2.2.2 skrll sizeof (struct ipw_cmd), 0, BUS_DMA_NOWAIT, &sc->cmd_map); 1050 1.2.2.2 skrll if (error != 0) { 1051 1.2.2.2 skrll errmsg = "could not create cmd dma map"; 1052 1.2.2.2 skrll goto fail; 1053 1.2.2.2 skrll } 1054 1.2.2.2 skrll 1055 1.2.2.2 skrll error = bus_dmamem_alloc(sc->sc_dmat, sizeof (struct ipw_cmd), 1056 1.2.2.2 skrll PAGE_SIZE, 0, &sc->cmd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 1057 1.2.2.2 skrll if (error != 0) { 1058 1.2.2.2 skrll errmsg = "could not allocate cmd dma memory"; 1059 1.2.2.2 skrll goto fail; 1060 1.2.2.2 skrll } 1061 1.2.2.2 skrll 1062 1.2.2.2 skrll error = bus_dmamem_map(sc->sc_dmat, &sc->cmd_seg, nsegs, 1063 1.2.2.2 skrll sizeof (struct ipw_cmd), (caddr_t *)&sc->cmd, BUS_DMA_NOWAIT); 1064 1.2.2.2 skrll if (error != 0) { 1065 1.2.2.2 skrll errmsg = "could not map cmd dma memory"; 1066 1.2.2.2 skrll goto fail; 1067 1.2.2.2 skrll } 1068 1.2.2.2 skrll 1069 1.2.2.2 skrll /* Allocate a pool of DMA-able headers */ 1070 1.2.2.2 skrll sc->shdr_list = malloc(IPW_NDATA * sizeof (struct ipw_soft_hdr), 1071 1.2.2.2 skrll M_DEVBUF, M_NOWAIT); 1072 1.2.2.2 skrll if (sc->shdr_list == NULL) { 1073 1.2.2.2 skrll errmsg = "could not allocate soft hdr"; 1074 1.2.2.2 skrll error = ENOMEM; 1075 1.2.2.2 skrll goto fail; 1076 1.2.2.2 skrll } 1077 1.2.2.2 skrll TAILQ_INIT(&sc->sc_free_shdr); 1078 1.2.2.2 skrll for (i = 0, shdr = sc->shdr_list; i < IPW_NDATA; i++, shdr++) { 1079 1.2.2.2 skrll error = bus_dmamap_create(sc->sc_dmat, 1080 1.2.2.2 skrll sizeof (struct ipw_soft_hdr), 1, 1081 1.2.2.2 skrll sizeof (struct ipw_soft_hdr), 0, BUS_DMA_NOWAIT, 1082 1.2.2.2 skrll &shdr->map); 1083 1.2.2.2 skrll if (error != 0) { 1084 1.2.2.2 skrll errmsg = "could not create hdr dma map"; 1085 1.2.2.2 skrll goto fail; 1086 1.2.2.2 skrll } 1087 1.2.2.2 skrll TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 1088 1.2.2.2 skrll } 1089 1.2.2.2 skrll 1090 1.2.2.2 skrll /* Allocate a pool of DMA-able buffers */ 1091 1.2.2.2 skrll sc->tx_sbuf_list = malloc(IPW_NDATA * sizeof (struct ipw_soft_buf), 1092 1.2.2.2 skrll M_DEVBUF, M_NOWAIT); 1093 1.2.2.2 skrll if (sc->tx_sbuf_list == NULL) { 1094 1.2.2.2 skrll errmsg = "could not allocate soft txbuf"; 1095 1.2.2.2 skrll error = ENOMEM; 1096 1.2.2.2 skrll goto fail; 1097 1.2.2.2 skrll } 1098 1.2.2.2 skrll TAILQ_INIT(&sc->sc_free_sbuf); 1099 1.2.2.2 skrll for (i = 0, sbuf = sc->tx_sbuf_list; i < IPW_NDATA; i++, sbuf++) { 1100 1.2.2.2 skrll error = bus_dmamap_create(sc->sc_dmat, IPW_NDATA * MCLBYTES, 1101 1.2.2.2 skrll IPW_NDATA, MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 1102 1.2.2.2 skrll if (error != 0) { 1103 1.2.2.2 skrll errmsg = "could not create txbuf dma map"; 1104 1.2.2.2 skrll goto fail; 1105 1.2.2.2 skrll } 1106 1.2.2.2 skrll TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 1107 1.2.2.2 skrll } 1108 1.2.2.2 skrll 1109 1.2.2.2 skrll return 0; 1110 1.2.2.2 skrll 1111 1.2.2.2 skrll fail: aprint_error("%s: %s\n", sc->sc_dev.dv_xname, errmsg); 1112 1.2.2.2 skrll ipw_tx_stop(sc); 1113 1.2.2.2 skrll 1114 1.2.2.2 skrll return error; 1115 1.2.2.2 skrll } 1116 1.2.2.2 skrll 1117 1.2.2.2 skrll static void 1118 1.2.2.2 skrll ipw_tx_stop(struct ipw_softc *sc) 1119 1.2.2.2 skrll { 1120 1.2.2.2 skrll struct ipw_soft_hdr *shdr; 1121 1.2.2.2 skrll struct ipw_soft_buf *sbuf; 1122 1.2.2.2 skrll int i; 1123 1.2.2.2 skrll 1124 1.2.2.2 skrll if (sc->tbd_map != NULL) { 1125 1.2.2.2 skrll if (sc->tbd_list != NULL) { 1126 1.2.2.2 skrll bus_dmamap_unload(sc->sc_dmat, sc->tbd_map); 1127 1.2.2.2 skrll bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->tbd_list, 1128 1.2.2.2 skrll IPW_TBD_SZ); 1129 1.2.2.2 skrll bus_dmamem_free(sc->sc_dmat, &sc->tbd_seg, 1); 1130 1.2.2.2 skrll sc->tbd_list = NULL; 1131 1.2.2.2 skrll } 1132 1.2.2.2 skrll bus_dmamap_destroy(sc->sc_dmat, sc->tbd_map); 1133 1.2.2.2 skrll sc->tbd_map = NULL; 1134 1.2.2.2 skrll } 1135 1.2.2.2 skrll 1136 1.2.2.2 skrll if (sc->stbd_list != NULL) { 1137 1.2.2.2 skrll for (i = 0; i < IPW_NTBD; i++) 1138 1.2.2.2 skrll ipw_release_sbd(sc, &sc->stbd_list[i]); 1139 1.2.2.2 skrll free(sc->stbd_list, M_DEVBUF); 1140 1.2.2.2 skrll sc->stbd_list = NULL; 1141 1.2.2.2 skrll } 1142 1.2.2.2 skrll 1143 1.2.2.2 skrll if (sc->cmd_map != NULL) { 1144 1.2.2.2 skrll if (sc->cmd != NULL) { 1145 1.2.2.2 skrll bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->cmd, 1146 1.2.2.2 skrll sizeof (struct ipw_cmd)); 1147 1.2.2.2 skrll bus_dmamem_free(sc->sc_dmat, &sc->cmd_seg, 1); 1148 1.2.2.2 skrll sc->cmd = NULL; 1149 1.2.2.2 skrll } 1150 1.2.2.2 skrll bus_dmamap_destroy(sc->sc_dmat, sc->cmd_map); 1151 1.2.2.2 skrll sc->cmd_map = NULL; 1152 1.2.2.2 skrll } 1153 1.2.2.2 skrll 1154 1.2.2.2 skrll if (sc->shdr_list != NULL) { 1155 1.2.2.2 skrll TAILQ_FOREACH(shdr, &sc->sc_free_shdr, next) 1156 1.2.2.2 skrll bus_dmamap_destroy(sc->sc_dmat, shdr->map); 1157 1.2.2.2 skrll free(sc->shdr_list, M_DEVBUF); 1158 1.2.2.2 skrll sc->shdr_list = NULL; 1159 1.2.2.2 skrll } 1160 1.2.2.2 skrll 1161 1.2.2.2 skrll 1162 1.2.2.2 skrll if (sc->tx_sbuf_list != NULL) { 1163 1.2.2.2 skrll TAILQ_FOREACH(sbuf, &sc->sc_free_sbuf, next) 1164 1.2.2.2 skrll bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 1165 1.2.2.2 skrll free(sc->tx_sbuf_list, M_DEVBUF); 1166 1.2.2.2 skrll sc->tx_sbuf_list = NULL; 1167 1.2.2.2 skrll } 1168 1.2.2.2 skrll } 1169 1.2.2.2 skrll 1170 1.2.2.2 skrll static int 1171 1.2.2.2 skrll ipw_rx_init(struct ipw_softc *sc) 1172 1.2.2.2 skrll { 1173 1.2.2.2 skrll char *errmsg; 1174 1.2.2.2 skrll struct ipw_bd *bd; 1175 1.2.2.2 skrll struct ipw_soft_bd *sbd; 1176 1.2.2.2 skrll struct ipw_soft_buf *sbuf; 1177 1.2.2.2 skrll int error, i, nsegs; 1178 1.2.2.2 skrll 1179 1.2.2.2 skrll /* Allocate reception buffer descriptors */ 1180 1.2.2.2 skrll error = bus_dmamap_create(sc->sc_dmat, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, 1181 1.2.2.2 skrll BUS_DMA_NOWAIT, &sc->rbd_map); 1182 1.2.2.2 skrll if (error != 0) { 1183 1.2.2.2 skrll errmsg = "could not create rbd dma map"; 1184 1.2.2.2 skrll goto fail; 1185 1.2.2.2 skrll } 1186 1.2.2.2 skrll 1187 1.2.2.2 skrll error = bus_dmamem_alloc(sc->sc_dmat, IPW_RBD_SZ, PAGE_SIZE, 0, 1188 1.2.2.2 skrll &sc->rbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 1189 1.2.2.2 skrll if (error != 0) { 1190 1.2.2.2 skrll errmsg = "could not allocate rbd dma memory"; 1191 1.2.2.2 skrll goto fail; 1192 1.2.2.2 skrll } 1193 1.2.2.2 skrll 1194 1.2.2.2 skrll error = bus_dmamem_map(sc->sc_dmat, &sc->rbd_seg, nsegs, IPW_RBD_SZ, 1195 1.2.2.2 skrll (caddr_t *)&sc->rbd_list, BUS_DMA_NOWAIT); 1196 1.2.2.2 skrll if (error != 0) { 1197 1.2.2.2 skrll errmsg = "could not map rbd dma memory"; 1198 1.2.2.2 skrll goto fail; 1199 1.2.2.2 skrll } 1200 1.2.2.2 skrll 1201 1.2.2.2 skrll error = bus_dmamap_load(sc->sc_dmat, sc->rbd_map, sc->rbd_list, 1202 1.2.2.2 skrll IPW_RBD_SZ, NULL, BUS_DMA_NOWAIT); 1203 1.2.2.2 skrll if (error != 0) { 1204 1.2.2.2 skrll errmsg = "could not load rbd dma memory"; 1205 1.2.2.2 skrll goto fail; 1206 1.2.2.2 skrll } 1207 1.2.2.2 skrll 1208 1.2.2.2 skrll sc->srbd_list = malloc(IPW_NRBD * sizeof (struct ipw_soft_bd), 1209 1.2.2.2 skrll M_DEVBUF, M_NOWAIT); 1210 1.2.2.2 skrll if (sc->srbd_list == NULL) { 1211 1.2.2.2 skrll errmsg = "could not allocate soft rbd"; 1212 1.2.2.2 skrll error = ENOMEM; 1213 1.2.2.2 skrll goto fail; 1214 1.2.2.2 skrll } 1215 1.2.2.2 skrll sbd = sc->srbd_list; 1216 1.2.2.2 skrll bd = sc->rbd_list; 1217 1.2.2.2 skrll for (i = 0; i < IPW_NRBD; i++, sbd++, bd++) { 1218 1.2.2.2 skrll sbd->type = IPW_SBD_TYPE_NOASSOC; 1219 1.2.2.2 skrll sbd->bd = bd; 1220 1.2.2.2 skrll } 1221 1.2.2.2 skrll 1222 1.2.2.2 skrll CSR_WRITE_4(sc, IPW_CSR_RX_BD_BASE, sc->rbd_map->dm_segs[0].ds_addr); 1223 1.2.2.2 skrll CSR_WRITE_4(sc, IPW_CSR_RX_BD_SIZE, IPW_NRBD); 1224 1.2.2.2 skrll CSR_WRITE_4(sc, IPW_CSR_RX_READ_INDEX, 0); 1225 1.2.2.2 skrll CSR_WRITE_4(sc, IPW_CSR_RX_WRITE_INDEX, IPW_NRBD - 1); 1226 1.2.2.2 skrll sc->rxcur = IPW_NRBD - 1; /* latest bd index I've read */ 1227 1.2.2.2 skrll 1228 1.2.2.2 skrll /* Allocate status descriptors */ 1229 1.2.2.2 skrll error = bus_dmamap_create(sc->sc_dmat, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 1230 1.2.2.2 skrll 0, BUS_DMA_NOWAIT, &sc->status_map); 1231 1.2.2.2 skrll if (error != 0) { 1232 1.2.2.2 skrll errmsg = "could not create status dma map"; 1233 1.2.2.2 skrll goto fail; 1234 1.2.2.2 skrll } 1235 1.2.2.2 skrll 1236 1.2.2.2 skrll error = bus_dmamem_alloc(sc->sc_dmat, IPW_STATUS_SZ, PAGE_SIZE, 0, 1237 1.2.2.2 skrll &sc->status_seg, 1, &nsegs, BUS_DMA_NOWAIT); 1238 1.2.2.2 skrll if (error != 0) { 1239 1.2.2.2 skrll errmsg = "could not allocate status dma memory"; 1240 1.2.2.2 skrll goto fail; 1241 1.2.2.2 skrll } 1242 1.2.2.2 skrll 1243 1.2.2.2 skrll error = bus_dmamem_map(sc->sc_dmat, &sc->status_seg, nsegs, 1244 1.2.2.2 skrll IPW_STATUS_SZ, (caddr_t *)&sc->status_list, BUS_DMA_NOWAIT); 1245 1.2.2.2 skrll if (error != 0) { 1246 1.2.2.2 skrll errmsg = "could not map status dma memory"; 1247 1.2.2.2 skrll goto fail; 1248 1.2.2.2 skrll } 1249 1.2.2.2 skrll 1250 1.2.2.2 skrll error = bus_dmamap_load(sc->sc_dmat, sc->status_map, sc->status_list, 1251 1.2.2.2 skrll IPW_STATUS_SZ, NULL, BUS_DMA_NOWAIT); 1252 1.2.2.2 skrll if (error != 0) { 1253 1.2.2.2 skrll errmsg = "could not load status dma memory"; 1254 1.2.2.2 skrll goto fail; 1255 1.2.2.2 skrll } 1256 1.2.2.2 skrll 1257 1.2.2.2 skrll CSR_WRITE_4(sc, IPW_CSR_RX_STATUS_BASE, 1258 1.2.2.2 skrll sc->status_map->dm_segs[0].ds_addr); 1259 1.2.2.2 skrll 1260 1.2.2.2 skrll sc->rx_sbuf_list = malloc(IPW_NRBD * sizeof (struct ipw_soft_buf), 1261 1.2.2.2 skrll M_DEVBUF, M_NOWAIT); 1262 1.2.2.2 skrll if (sc->rx_sbuf_list == NULL) { 1263 1.2.2.2 skrll errmsg = "could not allocate soft rxbuf"; 1264 1.2.2.2 skrll error = ENOMEM; 1265 1.2.2.2 skrll goto fail; 1266 1.2.2.2 skrll } 1267 1.2.2.2 skrll 1268 1.2.2.2 skrll sbuf = sc->rx_sbuf_list; 1269 1.2.2.2 skrll sbd = sc->srbd_list; 1270 1.2.2.2 skrll for (i = 0; i < IPW_NRBD; i++, sbuf++, sbd++) { 1271 1.2.2.2 skrll 1272 1.2.2.2 skrll MGETHDR(sbuf->m, M_DONTWAIT, MT_DATA); 1273 1.2.2.2 skrll if (sbuf->m == NULL) { 1274 1.2.2.2 skrll errmsg = "could not allocate rx mbuf"; 1275 1.2.2.2 skrll error = ENOMEM; 1276 1.2.2.2 skrll goto fail; 1277 1.2.2.2 skrll } 1278 1.2.2.2 skrll MCLGET(sbuf->m, M_DONTWAIT); 1279 1.2.2.2 skrll if (!(sbuf->m->m_flags & M_EXT)) { 1280 1.2.2.2 skrll m_freem(sbuf->m); 1281 1.2.2.2 skrll errmsg = "could not allocate rx mbuf cluster"; 1282 1.2.2.2 skrll error = ENOMEM; 1283 1.2.2.2 skrll goto fail; 1284 1.2.2.2 skrll } 1285 1.2.2.2 skrll 1286 1.2.2.2 skrll error = bus_dmamap_create(sc->sc_dmat, IPW_NRBD * MCLBYTES, 1287 1.2.2.2 skrll IPW_NRBD, MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 1288 1.2.2.2 skrll if (error != 0) { 1289 1.2.2.2 skrll m_freem(sbuf->m); 1290 1.2.2.2 skrll errmsg = "could not create rxbuf dma map"; 1291 1.2.2.2 skrll goto fail; 1292 1.2.2.2 skrll } 1293 1.2.2.2 skrll error = bus_dmamap_load(sc->sc_dmat, sbuf->map, 1294 1.2.2.2 skrll mtod(sbuf->m, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 1295 1.2.2.2 skrll if (error != 0) { 1296 1.2.2.2 skrll bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 1297 1.2.2.2 skrll m_freem(sbuf->m); 1298 1.2.2.2 skrll errmsg = "could not map rxbuf dma memory"; 1299 1.2.2.2 skrll goto fail; 1300 1.2.2.2 skrll } 1301 1.2.2.2 skrll sbd->type = IPW_SBD_TYPE_DATA; 1302 1.2.2.2 skrll sbd->priv = sbuf; 1303 1.2.2.2 skrll sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 1304 1.2.2.2 skrll sbd->bd->len = htole32(MCLBYTES); 1305 1.2.2.2 skrll } 1306 1.2.2.2 skrll 1307 1.2.2.2 skrll return 0; 1308 1.2.2.2 skrll 1309 1.2.2.2 skrll fail: aprint_error("%s: %s\n", sc->sc_dev.dv_xname, errmsg); 1310 1.2.2.2 skrll ipw_rx_stop(sc); 1311 1.2.2.2 skrll 1312 1.2.2.2 skrll return error; 1313 1.2.2.2 skrll } 1314 1.2.2.2 skrll 1315 1.2.2.2 skrll static void 1316 1.2.2.2 skrll ipw_rx_stop(struct ipw_softc *sc) 1317 1.2.2.2 skrll { 1318 1.2.2.2 skrll struct ipw_soft_bd *sbd; 1319 1.2.2.2 skrll struct ipw_soft_buf *sbuf; 1320 1.2.2.2 skrll int i; 1321 1.2.2.2 skrll 1322 1.2.2.2 skrll if (sc->rbd_map != NULL) { 1323 1.2.2.2 skrll if (sc->rbd_list != NULL) { 1324 1.2.2.2 skrll bus_dmamap_unload(sc->sc_dmat, sc->rbd_map); 1325 1.2.2.2 skrll bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->rbd_list, 1326 1.2.2.2 skrll IPW_RBD_SZ); 1327 1.2.2.2 skrll bus_dmamem_free(sc->sc_dmat, &sc->rbd_seg, 1); 1328 1.2.2.2 skrll sc->rbd_list = NULL; 1329 1.2.2.2 skrll } 1330 1.2.2.2 skrll bus_dmamap_destroy(sc->sc_dmat, sc->rbd_map); 1331 1.2.2.2 skrll sc->rbd_map = NULL; 1332 1.2.2.2 skrll } 1333 1.2.2.2 skrll 1334 1.2.2.2 skrll if (sc->status_map != NULL) { 1335 1.2.2.2 skrll if (sc->status_list != NULL) { 1336 1.2.2.2 skrll bus_dmamap_unload(sc->sc_dmat, sc->status_map); 1337 1.2.2.2 skrll bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->status_list, 1338 1.2.2.2 skrll IPW_STATUS_SZ); 1339 1.2.2.2 skrll bus_dmamem_free(sc->sc_dmat, &sc->status_seg, 1); 1340 1.2.2.2 skrll sc->status_list = NULL; 1341 1.2.2.2 skrll } 1342 1.2.2.2 skrll bus_dmamap_destroy(sc->sc_dmat, sc->status_map); 1343 1.2.2.2 skrll sc->status_map = NULL; 1344 1.2.2.2 skrll } 1345 1.2.2.2 skrll 1346 1.2.2.2 skrll if (sc->srbd_list != NULL) { 1347 1.2.2.2 skrll for (i = 0, sbd = sc->srbd_list; i < IPW_NRBD; i++, sbd++) { 1348 1.2.2.2 skrll if (sbd->type == IPW_SBD_TYPE_NOASSOC) 1349 1.2.2.2 skrll continue; 1350 1.2.2.2 skrll 1351 1.2.2.2 skrll sbuf = sbd->priv; 1352 1.2.2.2 skrll bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1353 1.2.2.2 skrll bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 1354 1.2.2.2 skrll m_freem(sbuf->m); 1355 1.2.2.2 skrll } 1356 1.2.2.2 skrll free(sc->srbd_list, M_DEVBUF); 1357 1.2.2.2 skrll sc->srbd_list = NULL; 1358 1.2.2.2 skrll } 1359 1.2.2.2 skrll 1360 1.2.2.2 skrll if (sc->rx_sbuf_list != NULL) { 1361 1.2.2.2 skrll free(sc->rx_sbuf_list, M_DEVBUF); 1362 1.2.2.2 skrll sc->rx_sbuf_list = NULL; 1363 1.2.2.2 skrll } 1364 1.2.2.2 skrll } 1365 1.2.2.2 skrll 1366 1.2.2.2 skrll static void 1367 1.2.2.2 skrll ipw_reset(struct ipw_softc *sc) 1368 1.2.2.2 skrll { 1369 1.2.2.2 skrll struct ifnet *ifp = &sc->sc_ic.ic_if; 1370 1.2.2.2 skrll int ntries; 1371 1.2.2.2 skrll 1372 1.2.2.2 skrll ipw_stop(ifp, 1); 1373 1.2.2.2 skrll 1374 1.2.2.2 skrll if (sc->flags & IPW_FLAG_FW_INITED) { 1375 1.2.2.2 skrll ipw_cmd(sc, IPW_CMD_DISABLE_PHY, NULL, 0); 1376 1.2.2.2 skrll ipw_cmd(sc, IPW_CMD_PREPARE_POWER_DOWN, NULL, 0); 1377 1.2.2.2 skrll 1378 1.2.2.2 skrll sc->flags &= ~IPW_FLAG_FW_INITED; 1379 1.2.2.2 skrll } 1380 1.2.2.2 skrll 1381 1.2.2.2 skrll /* Disable interrupts */ 1382 1.2.2.2 skrll CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1383 1.2.2.2 skrll 1384 1.2.2.2 skrll CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1385 1.2.2.2 skrll for (ntries = 0; ntries < 5; ntries++) { 1386 1.2.2.2 skrll if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1387 1.2.2.2 skrll break; 1388 1.2.2.2 skrll DELAY(10); 1389 1.2.2.2 skrll } 1390 1.2.2.2 skrll 1391 1.2.2.2 skrll CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 1392 1.2.2.2 skrll 1393 1.2.2.2 skrll ipw_rx_stop(sc); 1394 1.2.2.2 skrll ipw_tx_stop(sc); 1395 1.2.2.2 skrll 1396 1.2.2.2 skrll ifp->if_flags &= ~IFF_UP; 1397 1.2.2.2 skrll } 1398 1.2.2.2 skrll 1399 1.2.2.2 skrll static int 1400 1.2.2.2 skrll ipw_clock_sync(struct ipw_softc *sc) 1401 1.2.2.2 skrll { 1402 1.2.2.2 skrll int ntries; 1403 1.2.2.2 skrll u_int32_t r; 1404 1.2.2.2 skrll 1405 1.2.2.2 skrll CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 1406 1.2.2.2 skrll for (ntries = 0; ntries < 1000; ntries++) { 1407 1.2.2.2 skrll if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_PRINCETON_RESET) 1408 1.2.2.2 skrll break; 1409 1.2.2.2 skrll DELAY(10); 1410 1.2.2.2 skrll } 1411 1.2.2.2 skrll if (ntries == 1000) 1412 1.2.2.2 skrll return EIO; 1413 1.2.2.2 skrll 1414 1.2.2.2 skrll CSR_WRITE_4(sc, IPW_CSR_CTL, IPW_CTL_INIT_DONE); 1415 1.2.2.2 skrll for (ntries = 0; ntries < 1000; ntries++) { 1416 1.2.2.2 skrll if ((r = CSR_READ_4(sc, IPW_CSR_CTL)) & IPW_CTL_CLOCK_READY) 1417 1.2.2.2 skrll break; 1418 1.2.2.2 skrll DELAY(200); 1419 1.2.2.2 skrll } 1420 1.2.2.2 skrll if (ntries == 1000) 1421 1.2.2.2 skrll return EIO; 1422 1.2.2.2 skrll 1423 1.2.2.2 skrll CSR_WRITE_4(sc, IPW_CSR_CTL, r | IPW_CTL_ALLOW_STANDBY); 1424 1.2.2.2 skrll 1425 1.2.2.2 skrll return 0; 1426 1.2.2.2 skrll } 1427 1.2.2.2 skrll 1428 1.2.2.2 skrll static int 1429 1.2.2.2 skrll ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size) 1430 1.2.2.2 skrll { 1431 1.2.2.2 skrll int ntries; 1432 1.2.2.2 skrll 1433 1.2.2.2 skrll MEM_WRITE_2(sc, 0x220000, 0x0703); 1434 1.2.2.2 skrll MEM_WRITE_2(sc, 0x220000, 0x0707); 1435 1.2.2.2 skrll 1436 1.2.2.2 skrll MEM_WRITE_1(sc, 0x210014, 0x72); 1437 1.2.2.2 skrll MEM_WRITE_1(sc, 0x210014, 0x72); 1438 1.2.2.2 skrll 1439 1.2.2.2 skrll MEM_WRITE_1(sc, 0x210000, 0x40); 1440 1.2.2.2 skrll MEM_WRITE_1(sc, 0x210000, 0x00); 1441 1.2.2.2 skrll MEM_WRITE_1(sc, 0x210000, 0x40); 1442 1.2.2.2 skrll 1443 1.2.2.2 skrll MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1444 1.2.2.2 skrll 1445 1.2.2.2 skrll MEM_WRITE_1(sc, 0x210000, 0x00); 1446 1.2.2.2 skrll MEM_WRITE_1(sc, 0x210000, 0x00); 1447 1.2.2.2 skrll MEM_WRITE_1(sc, 0x210000, 0x80); 1448 1.2.2.2 skrll 1449 1.2.2.2 skrll MEM_WRITE_2(sc, 0x220000, 0x0703); 1450 1.2.2.2 skrll MEM_WRITE_2(sc, 0x220000, 0x0707); 1451 1.2.2.2 skrll 1452 1.2.2.2 skrll MEM_WRITE_1(sc, 0x210014, 0x72); 1453 1.2.2.2 skrll MEM_WRITE_1(sc, 0x210014, 0x72); 1454 1.2.2.2 skrll 1455 1.2.2.2 skrll MEM_WRITE_1(sc, 0x210000, 0x00); 1456 1.2.2.2 skrll MEM_WRITE_1(sc, 0x210000, 0x80); 1457 1.2.2.2 skrll 1458 1.2.2.2 skrll for (ntries = 0; ntries < 10; ntries++) { 1459 1.2.2.2 skrll if (MEM_READ_1(sc, 0x210000) & 1) 1460 1.2.2.2 skrll break; 1461 1.2.2.2 skrll DELAY(10); 1462 1.2.2.2 skrll } 1463 1.2.2.2 skrll if (ntries == 10) 1464 1.2.2.2 skrll return EIO; 1465 1.2.2.2 skrll 1466 1.2.2.2 skrll return 0; 1467 1.2.2.2 skrll } 1468 1.2.2.2 skrll 1469 1.2.2.2 skrll /* set of macros to handle unaligned little endian data in firmware image */ 1470 1.2.2.2 skrll #define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1471 1.2.2.2 skrll #define GETLE16(p) ((p)[0] | (p)[1] << 8) 1472 1.2.2.2 skrll static int 1473 1.2.2.2 skrll ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size) 1474 1.2.2.2 skrll { 1475 1.2.2.2 skrll u_char *p, *end; 1476 1.2.2.2 skrll u_int32_t addr; 1477 1.2.2.2 skrll u_int16_t len; 1478 1.2.2.2 skrll 1479 1.2.2.2 skrll p = fw; 1480 1.2.2.2 skrll end = fw + size; 1481 1.2.2.2 skrll while (p < end) { 1482 1.2.2.2 skrll if (p + 6 > end) 1483 1.2.2.2 skrll return EINVAL; 1484 1.2.2.2 skrll 1485 1.2.2.2 skrll addr = GETLE32(p); 1486 1.2.2.2 skrll p += 4; 1487 1.2.2.2 skrll len = GETLE16(p); 1488 1.2.2.2 skrll p += 2; 1489 1.2.2.2 skrll 1490 1.2.2.2 skrll if (p + len > end) 1491 1.2.2.2 skrll return EINVAL; 1492 1.2.2.2 skrll 1493 1.2.2.2 skrll ipw_write_mem_1(sc, addr, p, len); 1494 1.2.2.2 skrll p += len; 1495 1.2.2.2 skrll } 1496 1.2.2.2 skrll return 0; 1497 1.2.2.2 skrll } 1498 1.2.2.2 skrll 1499 1.2.2.2 skrll static int 1500 1.2.2.2 skrll ipw_firmware_init(struct ipw_softc *sc, u_char *data) 1501 1.2.2.2 skrll { 1502 1.2.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 1503 1.2.2.2 skrll struct ifnet *ifp = &ic->ic_if; 1504 1.2.2.2 skrll struct ipw_fw_hdr hdr; 1505 1.2.2.2 skrll u_int32_t r, len, fw_size, uc_size; 1506 1.2.2.2 skrll u_char *fw, *uc; 1507 1.2.2.2 skrll int error; 1508 1.2.2.2 skrll 1509 1.2.2.2 skrll ipw_reset(sc); 1510 1.2.2.2 skrll 1511 1.2.2.2 skrll if ((error = copyin(data, &hdr, sizeof hdr)) != 0) 1512 1.2.2.2 skrll goto fail1; 1513 1.2.2.2 skrll 1514 1.2.2.2 skrll fw_size = le32toh(hdr.fw_size); 1515 1.2.2.2 skrll uc_size = le32toh(hdr.uc_size); 1516 1.2.2.2 skrll data += sizeof hdr; 1517 1.2.2.2 skrll 1518 1.2.2.2 skrll if ((fw = malloc(fw_size, M_DEVBUF, M_NOWAIT)) == NULL) { 1519 1.2.2.2 skrll error = ENOMEM; 1520 1.2.2.2 skrll goto fail1; 1521 1.2.2.2 skrll } 1522 1.2.2.2 skrll 1523 1.2.2.2 skrll if ((error = copyin(data, fw, fw_size)) != 0) 1524 1.2.2.2 skrll goto fail2; 1525 1.2.2.2 skrll 1526 1.2.2.2 skrll data += fw_size; 1527 1.2.2.2 skrll 1528 1.2.2.2 skrll if ((uc = malloc(uc_size, M_DEVBUF, M_NOWAIT)) == NULL) { 1529 1.2.2.2 skrll error = ENOMEM; 1530 1.2.2.2 skrll goto fail2; 1531 1.2.2.2 skrll } 1532 1.2.2.2 skrll 1533 1.2.2.2 skrll if ((error = copyin(data, uc, uc_size)) != 0) 1534 1.2.2.2 skrll goto fail3; 1535 1.2.2.2 skrll 1536 1.2.2.2 skrll if ((error = ipw_clock_sync(sc)) != 0) { 1537 1.2.2.2 skrll aprint_error("%s: clock synchronization failed\n", 1538 1.2.2.2 skrll sc->sc_dev.dv_xname); 1539 1.2.2.2 skrll goto fail3; 1540 1.2.2.2 skrll } 1541 1.2.2.2 skrll 1542 1.2.2.2 skrll MEM_WRITE_4(sc, 0x003000e0, 0x80000000); 1543 1.2.2.2 skrll 1544 1.2.2.2 skrll CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1545 1.2.2.2 skrll 1546 1.2.2.2 skrll if ((error = ipw_load_ucode(sc, uc, uc_size)) != 0) { 1547 1.2.2.2 skrll aprint_error("%s: could not load microcode\n", 1548 1.2.2.2 skrll sc->sc_dev.dv_xname); 1549 1.2.2.2 skrll goto fail3; 1550 1.2.2.2 skrll } 1551 1.2.2.2 skrll 1552 1.2.2.2 skrll MEM_WRITE_4(sc, 0x003000e0, 0); 1553 1.2.2.2 skrll 1554 1.2.2.2 skrll if ((error = ipw_clock_sync(sc)) != 0) { 1555 1.2.2.2 skrll aprint_error("%s: clock synchronization failed\n", 1556 1.2.2.2 skrll sc->sc_dev.dv_xname); 1557 1.2.2.2 skrll goto fail3; 1558 1.2.2.2 skrll } 1559 1.2.2.2 skrll 1560 1.2.2.2 skrll if ((error = ipw_load_firmware(sc, fw, fw_size))) { 1561 1.2.2.2 skrll aprint_error("%s: could not load firmware\n", 1562 1.2.2.2 skrll sc->sc_dev.dv_xname); 1563 1.2.2.2 skrll goto fail3; 1564 1.2.2.2 skrll } 1565 1.2.2.2 skrll 1566 1.2.2.2 skrll ipw_zero_mem_4(sc, 0x0002f200, 196); 1567 1.2.2.2 skrll ipw_zero_mem_4(sc, 0x0002f610, 8); 1568 1.2.2.2 skrll ipw_zero_mem_4(sc, 0x0002fa00, 8); 1569 1.2.2.2 skrll ipw_zero_mem_4(sc, 0x0002fc00, 4); 1570 1.2.2.2 skrll ipw_zero_mem_4(sc, 0x0002ff80, 32); 1571 1.2.2.2 skrll 1572 1.2.2.2 skrll if ((error = ipw_rx_init(sc)) != 0) { 1573 1.2.2.2 skrll aprint_error("%s: could not initialize rx queue\n", 1574 1.2.2.2 skrll sc->sc_dev.dv_xname); 1575 1.2.2.2 skrll goto fail3; 1576 1.2.2.2 skrll } 1577 1.2.2.2 skrll 1578 1.2.2.2 skrll if ((error = ipw_tx_init(sc)) != 0) { 1579 1.2.2.2 skrll aprint_error("%s: could not initialize tx queue\n", 1580 1.2.2.2 skrll sc->sc_dev.dv_xname); 1581 1.2.2.2 skrll goto fail3; 1582 1.2.2.2 skrll } 1583 1.2.2.2 skrll 1584 1.2.2.2 skrll CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1585 1.2.2.2 skrll IPW_IO_LED_OFF); 1586 1.2.2.2 skrll 1587 1.2.2.2 skrll /* Enable interrupts */ 1588 1.2.2.2 skrll CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1589 1.2.2.2 skrll 1590 1.2.2.2 skrll /* Let's go! */ 1591 1.2.2.2 skrll CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1592 1.2.2.2 skrll 1593 1.2.2.2 skrll /* Wait at most 5 seconds for firmware initialization to complete */ 1594 1.2.2.2 skrll if ((error = tsleep(sc, 0, "ipwinit", 5 * hz)) != 0) { 1595 1.2.2.2 skrll aprint_error("%s: timeout waiting for firmware initialization " 1596 1.2.2.2 skrll "to complete\n", sc->sc_dev.dv_xname); 1597 1.2.2.2 skrll goto fail3; 1598 1.2.2.2 skrll } 1599 1.2.2.2 skrll 1600 1.2.2.2 skrll /* Firmware initialization completed */ 1601 1.2.2.2 skrll sc->flags |= IPW_FLAG_FW_INITED; 1602 1.2.2.2 skrll 1603 1.2.2.2 skrll free(uc, M_DEVBUF); 1604 1.2.2.2 skrll free(fw, M_DEVBUF); 1605 1.2.2.2 skrll 1606 1.2.2.2 skrll r = CSR_READ_4(sc, IPW_CSR_IO); 1607 1.2.2.2 skrll CSR_WRITE_4(sc, IPW_CSR_IO, r | IPW_IO_GPIO1_MASK | IPW_IO_GPIO3_MASK); 1608 1.2.2.2 skrll 1609 1.2.2.2 skrll /* Retrieve information tables base addresses */ 1610 1.2.2.2 skrll sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 1611 1.2.2.2 skrll sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 1612 1.2.2.2 skrll 1613 1.2.2.2 skrll ipw_write_table1(sc, IPW_INFO_LOCK, 0); 1614 1.2.2.2 skrll 1615 1.2.2.2 skrll /* Retrieve adapter MAC address */ 1616 1.2.2.2 skrll len = IEEE80211_ADDR_LEN; 1617 1.2.2.2 skrll ipw_read_table2(sc, IPW_INFO_ADAPTER_MAC, ic->ic_myaddr, &len); 1618 1.2.2.2 skrll 1619 1.2.2.2 skrll IEEE80211_ADDR_COPY(LLADDR(ifp->if_sadl), ic->ic_myaddr); 1620 1.2.2.2 skrll 1621 1.2.2.2 skrll return 0; 1622 1.2.2.2 skrll 1623 1.2.2.2 skrll fail3: free(uc, M_DEVBUF); 1624 1.2.2.2 skrll fail2: free(fw, M_DEVBUF); 1625 1.2.2.2 skrll fail1: ipw_reset(sc); 1626 1.2.2.2 skrll 1627 1.2.2.2 skrll return error; 1628 1.2.2.2 skrll } 1629 1.2.2.2 skrll 1630 1.2.2.2 skrll static int 1631 1.2.2.2 skrll ipw_config(struct ipw_softc *sc) 1632 1.2.2.2 skrll { 1633 1.2.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 1634 1.2.2.2 skrll struct ifnet *ifp = &ic->ic_if; 1635 1.2.2.2 skrll struct ipw_security security; 1636 1.2.2.2 skrll struct ieee80211_wepkey *k; 1637 1.2.2.2 skrll struct ipw_wep_key wepkey; 1638 1.2.2.2 skrll struct ipw_scan_options options; 1639 1.2.2.2 skrll struct ipw_configuration config; 1640 1.2.2.2 skrll u_int32_t data; 1641 1.2.2.2 skrll int error, i; 1642 1.2.2.2 skrll 1643 1.2.2.2 skrll DPRINTF(("Setting adapter MAC to %s\n", ether_sprintf(ic->ic_myaddr))); 1644 1.2.2.2 skrll IEEE80211_ADDR_COPY(LLADDR(ifp->if_sadl), ic->ic_myaddr); 1645 1.2.2.2 skrll error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 1646 1.2.2.2 skrll IEEE80211_ADDR_LEN); 1647 1.2.2.2 skrll if (error != 0) 1648 1.2.2.2 skrll return error; 1649 1.2.2.2 skrll 1650 1.2.2.2 skrll switch (ic->ic_opmode) { 1651 1.2.2.2 skrll case IEEE80211_M_STA: 1652 1.2.2.2 skrll case IEEE80211_M_HOSTAP: 1653 1.2.2.2 skrll data = htole32(IPW_MODE_BSS); 1654 1.2.2.2 skrll break; 1655 1.2.2.2 skrll 1656 1.2.2.2 skrll case IEEE80211_M_IBSS: 1657 1.2.2.2 skrll case IEEE80211_M_AHDEMO: 1658 1.2.2.2 skrll data = htole32(IPW_MODE_IBSS); 1659 1.2.2.2 skrll break; 1660 1.2.2.2 skrll 1661 1.2.2.2 skrll case IEEE80211_M_MONITOR: 1662 1.2.2.2 skrll data = htole32(IPW_MODE_MONITOR); 1663 1.2.2.2 skrll break; 1664 1.2.2.2 skrll } 1665 1.2.2.2 skrll DPRINTF(("Setting adapter mode to %u\n", data)); 1666 1.2.2.2 skrll error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 1667 1.2.2.2 skrll if (error != 0) 1668 1.2.2.2 skrll return error; 1669 1.2.2.2 skrll 1670 1.2.2.2 skrll if (ic->ic_opmode == IEEE80211_M_IBSS || 1671 1.2.2.2 skrll ic->ic_opmode == IEEE80211_M_MONITOR) { 1672 1.2.2.2 skrll data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); 1673 1.2.2.2 skrll DPRINTF(("Setting adapter channel to %u\n", data)); 1674 1.2.2.2 skrll error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 1675 1.2.2.2 skrll if (error != 0) 1676 1.2.2.2 skrll return error; 1677 1.2.2.2 skrll } 1678 1.2.2.2 skrll 1679 1.2.2.2 skrll config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 1680 1.2.2.2 skrll IPW_CFG_PREAMBLE_LEN | IPW_CFG_802_1x_ENABLE); 1681 1.2.2.2 skrll if (ic->ic_opmode == IEEE80211_M_IBSS) 1682 1.2.2.2 skrll config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 1683 1.2.2.2 skrll if (ifp->if_flags & IFF_PROMISC) 1684 1.2.2.2 skrll config.flags |= htole32(IPW_CFG_PROMISCUOUS); 1685 1.2.2.2 skrll config.channels = htole32(0x3fff); /* channels 1-14 */ 1686 1.2.2.2 skrll config.ibss_chan = htole32(0x7ff); 1687 1.2.2.2 skrll DPRINTF(("Setting adapter configuration 0x%08x\n", config.flags)); 1688 1.2.2.2 skrll error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 1689 1.2.2.2 skrll if (error != 0) 1690 1.2.2.2 skrll return error; 1691 1.2.2.2 skrll 1692 1.2.2.2 skrll data = htole32(0x3); /* 1, 2 */ 1693 1.2.2.2 skrll DPRINTF(("Setting adapter basic tx rates to 0x%x\n", data)); 1694 1.2.2.2 skrll error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 1695 1.2.2.2 skrll if (error != 0) 1696 1.2.2.2 skrll return error; 1697 1.2.2.2 skrll 1698 1.2.2.2 skrll data = htole32(0xf); /* 1, 2, 5.5, 11 */ 1699 1.2.2.2 skrll DPRINTF(("Setting adapter tx rates to 0x%x\n", data)); 1700 1.2.2.2 skrll error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 1701 1.2.2.2 skrll if (error != 0) 1702 1.2.2.2 skrll return error; 1703 1.2.2.2 skrll 1704 1.2.2.2 skrll data = htole32(IPW_POWER_MODE_CAM); 1705 1.2.2.2 skrll DPRINTF(("Setting adapter power mode to %u\n", data)); 1706 1.2.2.2 skrll error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 1707 1.2.2.2 skrll if (error != 0) 1708 1.2.2.2 skrll return error; 1709 1.2.2.2 skrll 1710 1.2.2.2 skrll if (ic->ic_opmode == IEEE80211_M_IBSS) { 1711 1.2.2.2 skrll data = htole32(ic->ic_txpower); 1712 1.2.2.2 skrll DPRINTF(("Setting adapter tx power index to %u\n", data)); 1713 1.2.2.2 skrll error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 1714 1.2.2.2 skrll sizeof data); 1715 1.2.2.2 skrll if (error != 0) 1716 1.2.2.2 skrll return error; 1717 1.2.2.2 skrll } 1718 1.2.2.2 skrll 1719 1.2.2.2 skrll data = htole32(ic->ic_rtsthreshold); 1720 1.2.2.2 skrll DPRINTF(("Setting adapter RTS threshold to %u\n", data)); 1721 1.2.2.2 skrll error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 1722 1.2.2.2 skrll if (error != 0) 1723 1.2.2.2 skrll return error; 1724 1.2.2.2 skrll 1725 1.2.2.2 skrll data = htole32(ic->ic_fragthreshold); 1726 1.2.2.2 skrll DPRINTF(("Setting adapter frag threshold to %u\n", data)); 1727 1.2.2.2 skrll error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 1728 1.2.2.2 skrll if (error != 0) 1729 1.2.2.2 skrll return error; 1730 1.2.2.2 skrll 1731 1.2.2.2 skrll #ifdef IPW_DEBUG 1732 1.2.2.2 skrll if (ipw_debug > 0) { 1733 1.2.2.2 skrll printf("Setting adapter ESSID to "); 1734 1.2.2.2 skrll ieee80211_print_essid(ic->ic_des_essid, ic->ic_des_esslen); 1735 1.2.2.2 skrll printf("\n"); 1736 1.2.2.2 skrll } 1737 1.2.2.2 skrll #endif 1738 1.2.2.2 skrll error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ic->ic_des_essid, 1739 1.2.2.2 skrll ic->ic_des_esslen); 1740 1.2.2.2 skrll if (error != 0) 1741 1.2.2.2 skrll return error; 1742 1.2.2.2 skrll 1743 1.2.2.2 skrll /* no mandatory BSSID */ 1744 1.2.2.2 skrll error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 1745 1.2.2.2 skrll if (error != 0) 1746 1.2.2.2 skrll return error; 1747 1.2.2.2 skrll 1748 1.2.2.2 skrll if (ic->ic_flags & IEEE80211_F_DESBSSID) { 1749 1.2.2.2 skrll DPRINTF(("Setting adapter desired BSSID to %s\n", 1750 1.2.2.2 skrll ether_sprintf(ic->ic_des_bssid))); 1751 1.2.2.2 skrll error = ipw_cmd(sc, IPW_CMD_SET_DESIRED_BSSID, 1752 1.2.2.2 skrll ic->ic_des_bssid, IEEE80211_ADDR_LEN); 1753 1.2.2.2 skrll if (error != 0) 1754 1.2.2.2 skrll return error; 1755 1.2.2.2 skrll } 1756 1.2.2.2 skrll 1757 1.2.2.2 skrll security.authmode = IPW_AUTH_OPEN; 1758 1.2.2.2 skrll security.ciphers = htole32(IPW_CIPHER_NONE); 1759 1.2.2.2 skrll security.version = htole16(0); 1760 1.2.2.2 skrll security.replay_counters_number = 0; 1761 1.2.2.2 skrll security.unicast_using_group = 0; 1762 1.2.2.2 skrll DPRINTF(("Setting adapter authmode to %u\n", security.authmode)); 1763 1.2.2.2 skrll error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 1764 1.2.2.2 skrll sizeof security); 1765 1.2.2.2 skrll if (error != 0) 1766 1.2.2.2 skrll return error; 1767 1.2.2.2 skrll 1768 1.2.2.2 skrll if (ic->ic_flags & IEEE80211_F_PRIVACY) { 1769 1.2.2.2 skrll k = ic->ic_nw_keys; 1770 1.2.2.2 skrll for (i = 0; i < IEEE80211_WEP_NKID; i++, k++) { 1771 1.2.2.2 skrll if (k->wk_len == 0) 1772 1.2.2.2 skrll continue; 1773 1.2.2.2 skrll 1774 1.2.2.2 skrll wepkey.idx = i; 1775 1.2.2.2 skrll wepkey.len = k->wk_len; 1776 1.2.2.2 skrll bzero(wepkey.key, sizeof wepkey.key); 1777 1.2.2.2 skrll bcopy(k->wk_key, wepkey.key, k->wk_len); 1778 1.2.2.2 skrll DPRINTF(("Setting wep key index %d len %d\n", 1779 1.2.2.2 skrll wepkey.idx, wepkey.len)); 1780 1.2.2.2 skrll error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY, &wepkey, 1781 1.2.2.2 skrll sizeof wepkey); 1782 1.2.2.2 skrll if (error != 0) 1783 1.2.2.2 skrll return error; 1784 1.2.2.2 skrll } 1785 1.2.2.2 skrll 1786 1.2.2.2 skrll data = htole32(ic->ic_wep_txkey); 1787 1.2.2.2 skrll DPRINTF(("Setting adapter tx key index to %u\n", data)); 1788 1.2.2.2 skrll error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY_INDEX, &data, 1789 1.2.2.2 skrll sizeof data); 1790 1.2.2.2 skrll if (error != 0) 1791 1.2.2.2 skrll return error; 1792 1.2.2.2 skrll } 1793 1.2.2.2 skrll 1794 1.2.2.2 skrll data = htole32((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) ? 0x8 : 0); 1795 1.2.2.2 skrll DPRINTF(("Setting adapter wep flags to 0x%x\n", data)); 1796 1.2.2.2 skrll error = ipw_cmd(sc, IPW_CMD_SET_WEP_FLAGS, &data, sizeof data); 1797 1.2.2.2 skrll if (error != 0) 1798 1.2.2.2 skrll return error; 1799 1.2.2.2 skrll 1800 1.2.2.2 skrll if (ic->ic_opmode == IEEE80211_M_IBSS || 1801 1.2.2.2 skrll ic->ic_opmode == IEEE80211_M_HOSTAP) { 1802 1.2.2.2 skrll data = htole32(ic->ic_lintval); 1803 1.2.2.2 skrll DPRINTF(("Setting adapter beacon interval to %u\n", data)); 1804 1.2.2.2 skrll error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 1805 1.2.2.2 skrll sizeof data); 1806 1.2.2.2 skrll if (error != 0) 1807 1.2.2.2 skrll return error; 1808 1.2.2.2 skrll } 1809 1.2.2.2 skrll 1810 1.2.2.2 skrll options.flags = htole32(0); 1811 1.2.2.2 skrll options.channels = htole32(0x3fff); /* scan channels 1-14 */ 1812 1.2.2.2 skrll error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &options, sizeof options); 1813 1.2.2.2 skrll if (error != 0) 1814 1.2.2.2 skrll return error; 1815 1.2.2.2 skrll 1816 1.2.2.2 skrll /* finally, enable adapter (start scanning for an access point) */ 1817 1.2.2.2 skrll DPRINTF(("Enabling adapter\n")); 1818 1.2.2.2 skrll error = ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1819 1.2.2.2 skrll if (error != 0) 1820 1.2.2.2 skrll return error; 1821 1.2.2.2 skrll 1822 1.2.2.2 skrll return 0; 1823 1.2.2.2 skrll } 1824 1.2.2.2 skrll 1825 1.2.2.2 skrll static int 1826 1.2.2.2 skrll ipw_init(struct ifnet *ifp) 1827 1.2.2.2 skrll { 1828 1.2.2.2 skrll struct ipw_softc *sc = ifp->if_softc; 1829 1.2.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 1830 1.2.2.2 skrll 1831 1.2.2.2 skrll /* exit immediately if firmware has not been ioctl'd */ 1832 1.2.2.2 skrll if (!(sc->flags & IPW_FLAG_FW_INITED)) { 1833 1.2.2.2 skrll ifp->if_flags &= ~IFF_UP; 1834 1.2.2.2 skrll return EIO; 1835 1.2.2.2 skrll } 1836 1.2.2.2 skrll 1837 1.2.2.2 skrll ipw_stop(ifp, 0); 1838 1.2.2.2 skrll 1839 1.2.2.2 skrll if (ipw_config(sc) != 0) { 1840 1.2.2.2 skrll aprint_error("%s: device configuration failed\n", 1841 1.2.2.2 skrll sc->sc_dev.dv_xname); 1842 1.2.2.2 skrll goto fail; 1843 1.2.2.2 skrll } 1844 1.2.2.2 skrll 1845 1.2.2.2 skrll ifp->if_flags &= ~IFF_OACTIVE; 1846 1.2.2.2 skrll ifp->if_flags |= IFF_RUNNING; 1847 1.2.2.2 skrll 1848 1.2.2.2 skrll ic->ic_bss->ni_chan = ic->ic_channels; 1849 1.2.2.2 skrll 1850 1.2.2.2 skrll return 0; 1851 1.2.2.2 skrll 1852 1.2.2.2 skrll fail: ipw_stop(ifp, 0); 1853 1.2.2.2 skrll 1854 1.2.2.2 skrll return EIO; 1855 1.2.2.2 skrll } 1856 1.2.2.2 skrll 1857 1.2.2.2 skrll static void 1858 1.2.2.2 skrll ipw_stop(struct ifnet *ifp, int disable) 1859 1.2.2.2 skrll { 1860 1.2.2.2 skrll struct ipw_softc *sc = ifp->if_softc; 1861 1.2.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 1862 1.2.2.2 skrll 1863 1.2.2.2 skrll if (ifp->if_flags & IFF_RUNNING) { 1864 1.2.2.2 skrll DPRINTF(("Disabling adapter\n")); 1865 1.2.2.2 skrll ipw_cmd(sc, IPW_CMD_DISABLE, NULL, 0); 1866 1.2.2.2 skrll } 1867 1.2.2.2 skrll 1868 1.2.2.2 skrll ifp->if_timer = 0; 1869 1.2.2.2 skrll ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1870 1.2.2.2 skrll 1871 1.2.2.2 skrll ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1872 1.2.2.2 skrll } 1873 1.2.2.2 skrll 1874 1.2.2.2 skrll static void 1875 1.2.2.2 skrll ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, u_int8_t *datap, 1876 1.2.2.2 skrll bus_size_t count) 1877 1.2.2.2 skrll { 1878 1.2.2.2 skrll for (; count > 0; offset++, datap++, count--) { 1879 1.2.2.2 skrll CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 1880 1.2.2.2 skrll *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 1881 1.2.2.2 skrll } 1882 1.2.2.2 skrll } 1883 1.2.2.2 skrll 1884 1.2.2.2 skrll static void 1885 1.2.2.2 skrll ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, u_int8_t *datap, 1886 1.2.2.2 skrll bus_size_t count) 1887 1.2.2.2 skrll { 1888 1.2.2.2 skrll for (; count > 0; offset++, datap++, count--) { 1889 1.2.2.2 skrll CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 1890 1.2.2.2 skrll CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 1891 1.2.2.2 skrll } 1892 1.2.2.2 skrll } 1893 1.2.2.2 skrll 1894 1.2.2.2 skrll static void 1895 1.2.2.2 skrll ipw_zero_mem_4(struct ipw_softc *sc, bus_size_t offset, bus_size_t count) 1896 1.2.2.2 skrll { 1897 1.2.2.2 skrll CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, offset); 1898 1.2.2.2 skrll while (count-- > 0) 1899 1.2.2.2 skrll CSR_WRITE_4(sc, IPW_CSR_AUTOINC_DATA, 0); 1900 1.2.2.2 skrll } 1901 1.2.2.2 skrll 1902 1.2.2.2 skrll #ifdef IPW_AS_LKM 1903 1.2.2.2 skrll 1904 1.2.2.2 skrll #include <sys/lkm.h> 1905 1.2.2.2 skrll #include <lkm/dev/pcilkm/pcilkm.h> 1906 1.2.2.2 skrll 1907 1.2.2.2 skrll MOD_MISC("ipw"); 1908 1.2.2.2 skrll 1909 1.2.2.2 skrll PCILKM_DECLARE(ipw, DV_DULL, NULL); 1910 1.2.2.2 skrll 1911 1.2.2.2 skrll #endif 1912
Indexes created Tue Sep 30 20:09:53 GMT 2025