if_ipw.c revision 1.1
1 /* Id: if_ipw.c,v 1.1.2.7 2004/08/20 11:20:11 damien Exp */ 2 3 /*- 4 * Copyright (c) 2004 5 * Damien Bergamini <damien.bergamini (at) free.fr>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$Id: if_ipw.c,v 1.1 2004/08/23 11:42:02 lukem Exp $"); 32 33 /*- 34 * Intel(R) PRO/Wireless 2100 MiniPCI driver 35 * http://www.intel.com/products/mobiletechnology/prowireless.htm 36 */ 37 38 #include "bpfilter.h" 39 40 #include <sys/param.h> 41 #include <sys/sockio.h> 42 #include <sys/sysctl.h> 43 #include <sys/mbuf.h> 44 #include <sys/kernel.h> 45 #include <sys/socket.h> 46 #include <sys/systm.h> 47 #include <sys/malloc.h> 48 #include <sys/conf.h> 49 50 #include <machine/bus.h> 51 #include <machine/endian.h> 52 #include <machine/intr.h> 53 54 #include <dev/pci/pcireg.h> 55 #include <dev/pci/pcivar.h> 56 #include <dev/pci/pcidevs.h> 57 58 #if NBPFILTER > 0 59 #include <net/bpf.h> 60 #endif 61 #include <net/if.h> 62 #include <net/if_arp.h> 63 #include <net/if_dl.h> 64 #include <net/if_ether.h> 65 #include <net/if_media.h> 66 #include <net/if_types.h> 67 68 #include <net80211/ieee80211_var.h> 69 70 #include <netinet/in.h> 71 #include <netinet/in_systm.h> 72 #include <netinet/in_var.h> 73 #include <netinet/ip.h> 74 75 #include "if_ipwreg.h" 76 #include "if_ipwvar.h" 77 78 static int ipw_match(struct device *, struct cfdata *, void *); 79 static void ipw_attach(struct device *, struct device *, void *); 80 static int ipw_detach(struct device *, int); 81 static int ipw_media_change(struct ifnet *); 82 static int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 83 static void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 84 static void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 85 static void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 86 struct ipw_soft_bd *, struct ipw_soft_buf *); 87 static void ipw_notification_intr(struct ipw_softc *, struct ipw_soft_buf *); 88 static void ipw_rx_intr(struct ipw_softc *); 89 static void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 90 static void ipw_tx_intr(struct ipw_softc *); 91 static int ipw_intr(void *); 92 static int ipw_cmd(struct ipw_softc *, u_int32_t, void *, u_int32_t); 93 static int ipw_tx_start(struct ifnet *, struct mbuf *, struct ieee80211_node *); 94 static void ipw_start(struct ifnet *); 95 static void ipw_watchdog(struct ifnet *); 96 static int ipw_get_table1(struct ipw_softc *, u_int32_t *); 97 static int ipw_get_radio(struct ipw_softc *, int *); 98 static int ipw_ioctl(struct ifnet *, u_long, caddr_t); 99 static u_int32_t ipw_read_table1(struct ipw_softc *, u_int32_t); 100 static void ipw_write_table1(struct ipw_softc *, u_int32_t, u_int32_t); 101 static int ipw_read_table2(struct ipw_softc *, u_int32_t, void *, u_int32_t *); 102 static int ipw_tx_init(struct ipw_softc *); 103 static void ipw_tx_stop(struct ipw_softc *); 104 static int ipw_rx_init(struct ipw_softc *); 105 static void ipw_rx_stop(struct ipw_softc *); 106 static void ipw_reset(struct ipw_softc *); 107 static int ipw_clock_sync(struct ipw_softc *); 108 static int ipw_load_ucode(struct ipw_softc *, u_char *, int); 109 static int ipw_load_firmware(struct ipw_softc *, u_char *, int); 110 static int ipw_firmware_init(struct ipw_softc *, u_char *); 111 static int ipw_config(struct ipw_softc *); 112 static int ipw_init(struct ifnet *); 113 static void ipw_stop(struct ifnet *, int); 114 static void ipw_read_mem_1(struct ipw_softc *, bus_size_t, u_int8_t *, 115 bus_size_t); 116 static void ipw_write_mem_1(struct ipw_softc *, bus_size_t, u_int8_t *, 117 bus_size_t); 118 static void ipw_zero_mem_4(struct ipw_softc *, bus_size_t, bus_size_t); 119 120 static inline u_int8_t MEM_READ_1(struct ipw_softc *sc, u_int32_t addr) 121 { 122 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 123 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); 124 } 125 126 static inline u_int16_t MEM_READ_2(struct ipw_softc *sc, u_int32_t addr) 127 { 128 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 129 return CSR_READ_2(sc, IPW_CSR_INDIRECT_DATA); 130 } 131 132 static inline u_int32_t MEM_READ_4(struct ipw_softc *sc, u_int32_t addr) 133 { 134 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 135 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); 136 } 137 138 #ifdef IPW_DEBUG 139 #define DPRINTF(x) if (ipw_debug > 0) printf x 140 #define DPRINTFN(n, x) if (ipw_debug >= (n)) printf x 141 int ipw_debug = 0; 142 #else 143 #define DPRINTF(x) 144 #define DPRINTFN(n, x) 145 #endif 146 147 CFATTACH_DECL(ipw, sizeof (struct ipw_softc), ipw_match, ipw_attach, 148 ipw_detach, NULL); 149 150 static int 151 ipw_match(struct device *parent, struct cfdata *match, void *aux) 152 { 153 struct pci_attach_args *pa = aux; 154 155 if (PCI_VENDOR (pa->pa_id) == PCI_VENDOR_INTEL && 156 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_PRO_WL_2100) 157 return 1; 158 159 return 0; 160 } 161 162 /* Base Address Register */ 163 #define IPW_PCI_BAR0 0x10 164 165 static void 166 ipw_attach(struct device *parent, struct device *self, void *aux) 167 { 168 struct ipw_softc *sc = (struct ipw_softc *)self; 169 struct ieee80211com *ic = &sc->sc_ic; 170 struct ifnet *ifp = &ic->ic_if; 171 struct ieee80211_rateset *rs; 172 struct pci_attach_args *pa = aux; 173 const char *intrstr; 174 char devinfo[256]; 175 bus_space_tag_t memt; 176 bus_space_handle_t memh; 177 bus_addr_t base; 178 pci_intr_handle_t ih; 179 u_int32_t data; 180 int i, revision, error; 181 182 sc->sc_pct = pa->pa_pc; 183 184 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof devinfo); 185 revision = PCI_REVISION(pa->pa_class); 186 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, revision); 187 188 /* enable bus-mastering */ 189 data = pci_conf_read(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG); 190 data |= PCI_COMMAND_MASTER_ENABLE; 191 pci_conf_write(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG, data); 192 193 /* map the register window */ 194 error = pci_mapreg_map(pa, IPW_PCI_BAR0, PCI_MAPREG_TYPE_MEM | 195 PCI_MAPREG_MEM_TYPE_32BIT, 0, &memt, &memh, &base, &sc->sc_sz); 196 if (error != 0) { 197 aprint_error("%s: could not map memory space\n", 198 sc->sc_dev.dv_xname); 199 return; 200 } 201 202 sc->sc_st = memt; 203 sc->sc_sh = memh; 204 sc->sc_dmat = pa->pa_dmat; 205 206 /* disable interrupts */ 207 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 208 209 if (pci_intr_map(pa, &ih) != 0) { 210 aprint_error("%s: could not map interrupt\n", 211 sc->sc_dev.dv_xname); 212 return; 213 } 214 215 intrstr = pci_intr_string(sc->sc_pct, ih); 216 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, ipw_intr, sc); 217 if (sc->sc_ih == NULL) { 218 aprint_error("%s: could not establish interrupt", 219 sc->sc_dev.dv_xname); 220 if (intrstr != NULL) 221 aprint_error(" at %s", intrstr); 222 aprint_error("\n"); 223 return; 224 } 225 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 226 227 ic->ic_phytype = IEEE80211_T_DS; 228 ic->ic_opmode = IEEE80211_M_STA; 229 ic->ic_state = IEEE80211_S_INIT; 230 231 /* set device capabilities */ 232 ic->ic_caps = IEEE80211_C_IBSS | IEEE80211_C_MONITOR | 233 IEEE80211_C_PMGT | IEEE80211_C_TXPMGT | IEEE80211_C_WEP; 234 235 /* set supported 11.b rates */ 236 rs = &ic->ic_sup_rates[IEEE80211_MODE_11B]; 237 rs->rs_nrates = 4; 238 rs->rs_rates[0] = 2; /* 1Mbps */ 239 rs->rs_rates[1] = 4; /* 2Mbps */ 240 rs->rs_rates[2] = 11; /* 5.5Mbps */ 241 rs->rs_rates[3] = 22; /* 11Mbps */ 242 243 /* set supported 11.b channels (1 through 14) */ 244 for (i = 1; i <= 14; i++) { 245 ic->ic_channels[i].ic_freq = 246 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 247 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 248 } 249 250 ic->ic_ibss_chan = &ic->ic_channels[0]; 251 252 ifp->if_softc = sc; 253 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 254 ifp->if_init = ipw_init; 255 ifp->if_stop = ipw_stop; 256 ifp->if_ioctl = ipw_ioctl; 257 ifp->if_start = ipw_start; 258 ifp->if_watchdog = ipw_watchdog; 259 IFQ_SET_READY(&ifp->if_snd); 260 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 261 262 if_attach(ifp); 263 ieee80211_ifattach(ifp); 264 /* override state transition machine */ 265 sc->sc_newstate = ic->ic_newstate; 266 ic->ic_newstate = ipw_newstate; 267 268 ieee80211_media_init(ifp, ipw_media_change, ieee80211_media_status); 269 } 270 271 static int 272 ipw_detach(struct device* self, int flags) 273 { 274 struct ipw_softc *sc = (struct ipw_softc *)self; 275 struct ifnet *ifp = &sc->sc_ic.ic_if; 276 277 ipw_reset(sc); 278 279 ieee80211_ifdetach(ifp); 280 if_detach(ifp); 281 282 if (sc->sc_ih != NULL) { 283 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 284 sc->sc_ih = NULL; 285 } 286 287 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 288 289 return 0; 290 } 291 292 static int 293 ipw_media_change(struct ifnet *ifp) 294 { 295 int error; 296 297 error = ieee80211_media_change(ifp); 298 if (error != ENETRESET) 299 return error; 300 301 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 302 ipw_init(ifp); 303 304 return 0; 305 } 306 307 static int 308 ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 309 { 310 struct ifnet *ifp = &ic->ic_if; 311 struct ipw_softc *sc = ifp->if_softc; 312 struct ieee80211_node *ni = ic->ic_bss; 313 u_int32_t val, len; 314 315 switch (nstate) { 316 case IEEE80211_S_INIT: 317 break; 318 319 case IEEE80211_S_RUN: 320 len = IEEE80211_NWID_LEN; 321 ipw_read_table2(sc, IPW_INFO_CURRENT_SSID, ni->ni_essid, &len); 322 ni->ni_esslen = len; 323 324 val = ipw_read_table1(sc, IPW_INFO_CURRENT_CHANNEL); 325 ni->ni_chan = &ic->ic_channels[val]; 326 327 DELAY(100); /* firmware needs a short delay here */ 328 329 len = IEEE80211_ADDR_LEN; 330 ipw_read_table2(sc, IPW_INFO_CURRENT_BSSID, ni->ni_bssid, &len); 331 break; 332 333 case IEEE80211_S_SCAN: 334 case IEEE80211_S_AUTH: 335 case IEEE80211_S_ASSOC: 336 break; 337 } 338 339 ic->ic_state = nstate; 340 return 0; 341 } 342 343 static void 344 ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 345 { 346 struct ipw_cmd *cmd; 347 348 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof (struct ipw_cmd), 349 BUS_DMASYNC_POSTREAD); 350 351 cmd = mtod(sbuf->m, struct ipw_cmd *); 352 353 DPRINTFN(2, ("RX!CMD!%u!%u!%u!%u!%u\n", 354 le32toh(cmd->type), le32toh(cmd->subtype), le32toh(cmd->seq), 355 le32toh(cmd->len), le32toh(cmd->status))); 356 357 /* 358 * Wake up processes waiting for command ack. In the case of the 359 * IPW_CMD_DISABLE command, wake up the process only when the adapter 360 * enters the IPW_STATE_DISABLED state. This is notified in 361 * ipw_newstate_intr(). 362 */ 363 if (le32toh(cmd->type) != IPW_CMD_DISABLE) 364 wakeup(sc->cmd); 365 } 366 367 static void 368 ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 369 { 370 struct ieee80211com *ic = &sc->sc_ic; 371 u_int32_t state; 372 373 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof state, 374 BUS_DMASYNC_POSTREAD); 375 376 state = le32toh(*mtod(sbuf->m, u_int32_t *)); 377 378 DPRINTFN(2, ("RX!NEWSTATE!%u\n", state)); 379 380 switch (state) { 381 case IPW_STATE_ASSOCIATED: 382 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 383 break; 384 385 case IPW_STATE_SCANNING: 386 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 387 break; 388 389 case IPW_STATE_ASSOCIATION_LOST: 390 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 391 break; 392 393 case IPW_STATE_DISABLED: 394 wakeup(sc->cmd); 395 break; 396 397 case IPW_STATE_RADIO_DISABLED: 398 /* XXX should turn the interface down */ 399 break; 400 } 401 } 402 403 static void 404 ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 405 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 406 { 407 struct ieee80211com *ic = &sc->sc_ic; 408 struct ifnet *ifp = &ic->ic_if; 409 struct mbuf *m; 410 struct ieee80211_frame *wh; 411 struct ieee80211_node *ni; 412 int error; 413 414 DPRINTFN(5, ("RX!DATA!%u!%u\n", le32toh(status->len), status->rssi)); 415 416 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, le32toh(status->len), 417 BUS_DMASYNC_POSTREAD); 418 419 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 420 421 /* Finalize mbuf */ 422 m = sbuf->m; 423 m->m_pkthdr.rcvif = ifp; 424 m->m_pkthdr.len = m->m_len = le32toh(status->len); 425 426 wh = mtod(m, struct ieee80211_frame *); 427 428 if (ic->ic_opmode != IEEE80211_M_STA) { 429 ni = ieee80211_find_node(ic, wh->i_addr2); 430 if (ni == NULL) 431 ni = ieee80211_ref_node(ic->ic_bss); 432 } else 433 ni = ieee80211_ref_node(ic->ic_bss); 434 435 /* Send it up to the upper layer */ 436 ieee80211_input(ifp, m, ni, status->rssi, 0/*rstamp*/); 437 438 ieee80211_release_node(ic, ni); 439 440 MGETHDR(m, M_DONTWAIT, MT_DATA); 441 if (m == NULL) { 442 aprint_error("%s: could not allocate rx mbuf\n", 443 sc->sc_dev.dv_xname); 444 return; 445 } 446 MCLGET(m, M_DONTWAIT); 447 if (!(m->m_flags & M_EXT)) { 448 m_freem(m); 449 aprint_error("%s: could not allocate rx mbuf cluster\n", 450 sc->sc_dev.dv_xname); 451 return; 452 } 453 454 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, mtod(m, void *), 455 MCLBYTES, NULL, BUS_DMA_NOWAIT); 456 if (error != 0) { 457 aprint_error("%s: could not map rxbuf dma memory\n", 458 sc->sc_dev.dv_xname); 459 m_freem(m); 460 return; 461 } 462 463 sbuf->m = m; 464 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 465 } 466 467 static void 468 ipw_notification_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 469 { 470 DPRINTFN(2, ("RX!NOTIFICATION\n")); 471 } 472 473 static void 474 ipw_rx_intr(struct ipw_softc *sc) 475 { 476 struct ipw_status *status; 477 struct ipw_soft_bd *sbd; 478 struct ipw_soft_buf *sbuf; 479 u_int32_t r, i; 480 481 r = CSR_READ_4(sc, IPW_CSR_RX_READ_INDEX); 482 483 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 484 485 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 486 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 487 BUS_DMASYNC_POSTREAD); 488 489 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 490 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 491 BUS_DMASYNC_POSTREAD); 492 493 status = &sc->status_list[i]; 494 sbd = &sc->srbd_list[i]; 495 sbuf = sbd->priv; 496 497 switch (le16toh(status->code) & 0xf) { 498 case IPW_STATUS_CODE_COMMAND: 499 ipw_command_intr(sc, sbuf); 500 break; 501 502 case IPW_STATUS_CODE_NEWSTATE: 503 ipw_newstate_intr(sc, sbuf); 504 break; 505 506 case IPW_STATUS_CODE_DATA_802_3: 507 case IPW_STATUS_CODE_DATA_802_11: 508 ipw_data_intr(sc, status, sbd, sbuf); 509 break; 510 511 case IPW_STATUS_CODE_NOTIFICATION: 512 ipw_notification_intr(sc, sbuf); 513 break; 514 515 default: 516 aprint_debug("%s: unknown status code %u\n", 517 sc->sc_dev.dv_xname, le16toh(status->code)); 518 } 519 sbd->bd->flags = 0; 520 521 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 522 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 523 BUS_DMASYNC_PREWRITE); 524 } 525 526 /* Tell the firmware what we have processed */ 527 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 528 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE_INDEX, sc->rxcur); 529 } 530 531 static void 532 ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 533 { 534 struct ieee80211com *ic; 535 struct ipw_soft_hdr *shdr; 536 struct ipw_soft_buf *sbuf; 537 538 switch (sbd->type) { 539 case IPW_SBD_TYPE_COMMAND: 540 bus_dmamap_unload(sc->sc_dmat, sc->cmd_map); 541 break; 542 543 case IPW_SBD_TYPE_HEADER: 544 shdr = sbd->priv; 545 bus_dmamap_unload(sc->sc_dmat, shdr->map); 546 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 547 break; 548 549 case IPW_SBD_TYPE_DATA: 550 ic = &sc->sc_ic; 551 sbuf = sbd->priv; 552 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 553 m_freem(sbuf->m); 554 if (sbuf->ni != NULL) 555 ieee80211_release_node(ic, sbuf->ni); 556 /* kill watchdog timer */ 557 sc->sc_tx_timer = 0; 558 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 559 break; 560 } 561 sbd->type = IPW_SBD_TYPE_NOASSOC; 562 } 563 564 static void 565 ipw_tx_intr(struct ipw_softc *sc) 566 { 567 struct ifnet *ifp = &sc->sc_ic.ic_if; 568 u_int32_t r, i; 569 570 r = CSR_READ_4(sc, IPW_CSR_TX_READ_INDEX); 571 572 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) 573 ipw_release_sbd(sc, &sc->stbd_list[i]); 574 575 /* Remember what the firmware has processed */ 576 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 577 578 /* Call start() since some buffer descriptors have been released */ 579 ifp->if_flags &= ~IFF_OACTIVE; 580 (*ifp->if_start)(ifp); 581 } 582 583 static int 584 ipw_intr(void *arg) 585 { 586 struct ipw_softc *sc = arg; 587 u_int32_t r; 588 589 if ((r = CSR_READ_4(sc, IPW_CSR_INTR)) == 0) 590 return 0; 591 592 /* Disable interrupts */ 593 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 594 595 DPRINTFN(8, ("INTR!0x%08x\n", r)); 596 597 if (r & IPW_INTR_RX_TRANSFER) 598 ipw_rx_intr(sc); 599 600 if (r & IPW_INTR_TX_TRANSFER) 601 ipw_tx_intr(sc); 602 603 if (r & IPW_INTR_FW_INIT_DONE) { 604 if (!(r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR))) 605 wakeup(sc); 606 } 607 608 /* Acknowledge interrupts */ 609 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 610 611 /* Re-enable interrupts */ 612 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 613 614 return 0; 615 } 616 617 static int 618 ipw_cmd(struct ipw_softc *sc, u_int32_t type, void *data, u_int32_t len) 619 { 620 struct ipw_soft_bd *sbd; 621 int error; 622 623 sbd = &sc->stbd_list[sc->txcur]; 624 625 error = bus_dmamap_load(sc->sc_dmat, sc->cmd_map, sc->cmd, 626 sizeof (struct ipw_cmd), NULL, BUS_DMA_NOWAIT); 627 if (error != 0) { 628 aprint_error("%s: could not map cmd dma memory\n", 629 sc->sc_dev.dv_xname); 630 return error; 631 } 632 633 sc->cmd->type = htole32(type); 634 sc->cmd->subtype = htole32(0); 635 sc->cmd->len = htole32(len); 636 sc->cmd->seq = htole32(0); 637 if (data != NULL) 638 bcopy(data, sc->cmd->data, len); 639 640 sbd->type = IPW_SBD_TYPE_COMMAND; 641 sbd->bd->physaddr = htole32(sc->cmd_map->dm_segs[0].ds_addr); 642 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 643 sbd->bd->nfrag = 1; 644 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 645 IPW_BD_FLAG_TX_LAST_FRAGMENT; 646 647 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 0, sizeof (struct ipw_cmd), 648 BUS_DMASYNC_PREWRITE); 649 650 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 651 sc->txcur * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 652 BUS_DMASYNC_PREWRITE); 653 654 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 655 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, sc->txcur); 656 657 DPRINTFN(2, ("TX!CMD!%u!%u!%u!%u\n", type, 0, 0, len)); 658 659 /* Wait at most two seconds for command to complete */ 660 return tsleep(sc->cmd, 0, "ipwcmd", 2 * hz); 661 } 662 663 static int 664 ipw_tx_start(struct ifnet *ifp, struct mbuf *m, struct ieee80211_node *ni) 665 { 666 struct ipw_softc *sc = ifp->if_softc; 667 struct ieee80211com *ic = &sc->sc_ic; 668 struct ieee80211_frame *wh; 669 struct ipw_soft_bd *sbd; 670 struct ipw_soft_hdr *shdr; 671 struct ipw_soft_buf *sbuf; 672 int error, i; 673 674 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 675 m = ieee80211_wep_crypt(ifp, m, 1); 676 if (m == NULL) 677 return ENOBUFS; 678 } 679 680 wh = mtod(m, struct ieee80211_frame *); 681 682 shdr = TAILQ_FIRST(&sc->sc_free_shdr); 683 sbuf = TAILQ_FIRST(&sc->sc_free_sbuf); 684 685 shdr->hdr.type = htole32(IPW_HDR_TYPE_SEND); 686 shdr->hdr.subtype = htole32(0); 687 shdr->hdr.encrypted = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0; 688 shdr->hdr.encrypt = 0; 689 shdr->hdr.keyidx = 0; 690 shdr->hdr.keysz = 0; 691 shdr->hdr.fragmentsz = htole16(0); 692 IEEE80211_ADDR_COPY(shdr->hdr.src_addr, wh->i_addr2); 693 if (ic->ic_opmode == IEEE80211_M_STA) 694 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr3); 695 else 696 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr1); 697 698 /* trim IEEE802.11 header */ 699 m_adj(m, sizeof (struct ieee80211_frame)); 700 701 /* 702 * We need to map the mbuf first to know how many buffer descriptors 703 * are needed for this transfer. 704 */ 705 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m, BUS_DMA_NOWAIT); 706 if (error != 0) { 707 aprint_error("%s: could not map mbuf (error %d)\n", 708 sc->sc_dev.dv_xname, error); 709 m_freem(m); 710 return error; 711 } 712 713 error = bus_dmamap_load(sc->sc_dmat, shdr->map, &shdr->hdr, 714 sizeof (struct ipw_hdr), NULL, BUS_DMA_NOWAIT); 715 if (error != 0) { 716 aprint_error("%s: could not map hdr (error %d)\n", 717 sc->sc_dev.dv_xname, error); 718 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 719 m_freem(m); 720 return error; 721 } 722 723 TAILQ_REMOVE(&sc->sc_free_sbuf, sbuf, next); 724 TAILQ_REMOVE(&sc->sc_free_shdr, shdr, next); 725 726 sbd = &sc->stbd_list[sc->txcur]; 727 sbd->type = IPW_SBD_TYPE_HEADER; 728 sbd->priv = shdr; 729 sbd->bd->physaddr = htole32(shdr->map->dm_segs[0].ds_addr); 730 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 731 sbd->bd->nfrag = 1 + sbuf->map->dm_nsegs; 732 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 733 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 734 735 DPRINTFN(5, ("TX!HDR!%u!%u!%u!%u\n", shdr->hdr.type, shdr->hdr.subtype, 736 shdr->hdr.encrypted, shdr->hdr.encrypt)); 737 DPRINTFN(5, ("!%s", ether_sprintf(shdr->hdr.src_addr))); 738 DPRINTFN(5, ("!%s\n", ether_sprintf(shdr->hdr.dst_addr))); 739 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 740 741 sbuf->m = m; 742 sbuf->ni = ni; 743 744 for (i = 0; i < sbuf->map->dm_nsegs; i++) { 745 sbd = &sc->stbd_list[sc->txcur]; 746 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[i].ds_addr); 747 sbd->bd->len = htole32(sbuf->map->dm_segs[i].ds_len); 748 sbd->bd->nfrag = 0; /* used only in first bd */ 749 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 750 if (i == sbuf->map->dm_nsegs - 1) { 751 sbd->type = IPW_SBD_TYPE_DATA; 752 sbd->priv = sbuf; 753 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 754 } else { 755 sbd->type = IPW_SBD_TYPE_NOASSOC; 756 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 757 } 758 759 DPRINTFN(5, ("TX!FRAG!%d!%ld\n", i, 760 sbuf->map->dm_segs[i].ds_len)); 761 762 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 763 sc->txcur * sizeof (struct ipw_bd), 764 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 765 766 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 767 } 768 769 bus_dmamap_sync(sc->sc_dmat, shdr->map, 0, sizeof (struct ipw_hdr), 770 BUS_DMASYNC_PREWRITE); 771 772 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, MCLBYTES, 773 BUS_DMASYNC_PREWRITE); 774 775 /* Inform firmware about this new packet */ 776 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, sc->txcur); 777 778 return 0; 779 } 780 781 static void 782 ipw_start(struct ifnet *ifp) 783 { 784 struct ipw_softc *sc = ifp->if_softc; 785 struct ieee80211com *ic = &sc->sc_ic; 786 struct mbuf *m; 787 struct ieee80211_node *ni; 788 789 for (;;) { 790 IF_DEQUEUE(&ifp->if_snd, m); 791 if (m == NULL) 792 break; 793 794 #if NBPFILTER > 0 795 if (ifp->if_bpf != NULL) 796 bpf_mtap(ifp->if_bpf, m); 797 #endif 798 799 m = ieee80211_encap(ifp, m, &ni); 800 if (m == NULL) 801 continue; 802 803 #if NBPFILTER > 0 804 if (ic->ic_rawbpf != NULL) 805 bpf_mtap(ic->ic_rawbpf, m); 806 #endif 807 808 if (ipw_tx_start(ifp, m, ni) != 0) { 809 if (ni != NULL) 810 ieee80211_release_node(ic, ni); 811 break; 812 } 813 814 /* start watchdog timer */ 815 sc->sc_tx_timer = 5; 816 ifp->if_timer = 1; 817 } 818 } 819 820 static void 821 ipw_watchdog(struct ifnet *ifp) 822 { 823 struct ipw_softc *sc = ifp->if_softc; 824 825 ifp->if_timer = 0; 826 827 if (sc->sc_tx_timer > 0) { 828 if (--sc->sc_tx_timer == 0) { 829 aprint_error("%s: device timeout\n", 830 sc->sc_dev.dv_xname); 831 #ifdef notyet 832 ipw_init(ifp); 833 #endif 834 return; 835 } 836 ifp->if_timer = 1; 837 } 838 839 ieee80211_watchdog(ifp); 840 } 841 842 static int 843 ipw_get_table1(struct ipw_softc *sc, u_int32_t *tbl) 844 { 845 u_int32_t addr, size, i; 846 847 if (!(sc->flags & IPW_FLAG_FW_INITED)) 848 return ENOTTY; 849 850 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, sc->table1_base); 851 852 size = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 853 if (suword(tbl, size) != 0) 854 return EFAULT; 855 856 for (i = 1, ++tbl; i < size; i++, tbl++) { 857 addr = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 858 if (suword(tbl, MEM_READ_4(sc, addr)) != 0) 859 return EFAULT; 860 } 861 return 0; 862 } 863 864 static int 865 ipw_get_radio(struct ipw_softc *sc, int *ret) 866 { 867 u_int32_t addr; 868 869 if (!(sc->flags & IPW_FLAG_FW_INITED)) 870 return ENOTTY; 871 872 addr = ipw_read_table1(sc, IPW_INFO_EEPROM_ADDRESS); 873 if ((MEM_READ_4(sc, addr + 32) >> 24) & 1) { 874 suword(ret, -1); 875 return 0; 876 } 877 878 if (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED) 879 suword(ret, 0); 880 else 881 suword(ret, 1); 882 883 return 0; 884 } 885 886 static int 887 ipw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 888 { 889 struct ipw_softc *sc = ifp->if_softc; 890 struct ifreq *ifr; 891 int s, error = 0; 892 893 s = splnet(); 894 895 switch (cmd) { 896 case SIOCSIFFLAGS: 897 if (ifp->if_flags & IFF_UP) { 898 if (!(ifp->if_flags & IFF_RUNNING)) 899 ipw_init(ifp); 900 } else { 901 if (ifp->if_flags & IFF_RUNNING) 902 ipw_stop(ifp, 1); 903 } 904 break; 905 906 case SIOCGTABLE1: 907 ifr = (struct ifreq *)data; 908 error = ipw_get_table1(sc, (u_int32_t *)ifr->ifr_data); 909 break; 910 911 case SIOCGRADIO: 912 ifr = (struct ifreq *)data; 913 error = ipw_get_radio(sc, (int *)ifr->ifr_data); 914 break; 915 916 case SIOCSLOADFW: 917 /* only super-user can do that! */ 918 if ((error = suser(curproc->p_ucred, &curproc->p_acflag)) != 0) 919 break; 920 921 ifr = (struct ifreq *)data; 922 error = ipw_firmware_init(sc, (u_char *)ifr->ifr_data); 923 break; 924 925 case SIOCSKILLFW: 926 /* only super-user can do that! */ 927 if ((error = suser(curproc->p_ucred, &curproc->p_acflag)) != 0) 928 break; 929 930 ipw_reset(sc); 931 break; 932 933 default: 934 error = ieee80211_ioctl(ifp, cmd, data); 935 if (error != ENETRESET) 936 break; 937 938 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 939 (IFF_UP | IFF_RUNNING)) 940 ipw_init(ifp); 941 error = 0; 942 } 943 944 splx(s); 945 return error; 946 } 947 948 static u_int32_t 949 ipw_read_table1(struct ipw_softc *sc, u_int32_t off) 950 { 951 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 952 } 953 954 static void 955 ipw_write_table1(struct ipw_softc *sc, u_int32_t off, u_int32_t info) 956 { 957 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 958 } 959 960 static int 961 ipw_read_table2(struct ipw_softc *sc, u_int32_t off, void *buf, u_int32_t *len) 962 { 963 u_int32_t addr, info; 964 u_int16_t count, size; 965 u_int32_t total; 966 967 /* addr[4] + count[2] + size[2] */ 968 addr = MEM_READ_4(sc, sc->table2_base + off); 969 info = MEM_READ_4(sc, sc->table2_base + off + 4); 970 971 count = info >> 16; 972 size = info & 0xffff; 973 total = count * size; 974 975 if (total > *len) { 976 *len = total; 977 return EINVAL; 978 } 979 980 *len = total; 981 ipw_read_mem_1(sc, addr, buf, total); 982 983 return 0; 984 } 985 986 static int 987 ipw_tx_init(struct ipw_softc *sc) 988 { 989 char *errmsg; 990 struct ipw_bd *bd; 991 struct ipw_soft_bd *sbd; 992 struct ipw_soft_hdr *shdr; 993 struct ipw_soft_buf *sbuf; 994 int error, i, nsegs; 995 996 /* Allocate transmission buffer descriptors */ 997 error = bus_dmamap_create(sc->sc_dmat, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, 998 BUS_DMA_NOWAIT, &sc->tbd_map); 999 if (error != 0) { 1000 errmsg = "could not create tbd dma map"; 1001 goto fail; 1002 } 1003 1004 error = bus_dmamem_alloc(sc->sc_dmat, IPW_TBD_SZ, PAGE_SIZE, 0, 1005 &sc->tbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 1006 if (error != 0) { 1007 errmsg = "could not allocate tbd dma memory"; 1008 goto fail; 1009 } 1010 1011 error = bus_dmamem_map(sc->sc_dmat, &sc->tbd_seg, nsegs, IPW_TBD_SZ, 1012 (caddr_t *)&sc->tbd_list, BUS_DMA_NOWAIT); 1013 if (error != 0) { 1014 errmsg = "could not map tbd dma memory"; 1015 goto fail; 1016 } 1017 1018 error = bus_dmamap_load(sc->sc_dmat, sc->tbd_map, sc->tbd_list, 1019 IPW_TBD_SZ, NULL, BUS_DMA_NOWAIT); 1020 if (error != 0) { 1021 errmsg = "could not load tbd dma memory"; 1022 goto fail; 1023 } 1024 1025 sc->stbd_list = malloc(IPW_NTBD * sizeof (struct ipw_soft_bd), 1026 M_DEVBUF, M_NOWAIT); 1027 if (sc->stbd_list == NULL) { 1028 errmsg = "could not allocate soft tbd"; 1029 error = ENOMEM; 1030 goto fail; 1031 } 1032 sbd = sc->stbd_list; 1033 bd = sc->tbd_list; 1034 for (i = 0; i < IPW_NTBD; i++, sbd++, bd++) { 1035 sbd->type = IPW_SBD_TYPE_NOASSOC; 1036 sbd->bd = bd; 1037 } 1038 1039 CSR_WRITE_4(sc, IPW_CSR_TX_BD_BASE, sc->tbd_map->dm_segs[0].ds_addr); 1040 CSR_WRITE_4(sc, IPW_CSR_TX_BD_SIZE, IPW_NTBD); 1041 CSR_WRITE_4(sc, IPW_CSR_TX_READ_INDEX, 0); 1042 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, 0); 1043 sc->txold = IPW_NTBD - 1; /* latest bd index ack'ed by firmware */ 1044 sc->txcur = 0; /* bd index to write to */ 1045 1046 /* Allocate a DMA-able command */ 1047 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_cmd), 1, 1048 sizeof (struct ipw_cmd), 0, BUS_DMA_NOWAIT, &sc->cmd_map); 1049 if (error != 0) { 1050 errmsg = "could not create cmd dma map"; 1051 goto fail; 1052 } 1053 1054 error = bus_dmamem_alloc(sc->sc_dmat, sizeof (struct ipw_cmd), 1055 PAGE_SIZE, 0, &sc->cmd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 1056 if (error != 0) { 1057 errmsg = "could not allocate cmd dma memory"; 1058 goto fail; 1059 } 1060 1061 error = bus_dmamem_map(sc->sc_dmat, &sc->cmd_seg, nsegs, 1062 sizeof (struct ipw_cmd), (caddr_t *)&sc->cmd, BUS_DMA_NOWAIT); 1063 if (error != 0) { 1064 errmsg = "could not map cmd dma memory"; 1065 goto fail; 1066 } 1067 1068 /* Allocate a pool of DMA-able headers */ 1069 sc->shdr_list = malloc(IPW_NDATA * sizeof (struct ipw_soft_hdr), 1070 M_DEVBUF, M_NOWAIT); 1071 if (sc->shdr_list == NULL) { 1072 errmsg = "could not allocate soft hdr"; 1073 error = ENOMEM; 1074 goto fail; 1075 } 1076 TAILQ_INIT(&sc->sc_free_shdr); 1077 for (i = 0, shdr = sc->shdr_list; i < IPW_NDATA; i++, shdr++) { 1078 error = bus_dmamap_create(sc->sc_dmat, 1079 sizeof (struct ipw_soft_hdr), 1, 1080 sizeof (struct ipw_soft_hdr), 0, BUS_DMA_NOWAIT, 1081 &shdr->map); 1082 if (error != 0) { 1083 errmsg = "could not create hdr dma map"; 1084 goto fail; 1085 } 1086 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 1087 } 1088 1089 /* Allocate a pool of DMA-able buffers */ 1090 sc->tx_sbuf_list = malloc(IPW_NDATA * sizeof (struct ipw_soft_buf), 1091 M_DEVBUF, M_NOWAIT); 1092 if (sc->tx_sbuf_list == NULL) { 1093 errmsg = "could not allocate soft txbuf"; 1094 error = ENOMEM; 1095 goto fail; 1096 } 1097 TAILQ_INIT(&sc->sc_free_sbuf); 1098 for (i = 0, sbuf = sc->tx_sbuf_list; i < IPW_NDATA; i++, sbuf++) { 1099 error = bus_dmamap_create(sc->sc_dmat, IPW_NDATA * MCLBYTES, 1100 IPW_NDATA, MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 1101 if (error != 0) { 1102 errmsg = "could not create txbuf dma map"; 1103 goto fail; 1104 } 1105 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 1106 } 1107 1108 return 0; 1109 1110 fail: aprint_error("%s: %s\n", sc->sc_dev.dv_xname, errmsg); 1111 ipw_tx_stop(sc); 1112 1113 return error; 1114 } 1115 1116 static void 1117 ipw_tx_stop(struct ipw_softc *sc) 1118 { 1119 struct ipw_soft_hdr *shdr; 1120 struct ipw_soft_buf *sbuf; 1121 int i; 1122 1123 if (sc->tbd_map != NULL) { 1124 if (sc->tbd_list != NULL) { 1125 bus_dmamap_unload(sc->sc_dmat, sc->tbd_map); 1126 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->tbd_list, 1127 IPW_TBD_SZ); 1128 bus_dmamem_free(sc->sc_dmat, &sc->tbd_seg, 1); 1129 sc->tbd_list = NULL; 1130 } 1131 bus_dmamap_destroy(sc->sc_dmat, sc->tbd_map); 1132 sc->tbd_map = NULL; 1133 } 1134 1135 if (sc->stbd_list != NULL) { 1136 for (i = 0; i < IPW_NTBD; i++) 1137 ipw_release_sbd(sc, &sc->stbd_list[i]); 1138 free(sc->stbd_list, M_DEVBUF); 1139 sc->stbd_list = NULL; 1140 } 1141 1142 if (sc->cmd_map != NULL) { 1143 if (sc->cmd != NULL) { 1144 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->cmd, 1145 sizeof (struct ipw_cmd)); 1146 bus_dmamem_free(sc->sc_dmat, &sc->cmd_seg, 1); 1147 sc->cmd = NULL; 1148 } 1149 bus_dmamap_destroy(sc->sc_dmat, sc->cmd_map); 1150 sc->cmd_map = NULL; 1151 } 1152 1153 if (sc->shdr_list != NULL) { 1154 TAILQ_FOREACH(shdr, &sc->sc_free_shdr, next) 1155 bus_dmamap_destroy(sc->sc_dmat, shdr->map); 1156 free(sc->shdr_list, M_DEVBUF); 1157 sc->shdr_list = NULL; 1158 } 1159 1160 1161 if (sc->tx_sbuf_list != NULL) { 1162 TAILQ_FOREACH(sbuf, &sc->sc_free_sbuf, next) 1163 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 1164 free(sc->tx_sbuf_list, M_DEVBUF); 1165 sc->tx_sbuf_list = NULL; 1166 } 1167 } 1168 1169 static int 1170 ipw_rx_init(struct ipw_softc *sc) 1171 { 1172 char *errmsg; 1173 struct ipw_bd *bd; 1174 struct ipw_soft_bd *sbd; 1175 struct ipw_soft_buf *sbuf; 1176 int error, i, nsegs; 1177 1178 /* Allocate reception buffer descriptors */ 1179 error = bus_dmamap_create(sc->sc_dmat, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, 1180 BUS_DMA_NOWAIT, &sc->rbd_map); 1181 if (error != 0) { 1182 errmsg = "could not create rbd dma map"; 1183 goto fail; 1184 } 1185 1186 error = bus_dmamem_alloc(sc->sc_dmat, IPW_RBD_SZ, PAGE_SIZE, 0, 1187 &sc->rbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 1188 if (error != 0) { 1189 errmsg = "could not allocate rbd dma memory"; 1190 goto fail; 1191 } 1192 1193 error = bus_dmamem_map(sc->sc_dmat, &sc->rbd_seg, nsegs, IPW_RBD_SZ, 1194 (caddr_t *)&sc->rbd_list, BUS_DMA_NOWAIT); 1195 if (error != 0) { 1196 errmsg = "could not map rbd dma memory"; 1197 goto fail; 1198 } 1199 1200 error = bus_dmamap_load(sc->sc_dmat, sc->rbd_map, sc->rbd_list, 1201 IPW_RBD_SZ, NULL, BUS_DMA_NOWAIT); 1202 if (error != 0) { 1203 errmsg = "could not load rbd dma memory"; 1204 goto fail; 1205 } 1206 1207 sc->srbd_list = malloc(IPW_NRBD * sizeof (struct ipw_soft_bd), 1208 M_DEVBUF, M_NOWAIT); 1209 if (sc->srbd_list == NULL) { 1210 errmsg = "could not allocate soft rbd"; 1211 error = ENOMEM; 1212 goto fail; 1213 } 1214 sbd = sc->srbd_list; 1215 bd = sc->rbd_list; 1216 for (i = 0; i < IPW_NRBD; i++, sbd++, bd++) { 1217 sbd->type = IPW_SBD_TYPE_NOASSOC; 1218 sbd->bd = bd; 1219 } 1220 1221 CSR_WRITE_4(sc, IPW_CSR_RX_BD_BASE, sc->rbd_map->dm_segs[0].ds_addr); 1222 CSR_WRITE_4(sc, IPW_CSR_RX_BD_SIZE, IPW_NRBD); 1223 CSR_WRITE_4(sc, IPW_CSR_RX_READ_INDEX, 0); 1224 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE_INDEX, IPW_NRBD - 1); 1225 sc->rxcur = IPW_NRBD - 1; /* latest bd index I've read */ 1226 1227 /* Allocate status descriptors */ 1228 error = bus_dmamap_create(sc->sc_dmat, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 1229 0, BUS_DMA_NOWAIT, &sc->status_map); 1230 if (error != 0) { 1231 errmsg = "could not create status dma map"; 1232 goto fail; 1233 } 1234 1235 error = bus_dmamem_alloc(sc->sc_dmat, IPW_STATUS_SZ, PAGE_SIZE, 0, 1236 &sc->status_seg, 1, &nsegs, BUS_DMA_NOWAIT); 1237 if (error != 0) { 1238 errmsg = "could not allocate status dma memory"; 1239 goto fail; 1240 } 1241 1242 error = bus_dmamem_map(sc->sc_dmat, &sc->status_seg, nsegs, 1243 IPW_STATUS_SZ, (caddr_t *)&sc->status_list, BUS_DMA_NOWAIT); 1244 if (error != 0) { 1245 errmsg = "could not map status dma memory"; 1246 goto fail; 1247 } 1248 1249 error = bus_dmamap_load(sc->sc_dmat, sc->status_map, sc->status_list, 1250 IPW_STATUS_SZ, NULL, BUS_DMA_NOWAIT); 1251 if (error != 0) { 1252 errmsg = "could not load status dma memory"; 1253 goto fail; 1254 } 1255 1256 CSR_WRITE_4(sc, IPW_CSR_RX_STATUS_BASE, 1257 sc->status_map->dm_segs[0].ds_addr); 1258 1259 sc->rx_sbuf_list = malloc(IPW_NRBD * sizeof (struct ipw_soft_buf), 1260 M_DEVBUF, M_NOWAIT); 1261 if (sc->rx_sbuf_list == NULL) { 1262 errmsg = "could not allocate soft rxbuf"; 1263 error = ENOMEM; 1264 goto fail; 1265 } 1266 1267 sbuf = sc->rx_sbuf_list; 1268 sbd = sc->srbd_list; 1269 for (i = 0; i < IPW_NRBD; i++, sbuf++, sbd++) { 1270 1271 MGETHDR(sbuf->m, M_DONTWAIT, MT_DATA); 1272 if (sbuf->m == NULL) { 1273 errmsg = "could not allocate rx mbuf"; 1274 error = ENOMEM; 1275 goto fail; 1276 } 1277 MCLGET(sbuf->m, M_DONTWAIT); 1278 if (!(sbuf->m->m_flags & M_EXT)) { 1279 m_freem(sbuf->m); 1280 errmsg = "could not allocate rx mbuf cluster"; 1281 error = ENOMEM; 1282 goto fail; 1283 } 1284 1285 error = bus_dmamap_create(sc->sc_dmat, IPW_NRBD * MCLBYTES, 1286 IPW_NRBD, MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 1287 if (error != 0) { 1288 m_freem(sbuf->m); 1289 errmsg = "could not create rxbuf dma map"; 1290 goto fail; 1291 } 1292 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, 1293 mtod(sbuf->m, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 1294 if (error != 0) { 1295 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 1296 m_freem(sbuf->m); 1297 errmsg = "could not map rxbuf dma memory"; 1298 goto fail; 1299 } 1300 sbd->type = IPW_SBD_TYPE_DATA; 1301 sbd->priv = sbuf; 1302 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 1303 sbd->bd->len = htole32(MCLBYTES); 1304 } 1305 1306 return 0; 1307 1308 fail: aprint_error("%s: %s\n", sc->sc_dev.dv_xname, errmsg); 1309 ipw_rx_stop(sc); 1310 1311 return error; 1312 } 1313 1314 static void 1315 ipw_rx_stop(struct ipw_softc *sc) 1316 { 1317 struct ipw_soft_bd *sbd; 1318 struct ipw_soft_buf *sbuf; 1319 int i; 1320 1321 if (sc->rbd_map != NULL) { 1322 if (sc->rbd_list != NULL) { 1323 bus_dmamap_unload(sc->sc_dmat, sc->rbd_map); 1324 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->rbd_list, 1325 IPW_RBD_SZ); 1326 bus_dmamem_free(sc->sc_dmat, &sc->rbd_seg, 1); 1327 sc->rbd_list = NULL; 1328 } 1329 bus_dmamap_destroy(sc->sc_dmat, sc->rbd_map); 1330 sc->rbd_map = NULL; 1331 } 1332 1333 if (sc->status_map != NULL) { 1334 if (sc->status_list != NULL) { 1335 bus_dmamap_unload(sc->sc_dmat, sc->status_map); 1336 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->status_list, 1337 IPW_STATUS_SZ); 1338 bus_dmamem_free(sc->sc_dmat, &sc->status_seg, 1); 1339 sc->status_list = NULL; 1340 } 1341 bus_dmamap_destroy(sc->sc_dmat, sc->status_map); 1342 sc->status_map = NULL; 1343 } 1344 1345 if (sc->srbd_list != NULL) { 1346 for (i = 0, sbd = sc->srbd_list; i < IPW_NRBD; i++, sbd++) { 1347 if (sbd->type == IPW_SBD_TYPE_NOASSOC) 1348 continue; 1349 1350 sbuf = sbd->priv; 1351 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1352 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 1353 m_freem(sbuf->m); 1354 } 1355 free(sc->srbd_list, M_DEVBUF); 1356 sc->srbd_list = NULL; 1357 } 1358 1359 if (sc->rx_sbuf_list != NULL) { 1360 free(sc->rx_sbuf_list, M_DEVBUF); 1361 sc->rx_sbuf_list = NULL; 1362 } 1363 } 1364 1365 static void 1366 ipw_reset(struct ipw_softc *sc) 1367 { 1368 struct ifnet *ifp = &sc->sc_ic.ic_if; 1369 int ntries; 1370 1371 ipw_stop(ifp, 1); 1372 1373 if (sc->flags & IPW_FLAG_FW_INITED) { 1374 ipw_cmd(sc, IPW_CMD_DISABLE_PHY, NULL, 0); 1375 ipw_cmd(sc, IPW_CMD_PREPARE_POWER_DOWN, NULL, 0); 1376 1377 sc->flags &= ~IPW_FLAG_FW_INITED; 1378 } 1379 1380 /* Disable interrupts */ 1381 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1382 1383 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1384 for (ntries = 0; ntries < 5; ntries++) { 1385 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1386 break; 1387 DELAY(10); 1388 } 1389 1390 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 1391 1392 ipw_rx_stop(sc); 1393 ipw_tx_stop(sc); 1394 1395 ifp->if_flags &= ~IFF_UP; 1396 } 1397 1398 static int 1399 ipw_clock_sync(struct ipw_softc *sc) 1400 { 1401 int ntries; 1402 u_int32_t r; 1403 1404 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 1405 for (ntries = 0; ntries < 1000; ntries++) { 1406 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_PRINCETON_RESET) 1407 break; 1408 DELAY(10); 1409 } 1410 if (ntries == 1000) 1411 return EIO; 1412 1413 CSR_WRITE_4(sc, IPW_CSR_CTL, IPW_CTL_INIT_DONE); 1414 for (ntries = 0; ntries < 1000; ntries++) { 1415 if ((r = CSR_READ_4(sc, IPW_CSR_CTL)) & IPW_CTL_CLOCK_READY) 1416 break; 1417 DELAY(200); 1418 } 1419 if (ntries == 1000) 1420 return EIO; 1421 1422 CSR_WRITE_4(sc, IPW_CSR_CTL, r | IPW_CTL_ALLOW_STANDBY); 1423 1424 return 0; 1425 } 1426 1427 static int 1428 ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size) 1429 { 1430 int ntries; 1431 1432 MEM_WRITE_2(sc, 0x220000, 0x0703); 1433 MEM_WRITE_2(sc, 0x220000, 0x0707); 1434 1435 MEM_WRITE_1(sc, 0x210014, 0x72); 1436 MEM_WRITE_1(sc, 0x210014, 0x72); 1437 1438 MEM_WRITE_1(sc, 0x210000, 0x40); 1439 MEM_WRITE_1(sc, 0x210000, 0x00); 1440 MEM_WRITE_1(sc, 0x210000, 0x40); 1441 1442 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1443 1444 MEM_WRITE_1(sc, 0x210000, 0x00); 1445 MEM_WRITE_1(sc, 0x210000, 0x00); 1446 MEM_WRITE_1(sc, 0x210000, 0x80); 1447 1448 MEM_WRITE_2(sc, 0x220000, 0x0703); 1449 MEM_WRITE_2(sc, 0x220000, 0x0707); 1450 1451 MEM_WRITE_1(sc, 0x210014, 0x72); 1452 MEM_WRITE_1(sc, 0x210014, 0x72); 1453 1454 MEM_WRITE_1(sc, 0x210000, 0x00); 1455 MEM_WRITE_1(sc, 0x210000, 0x80); 1456 1457 for (ntries = 0; ntries < 10; ntries++) { 1458 if (MEM_READ_1(sc, 0x210000) & 1) 1459 break; 1460 DELAY(10); 1461 } 1462 if (ntries == 10) 1463 return EIO; 1464 1465 return 0; 1466 } 1467 1468 /* set of macros to handle unaligned little endian data in firmware image */ 1469 #define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1470 #define GETLE16(p) ((p)[0] | (p)[1] << 8) 1471 static int 1472 ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size) 1473 { 1474 u_char *p, *end; 1475 u_int32_t addr; 1476 u_int16_t len; 1477 1478 p = fw; 1479 end = fw + size; 1480 while (p < end) { 1481 if (p + 6 > end) 1482 return EINVAL; 1483 1484 addr = GETLE32(p); 1485 p += 4; 1486 len = GETLE16(p); 1487 p += 2; 1488 1489 if (p + len > end) 1490 return EINVAL; 1491 1492 ipw_write_mem_1(sc, addr, p, len); 1493 p += len; 1494 } 1495 return 0; 1496 } 1497 1498 static int 1499 ipw_firmware_init(struct ipw_softc *sc, u_char *data) 1500 { 1501 struct ieee80211com *ic = &sc->sc_ic; 1502 struct ifnet *ifp = &ic->ic_if; 1503 struct ipw_fw_hdr hdr; 1504 u_int32_t r, len, fw_size, uc_size; 1505 u_char *fw, *uc; 1506 int error; 1507 1508 ipw_reset(sc); 1509 1510 if ((error = copyin(data, &hdr, sizeof hdr)) != 0) 1511 goto fail1; 1512 1513 fw_size = le32toh(hdr.fw_size); 1514 uc_size = le32toh(hdr.uc_size); 1515 data += sizeof hdr; 1516 1517 if ((fw = malloc(fw_size, M_DEVBUF, M_NOWAIT)) == NULL) { 1518 error = ENOMEM; 1519 goto fail1; 1520 } 1521 1522 if ((error = copyin(data, fw, fw_size)) != 0) 1523 goto fail2; 1524 1525 data += fw_size; 1526 1527 if ((uc = malloc(uc_size, M_DEVBUF, M_NOWAIT)) == NULL) { 1528 error = ENOMEM; 1529 goto fail2; 1530 } 1531 1532 if ((error = copyin(data, uc, uc_size)) != 0) 1533 goto fail3; 1534 1535 if ((error = ipw_clock_sync(sc)) != 0) { 1536 aprint_error("%s: clock synchronization failed\n", 1537 sc->sc_dev.dv_xname); 1538 goto fail3; 1539 } 1540 1541 MEM_WRITE_4(sc, 0x003000e0, 0x80000000); 1542 1543 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1544 1545 if ((error = ipw_load_ucode(sc, uc, uc_size)) != 0) { 1546 aprint_error("%s: could not load microcode\n", 1547 sc->sc_dev.dv_xname); 1548 goto fail3; 1549 } 1550 1551 MEM_WRITE_4(sc, 0x003000e0, 0); 1552 1553 if ((error = ipw_clock_sync(sc)) != 0) { 1554 aprint_error("%s: clock synchronization failed\n", 1555 sc->sc_dev.dv_xname); 1556 goto fail3; 1557 } 1558 1559 if ((error = ipw_load_firmware(sc, fw, fw_size))) { 1560 aprint_error("%s: could not load firmware\n", 1561 sc->sc_dev.dv_xname); 1562 goto fail3; 1563 } 1564 1565 ipw_zero_mem_4(sc, 0x0002f200, 196); 1566 ipw_zero_mem_4(sc, 0x0002f610, 8); 1567 ipw_zero_mem_4(sc, 0x0002fa00, 8); 1568 ipw_zero_mem_4(sc, 0x0002fc00, 4); 1569 ipw_zero_mem_4(sc, 0x0002ff80, 32); 1570 1571 if ((error = ipw_rx_init(sc)) != 0) { 1572 aprint_error("%s: could not initialize rx queue\n", 1573 sc->sc_dev.dv_xname); 1574 goto fail3; 1575 } 1576 1577 if ((error = ipw_tx_init(sc)) != 0) { 1578 aprint_error("%s: could not initialize tx queue\n", 1579 sc->sc_dev.dv_xname); 1580 goto fail3; 1581 } 1582 1583 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1584 IPW_IO_LED_OFF); 1585 1586 /* Enable interrupts */ 1587 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1588 1589 /* Let's go! */ 1590 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1591 1592 /* Wait at most 5 seconds for firmware initialization to complete */ 1593 if ((error = tsleep(sc, 0, "ipwinit", 5 * hz)) != 0) { 1594 aprint_error("%s: timeout waiting for firmware initialization " 1595 "to complete\n", sc->sc_dev.dv_xname); 1596 goto fail3; 1597 } 1598 1599 /* Firmware initialization completed */ 1600 sc->flags |= IPW_FLAG_FW_INITED; 1601 1602 free(uc, M_DEVBUF); 1603 free(fw, M_DEVBUF); 1604 1605 r = CSR_READ_4(sc, IPW_CSR_IO); 1606 CSR_WRITE_4(sc, IPW_CSR_IO, r | IPW_IO_GPIO1_MASK | IPW_IO_GPIO3_MASK); 1607 1608 /* Retrieve information tables base addresses */ 1609 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 1610 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 1611 1612 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 1613 1614 /* Retrieve adapter MAC address */ 1615 len = IEEE80211_ADDR_LEN; 1616 ipw_read_table2(sc, IPW_INFO_ADAPTER_MAC, ic->ic_myaddr, &len); 1617 1618 IEEE80211_ADDR_COPY(LLADDR(ifp->if_sadl), ic->ic_myaddr); 1619 1620 return 0; 1621 1622 fail3: free(uc, M_DEVBUF); 1623 fail2: free(fw, M_DEVBUF); 1624 fail1: ipw_reset(sc); 1625 1626 return error; 1627 } 1628 1629 static int 1630 ipw_config(struct ipw_softc *sc) 1631 { 1632 struct ieee80211com *ic = &sc->sc_ic; 1633 struct ifnet *ifp = &ic->ic_if; 1634 struct ipw_security security; 1635 struct ieee80211_wepkey *k; 1636 struct ipw_wep_key wepkey; 1637 struct ipw_scan_options options; 1638 struct ipw_configuration config; 1639 u_int32_t data; 1640 int error, i; 1641 1642 DPRINTF(("Setting adapter MAC to %s\n", ether_sprintf(ic->ic_myaddr))); 1643 IEEE80211_ADDR_COPY(LLADDR(ifp->if_sadl), ic->ic_myaddr); 1644 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 1645 IEEE80211_ADDR_LEN); 1646 if (error != 0) 1647 return error; 1648 1649 switch (ic->ic_opmode) { 1650 case IEEE80211_M_STA: 1651 case IEEE80211_M_HOSTAP: 1652 data = htole32(IPW_MODE_BSS); 1653 break; 1654 1655 case IEEE80211_M_IBSS: 1656 case IEEE80211_M_AHDEMO: 1657 data = htole32(IPW_MODE_IBSS); 1658 break; 1659 1660 case IEEE80211_M_MONITOR: 1661 data = htole32(IPW_MODE_MONITOR); 1662 break; 1663 } 1664 DPRINTF(("Setting adapter mode to %u\n", data)); 1665 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 1666 if (error != 0) 1667 return error; 1668 1669 if (ic->ic_opmode == IEEE80211_M_IBSS || 1670 ic->ic_opmode == IEEE80211_M_MONITOR) { 1671 data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); 1672 DPRINTF(("Setting adapter channel to %u\n", data)); 1673 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 1674 if (error != 0) 1675 return error; 1676 } 1677 1678 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 1679 IPW_CFG_PREAMBLE_LEN | IPW_CFG_802_1x_ENABLE); 1680 if (ic->ic_opmode == IEEE80211_M_IBSS) 1681 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 1682 if (ifp->if_flags & IFF_PROMISC) 1683 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 1684 config.channels = htole32(0x3fff); /* channels 1-14 */ 1685 config.ibss_chan = htole32(0x7ff); 1686 DPRINTF(("Setting adapter configuration 0x%08x\n", config.flags)); 1687 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 1688 if (error != 0) 1689 return error; 1690 1691 data = htole32(0x3); /* 1, 2 */ 1692 DPRINTF(("Setting adapter basic tx rates to 0x%x\n", data)); 1693 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 1694 if (error != 0) 1695 return error; 1696 1697 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 1698 DPRINTF(("Setting adapter tx rates to 0x%x\n", data)); 1699 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 1700 if (error != 0) 1701 return error; 1702 1703 data = htole32(IPW_POWER_MODE_CAM); 1704 DPRINTF(("Setting adapter power mode to %u\n", data)); 1705 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 1706 if (error != 0) 1707 return error; 1708 1709 if (ic->ic_opmode == IEEE80211_M_IBSS) { 1710 data = htole32(ic->ic_txpower); 1711 DPRINTF(("Setting adapter tx power index to %u\n", data)); 1712 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 1713 sizeof data); 1714 if (error != 0) 1715 return error; 1716 } 1717 1718 data = htole32(ic->ic_rtsthreshold); 1719 DPRINTF(("Setting adapter RTS threshold to %u\n", data)); 1720 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 1721 if (error != 0) 1722 return error; 1723 1724 data = htole32(ic->ic_fragthreshold); 1725 DPRINTF(("Setting adapter frag threshold to %u\n", data)); 1726 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 1727 if (error != 0) 1728 return error; 1729 1730 #ifdef IPW_DEBUG 1731 if (ipw_debug > 0) { 1732 printf("Setting adapter ESSID to "); 1733 ieee80211_print_essid(ic->ic_des_essid, ic->ic_des_esslen); 1734 printf("\n"); 1735 } 1736 #endif 1737 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ic->ic_des_essid, 1738 ic->ic_des_esslen); 1739 if (error != 0) 1740 return error; 1741 1742 /* no mandatory BSSID */ 1743 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 1744 if (error != 0) 1745 return error; 1746 1747 if (ic->ic_flags & IEEE80211_F_DESBSSID) { 1748 DPRINTF(("Setting adapter desired BSSID to %s\n", 1749 ether_sprintf(ic->ic_des_bssid))); 1750 error = ipw_cmd(sc, IPW_CMD_SET_DESIRED_BSSID, 1751 ic->ic_des_bssid, IEEE80211_ADDR_LEN); 1752 if (error != 0) 1753 return error; 1754 } 1755 1756 security.authmode = IPW_AUTH_OPEN; 1757 security.ciphers = htole32(IPW_CIPHER_NONE); 1758 security.version = htole16(0); 1759 security.replay_counters_number = 0; 1760 security.unicast_using_group = 0; 1761 DPRINTF(("Setting adapter authmode to %u\n", security.authmode)); 1762 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 1763 sizeof security); 1764 if (error != 0) 1765 return error; 1766 1767 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 1768 k = ic->ic_nw_keys; 1769 for (i = 0; i < IEEE80211_WEP_NKID; i++, k++) { 1770 if (k->wk_len == 0) 1771 continue; 1772 1773 wepkey.idx = i; 1774 wepkey.len = k->wk_len; 1775 bzero(wepkey.key, sizeof wepkey.key); 1776 bcopy(k->wk_key, wepkey.key, k->wk_len); 1777 DPRINTF(("Setting wep key index %d len %d\n", 1778 wepkey.idx, wepkey.len)); 1779 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY, &wepkey, 1780 sizeof wepkey); 1781 if (error != 0) 1782 return error; 1783 } 1784 1785 data = htole32(ic->ic_wep_txkey); 1786 DPRINTF(("Setting adapter tx key index to %u\n", data)); 1787 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY_INDEX, &data, 1788 sizeof data); 1789 if (error != 0) 1790 return error; 1791 } 1792 1793 data = htole32((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) ? 0x8 : 0); 1794 DPRINTF(("Setting adapter wep flags to 0x%x\n", data)); 1795 error = ipw_cmd(sc, IPW_CMD_SET_WEP_FLAGS, &data, sizeof data); 1796 if (error != 0) 1797 return error; 1798 1799 if (ic->ic_opmode == IEEE80211_M_IBSS || 1800 ic->ic_opmode == IEEE80211_M_HOSTAP) { 1801 data = htole32(ic->ic_lintval); 1802 DPRINTF(("Setting adapter beacon interval to %u\n", data)); 1803 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 1804 sizeof data); 1805 if (error != 0) 1806 return error; 1807 } 1808 1809 options.flags = htole32(0); 1810 options.channels = htole32(0x3fff); /* scan channels 1-14 */ 1811 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &options, sizeof options); 1812 if (error != 0) 1813 return error; 1814 1815 /* finally, enable adapter (start scanning for an access point) */ 1816 DPRINTF(("Enabling adapter\n")); 1817 error = ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1818 if (error != 0) 1819 return error; 1820 1821 return 0; 1822 } 1823 1824 static int 1825 ipw_init(struct ifnet *ifp) 1826 { 1827 struct ipw_softc *sc = ifp->if_softc; 1828 struct ieee80211com *ic = &sc->sc_ic; 1829 1830 /* exit immediately if firmware has not been ioctl'd */ 1831 if (!(sc->flags & IPW_FLAG_FW_INITED)) { 1832 ifp->if_flags &= ~IFF_UP; 1833 return EIO; 1834 } 1835 1836 ipw_stop(ifp, 0); 1837 1838 if (ipw_config(sc) != 0) { 1839 aprint_error("%s: device configuration failed\n", 1840 sc->sc_dev.dv_xname); 1841 goto fail; 1842 } 1843 1844 ifp->if_flags &= ~IFF_OACTIVE; 1845 ifp->if_flags |= IFF_RUNNING; 1846 1847 ic->ic_bss->ni_chan = ic->ic_channels; 1848 1849 return 0; 1850 1851 fail: ipw_stop(ifp, 0); 1852 1853 return EIO; 1854 } 1855 1856 static void 1857 ipw_stop(struct ifnet *ifp, int disable) 1858 { 1859 struct ipw_softc *sc = ifp->if_softc; 1860 struct ieee80211com *ic = &sc->sc_ic; 1861 1862 if (ifp->if_flags & IFF_RUNNING) { 1863 DPRINTF(("Disabling adapter\n")); 1864 ipw_cmd(sc, IPW_CMD_DISABLE, NULL, 0); 1865 } 1866 1867 ifp->if_timer = 0; 1868 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1869 1870 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1871 } 1872 1873 static void 1874 ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, u_int8_t *datap, 1875 bus_size_t count) 1876 { 1877 for (; count > 0; offset++, datap++, count--) { 1878 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 1879 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 1880 } 1881 } 1882 1883 static void 1884 ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, u_int8_t *datap, 1885 bus_size_t count) 1886 { 1887 for (; count > 0; offset++, datap++, count--) { 1888 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 1889 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 1890 } 1891 } 1892 1893 static void 1894 ipw_zero_mem_4(struct ipw_softc *sc, bus_size_t offset, bus_size_t count) 1895 { 1896 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, offset); 1897 while (count-- > 0) 1898 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_DATA, 0); 1899 } 1900 1901 #ifdef IPW_AS_LKM 1902 1903 #include <sys/lkm.h> 1904 #include <lkm/dev/pcilkm/pcilkm.h> 1905 1906 MOD_MISC("ipw"); 1907 1908 PCILKM_DECLARE(ipw, DV_DULL, NULL); 1909 1910 #endif 1911
Indexes created Tue Sep 30 11:09:46 GMT 2025