if_ipw.c revision 1.10
1 /* $NetBSD: if_ipw.c,v 1.10 2005/01/19 06:00:22 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 5 * Damien Bergamini <damien.bergamini (at) free.fr>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: if_ipw.c,v 1.10 2005/01/19 06:00:22 dyoung Exp $"); 32 33 /*- 34 * Intel(R) PRO/Wireless 2100 MiniPCI driver 35 * http://www.intel.com/products/mobiletechnology/prowireless.htm 36 */ 37 38 #include "bpfilter.h" 39 40 #include <sys/param.h> 41 #include <sys/sockio.h> 42 #include <sys/sysctl.h> 43 #include <sys/mbuf.h> 44 #include <sys/kernel.h> 45 #include <sys/socket.h> 46 #include <sys/systm.h> 47 #include <sys/malloc.h> 48 #include <sys/conf.h> 49 50 #include <machine/bus.h> 51 #include <machine/endian.h> 52 #include <machine/intr.h> 53 54 #include <dev/pci/pcireg.h> 55 #include <dev/pci/pcivar.h> 56 #include <dev/pci/pcidevs.h> 57 58 #if NBPFILTER > 0 59 #include <net/bpf.h> 60 #endif 61 #include <net/if.h> 62 #include <net/if_arp.h> 63 #include <net/if_dl.h> 64 #include <net/if_ether.h> 65 #include <net/if_media.h> 66 #include <net/if_types.h> 67 68 #include <net80211/ieee80211_var.h> 69 #include <net80211/ieee80211_radiotap.h> 70 71 #include <netinet/in.h> 72 #include <netinet/in_systm.h> 73 #include <netinet/in_var.h> 74 #include <netinet/ip.h> 75 76 #include <dev/pci/if_ipwreg.h> 77 #include <dev/pci/if_ipwvar.h> 78 79 static int ipw_match(struct device *, struct cfdata *, void *); 80 static void ipw_attach(struct device *, struct device *, void *); 81 static int ipw_detach(struct device *, int); 82 static int ipw_media_change(struct ifnet *); 83 static int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 84 static void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 85 static void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 86 static void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 87 struct ipw_soft_bd *, struct ipw_soft_buf *); 88 static void ipw_notification_intr(struct ipw_softc *, struct ipw_soft_buf *); 89 static void ipw_rx_intr(struct ipw_softc *); 90 static void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 91 static void ipw_tx_intr(struct ipw_softc *); 92 static int ipw_intr(void *); 93 static int ipw_cmd(struct ipw_softc *, u_int32_t, void *, u_int32_t); 94 static int ipw_tx_start(struct ifnet *, struct mbuf *, struct ieee80211_node *); 95 static void ipw_start(struct ifnet *); 96 static void ipw_watchdog(struct ifnet *); 97 static int ipw_get_table1(struct ipw_softc *, u_int32_t *); 98 static int ipw_get_radio(struct ipw_softc *, int *); 99 static int ipw_ioctl(struct ifnet *, u_long, caddr_t); 100 static u_int32_t ipw_read_table1(struct ipw_softc *, u_int32_t); 101 static void ipw_write_table1(struct ipw_softc *, u_int32_t, u_int32_t); 102 static int ipw_read_table2(struct ipw_softc *, u_int32_t, void *, u_int32_t *); 103 static int ipw_tx_init(struct ipw_softc *); 104 static void ipw_tx_stop(struct ipw_softc *); 105 static int ipw_rx_init(struct ipw_softc *); 106 static void ipw_rx_stop(struct ipw_softc *); 107 static void ipw_reset(struct ipw_softc *); 108 static int ipw_clock_sync(struct ipw_softc *); 109 static int ipw_load_ucode(struct ipw_softc *, u_char *, int); 110 static int ipw_load_firmware(struct ipw_softc *, u_char *, int); 111 static int ipw_firmware_init(struct ipw_softc *, u_char *); 112 static int ipw_config(struct ipw_softc *); 113 static int ipw_init(struct ifnet *); 114 static void ipw_stop(struct ifnet *, int); 115 static void ipw_read_mem_1(struct ipw_softc *, bus_size_t, u_int8_t *, 116 bus_size_t); 117 static void ipw_write_mem_1(struct ipw_softc *, bus_size_t, u_int8_t *, 118 bus_size_t); 119 static void ipw_zero_mem_4(struct ipw_softc *, bus_size_t, bus_size_t); 120 121 static inline u_int8_t MEM_READ_1(struct ipw_softc *sc, u_int32_t addr) 122 { 123 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 124 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); 125 } 126 127 static inline u_int16_t MEM_READ_2(struct ipw_softc *sc, u_int32_t addr) 128 { 129 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 130 return CSR_READ_2(sc, IPW_CSR_INDIRECT_DATA); 131 } 132 133 static inline u_int32_t MEM_READ_4(struct ipw_softc *sc, u_int32_t addr) 134 { 135 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 136 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); 137 } 138 139 #ifdef IPW_DEBUG 140 #define DPRINTF(x) if (ipw_debug > 0) printf x 141 #define DPRINTFN(n, x) if (ipw_debug >= (n)) printf x 142 int ipw_debug = 0; 143 #else 144 #define DPRINTF(x) 145 #define DPRINTFN(n, x) 146 #endif 147 148 CFATTACH_DECL(ipw, sizeof (struct ipw_softc), ipw_match, ipw_attach, 149 ipw_detach, NULL); 150 151 static int 152 ipw_match(struct device *parent, struct cfdata *match, void *aux) 153 { 154 struct pci_attach_args *pa = aux; 155 156 if (PCI_VENDOR (pa->pa_id) == PCI_VENDOR_INTEL && 157 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_PRO_WL_2100) 158 return 1; 159 160 return 0; 161 } 162 163 /* Base Address Register */ 164 #define IPW_PCI_BAR0 0x10 165 166 static void 167 ipw_attach(struct device *parent, struct device *self, void *aux) 168 { 169 struct ipw_softc *sc = (struct ipw_softc *)self; 170 struct ieee80211com *ic = &sc->sc_ic; 171 struct ifnet *ifp = &ic->ic_if; 172 struct ieee80211_rateset *rs; 173 struct pci_attach_args *pa = aux; 174 const char *intrstr; 175 char devinfo[256]; 176 bus_space_tag_t memt; 177 bus_space_handle_t memh; 178 bus_addr_t base; 179 pci_intr_handle_t ih; 180 u_int32_t data; 181 int i, revision, error; 182 183 sc->sc_pct = pa->pa_pc; 184 185 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof devinfo); 186 revision = PCI_REVISION(pa->pa_class); 187 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, revision); 188 189 /* enable bus-mastering */ 190 data = pci_conf_read(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG); 191 data |= PCI_COMMAND_MASTER_ENABLE; 192 pci_conf_write(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG, data); 193 194 /* map the register window */ 195 error = pci_mapreg_map(pa, IPW_PCI_BAR0, PCI_MAPREG_TYPE_MEM | 196 PCI_MAPREG_MEM_TYPE_32BIT, 0, &memt, &memh, &base, &sc->sc_sz); 197 if (error != 0) { 198 aprint_error("%s: could not map memory space\n", 199 sc->sc_dev.dv_xname); 200 return; 201 } 202 203 sc->sc_st = memt; 204 sc->sc_sh = memh; 205 sc->sc_dmat = pa->pa_dmat; 206 207 /* disable interrupts */ 208 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 209 210 if (pci_intr_map(pa, &ih) != 0) { 211 aprint_error("%s: could not map interrupt\n", 212 sc->sc_dev.dv_xname); 213 return; 214 } 215 216 intrstr = pci_intr_string(sc->sc_pct, ih); 217 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, ipw_intr, sc); 218 if (sc->sc_ih == NULL) { 219 aprint_error("%s: could not establish interrupt", 220 sc->sc_dev.dv_xname); 221 if (intrstr != NULL) 222 aprint_error(" at %s", intrstr); 223 aprint_error("\n"); 224 return; 225 } 226 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 227 228 ic->ic_phytype = IEEE80211_T_DS; 229 ic->ic_opmode = IEEE80211_M_STA; 230 ic->ic_state = IEEE80211_S_INIT; 231 232 /* set device capabilities */ 233 ic->ic_caps = IEEE80211_C_IBSS | IEEE80211_C_MONITOR | 234 IEEE80211_C_PMGT | IEEE80211_C_TXPMGT | IEEE80211_C_WEP; 235 236 /* set supported 11.b rates */ 237 rs = &ic->ic_sup_rates[IEEE80211_MODE_11B]; 238 rs->rs_nrates = 4; 239 rs->rs_rates[0] = 2; /* 1Mbps */ 240 rs->rs_rates[1] = 4; /* 2Mbps */ 241 rs->rs_rates[2] = 11; /* 5.5Mbps */ 242 rs->rs_rates[3] = 22; /* 11Mbps */ 243 244 /* set supported 11.b channels (1 through 14) */ 245 for (i = 1; i <= 14; i++) { 246 ic->ic_channels[i].ic_freq = 247 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 248 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 249 } 250 251 ic->ic_ibss_chan = &ic->ic_channels[0]; 252 253 ifp->if_softc = sc; 254 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 255 ifp->if_init = ipw_init; 256 ifp->if_stop = ipw_stop; 257 ifp->if_ioctl = ipw_ioctl; 258 ifp->if_start = ipw_start; 259 ifp->if_watchdog = ipw_watchdog; 260 IFQ_SET_READY(&ifp->if_snd); 261 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 262 263 if_attach(ifp); 264 ieee80211_ifattach(ifp); 265 /* override state transition machine */ 266 sc->sc_newstate = ic->ic_newstate; 267 ic->ic_newstate = ipw_newstate; 268 269 ieee80211_media_init(ifp, ipw_media_change, ieee80211_media_status); 270 271 #if NBPFILTER > 0 272 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 273 sizeof (struct ieee80211_frame) + 64, &sc->sc_drvbpf); 274 275 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 276 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 277 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 278 279 sc->sc_txtap_len = sizeof sc->sc_txtapu; 280 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 281 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 282 #endif 283 } 284 285 static int 286 ipw_detach(struct device* self, int flags) 287 { 288 struct ipw_softc *sc = (struct ipw_softc *)self; 289 struct ifnet *ifp = &sc->sc_ic.ic_if; 290 291 ipw_reset(sc); 292 293 #if NBPFILTER > 0 294 bpfdetach(ifp); 295 #endif 296 ieee80211_ifdetach(ifp); 297 if_detach(ifp); 298 299 if (sc->sc_ih != NULL) { 300 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 301 sc->sc_ih = NULL; 302 } 303 304 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 305 306 return 0; 307 } 308 309 static int 310 ipw_media_change(struct ifnet *ifp) 311 { 312 int error; 313 314 error = ieee80211_media_change(ifp); 315 if (error != ENETRESET) 316 return error; 317 318 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 319 ipw_init(ifp); 320 321 return 0; 322 } 323 324 static int 325 ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 326 { 327 struct ifnet *ifp = &ic->ic_if; 328 struct ipw_softc *sc = ifp->if_softc; 329 struct ieee80211_node *ni = ic->ic_bss; 330 u_int32_t val, len; 331 332 switch (nstate) { 333 case IEEE80211_S_INIT: 334 break; 335 336 case IEEE80211_S_RUN: 337 len = IEEE80211_NWID_LEN; 338 ipw_read_table2(sc, IPW_INFO_CURRENT_SSID, ni->ni_essid, &len); 339 ni->ni_esslen = len; 340 341 val = ipw_read_table1(sc, IPW_INFO_CURRENT_CHANNEL); 342 ni->ni_chan = &ic->ic_channels[val]; 343 344 DELAY(100); /* firmware needs a short delay here */ 345 346 len = IEEE80211_ADDR_LEN; 347 ipw_read_table2(sc, IPW_INFO_CURRENT_BSSID, ni->ni_bssid, &len); 348 break; 349 350 case IEEE80211_S_SCAN: 351 case IEEE80211_S_AUTH: 352 case IEEE80211_S_ASSOC: 353 break; 354 } 355 356 ic->ic_state = nstate; 357 return 0; 358 } 359 360 static void 361 ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 362 { 363 struct ipw_cmd *cmd; 364 365 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof (struct ipw_cmd), 366 BUS_DMASYNC_POSTREAD); 367 368 cmd = mtod(sbuf->m, struct ipw_cmd *); 369 370 DPRINTFN(2, ("RX!CMD!%u!%u!%u!%u!%u\n", 371 le32toh(cmd->type), le32toh(cmd->subtype), le32toh(cmd->seq), 372 le32toh(cmd->len), le32toh(cmd->status))); 373 374 /* 375 * Wake up processes waiting for command ack. In the case of the 376 * IPW_CMD_DISABLE command, wake up the process only when the adapter 377 * enters the IPW_STATE_DISABLED state. This is notified in 378 * ipw_newstate_intr(). 379 */ 380 if (le32toh(cmd->type) != IPW_CMD_DISABLE) 381 wakeup(sc->cmd); 382 } 383 384 static void 385 ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 386 { 387 struct ieee80211com *ic = &sc->sc_ic; 388 u_int32_t state; 389 390 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof state, 391 BUS_DMASYNC_POSTREAD); 392 393 state = le32toh(*mtod(sbuf->m, u_int32_t *)); 394 395 DPRINTFN(2, ("RX!NEWSTATE!%u\n", state)); 396 397 switch (state) { 398 case IPW_STATE_ASSOCIATED: 399 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 400 break; 401 402 case IPW_STATE_SCANNING: 403 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 404 break; 405 406 case IPW_STATE_ASSOCIATION_LOST: 407 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 408 break; 409 410 case IPW_STATE_DISABLED: 411 wakeup(sc->cmd); 412 break; 413 414 case IPW_STATE_RADIO_DISABLED: 415 /* XXX should turn the interface down */ 416 break; 417 } 418 } 419 420 static void 421 ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 422 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 423 { 424 struct ieee80211com *ic = &sc->sc_ic; 425 struct ifnet *ifp = &ic->ic_if; 426 struct mbuf *m; 427 struct ieee80211_frame *wh; 428 struct ieee80211_node *ni; 429 int error; 430 431 DPRINTFN(5, ("RX!DATA!%u!%u\n", le32toh(status->len), status->rssi)); 432 433 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, le32toh(status->len), 434 BUS_DMASYNC_POSTREAD); 435 436 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 437 438 /* Finalize mbuf */ 439 m = sbuf->m; 440 m->m_pkthdr.rcvif = ifp; 441 m->m_pkthdr.len = m->m_len = le32toh(status->len); 442 443 #if NBPFILTER > 0 444 if (sc->sc_drvbpf != NULL) { 445 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 446 447 tap->wr_flags = 0; 448 tap->wr_antsignal = status->rssi; 449 tap->wr_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 450 tap->wr_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 451 452 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 453 } 454 #endif 455 456 wh = mtod(m, struct ieee80211_frame *); 457 458 ni = ieee80211_find_rxnode(ic, wh); 459 460 /* Send it up to the upper layer */ 461 ieee80211_input(ifp, m, ni, status->rssi, 0/*rstamp*/); 462 463 ieee80211_release_node(ic, ni); 464 465 MGETHDR(m, M_DONTWAIT, MT_DATA); 466 if (m == NULL) { 467 aprint_error("%s: could not allocate rx mbuf\n", 468 sc->sc_dev.dv_xname); 469 return; 470 } 471 MCLGET(m, M_DONTWAIT); 472 if (!(m->m_flags & M_EXT)) { 473 m_freem(m); 474 aprint_error("%s: could not allocate rx mbuf cluster\n", 475 sc->sc_dev.dv_xname); 476 return; 477 } 478 479 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, mtod(m, void *), 480 MCLBYTES, NULL, BUS_DMA_NOWAIT); 481 if (error != 0) { 482 aprint_error("%s: could not map rxbuf dma memory\n", 483 sc->sc_dev.dv_xname); 484 m_freem(m); 485 return; 486 } 487 488 sbuf->m = m; 489 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 490 } 491 492 static void 493 ipw_notification_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 494 { 495 DPRINTFN(2, ("RX!NOTIFICATION\n")); 496 } 497 498 static void 499 ipw_rx_intr(struct ipw_softc *sc) 500 { 501 struct ipw_status *status; 502 struct ipw_soft_bd *sbd; 503 struct ipw_soft_buf *sbuf; 504 u_int32_t r, i; 505 506 r = CSR_READ_4(sc, IPW_CSR_RX_READ_INDEX); 507 508 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 509 510 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 511 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 512 BUS_DMASYNC_POSTREAD); 513 514 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 515 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 516 BUS_DMASYNC_POSTREAD); 517 518 status = &sc->status_list[i]; 519 sbd = &sc->srbd_list[i]; 520 sbuf = sbd->priv; 521 522 switch (le16toh(status->code) & 0xf) { 523 case IPW_STATUS_CODE_COMMAND: 524 ipw_command_intr(sc, sbuf); 525 break; 526 527 case IPW_STATUS_CODE_NEWSTATE: 528 ipw_newstate_intr(sc, sbuf); 529 break; 530 531 case IPW_STATUS_CODE_DATA_802_3: 532 case IPW_STATUS_CODE_DATA_802_11: 533 ipw_data_intr(sc, status, sbd, sbuf); 534 break; 535 536 case IPW_STATUS_CODE_NOTIFICATION: 537 ipw_notification_intr(sc, sbuf); 538 break; 539 540 default: 541 aprint_debug("%s: unknown status code %u\n", 542 sc->sc_dev.dv_xname, le16toh(status->code)); 543 } 544 sbd->bd->flags = 0; 545 546 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 547 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 548 BUS_DMASYNC_PREWRITE); 549 } 550 551 /* Tell the firmware what we have processed */ 552 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 553 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE_INDEX, sc->rxcur); 554 } 555 556 static void 557 ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 558 { 559 struct ieee80211com *ic; 560 struct ipw_soft_hdr *shdr; 561 struct ipw_soft_buf *sbuf; 562 563 switch (sbd->type) { 564 case IPW_SBD_TYPE_COMMAND: 565 bus_dmamap_unload(sc->sc_dmat, sc->cmd_map); 566 break; 567 568 case IPW_SBD_TYPE_HEADER: 569 shdr = sbd->priv; 570 bus_dmamap_unload(sc->sc_dmat, shdr->map); 571 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 572 break; 573 574 case IPW_SBD_TYPE_DATA: 575 ic = &sc->sc_ic; 576 sbuf = sbd->priv; 577 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 578 m_freem(sbuf->m); 579 if (sbuf->ni != NULL) 580 ieee80211_release_node(ic, sbuf->ni); 581 /* kill watchdog timer */ 582 sc->sc_tx_timer = 0; 583 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 584 break; 585 } 586 ++sc->txfree; 587 sbd->type = IPW_SBD_TYPE_NOASSOC; 588 } 589 590 static void 591 ipw_tx_intr(struct ipw_softc *sc) 592 { 593 struct ifnet *ifp = &sc->sc_ic.ic_if; 594 u_int32_t r, i; 595 596 r = CSR_READ_4(sc, IPW_CSR_TX_READ_INDEX); 597 598 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) 599 ipw_release_sbd(sc, &sc->stbd_list[i]); 600 601 /* Remember what the firmware has processed */ 602 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 603 604 /* Call start() since some buffer descriptors have been released */ 605 ifp->if_flags &= ~IFF_OACTIVE; 606 (*ifp->if_start)(ifp); 607 } 608 609 static int 610 ipw_intr(void *arg) 611 { 612 struct ipw_softc *sc = arg; 613 u_int32_t r; 614 615 if ((r = CSR_READ_4(sc, IPW_CSR_INTR)) == 0) 616 return 0; 617 618 /* Disable interrupts */ 619 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 620 621 DPRINTFN(8, ("INTR!0x%08x\n", r)); 622 623 if (r & IPW_INTR_RX_TRANSFER) 624 ipw_rx_intr(sc); 625 626 if (r & IPW_INTR_TX_TRANSFER) 627 ipw_tx_intr(sc); 628 629 if (r & IPW_INTR_FW_INIT_DONE) { 630 if (!(r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR))) 631 wakeup(sc); 632 } 633 634 /* Acknowledge interrupts */ 635 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 636 637 /* Re-enable interrupts */ 638 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 639 640 return 0; 641 } 642 643 static int 644 ipw_cmd(struct ipw_softc *sc, u_int32_t type, void *data, u_int32_t len) 645 { 646 struct ipw_soft_bd *sbd; 647 int error; 648 649 #ifdef DIAGNOSTIC 650 KASSERT(sc->txfree != 0); 651 #endif /* DIAGNOSTIC */ 652 653 sbd = &sc->stbd_list[sc->txcur]; 654 655 error = bus_dmamap_load(sc->sc_dmat, sc->cmd_map, sc->cmd, 656 sizeof (struct ipw_cmd), NULL, BUS_DMA_NOWAIT); 657 if (error != 0) { 658 aprint_error("%s: could not map cmd dma memory\n", 659 sc->sc_dev.dv_xname); 660 return error; 661 } 662 663 sc->cmd->type = htole32(type); 664 sc->cmd->subtype = htole32(0); 665 sc->cmd->len = htole32(len); 666 sc->cmd->seq = htole32(0); 667 if (data != NULL) 668 bcopy(data, sc->cmd->data, len); 669 670 sbd->type = IPW_SBD_TYPE_COMMAND; 671 sbd->bd->physaddr = htole32(sc->cmd_map->dm_segs[0].ds_addr); 672 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 673 sbd->bd->nfrag = 1; 674 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 675 IPW_BD_FLAG_TX_LAST_FRAGMENT; 676 677 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 0, sizeof (struct ipw_cmd), 678 BUS_DMASYNC_PREWRITE); 679 680 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 681 sc->txcur * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 682 BUS_DMASYNC_PREWRITE); 683 684 --sc->txfree; 685 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 686 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, sc->txcur); 687 688 DPRINTFN(2, ("TX!CMD!%u!%u!%u!%u\n", type, 0, 0, len)); 689 690 /* Wait at most two seconds for command to complete */ 691 return tsleep(sc->cmd, 0, "ipwcmd", 2 * hz); 692 } 693 694 /* Check that descriptors are available to transmit one packet. 695 * Always reserve one transmit-buffer descriptor for ipw_cmd. 696 */ 697 static __inline int 698 ipw_tx_ready(struct ipw_softc *sc) 699 { 700 return !TAILQ_EMPTY(&sc->sc_free_shdr) && 701 !TAILQ_EMPTY(&sc->sc_free_sbuf) && sc->txfree > 1; 702 } 703 704 /* Must not be called unless ipw_tx_ready(sc). */ 705 static int 706 ipw_tx_start(struct ifnet *ifp, struct mbuf *m, struct ieee80211_node *ni) 707 { 708 struct ipw_softc *sc = ifp->if_softc; 709 struct ieee80211com *ic = &sc->sc_ic; 710 struct ieee80211_frame *wh; 711 struct ipw_soft_bd *sbd; 712 struct ipw_soft_hdr *shdr; 713 struct ipw_soft_buf *sbuf; 714 int error, i; 715 716 #ifdef DIAGNOSTIC 717 KASSERT(ipw_tx_ready(sc)); 718 #endif 719 720 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 721 m = ieee80211_wep_crypt(ifp, m, 1); 722 if (m == NULL) 723 return ENOBUFS; 724 } 725 726 #if NBPFILTER > 0 727 if (sc->sc_drvbpf != NULL) { 728 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 729 730 tap->wt_flags = 0; 731 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 732 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 733 734 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m); 735 } 736 #endif 737 738 wh = mtod(m, struct ieee80211_frame *); 739 740 shdr = TAILQ_FIRST(&sc->sc_free_shdr); 741 sbuf = TAILQ_FIRST(&sc->sc_free_sbuf); 742 743 shdr->hdr.type = htole32(IPW_HDR_TYPE_SEND); 744 shdr->hdr.subtype = htole32(0); 745 shdr->hdr.encrypted = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0; 746 shdr->hdr.encrypt = 0; 747 shdr->hdr.keyidx = 0; 748 shdr->hdr.keysz = 0; 749 shdr->hdr.fragmentsz = htole16(0); 750 IEEE80211_ADDR_COPY(shdr->hdr.src_addr, wh->i_addr2); 751 if (ic->ic_opmode == IEEE80211_M_STA) 752 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr3); 753 else 754 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr1); 755 756 /* trim IEEE802.11 header */ 757 m_adj(m, sizeof (struct ieee80211_frame)); 758 759 /* 760 * We need to map the mbuf first to know how many buffer descriptors 761 * are needed for this transfer. 762 */ 763 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m, BUS_DMA_NOWAIT); 764 if (error != 0) { 765 aprint_error("%s: could not map mbuf (error %d)\n", 766 sc->sc_dev.dv_xname, error); 767 m_freem(m); 768 return error; 769 } 770 771 error = bus_dmamap_load(sc->sc_dmat, shdr->map, &shdr->hdr, 772 sizeof (struct ipw_hdr), NULL, BUS_DMA_NOWAIT); 773 if (error != 0) { 774 aprint_error("%s: could not map hdr (error %d)\n", 775 sc->sc_dev.dv_xname, error); 776 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 777 m_freem(m); 778 return error; 779 } 780 781 TAILQ_REMOVE(&sc->sc_free_sbuf, sbuf, next); 782 TAILQ_REMOVE(&sc->sc_free_shdr, shdr, next); 783 784 sbd = &sc->stbd_list[sc->txcur]; 785 sbd->type = IPW_SBD_TYPE_HEADER; 786 sbd->priv = shdr; 787 sbd->bd->physaddr = htole32(shdr->map->dm_segs[0].ds_addr); 788 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 789 sbd->bd->nfrag = 1 + sbuf->map->dm_nsegs; 790 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 791 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 792 793 DPRINTFN(5, ("TX!HDR!%u!%u!%u!%u\n", shdr->hdr.type, shdr->hdr.subtype, 794 shdr->hdr.encrypted, shdr->hdr.encrypt)); 795 DPRINTFN(5, ("!%s", ether_sprintf(shdr->hdr.src_addr))); 796 DPRINTFN(5, ("!%s\n", ether_sprintf(shdr->hdr.dst_addr))); 797 798 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 799 sc->txcur * sizeof (struct ipw_bd), 800 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 801 802 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 803 --sc->txfree; 804 805 sbuf->m = m; 806 sbuf->ni = ni; 807 808 for (i = 0; i < sbuf->map->dm_nsegs; i++) { 809 sbd = &sc->stbd_list[sc->txcur]; 810 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[i].ds_addr); 811 sbd->bd->len = htole32(sbuf->map->dm_segs[i].ds_len); 812 sbd->bd->nfrag = 0; /* used only in first bd */ 813 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 814 if (i == sbuf->map->dm_nsegs - 1) { 815 sbd->type = IPW_SBD_TYPE_DATA; 816 sbd->priv = sbuf; 817 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 818 } else { 819 sbd->type = IPW_SBD_TYPE_NOASSOC; 820 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 821 } 822 823 DPRINTFN(5, ("TX!FRAG!%d!%ld\n", i, 824 sbuf->map->dm_segs[i].ds_len)); 825 826 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 827 sc->txcur * sizeof (struct ipw_bd), 828 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 829 830 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 831 } 832 833 bus_dmamap_sync(sc->sc_dmat, shdr->map, 0, sizeof (struct ipw_hdr), 834 BUS_DMASYNC_PREWRITE); 835 836 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, MCLBYTES, 837 BUS_DMASYNC_PREWRITE); 838 839 /* Inform firmware about this new packet */ 840 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, sc->txcur); 841 842 return 0; 843 } 844 845 static void 846 ipw_start(struct ifnet *ifp) 847 { 848 struct ipw_softc *sc = ifp->if_softc; 849 struct ieee80211com *ic = &sc->sc_ic; 850 struct mbuf *m; 851 struct ieee80211_node *ni; 852 853 for (;;) { 854 if (!ipw_tx_ready(sc)) { 855 DPRINTFN(2, ("%s: no tx descriptors\n", ifp->if_xname)); 856 ifp->if_flags |= IFF_OACTIVE; 857 break; 858 } 859 IFQ_DEQUEUE(&ifp->if_snd, m); 860 if (m == NULL) 861 break; 862 863 #if NBPFILTER > 0 864 if (ifp->if_bpf != NULL) 865 bpf_mtap(ifp->if_bpf, m); 866 #endif 867 868 m = ieee80211_encap(ifp, m, &ni); 869 if (m == NULL) 870 continue; 871 872 #if NBPFILTER > 0 873 if (ic->ic_rawbpf != NULL) 874 bpf_mtap(ic->ic_rawbpf, m); 875 #endif 876 877 if (ipw_tx_start(ifp, m, ni) != 0) { 878 if (ni != NULL) 879 ieee80211_release_node(ic, ni); 880 break; 881 } 882 883 /* start watchdog timer */ 884 sc->sc_tx_timer = 5; 885 ifp->if_timer = 1; 886 } 887 } 888 889 static void 890 ipw_watchdog(struct ifnet *ifp) 891 { 892 struct ipw_softc *sc = ifp->if_softc; 893 894 ifp->if_timer = 0; 895 896 if (sc->sc_tx_timer > 0) { 897 if (--sc->sc_tx_timer == 0) { 898 aprint_error("%s: device timeout\n", 899 sc->sc_dev.dv_xname); 900 #ifdef notyet 901 ipw_init(ifp); 902 #endif 903 return; 904 } 905 ifp->if_timer = 1; 906 } 907 908 ieee80211_watchdog(ifp); 909 } 910 911 static int 912 ipw_get_table1(struct ipw_softc *sc, u_int32_t *tbl) 913 { 914 u_int32_t addr, size, i; 915 916 if (!(sc->flags & IPW_FLAG_FW_INITED)) 917 return ENOTTY; 918 919 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, sc->table1_base); 920 921 size = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 922 if (suword(tbl, size) != 0) 923 return EFAULT; 924 925 for (i = 1, ++tbl; i < size; i++, tbl++) { 926 addr = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 927 if (suword(tbl, MEM_READ_4(sc, addr)) != 0) 928 return EFAULT; 929 } 930 return 0; 931 } 932 933 static int 934 ipw_get_radio(struct ipw_softc *sc, int *ret) 935 { 936 u_int32_t addr; 937 938 if (!(sc->flags & IPW_FLAG_FW_INITED)) 939 return ENOTTY; 940 941 addr = ipw_read_table1(sc, IPW_INFO_EEPROM_ADDRESS); 942 if ((MEM_READ_4(sc, addr + 32) >> 24) & 1) { 943 suword(ret, -1); 944 return 0; 945 } 946 947 if (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED) 948 suword(ret, 0); 949 else 950 suword(ret, 1); 951 952 return 0; 953 } 954 955 static int 956 ipw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 957 { 958 struct ipw_softc *sc = ifp->if_softc; 959 struct ifreq *ifr; 960 int s, error = 0; 961 962 s = splnet(); 963 964 switch (cmd) { 965 case SIOCSIFFLAGS: 966 if (ifp->if_flags & IFF_UP) { 967 if (!(ifp->if_flags & IFF_RUNNING)) 968 ipw_init(ifp); 969 } else { 970 if (ifp->if_flags & IFF_RUNNING) 971 ipw_stop(ifp, 1); 972 } 973 break; 974 975 case SIOCGTABLE1: 976 ifr = (struct ifreq *)data; 977 error = ipw_get_table1(sc, (u_int32_t *)ifr->ifr_data); 978 break; 979 980 case SIOCGRADIO: 981 ifr = (struct ifreq *)data; 982 error = ipw_get_radio(sc, (int *)ifr->ifr_data); 983 break; 984 985 case SIOCSLOADFW: 986 /* only super-user can do that! */ 987 if ((error = suser(curproc->p_ucred, &curproc->p_acflag)) != 0) 988 break; 989 990 ifr = (struct ifreq *)data; 991 error = ipw_firmware_init(sc, (u_char *)ifr->ifr_data); 992 break; 993 994 case SIOCSKILLFW: 995 /* only super-user can do that! */ 996 if ((error = suser(curproc->p_ucred, &curproc->p_acflag)) != 0) 997 break; 998 999 ipw_reset(sc); 1000 break; 1001 1002 default: 1003 error = ieee80211_ioctl(ifp, cmd, data); 1004 if (error != ENETRESET) 1005 break; 1006 1007 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1008 (IFF_UP | IFF_RUNNING)) 1009 ipw_init(ifp); 1010 error = 0; 1011 } 1012 1013 splx(s); 1014 return error; 1015 } 1016 1017 static u_int32_t 1018 ipw_read_table1(struct ipw_softc *sc, u_int32_t off) 1019 { 1020 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 1021 } 1022 1023 static void 1024 ipw_write_table1(struct ipw_softc *sc, u_int32_t off, u_int32_t info) 1025 { 1026 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 1027 } 1028 1029 static int 1030 ipw_read_table2(struct ipw_softc *sc, u_int32_t off, void *buf, u_int32_t *len) 1031 { 1032 u_int32_t addr, info; 1033 u_int16_t count, size; 1034 u_int32_t total; 1035 1036 /* addr[4] + count[2] + size[2] */ 1037 addr = MEM_READ_4(sc, sc->table2_base + off); 1038 info = MEM_READ_4(sc, sc->table2_base + off + 4); 1039 1040 count = info >> 16; 1041 size = info & 0xffff; 1042 total = count * size; 1043 1044 if (total > *len) { 1045 *len = total; 1046 return EINVAL; 1047 } 1048 1049 *len = total; 1050 ipw_read_mem_1(sc, addr, buf, total); 1051 1052 return 0; 1053 } 1054 1055 static int 1056 ipw_tx_init(struct ipw_softc *sc) 1057 { 1058 char *errmsg; 1059 struct ipw_bd *bd; 1060 struct ipw_soft_bd *sbd; 1061 struct ipw_soft_hdr *shdr; 1062 struct ipw_soft_buf *sbuf; 1063 int error, i, nsegs; 1064 1065 /* Allocate transmission buffer descriptors */ 1066 error = bus_dmamap_create(sc->sc_dmat, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, 1067 BUS_DMA_NOWAIT, &sc->tbd_map); 1068 if (error != 0) { 1069 errmsg = "could not create tbd dma map"; 1070 goto fail; 1071 } 1072 1073 error = bus_dmamem_alloc(sc->sc_dmat, IPW_TBD_SZ, PAGE_SIZE, 0, 1074 &sc->tbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 1075 if (error != 0) { 1076 errmsg = "could not allocate tbd dma memory"; 1077 goto fail; 1078 } 1079 1080 error = bus_dmamem_map(sc->sc_dmat, &sc->tbd_seg, nsegs, IPW_TBD_SZ, 1081 (caddr_t *)&sc->tbd_list, BUS_DMA_NOWAIT); 1082 if (error != 0) { 1083 errmsg = "could not map tbd dma memory"; 1084 goto fail; 1085 } 1086 1087 error = bus_dmamap_load(sc->sc_dmat, sc->tbd_map, sc->tbd_list, 1088 IPW_TBD_SZ, NULL, BUS_DMA_NOWAIT); 1089 if (error != 0) { 1090 errmsg = "could not load tbd dma memory"; 1091 goto fail; 1092 } 1093 1094 sc->stbd_list = malloc(IPW_NTBD * sizeof (struct ipw_soft_bd), 1095 M_DEVBUF, M_NOWAIT); 1096 if (sc->stbd_list == NULL) { 1097 errmsg = "could not allocate soft tbd"; 1098 error = ENOMEM; 1099 goto fail; 1100 } 1101 sbd = sc->stbd_list; 1102 bd = sc->tbd_list; 1103 for (i = 0; i < IPW_NTBD; i++, sbd++, bd++) { 1104 sbd->type = IPW_SBD_TYPE_NOASSOC; 1105 sbd->bd = bd; 1106 } 1107 1108 CSR_WRITE_4(sc, IPW_CSR_TX_BD_BASE, sc->tbd_map->dm_segs[0].ds_addr); 1109 CSR_WRITE_4(sc, IPW_CSR_TX_BD_SIZE, IPW_NTBD); 1110 CSR_WRITE_4(sc, IPW_CSR_TX_READ_INDEX, 0); 1111 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, 0); 1112 sc->txold = IPW_NTBD - 1; /* latest bd index ack'ed by firmware */ 1113 sc->txfree = IPW_NTBD; /* number of descriptors free */ 1114 sc->txcur = 0; /* bd index to write to */ 1115 1116 /* Allocate a DMA-able command */ 1117 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_cmd), 1, 1118 sizeof (struct ipw_cmd), 0, BUS_DMA_NOWAIT, &sc->cmd_map); 1119 if (error != 0) { 1120 errmsg = "could not create cmd dma map"; 1121 goto fail; 1122 } 1123 1124 error = bus_dmamem_alloc(sc->sc_dmat, sizeof (struct ipw_cmd), 1125 PAGE_SIZE, 0, &sc->cmd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 1126 if (error != 0) { 1127 errmsg = "could not allocate cmd dma memory"; 1128 goto fail; 1129 } 1130 1131 error = bus_dmamem_map(sc->sc_dmat, &sc->cmd_seg, nsegs, 1132 sizeof (struct ipw_cmd), (caddr_t *)&sc->cmd, BUS_DMA_NOWAIT); 1133 if (error != 0) { 1134 errmsg = "could not map cmd dma memory"; 1135 goto fail; 1136 } 1137 1138 /* Allocate a pool of DMA-able headers */ 1139 sc->shdr_list = malloc(IPW_NDATA * sizeof (struct ipw_soft_hdr), 1140 M_DEVBUF, M_NOWAIT); 1141 if (sc->shdr_list == NULL) { 1142 errmsg = "could not allocate soft hdr"; 1143 error = ENOMEM; 1144 goto fail; 1145 } 1146 TAILQ_INIT(&sc->sc_free_shdr); 1147 for (i = 0, shdr = sc->shdr_list; i < IPW_NDATA; i++, shdr++) { 1148 error = bus_dmamap_create(sc->sc_dmat, 1149 sizeof (struct ipw_soft_hdr), 1, 1150 sizeof (struct ipw_soft_hdr), 0, BUS_DMA_NOWAIT, 1151 &shdr->map); 1152 if (error != 0) { 1153 errmsg = "could not create hdr dma map"; 1154 goto fail; 1155 } 1156 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 1157 } 1158 1159 /* Allocate a pool of DMA-able buffers */ 1160 sc->tx_sbuf_list = malloc(IPW_NDATA * sizeof (struct ipw_soft_buf), 1161 M_DEVBUF, M_NOWAIT); 1162 if (sc->tx_sbuf_list == NULL) { 1163 errmsg = "could not allocate soft txbuf"; 1164 error = ENOMEM; 1165 goto fail; 1166 } 1167 TAILQ_INIT(&sc->sc_free_sbuf); 1168 for (i = 0, sbuf = sc->tx_sbuf_list; i < IPW_NDATA; i++, sbuf++) { 1169 error = bus_dmamap_create(sc->sc_dmat, IPW_NDATA * MCLBYTES, 1170 IPW_NDATA, MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 1171 if (error != 0) { 1172 errmsg = "could not create txbuf dma map"; 1173 goto fail; 1174 } 1175 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 1176 } 1177 1178 return 0; 1179 1180 fail: aprint_error("%s: %s\n", sc->sc_dev.dv_xname, errmsg); 1181 ipw_tx_stop(sc); 1182 1183 return error; 1184 } 1185 1186 static void 1187 ipw_tx_stop(struct ipw_softc *sc) 1188 { 1189 struct ipw_soft_hdr *shdr; 1190 struct ipw_soft_buf *sbuf; 1191 int i; 1192 1193 if (sc->tbd_map != NULL) { 1194 if (sc->tbd_list != NULL) { 1195 bus_dmamap_unload(sc->sc_dmat, sc->tbd_map); 1196 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->tbd_list, 1197 IPW_TBD_SZ); 1198 bus_dmamem_free(sc->sc_dmat, &sc->tbd_seg, 1); 1199 sc->tbd_list = NULL; 1200 } 1201 bus_dmamap_destroy(sc->sc_dmat, sc->tbd_map); 1202 sc->tbd_map = NULL; 1203 } 1204 1205 if (sc->stbd_list != NULL) { 1206 for (i = 0; i < IPW_NTBD; i++) 1207 ipw_release_sbd(sc, &sc->stbd_list[i]); 1208 free(sc->stbd_list, M_DEVBUF); 1209 sc->stbd_list = NULL; 1210 } 1211 1212 if (sc->cmd_map != NULL) { 1213 if (sc->cmd != NULL) { 1214 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->cmd, 1215 sizeof (struct ipw_cmd)); 1216 bus_dmamem_free(sc->sc_dmat, &sc->cmd_seg, 1); 1217 sc->cmd = NULL; 1218 } 1219 bus_dmamap_destroy(sc->sc_dmat, sc->cmd_map); 1220 sc->cmd_map = NULL; 1221 } 1222 1223 if (sc->shdr_list != NULL) { 1224 TAILQ_FOREACH(shdr, &sc->sc_free_shdr, next) 1225 bus_dmamap_destroy(sc->sc_dmat, shdr->map); 1226 free(sc->shdr_list, M_DEVBUF); 1227 sc->shdr_list = NULL; 1228 } 1229 1230 1231 if (sc->tx_sbuf_list != NULL) { 1232 TAILQ_FOREACH(sbuf, &sc->sc_free_sbuf, next) 1233 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 1234 free(sc->tx_sbuf_list, M_DEVBUF); 1235 sc->tx_sbuf_list = NULL; 1236 } 1237 } 1238 1239 static int 1240 ipw_rx_init(struct ipw_softc *sc) 1241 { 1242 char *errmsg; 1243 struct ipw_bd *bd; 1244 struct ipw_soft_bd *sbd; 1245 struct ipw_soft_buf *sbuf; 1246 int error, i, nsegs; 1247 1248 /* Allocate reception buffer descriptors */ 1249 error = bus_dmamap_create(sc->sc_dmat, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, 1250 BUS_DMA_NOWAIT, &sc->rbd_map); 1251 if (error != 0) { 1252 errmsg = "could not create rbd dma map"; 1253 goto fail; 1254 } 1255 1256 error = bus_dmamem_alloc(sc->sc_dmat, IPW_RBD_SZ, PAGE_SIZE, 0, 1257 &sc->rbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 1258 if (error != 0) { 1259 errmsg = "could not allocate rbd dma memory"; 1260 goto fail; 1261 } 1262 1263 error = bus_dmamem_map(sc->sc_dmat, &sc->rbd_seg, nsegs, IPW_RBD_SZ, 1264 (caddr_t *)&sc->rbd_list, BUS_DMA_NOWAIT); 1265 if (error != 0) { 1266 errmsg = "could not map rbd dma memory"; 1267 goto fail; 1268 } 1269 1270 error = bus_dmamap_load(sc->sc_dmat, sc->rbd_map, sc->rbd_list, 1271 IPW_RBD_SZ, NULL, BUS_DMA_NOWAIT); 1272 if (error != 0) { 1273 errmsg = "could not load rbd dma memory"; 1274 goto fail; 1275 } 1276 1277 sc->srbd_list = malloc(IPW_NRBD * sizeof (struct ipw_soft_bd), 1278 M_DEVBUF, M_NOWAIT); 1279 if (sc->srbd_list == NULL) { 1280 errmsg = "could not allocate soft rbd"; 1281 error = ENOMEM; 1282 goto fail; 1283 } 1284 sbd = sc->srbd_list; 1285 bd = sc->rbd_list; 1286 for (i = 0; i < IPW_NRBD; i++, sbd++, bd++) { 1287 sbd->type = IPW_SBD_TYPE_NOASSOC; 1288 sbd->bd = bd; 1289 } 1290 1291 CSR_WRITE_4(sc, IPW_CSR_RX_BD_BASE, sc->rbd_map->dm_segs[0].ds_addr); 1292 CSR_WRITE_4(sc, IPW_CSR_RX_BD_SIZE, IPW_NRBD); 1293 CSR_WRITE_4(sc, IPW_CSR_RX_READ_INDEX, 0); 1294 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE_INDEX, IPW_NRBD - 1); 1295 sc->rxcur = IPW_NRBD - 1; /* latest bd index I've read */ 1296 1297 /* Allocate status descriptors */ 1298 error = bus_dmamap_create(sc->sc_dmat, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 1299 0, BUS_DMA_NOWAIT, &sc->status_map); 1300 if (error != 0) { 1301 errmsg = "could not create status dma map"; 1302 goto fail; 1303 } 1304 1305 error = bus_dmamem_alloc(sc->sc_dmat, IPW_STATUS_SZ, PAGE_SIZE, 0, 1306 &sc->status_seg, 1, &nsegs, BUS_DMA_NOWAIT); 1307 if (error != 0) { 1308 errmsg = "could not allocate status dma memory"; 1309 goto fail; 1310 } 1311 1312 error = bus_dmamem_map(sc->sc_dmat, &sc->status_seg, nsegs, 1313 IPW_STATUS_SZ, (caddr_t *)&sc->status_list, BUS_DMA_NOWAIT); 1314 if (error != 0) { 1315 errmsg = "could not map status dma memory"; 1316 goto fail; 1317 } 1318 1319 error = bus_dmamap_load(sc->sc_dmat, sc->status_map, sc->status_list, 1320 IPW_STATUS_SZ, NULL, BUS_DMA_NOWAIT); 1321 if (error != 0) { 1322 errmsg = "could not load status dma memory"; 1323 goto fail; 1324 } 1325 1326 CSR_WRITE_4(sc, IPW_CSR_RX_STATUS_BASE, 1327 sc->status_map->dm_segs[0].ds_addr); 1328 1329 sc->rx_sbuf_list = malloc(IPW_NRBD * sizeof (struct ipw_soft_buf), 1330 M_DEVBUF, M_NOWAIT); 1331 if (sc->rx_sbuf_list == NULL) { 1332 errmsg = "could not allocate soft rxbuf"; 1333 error = ENOMEM; 1334 goto fail; 1335 } 1336 1337 sbuf = sc->rx_sbuf_list; 1338 sbd = sc->srbd_list; 1339 for (i = 0; i < IPW_NRBD; i++, sbuf++, sbd++) { 1340 1341 MGETHDR(sbuf->m, M_DONTWAIT, MT_DATA); 1342 if (sbuf->m == NULL) { 1343 errmsg = "could not allocate rx mbuf"; 1344 error = ENOMEM; 1345 goto fail; 1346 } 1347 MCLGET(sbuf->m, M_DONTWAIT); 1348 if (!(sbuf->m->m_flags & M_EXT)) { 1349 m_freem(sbuf->m); 1350 errmsg = "could not allocate rx mbuf cluster"; 1351 error = ENOMEM; 1352 goto fail; 1353 } 1354 1355 error = bus_dmamap_create(sc->sc_dmat, IPW_NRBD * MCLBYTES, 1356 IPW_NRBD, MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 1357 if (error != 0) { 1358 m_freem(sbuf->m); 1359 errmsg = "could not create rxbuf dma map"; 1360 goto fail; 1361 } 1362 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, 1363 mtod(sbuf->m, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 1364 if (error != 0) { 1365 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 1366 m_freem(sbuf->m); 1367 errmsg = "could not map rxbuf dma memory"; 1368 goto fail; 1369 } 1370 sbd->type = IPW_SBD_TYPE_DATA; 1371 sbd->priv = sbuf; 1372 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 1373 sbd->bd->len = htole32(MCLBYTES); 1374 } 1375 1376 return 0; 1377 1378 fail: aprint_error("%s: %s\n", sc->sc_dev.dv_xname, errmsg); 1379 ipw_rx_stop(sc); 1380 1381 return error; 1382 } 1383 1384 static void 1385 ipw_rx_stop(struct ipw_softc *sc) 1386 { 1387 struct ipw_soft_bd *sbd; 1388 struct ipw_soft_buf *sbuf; 1389 int i; 1390 1391 if (sc->rbd_map != NULL) { 1392 if (sc->rbd_list != NULL) { 1393 bus_dmamap_unload(sc->sc_dmat, sc->rbd_map); 1394 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->rbd_list, 1395 IPW_RBD_SZ); 1396 bus_dmamem_free(sc->sc_dmat, &sc->rbd_seg, 1); 1397 sc->rbd_list = NULL; 1398 } 1399 bus_dmamap_destroy(sc->sc_dmat, sc->rbd_map); 1400 sc->rbd_map = NULL; 1401 } 1402 1403 if (sc->status_map != NULL) { 1404 if (sc->status_list != NULL) { 1405 bus_dmamap_unload(sc->sc_dmat, sc->status_map); 1406 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->status_list, 1407 IPW_STATUS_SZ); 1408 bus_dmamem_free(sc->sc_dmat, &sc->status_seg, 1); 1409 sc->status_list = NULL; 1410 } 1411 bus_dmamap_destroy(sc->sc_dmat, sc->status_map); 1412 sc->status_map = NULL; 1413 } 1414 1415 if (sc->srbd_list != NULL) { 1416 for (i = 0, sbd = sc->srbd_list; i < IPW_NRBD; i++, sbd++) { 1417 if (sbd->type == IPW_SBD_TYPE_NOASSOC) 1418 continue; 1419 1420 sbuf = sbd->priv; 1421 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1422 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 1423 m_freem(sbuf->m); 1424 } 1425 free(sc->srbd_list, M_DEVBUF); 1426 sc->srbd_list = NULL; 1427 } 1428 1429 if (sc->rx_sbuf_list != NULL) { 1430 free(sc->rx_sbuf_list, M_DEVBUF); 1431 sc->rx_sbuf_list = NULL; 1432 } 1433 } 1434 1435 static void 1436 ipw_reset(struct ipw_softc *sc) 1437 { 1438 struct ifnet *ifp = &sc->sc_ic.ic_if; 1439 int ntries; 1440 1441 ipw_stop(ifp, 1); 1442 1443 if (sc->flags & IPW_FLAG_FW_INITED) { 1444 ipw_cmd(sc, IPW_CMD_DISABLE_PHY, NULL, 0); 1445 ipw_cmd(sc, IPW_CMD_PREPARE_POWER_DOWN, NULL, 0); 1446 1447 sc->flags &= ~IPW_FLAG_FW_INITED; 1448 } 1449 1450 /* Disable interrupts */ 1451 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1452 1453 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1454 for (ntries = 0; ntries < 5; ntries++) { 1455 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1456 break; 1457 DELAY(10); 1458 } 1459 1460 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 1461 1462 ipw_rx_stop(sc); 1463 ipw_tx_stop(sc); 1464 1465 ifp->if_flags &= ~IFF_UP; 1466 } 1467 1468 static int 1469 ipw_clock_sync(struct ipw_softc *sc) 1470 { 1471 int ntries; 1472 u_int32_t r; 1473 1474 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 1475 for (ntries = 0; ntries < 1000; ntries++) { 1476 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_PRINCETON_RESET) 1477 break; 1478 DELAY(10); 1479 } 1480 if (ntries == 1000) 1481 return EIO; 1482 1483 CSR_WRITE_4(sc, IPW_CSR_CTL, IPW_CTL_INIT_DONE); 1484 for (ntries = 0; ntries < 1000; ntries++) { 1485 if ((r = CSR_READ_4(sc, IPW_CSR_CTL)) & IPW_CTL_CLOCK_READY) 1486 break; 1487 DELAY(200); 1488 } 1489 if (ntries == 1000) 1490 return EIO; 1491 1492 CSR_WRITE_4(sc, IPW_CSR_CTL, r | IPW_CTL_ALLOW_STANDBY); 1493 1494 return 0; 1495 } 1496 1497 static int 1498 ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size) 1499 { 1500 int ntries; 1501 1502 MEM_WRITE_2(sc, 0x220000, 0x0703); 1503 MEM_WRITE_2(sc, 0x220000, 0x0707); 1504 1505 MEM_WRITE_1(sc, 0x210014, 0x72); 1506 MEM_WRITE_1(sc, 0x210014, 0x72); 1507 1508 MEM_WRITE_1(sc, 0x210000, 0x40); 1509 MEM_WRITE_1(sc, 0x210000, 0x00); 1510 MEM_WRITE_1(sc, 0x210000, 0x40); 1511 1512 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1513 1514 MEM_WRITE_1(sc, 0x210000, 0x00); 1515 MEM_WRITE_1(sc, 0x210000, 0x00); 1516 MEM_WRITE_1(sc, 0x210000, 0x80); 1517 1518 MEM_WRITE_2(sc, 0x220000, 0x0703); 1519 MEM_WRITE_2(sc, 0x220000, 0x0707); 1520 1521 MEM_WRITE_1(sc, 0x210014, 0x72); 1522 MEM_WRITE_1(sc, 0x210014, 0x72); 1523 1524 MEM_WRITE_1(sc, 0x210000, 0x00); 1525 MEM_WRITE_1(sc, 0x210000, 0x80); 1526 1527 for (ntries = 0; ntries < 10; ntries++) { 1528 if (MEM_READ_1(sc, 0x210000) & 1) 1529 break; 1530 DELAY(10); 1531 } 1532 if (ntries == 10) 1533 return EIO; 1534 1535 return 0; 1536 } 1537 1538 /* set of macros to handle unaligned little endian data in firmware image */ 1539 #define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1540 #define GETLE16(p) ((p)[0] | (p)[1] << 8) 1541 static int 1542 ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size) 1543 { 1544 u_char *p, *end; 1545 u_int32_t addr; 1546 u_int16_t len; 1547 1548 p = fw; 1549 end = fw + size; 1550 while (p < end) { 1551 if (p + 6 > end) 1552 return EINVAL; 1553 1554 addr = GETLE32(p); 1555 p += 4; 1556 len = GETLE16(p); 1557 p += 2; 1558 1559 if (p + len > end) 1560 return EINVAL; 1561 1562 ipw_write_mem_1(sc, addr, p, len); 1563 p += len; 1564 } 1565 return 0; 1566 } 1567 1568 static int 1569 ipw_firmware_init(struct ipw_softc *sc, u_char *data) 1570 { 1571 struct ieee80211com *ic = &sc->sc_ic; 1572 struct ifnet *ifp = &ic->ic_if; 1573 struct ipw_fw_hdr hdr; 1574 u_int32_t r, len, fw_size, uc_size; 1575 u_char *fw, *uc; 1576 int error; 1577 1578 ipw_reset(sc); 1579 1580 if ((error = copyin(data, &hdr, sizeof hdr)) != 0) 1581 goto fail1; 1582 1583 fw_size = le32toh(hdr.fw_size); 1584 uc_size = le32toh(hdr.uc_size); 1585 data += sizeof hdr; 1586 1587 if ((fw = malloc(fw_size, M_DEVBUF, M_NOWAIT)) == NULL) { 1588 error = ENOMEM; 1589 goto fail1; 1590 } 1591 1592 if ((error = copyin(data, fw, fw_size)) != 0) 1593 goto fail2; 1594 1595 data += fw_size; 1596 1597 if ((uc = malloc(uc_size, M_DEVBUF, M_NOWAIT)) == NULL) { 1598 error = ENOMEM; 1599 goto fail2; 1600 } 1601 1602 if ((error = copyin(data, uc, uc_size)) != 0) 1603 goto fail3; 1604 1605 if ((error = ipw_clock_sync(sc)) != 0) { 1606 aprint_error("%s: clock synchronization failed\n", 1607 sc->sc_dev.dv_xname); 1608 goto fail3; 1609 } 1610 1611 MEM_WRITE_4(sc, 0x003000e0, 0x80000000); 1612 1613 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1614 1615 if ((error = ipw_load_ucode(sc, uc, uc_size)) != 0) { 1616 aprint_error("%s: could not load microcode\n", 1617 sc->sc_dev.dv_xname); 1618 goto fail3; 1619 } 1620 1621 MEM_WRITE_4(sc, 0x003000e0, 0); 1622 1623 if ((error = ipw_clock_sync(sc)) != 0) { 1624 aprint_error("%s: clock synchronization failed\n", 1625 sc->sc_dev.dv_xname); 1626 goto fail3; 1627 } 1628 1629 if ((error = ipw_load_firmware(sc, fw, fw_size))) { 1630 aprint_error("%s: could not load firmware\n", 1631 sc->sc_dev.dv_xname); 1632 goto fail3; 1633 } 1634 1635 ipw_zero_mem_4(sc, 0x0002f200, 196); 1636 ipw_zero_mem_4(sc, 0x0002f610, 8); 1637 ipw_zero_mem_4(sc, 0x0002fa00, 8); 1638 ipw_zero_mem_4(sc, 0x0002fc00, 4); 1639 ipw_zero_mem_4(sc, 0x0002ff80, 32); 1640 1641 if ((error = ipw_rx_init(sc)) != 0) { 1642 aprint_error("%s: could not initialize rx queue\n", 1643 sc->sc_dev.dv_xname); 1644 goto fail3; 1645 } 1646 1647 if ((error = ipw_tx_init(sc)) != 0) { 1648 aprint_error("%s: could not initialize tx queue\n", 1649 sc->sc_dev.dv_xname); 1650 goto fail3; 1651 } 1652 1653 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1654 IPW_IO_LED_OFF); 1655 1656 /* Enable interrupts */ 1657 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1658 1659 /* Let's go! */ 1660 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1661 1662 /* Wait at most 5 seconds for firmware initialization to complete */ 1663 if ((error = tsleep(sc, 0, "ipwinit", 5 * hz)) != 0) { 1664 aprint_error("%s: timeout waiting for firmware initialization " 1665 "to complete\n", sc->sc_dev.dv_xname); 1666 goto fail3; 1667 } 1668 1669 /* Firmware initialization completed */ 1670 sc->flags |= IPW_FLAG_FW_INITED; 1671 1672 free(uc, M_DEVBUF); 1673 free(fw, M_DEVBUF); 1674 1675 r = CSR_READ_4(sc, IPW_CSR_IO); 1676 CSR_WRITE_4(sc, IPW_CSR_IO, r | IPW_IO_GPIO1_MASK | IPW_IO_GPIO3_MASK); 1677 1678 /* Retrieve information tables base addresses */ 1679 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 1680 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 1681 1682 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 1683 1684 /* Retrieve adapter MAC address */ 1685 len = IEEE80211_ADDR_LEN; 1686 ipw_read_table2(sc, IPW_INFO_ADAPTER_MAC, ic->ic_myaddr, &len); 1687 1688 IEEE80211_ADDR_COPY(LLADDR(ifp->if_sadl), ic->ic_myaddr); 1689 1690 return 0; 1691 1692 fail3: free(uc, M_DEVBUF); 1693 fail2: free(fw, M_DEVBUF); 1694 fail1: ipw_reset(sc); 1695 1696 return error; 1697 } 1698 1699 static int 1700 ipw_config(struct ipw_softc *sc) 1701 { 1702 struct ieee80211com *ic = &sc->sc_ic; 1703 struct ifnet *ifp = &ic->ic_if; 1704 struct ipw_security security; 1705 struct ieee80211_wepkey *k; 1706 struct ipw_wep_key wepkey; 1707 struct ipw_scan_options options; 1708 struct ipw_configuration config; 1709 u_int32_t data; 1710 int error, i; 1711 1712 switch (ic->ic_opmode) { 1713 case IEEE80211_M_STA: 1714 case IEEE80211_M_HOSTAP: 1715 data = htole32(IPW_MODE_BSS); 1716 break; 1717 1718 case IEEE80211_M_IBSS: 1719 case IEEE80211_M_AHDEMO: 1720 data = htole32(IPW_MODE_IBSS); 1721 break; 1722 1723 case IEEE80211_M_MONITOR: 1724 data = htole32(IPW_MODE_MONITOR); 1725 break; 1726 } 1727 DPRINTF(("Setting adapter mode to %u\n", data)); 1728 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 1729 if (error != 0) 1730 return error; 1731 1732 if (ic->ic_opmode == IEEE80211_M_IBSS || 1733 ic->ic_opmode == IEEE80211_M_MONITOR) { 1734 data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); 1735 DPRINTF(("Setting adapter channel to %u\n", data)); 1736 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 1737 if (error != 0) 1738 return error; 1739 } 1740 1741 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1742 DPRINTF(("Enabling adapter\n")); 1743 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1744 } 1745 1746 DPRINTF(("Setting adapter MAC to %s\n", ether_sprintf(ic->ic_myaddr))); 1747 IEEE80211_ADDR_COPY(LLADDR(ifp->if_sadl), ic->ic_myaddr); 1748 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 1749 IEEE80211_ADDR_LEN); 1750 if (error != 0) 1751 return error; 1752 1753 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 1754 IPW_CFG_PREAMBLE_LEN | IPW_CFG_802_1x_ENABLE); 1755 if (ic->ic_opmode == IEEE80211_M_IBSS) 1756 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 1757 if (ifp->if_flags & IFF_PROMISC) 1758 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 1759 config.channels = htole32(0x3fff); /* channels 1-14 */ 1760 config.ibss_chan = htole32(0x7ff); 1761 DPRINTF(("Setting adapter configuration 0x%08x\n", config.flags)); 1762 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 1763 if (error != 0) 1764 return error; 1765 1766 data = htole32(0x3); /* 1, 2 */ 1767 DPRINTF(("Setting adapter basic tx rates to 0x%x\n", data)); 1768 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 1769 if (error != 0) 1770 return error; 1771 1772 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 1773 DPRINTF(("Setting adapter tx rates to 0x%x\n", data)); 1774 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 1775 if (error != 0) 1776 return error; 1777 1778 data = htole32(IPW_POWER_MODE_CAM); 1779 DPRINTF(("Setting adapter power mode to %u\n", data)); 1780 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 1781 if (error != 0) 1782 return error; 1783 1784 if (ic->ic_opmode == IEEE80211_M_IBSS) { 1785 data = htole32(ic->ic_txpower); 1786 DPRINTF(("Setting adapter tx power index to %u\n", data)); 1787 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 1788 sizeof data); 1789 if (error != 0) 1790 return error; 1791 } 1792 1793 data = htole32(ic->ic_rtsthreshold); 1794 DPRINTF(("Setting adapter RTS threshold to %u\n", data)); 1795 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 1796 if (error != 0) 1797 return error; 1798 1799 data = htole32(ic->ic_fragthreshold); 1800 DPRINTF(("Setting adapter frag threshold to %u\n", data)); 1801 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 1802 if (error != 0) 1803 return error; 1804 1805 #ifdef IPW_DEBUG 1806 if (ipw_debug > 0) { 1807 printf("Setting adapter ESSID to "); 1808 ieee80211_print_essid(ic->ic_des_essid, ic->ic_des_esslen); 1809 printf("\n"); 1810 } 1811 #endif 1812 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ic->ic_des_essid, 1813 ic->ic_des_esslen); 1814 if (error != 0) 1815 return error; 1816 1817 /* no mandatory BSSID */ 1818 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 1819 if (error != 0) 1820 return error; 1821 1822 if (ic->ic_flags & IEEE80211_F_DESBSSID) { 1823 DPRINTF(("Setting adapter desired BSSID to %s\n", 1824 ether_sprintf(ic->ic_des_bssid))); 1825 error = ipw_cmd(sc, IPW_CMD_SET_DESIRED_BSSID, 1826 ic->ic_des_bssid, IEEE80211_ADDR_LEN); 1827 if (error != 0) 1828 return error; 1829 } 1830 1831 security.authmode = IPW_AUTH_OPEN; 1832 security.ciphers = htole32(IPW_CIPHER_NONE); 1833 security.version = htole16(0); 1834 security.replay_counters_number = 0; 1835 security.unicast_using_group = 0; 1836 DPRINTF(("Setting adapter authmode to %u\n", security.authmode)); 1837 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 1838 sizeof security); 1839 if (error != 0) 1840 return error; 1841 1842 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 1843 k = ic->ic_nw_keys; 1844 for (i = 0; i < IEEE80211_WEP_NKID; i++, k++) { 1845 if (k->wk_len == 0) 1846 continue; 1847 1848 wepkey.idx = i; 1849 wepkey.len = k->wk_len; 1850 bzero(wepkey.key, sizeof wepkey.key); 1851 bcopy(k->wk_key, wepkey.key, k->wk_len); 1852 DPRINTF(("Setting wep key index %d len %d\n", 1853 wepkey.idx, wepkey.len)); 1854 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY, &wepkey, 1855 sizeof wepkey); 1856 if (error != 0) 1857 return error; 1858 } 1859 1860 data = htole32(ic->ic_wep_txkey); 1861 DPRINTF(("Setting adapter tx key index to %u\n", data)); 1862 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY_INDEX, &data, 1863 sizeof data); 1864 if (error != 0) 1865 return error; 1866 } 1867 1868 data = htole32((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) ? 0x8 : 0); 1869 DPRINTF(("Setting adapter wep flags to 0x%x\n", data)); 1870 error = ipw_cmd(sc, IPW_CMD_SET_WEP_FLAGS, &data, sizeof data); 1871 if (error != 0) 1872 return error; 1873 1874 if (ic->ic_opmode == IEEE80211_M_IBSS || 1875 ic->ic_opmode == IEEE80211_M_HOSTAP) { 1876 data = htole32(ic->ic_lintval); 1877 DPRINTF(("Setting adapter beacon interval to %u\n", data)); 1878 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 1879 sizeof data); 1880 if (error != 0) 1881 return error; 1882 } 1883 1884 options.flags = htole32(0); 1885 options.channels = htole32(0x3fff); /* scan channels 1-14 */ 1886 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &options, sizeof options); 1887 if (error != 0) 1888 return error; 1889 1890 /* finally, enable adapter (start scanning for an access point) */ 1891 DPRINTF(("Enabling adapter\n")); 1892 error = ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1893 if (error != 0) 1894 return error; 1895 1896 return 0; 1897 } 1898 1899 static int 1900 ipw_init(struct ifnet *ifp) 1901 { 1902 struct ipw_softc *sc = ifp->if_softc; 1903 struct ieee80211com *ic = &sc->sc_ic; 1904 1905 /* exit immediately if firmware has not been ioctl'd */ 1906 if (!(sc->flags & IPW_FLAG_FW_INITED)) { 1907 ifp->if_flags &= ~IFF_UP; 1908 return EIO; 1909 } 1910 1911 ipw_stop(ifp, 0); 1912 1913 if (ipw_config(sc) != 0) { 1914 aprint_error("%s: device configuration failed\n", 1915 sc->sc_dev.dv_xname); 1916 goto fail; 1917 } 1918 1919 ifp->if_flags &= ~IFF_OACTIVE; 1920 ifp->if_flags |= IFF_RUNNING; 1921 1922 ic->ic_bss->ni_chan = ic->ic_channels; 1923 1924 return 0; 1925 1926 fail: ipw_stop(ifp, 0); 1927 1928 return EIO; 1929 } 1930 1931 static void 1932 ipw_stop(struct ifnet *ifp, int disable) 1933 { 1934 struct ipw_softc *sc = ifp->if_softc; 1935 struct ieee80211com *ic = &sc->sc_ic; 1936 1937 if (ifp->if_flags & IFF_RUNNING) { 1938 DPRINTF(("Disabling adapter\n")); 1939 ipw_cmd(sc, IPW_CMD_DISABLE, NULL, 0); 1940 } 1941 1942 ifp->if_timer = 0; 1943 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1944 1945 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1946 } 1947 1948 static void 1949 ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, u_int8_t *datap, 1950 bus_size_t count) 1951 { 1952 for (; count > 0; offset++, datap++, count--) { 1953 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 1954 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 1955 } 1956 } 1957 1958 static void 1959 ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, u_int8_t *datap, 1960 bus_size_t count) 1961 { 1962 for (; count > 0; offset++, datap++, count--) { 1963 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 1964 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 1965 } 1966 } 1967 1968 static void 1969 ipw_zero_mem_4(struct ipw_softc *sc, bus_size_t offset, bus_size_t count) 1970 { 1971 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, offset); 1972 while (count-- > 0) 1973 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_DATA, 0); 1974 } 1975 1976
Indexes created Tue Sep 30 06:09:59 GMT 2025