if_ipw.c revision 1.12
1 /* $NetBSD: if_ipw.c,v 1.12 2005/06/22 06:16:02 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 5 * Damien Bergamini <damien.bergamini (at) free.fr>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: if_ipw.c,v 1.12 2005/06/22 06:16:02 dyoung Exp $"); 32 33 /*- 34 * Intel(R) PRO/Wireless 2100 MiniPCI driver 35 * http://www.intel.com/products/mobiletechnology/prowireless.htm 36 */ 37 38 #include "bpfilter.h" 39 40 #include <sys/param.h> 41 #include <sys/sockio.h> 42 #include <sys/sysctl.h> 43 #include <sys/mbuf.h> 44 #include <sys/kernel.h> 45 #include <sys/socket.h> 46 #include <sys/systm.h> 47 #include <sys/malloc.h> 48 #include <sys/conf.h> 49 50 #include <machine/bus.h> 51 #include <machine/endian.h> 52 #include <machine/intr.h> 53 54 #include <dev/pci/pcireg.h> 55 #include <dev/pci/pcivar.h> 56 #include <dev/pci/pcidevs.h> 57 58 #if NBPFILTER > 0 59 #include <net/bpf.h> 60 #endif 61 #include <net/if.h> 62 #include <net/if_arp.h> 63 #include <net/if_dl.h> 64 #include <net/if_ether.h> 65 #include <net/if_media.h> 66 #include <net/if_types.h> 67 68 #include <net80211/ieee80211_var.h> 69 #include <net80211/ieee80211_radiotap.h> 70 71 #include <netinet/in.h> 72 #include <netinet/in_systm.h> 73 #include <netinet/in_var.h> 74 #include <netinet/ip.h> 75 76 #include <dev/pci/if_ipwreg.h> 77 #include <dev/pci/if_ipwvar.h> 78 79 static int ipw_match(struct device *, struct cfdata *, void *); 80 static void ipw_attach(struct device *, struct device *, void *); 81 static int ipw_detach(struct device *, int); 82 static int ipw_media_change(struct ifnet *); 83 static int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 84 static void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 85 static void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 86 static void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 87 struct ipw_soft_bd *, struct ipw_soft_buf *); 88 static void ipw_notification_intr(struct ipw_softc *, struct ipw_soft_buf *); 89 static void ipw_rx_intr(struct ipw_softc *); 90 static void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 91 static void ipw_tx_intr(struct ipw_softc *); 92 static int ipw_intr(void *); 93 static int ipw_cmd(struct ipw_softc *, u_int32_t, void *, u_int32_t); 94 static int ipw_tx_start(struct ifnet *, struct mbuf *, struct ieee80211_node *); 95 static void ipw_start(struct ifnet *); 96 static void ipw_watchdog(struct ifnet *); 97 static int ipw_get_table1(struct ipw_softc *, u_int32_t *); 98 static int ipw_get_radio(struct ipw_softc *, int *); 99 static int ipw_ioctl(struct ifnet *, u_long, caddr_t); 100 static u_int32_t ipw_read_table1(struct ipw_softc *, u_int32_t); 101 static void ipw_write_table1(struct ipw_softc *, u_int32_t, u_int32_t); 102 static int ipw_read_table2(struct ipw_softc *, u_int32_t, void *, u_int32_t *); 103 static int ipw_tx_init(struct ipw_softc *); 104 static void ipw_tx_stop(struct ipw_softc *); 105 static int ipw_rx_init(struct ipw_softc *); 106 static void ipw_rx_stop(struct ipw_softc *); 107 static void ipw_reset(struct ipw_softc *); 108 static int ipw_clock_sync(struct ipw_softc *); 109 static int ipw_load_ucode(struct ipw_softc *, u_char *, int); 110 static int ipw_load_firmware(struct ipw_softc *, u_char *, int); 111 static int ipw_firmware_init(struct ipw_softc *, u_char *); 112 static int ipw_config(struct ipw_softc *); 113 static int ipw_init(struct ifnet *); 114 static void ipw_stop(struct ifnet *, int); 115 static void ipw_read_mem_1(struct ipw_softc *, bus_size_t, u_int8_t *, 116 bus_size_t); 117 static void ipw_write_mem_1(struct ipw_softc *, bus_size_t, u_int8_t *, 118 bus_size_t); 119 static void ipw_zero_mem_4(struct ipw_softc *, bus_size_t, bus_size_t); 120 121 static inline u_int8_t MEM_READ_1(struct ipw_softc *sc, u_int32_t addr) 122 { 123 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 124 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); 125 } 126 127 static inline u_int16_t MEM_READ_2(struct ipw_softc *sc, u_int32_t addr) 128 { 129 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 130 return CSR_READ_2(sc, IPW_CSR_INDIRECT_DATA); 131 } 132 133 static inline u_int32_t MEM_READ_4(struct ipw_softc *sc, u_int32_t addr) 134 { 135 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 136 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); 137 } 138 139 #ifdef IPW_DEBUG 140 #define DPRINTF(x) if (ipw_debug > 0) printf x 141 #define DPRINTFN(n, x) if (ipw_debug >= (n)) printf x 142 int ipw_debug = 0; 143 #else 144 #define DPRINTF(x) 145 #define DPRINTFN(n, x) 146 #endif 147 148 CFATTACH_DECL(ipw, sizeof (struct ipw_softc), ipw_match, ipw_attach, 149 ipw_detach, NULL); 150 151 static int 152 ipw_match(struct device *parent, struct cfdata *match, void *aux) 153 { 154 struct pci_attach_args *pa = aux; 155 156 if (PCI_VENDOR (pa->pa_id) == PCI_VENDOR_INTEL && 157 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_PRO_WL_2100) 158 return 1; 159 160 return 0; 161 } 162 163 /* Base Address Register */ 164 #define IPW_PCI_BAR0 0x10 165 166 static void 167 ipw_attach(struct device *parent, struct device *self, void *aux) 168 { 169 struct ipw_softc *sc = (struct ipw_softc *)self; 170 struct ieee80211com *ic = &sc->sc_ic; 171 struct ifnet *ifp = &sc->sc_if; 172 struct ieee80211_rateset *rs; 173 struct pci_attach_args *pa = aux; 174 const char *intrstr; 175 char devinfo[256]; 176 bus_space_tag_t memt; 177 bus_space_handle_t memh; 178 bus_addr_t base; 179 pci_intr_handle_t ih; 180 u_int32_t data; 181 int i, revision, error; 182 183 sc->sc_pct = pa->pa_pc; 184 185 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof devinfo); 186 revision = PCI_REVISION(pa->pa_class); 187 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, revision); 188 189 /* enable bus-mastering */ 190 data = pci_conf_read(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG); 191 data |= PCI_COMMAND_MASTER_ENABLE; 192 pci_conf_write(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG, data); 193 194 /* map the register window */ 195 error = pci_mapreg_map(pa, IPW_PCI_BAR0, PCI_MAPREG_TYPE_MEM | 196 PCI_MAPREG_MEM_TYPE_32BIT, 0, &memt, &memh, &base, &sc->sc_sz); 197 if (error != 0) { 198 aprint_error("%s: could not map memory space\n", 199 sc->sc_dev.dv_xname); 200 return; 201 } 202 203 sc->sc_st = memt; 204 sc->sc_sh = memh; 205 sc->sc_dmat = pa->pa_dmat; 206 207 /* disable interrupts */ 208 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 209 210 if (pci_intr_map(pa, &ih) != 0) { 211 aprint_error("%s: could not map interrupt\n", 212 sc->sc_dev.dv_xname); 213 return; 214 } 215 216 intrstr = pci_intr_string(sc->sc_pct, ih); 217 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, ipw_intr, sc); 218 if (sc->sc_ih == NULL) { 219 aprint_error("%s: could not establish interrupt", 220 sc->sc_dev.dv_xname); 221 if (intrstr != NULL) 222 aprint_error(" at %s", intrstr); 223 aprint_error("\n"); 224 return; 225 } 226 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 227 228 ic->ic_ifp = ifp; 229 ic->ic_phytype = IEEE80211_T_DS; 230 ic->ic_opmode = IEEE80211_M_STA; 231 ic->ic_state = IEEE80211_S_INIT; 232 233 /* set device capabilities */ 234 ic->ic_caps = IEEE80211_C_IBSS | IEEE80211_C_MONITOR | 235 IEEE80211_C_PMGT | IEEE80211_C_TXPMGT | IEEE80211_C_WEP; 236 237 /* set supported 11.b rates */ 238 rs = &ic->ic_sup_rates[IEEE80211_MODE_11B]; 239 rs->rs_nrates = 4; 240 rs->rs_rates[0] = 2; /* 1Mbps */ 241 rs->rs_rates[1] = 4; /* 2Mbps */ 242 rs->rs_rates[2] = 11; /* 5.5Mbps */ 243 rs->rs_rates[3] = 22; /* 11Mbps */ 244 245 /* set supported 11.b channels (1 through 14) */ 246 for (i = 1; i <= 14; i++) { 247 ic->ic_channels[i].ic_freq = 248 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 249 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 250 } 251 252 ic->ic_ibss_chan = &ic->ic_channels[0]; 253 254 ifp->if_softc = sc; 255 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 256 ifp->if_init = ipw_init; 257 ifp->if_stop = ipw_stop; 258 ifp->if_ioctl = ipw_ioctl; 259 ifp->if_start = ipw_start; 260 ifp->if_watchdog = ipw_watchdog; 261 IFQ_SET_READY(&ifp->if_snd); 262 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 263 264 if_attach(ifp); 265 ieee80211_ifattach(ic); 266 /* override state transition machine */ 267 sc->sc_newstate = ic->ic_newstate; 268 ic->ic_newstate = ipw_newstate; 269 270 ieee80211_media_init(ic, ipw_media_change, ieee80211_media_status); 271 272 #if NBPFILTER > 0 273 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 274 sizeof (struct ieee80211_frame) + 64, &sc->sc_drvbpf); 275 276 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 277 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 278 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 279 280 sc->sc_txtap_len = sizeof sc->sc_txtapu; 281 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 282 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 283 #endif 284 } 285 286 static int 287 ipw_detach(struct device* self, int flags) 288 { 289 struct ipw_softc *sc = (struct ipw_softc *)self; 290 struct ifnet *ifp = &sc->sc_if; 291 292 ipw_reset(sc); 293 294 #if NBPFILTER > 0 295 bpfdetach(ifp); 296 #endif 297 ieee80211_ifdetach(&sc->sc_ic); 298 if_detach(ifp); 299 300 if (sc->sc_ih != NULL) { 301 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 302 sc->sc_ih = NULL; 303 } 304 305 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 306 307 return 0; 308 } 309 310 static int 311 ipw_media_change(struct ifnet *ifp) 312 { 313 int error; 314 315 error = ieee80211_media_change(ifp); 316 if (error != ENETRESET) 317 return error; 318 319 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 320 ipw_init(ifp); 321 322 return 0; 323 } 324 325 static int 326 ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 327 { 328 struct ifnet *ifp = ic->ic_ifp; 329 struct ipw_softc *sc = ifp->if_softc; 330 struct ieee80211_node *ni = ic->ic_bss; 331 u_int32_t val, len; 332 333 switch (nstate) { 334 case IEEE80211_S_INIT: 335 break; 336 337 case IEEE80211_S_RUN: 338 len = IEEE80211_NWID_LEN; 339 ipw_read_table2(sc, IPW_INFO_CURRENT_SSID, ni->ni_essid, &len); 340 ni->ni_esslen = len; 341 342 val = ipw_read_table1(sc, IPW_INFO_CURRENT_CHANNEL); 343 ni->ni_chan = &ic->ic_channels[val]; 344 345 DELAY(100); /* firmware needs a short delay here */ 346 347 len = IEEE80211_ADDR_LEN; 348 ipw_read_table2(sc, IPW_INFO_CURRENT_BSSID, ni->ni_bssid, &len); 349 break; 350 351 case IEEE80211_S_SCAN: 352 case IEEE80211_S_AUTH: 353 case IEEE80211_S_ASSOC: 354 break; 355 } 356 357 ic->ic_state = nstate; 358 return 0; 359 } 360 361 static void 362 ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 363 { 364 struct ipw_cmd *cmd; 365 366 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof (struct ipw_cmd), 367 BUS_DMASYNC_POSTREAD); 368 369 cmd = mtod(sbuf->m, struct ipw_cmd *); 370 371 DPRINTFN(2, ("RX!CMD!%u!%u!%u!%u!%u\n", 372 le32toh(cmd->type), le32toh(cmd->subtype), le32toh(cmd->seq), 373 le32toh(cmd->len), le32toh(cmd->status))); 374 375 /* 376 * Wake up processes waiting for command ack. In the case of the 377 * IPW_CMD_DISABLE command, wake up the process only when the adapter 378 * enters the IPW_STATE_DISABLED state. This is notified in 379 * ipw_newstate_intr(). 380 */ 381 if (le32toh(cmd->type) != IPW_CMD_DISABLE) 382 wakeup(sc->cmd); 383 } 384 385 static void 386 ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 387 { 388 struct ieee80211com *ic = &sc->sc_ic; 389 u_int32_t state; 390 391 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof state, 392 BUS_DMASYNC_POSTREAD); 393 394 state = le32toh(*mtod(sbuf->m, u_int32_t *)); 395 396 DPRINTFN(2, ("RX!NEWSTATE!%u\n", state)); 397 398 switch (state) { 399 case IPW_STATE_ASSOCIATED: 400 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 401 break; 402 403 case IPW_STATE_SCANNING: 404 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 405 break; 406 407 case IPW_STATE_ASSOCIATION_LOST: 408 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 409 break; 410 411 case IPW_STATE_DISABLED: 412 wakeup(sc->cmd); 413 break; 414 415 case IPW_STATE_RADIO_DISABLED: 416 /* XXX should turn the interface down */ 417 break; 418 } 419 } 420 421 static void 422 ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 423 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 424 { 425 struct ieee80211com *ic = &sc->sc_ic; 426 struct ifnet *ifp = &sc->sc_if; 427 struct mbuf *m; 428 struct ieee80211_frame_min *wh; 429 struct ieee80211_node *ni; 430 int error; 431 432 DPRINTFN(5, ("RX!DATA!%u!%u\n", le32toh(status->len), status->rssi)); 433 434 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, le32toh(status->len), 435 BUS_DMASYNC_POSTREAD); 436 437 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 438 439 /* Finalize mbuf */ 440 m = sbuf->m; 441 m->m_pkthdr.rcvif = ifp; 442 m->m_pkthdr.len = m->m_len = le32toh(status->len); 443 444 #if NBPFILTER > 0 445 if (sc->sc_drvbpf != NULL) { 446 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 447 448 tap->wr_flags = 0; 449 tap->wr_antsignal = status->rssi; 450 tap->wr_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 451 tap->wr_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 452 453 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 454 } 455 #endif 456 457 wh = mtod(m, struct ieee80211_frame_min *); 458 459 ni = ieee80211_find_rxnode(ic, wh); 460 461 /* Send it up to the upper layer */ 462 ieee80211_input(ic, m, ni, status->rssi, 0/*rstamp*/); 463 464 ieee80211_free_node(ni); 465 466 MGETHDR(m, M_DONTWAIT, MT_DATA); 467 if (m == NULL) { 468 aprint_error("%s: could not allocate rx mbuf\n", 469 sc->sc_dev.dv_xname); 470 return; 471 } 472 MCLGET(m, M_DONTWAIT); 473 if (!(m->m_flags & M_EXT)) { 474 m_freem(m); 475 aprint_error("%s: could not allocate rx mbuf cluster\n", 476 sc->sc_dev.dv_xname); 477 return; 478 } 479 480 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, mtod(m, void *), 481 MCLBYTES, NULL, BUS_DMA_NOWAIT); 482 if (error != 0) { 483 aprint_error("%s: could not map rxbuf dma memory\n", 484 sc->sc_dev.dv_xname); 485 m_freem(m); 486 return; 487 } 488 489 sbuf->m = m; 490 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 491 } 492 493 static void 494 ipw_notification_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 495 { 496 DPRINTFN(2, ("RX!NOTIFICATION\n")); 497 } 498 499 static void 500 ipw_rx_intr(struct ipw_softc *sc) 501 { 502 struct ipw_status *status; 503 struct ipw_soft_bd *sbd; 504 struct ipw_soft_buf *sbuf; 505 u_int32_t r, i; 506 507 r = CSR_READ_4(sc, IPW_CSR_RX_READ_INDEX); 508 509 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 510 511 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 512 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 513 BUS_DMASYNC_POSTREAD); 514 515 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 516 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 517 BUS_DMASYNC_POSTREAD); 518 519 status = &sc->status_list[i]; 520 sbd = &sc->srbd_list[i]; 521 sbuf = sbd->priv; 522 523 switch (le16toh(status->code) & 0xf) { 524 case IPW_STATUS_CODE_COMMAND: 525 ipw_command_intr(sc, sbuf); 526 break; 527 528 case IPW_STATUS_CODE_NEWSTATE: 529 ipw_newstate_intr(sc, sbuf); 530 break; 531 532 case IPW_STATUS_CODE_DATA_802_3: 533 case IPW_STATUS_CODE_DATA_802_11: 534 ipw_data_intr(sc, status, sbd, sbuf); 535 break; 536 537 case IPW_STATUS_CODE_NOTIFICATION: 538 ipw_notification_intr(sc, sbuf); 539 break; 540 541 default: 542 aprint_debug("%s: unknown status code %u\n", 543 sc->sc_dev.dv_xname, le16toh(status->code)); 544 } 545 sbd->bd->flags = 0; 546 547 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 548 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 549 BUS_DMASYNC_PREWRITE); 550 } 551 552 /* Tell the firmware what we have processed */ 553 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 554 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE_INDEX, sc->rxcur); 555 } 556 557 static void 558 ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 559 { 560 struct ieee80211com *ic; 561 struct ipw_soft_hdr *shdr; 562 struct ipw_soft_buf *sbuf; 563 564 switch (sbd->type) { 565 case IPW_SBD_TYPE_COMMAND: 566 bus_dmamap_unload(sc->sc_dmat, sc->cmd_map); 567 break; 568 569 case IPW_SBD_TYPE_HEADER: 570 shdr = sbd->priv; 571 bus_dmamap_unload(sc->sc_dmat, shdr->map); 572 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 573 break; 574 575 case IPW_SBD_TYPE_DATA: 576 ic = &sc->sc_ic; 577 sbuf = sbd->priv; 578 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 579 m_freem(sbuf->m); 580 if (sbuf->ni != NULL) 581 ieee80211_free_node(sbuf->ni); 582 /* kill watchdog timer */ 583 sc->sc_tx_timer = 0; 584 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 585 break; 586 } 587 ++sc->txfree; 588 sbd->type = IPW_SBD_TYPE_NOASSOC; 589 } 590 591 static void 592 ipw_tx_intr(struct ipw_softc *sc) 593 { 594 struct ifnet *ifp = &sc->sc_if; 595 u_int32_t r, i; 596 597 r = CSR_READ_4(sc, IPW_CSR_TX_READ_INDEX); 598 599 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) 600 ipw_release_sbd(sc, &sc->stbd_list[i]); 601 602 /* Remember what the firmware has processed */ 603 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 604 605 /* Call start() since some buffer descriptors have been released */ 606 ifp->if_flags &= ~IFF_OACTIVE; 607 (*ifp->if_start)(ifp); 608 } 609 610 static int 611 ipw_intr(void *arg) 612 { 613 struct ipw_softc *sc = arg; 614 u_int32_t r; 615 616 if ((r = CSR_READ_4(sc, IPW_CSR_INTR)) == 0) 617 return 0; 618 619 /* Disable interrupts */ 620 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 621 622 DPRINTFN(8, ("INTR!0x%08x\n", r)); 623 624 if (r & IPW_INTR_RX_TRANSFER) 625 ipw_rx_intr(sc); 626 627 if (r & IPW_INTR_TX_TRANSFER) 628 ipw_tx_intr(sc); 629 630 if (r & IPW_INTR_FW_INIT_DONE) { 631 if (!(r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR))) 632 wakeup(sc); 633 } 634 635 /* Acknowledge interrupts */ 636 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 637 638 /* Re-enable interrupts */ 639 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 640 641 return 0; 642 } 643 644 static int 645 ipw_cmd(struct ipw_softc *sc, u_int32_t type, void *data, u_int32_t len) 646 { 647 struct ipw_soft_bd *sbd; 648 int error; 649 650 #ifdef DIAGNOSTIC 651 KASSERT(sc->txfree != 0); 652 #endif /* DIAGNOSTIC */ 653 654 sbd = &sc->stbd_list[sc->txcur]; 655 656 error = bus_dmamap_load(sc->sc_dmat, sc->cmd_map, sc->cmd, 657 sizeof (struct ipw_cmd), NULL, BUS_DMA_NOWAIT); 658 if (error != 0) { 659 aprint_error("%s: could not map cmd dma memory\n", 660 sc->sc_dev.dv_xname); 661 return error; 662 } 663 664 sc->cmd->type = htole32(type); 665 sc->cmd->subtype = htole32(0); 666 sc->cmd->len = htole32(len); 667 sc->cmd->seq = htole32(0); 668 if (data != NULL) 669 bcopy(data, sc->cmd->data, len); 670 671 sbd->type = IPW_SBD_TYPE_COMMAND; 672 sbd->bd->physaddr = htole32(sc->cmd_map->dm_segs[0].ds_addr); 673 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 674 sbd->bd->nfrag = 1; 675 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 676 IPW_BD_FLAG_TX_LAST_FRAGMENT; 677 678 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 0, sizeof (struct ipw_cmd), 679 BUS_DMASYNC_PREWRITE); 680 681 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 682 sc->txcur * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 683 BUS_DMASYNC_PREWRITE); 684 685 --sc->txfree; 686 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 687 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, sc->txcur); 688 689 DPRINTFN(2, ("TX!CMD!%u!%u!%u!%u\n", type, 0, 0, len)); 690 691 /* Wait at most two seconds for command to complete */ 692 return tsleep(sc->cmd, 0, "ipwcmd", 2 * hz); 693 } 694 695 /* Check that descriptors are available to transmit one packet. 696 * Always reserve one transmit-buffer descriptor for ipw_cmd. 697 */ 698 static __inline int 699 ipw_tx_ready(struct ipw_softc *sc) 700 { 701 return !TAILQ_EMPTY(&sc->sc_free_shdr) && 702 !TAILQ_EMPTY(&sc->sc_free_sbuf) && sc->txfree > 1; 703 } 704 705 /* Must not be called unless ipw_tx_ready(sc). */ 706 static int 707 ipw_tx_start(struct ifnet *ifp, struct mbuf *m, struct ieee80211_node *ni) 708 { 709 struct ipw_softc *sc = ifp->if_softc; 710 struct ieee80211com *ic = &sc->sc_ic; 711 struct ieee80211_frame *wh; 712 struct ieee80211_key *k; 713 struct ipw_soft_bd *sbd; 714 struct ipw_soft_hdr *shdr; 715 struct ipw_soft_buf *sbuf; 716 int error, i, iswep; 717 718 #ifdef DIAGNOSTIC 719 KASSERT(ipw_tx_ready(sc)); 720 #endif 721 722 wh = mtod(m, struct ieee80211_frame *); 723 724 iswep = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0; 725 726 if (iswep && (k = ieee80211_crypto_encap(ic, ni, m)) == NULL) 727 return EIO; 728 729 #if NBPFILTER > 0 730 if (sc->sc_drvbpf != NULL) { 731 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 732 733 tap->wt_flags = 0; 734 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 735 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 736 737 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m); 738 } 739 #endif 740 741 shdr = TAILQ_FIRST(&sc->sc_free_shdr); 742 sbuf = TAILQ_FIRST(&sc->sc_free_sbuf); 743 744 shdr->hdr.type = htole32(IPW_HDR_TYPE_SEND); 745 shdr->hdr.subtype = htole32(0); 746 shdr->hdr.encrypted = iswep; 747 shdr->hdr.encrypt = 0; 748 shdr->hdr.keyidx = 0; 749 shdr->hdr.keysz = 0; 750 shdr->hdr.fragmentsz = htole16(0); 751 IEEE80211_ADDR_COPY(shdr->hdr.src_addr, wh->i_addr2); 752 if (ic->ic_opmode == IEEE80211_M_STA) 753 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr3); 754 else 755 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr1); 756 757 /* trim IEEE802.11 header */ 758 m_adj(m, sizeof (struct ieee80211_frame)); 759 760 /* 761 * We need to map the mbuf first to know how many buffer descriptors 762 * are needed for this transfer. 763 */ 764 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m, BUS_DMA_NOWAIT); 765 if (error != 0) { 766 aprint_error("%s: could not map mbuf (error %d)\n", 767 sc->sc_dev.dv_xname, error); 768 m_freem(m); 769 return error; 770 } 771 772 error = bus_dmamap_load(sc->sc_dmat, shdr->map, &shdr->hdr, 773 sizeof (struct ipw_hdr), NULL, BUS_DMA_NOWAIT); 774 if (error != 0) { 775 aprint_error("%s: could not map hdr (error %d)\n", 776 sc->sc_dev.dv_xname, error); 777 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 778 m_freem(m); 779 return error; 780 } 781 782 TAILQ_REMOVE(&sc->sc_free_sbuf, sbuf, next); 783 TAILQ_REMOVE(&sc->sc_free_shdr, shdr, next); 784 785 sbd = &sc->stbd_list[sc->txcur]; 786 sbd->type = IPW_SBD_TYPE_HEADER; 787 sbd->priv = shdr; 788 sbd->bd->physaddr = htole32(shdr->map->dm_segs[0].ds_addr); 789 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 790 sbd->bd->nfrag = 1 + sbuf->map->dm_nsegs; 791 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 792 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 793 794 DPRINTFN(5, ("TX!HDR!%u!%u!%u!%u\n", shdr->hdr.type, shdr->hdr.subtype, 795 shdr->hdr.encrypted, shdr->hdr.encrypt)); 796 DPRINTFN(5, ("!%s", ether_sprintf(shdr->hdr.src_addr))); 797 DPRINTFN(5, ("!%s\n", ether_sprintf(shdr->hdr.dst_addr))); 798 799 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 800 sc->txcur * sizeof (struct ipw_bd), 801 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 802 803 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 804 --sc->txfree; 805 806 sbuf->m = m; 807 sbuf->ni = ni; 808 809 for (i = 0; i < sbuf->map->dm_nsegs; i++) { 810 sbd = &sc->stbd_list[sc->txcur]; 811 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[i].ds_addr); 812 sbd->bd->len = htole32(sbuf->map->dm_segs[i].ds_len); 813 sbd->bd->nfrag = 0; /* used only in first bd */ 814 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 815 if (i == sbuf->map->dm_nsegs - 1) { 816 sbd->type = IPW_SBD_TYPE_DATA; 817 sbd->priv = sbuf; 818 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 819 } else { 820 sbd->type = IPW_SBD_TYPE_NOASSOC; 821 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 822 } 823 824 DPRINTFN(5, ("TX!FRAG!%d!%ld\n", i, 825 sbuf->map->dm_segs[i].ds_len)); 826 827 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 828 sc->txcur * sizeof (struct ipw_bd), 829 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 830 831 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 832 } 833 834 bus_dmamap_sync(sc->sc_dmat, shdr->map, 0, sizeof (struct ipw_hdr), 835 BUS_DMASYNC_PREWRITE); 836 837 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, MCLBYTES, 838 BUS_DMASYNC_PREWRITE); 839 840 /* Inform firmware about this new packet */ 841 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, sc->txcur); 842 843 return 0; 844 } 845 846 static void 847 ipw_start(struct ifnet *ifp) 848 { 849 struct ipw_softc *sc = ifp->if_softc; 850 struct ieee80211com *ic = &sc->sc_ic; 851 struct mbuf *m; 852 struct ieee80211_node *ni; 853 854 for (;;) { 855 if (!ipw_tx_ready(sc)) { 856 DPRINTFN(2, ("%s: no tx descriptors\n", ifp->if_xname)); 857 ifp->if_flags |= IFF_OACTIVE; 858 break; 859 } 860 IFQ_DEQUEUE(&ifp->if_snd, m); 861 if (m == NULL) 862 break; 863 864 #if NBPFILTER > 0 865 if (ifp->if_bpf != NULL) 866 bpf_mtap(ifp->if_bpf, m); 867 #endif 868 869 ni = ieee80211_find_txnode(ic, 870 mtod(m, struct ether_header *)->ether_dhost); 871 if (ni == NULL) { 872 /* NB: ieee80211_find_txnode does stat+msg */ 873 continue; 874 } 875 m = ieee80211_encap(ic, m, ni); 876 if (m == NULL) 877 continue; 878 879 #if NBPFILTER > 0 880 if (ic->ic_rawbpf != NULL) 881 bpf_mtap(ic->ic_rawbpf, m); 882 #endif 883 884 if (ipw_tx_start(ifp, m, ni) != 0) { 885 if (ni != NULL) 886 ieee80211_free_node(ni); 887 break; 888 } 889 890 /* start watchdog timer */ 891 sc->sc_tx_timer = 5; 892 ifp->if_timer = 1; 893 } 894 } 895 896 static void 897 ipw_watchdog(struct ifnet *ifp) 898 { 899 struct ipw_softc *sc = ifp->if_softc; 900 901 ifp->if_timer = 0; 902 903 if (sc->sc_tx_timer > 0) { 904 if (--sc->sc_tx_timer == 0) { 905 aprint_error("%s: device timeout\n", 906 sc->sc_dev.dv_xname); 907 #ifdef notyet 908 ipw_init(ifp); 909 #endif 910 return; 911 } 912 ifp->if_timer = 1; 913 } 914 915 ieee80211_watchdog(&sc->sc_ic); 916 } 917 918 static int 919 ipw_get_table1(struct ipw_softc *sc, u_int32_t *tbl) 920 { 921 u_int32_t addr, size, i; 922 923 if (!(sc->flags & IPW_FLAG_FW_INITED)) 924 return ENOTTY; 925 926 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, sc->table1_base); 927 928 size = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 929 if (suword(tbl, size) != 0) 930 return EFAULT; 931 932 for (i = 1, ++tbl; i < size; i++, tbl++) { 933 addr = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 934 if (suword(tbl, MEM_READ_4(sc, addr)) != 0) 935 return EFAULT; 936 } 937 return 0; 938 } 939 940 static int 941 ipw_get_radio(struct ipw_softc *sc, int *ret) 942 { 943 u_int32_t addr; 944 945 if (!(sc->flags & IPW_FLAG_FW_INITED)) 946 return ENOTTY; 947 948 addr = ipw_read_table1(sc, IPW_INFO_EEPROM_ADDRESS); 949 if ((MEM_READ_4(sc, addr + 32) >> 24) & 1) { 950 suword(ret, -1); 951 return 0; 952 } 953 954 if (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED) 955 suword(ret, 0); 956 else 957 suword(ret, 1); 958 959 return 0; 960 } 961 962 static int 963 ipw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 964 { 965 struct ipw_softc *sc = ifp->if_softc; 966 struct ifreq *ifr; 967 int s, error = 0; 968 969 s = splnet(); 970 971 switch (cmd) { 972 case SIOCSIFFLAGS: 973 if (ifp->if_flags & IFF_UP) { 974 if (!(ifp->if_flags & IFF_RUNNING)) 975 ipw_init(ifp); 976 } else { 977 if (ifp->if_flags & IFF_RUNNING) 978 ipw_stop(ifp, 1); 979 } 980 break; 981 982 case SIOCGTABLE1: 983 ifr = (struct ifreq *)data; 984 error = ipw_get_table1(sc, (u_int32_t *)ifr->ifr_data); 985 break; 986 987 case SIOCGRADIO: 988 ifr = (struct ifreq *)data; 989 error = ipw_get_radio(sc, (int *)ifr->ifr_data); 990 break; 991 992 case SIOCSLOADFW: 993 /* only super-user can do that! */ 994 if ((error = suser(curproc->p_ucred, &curproc->p_acflag)) != 0) 995 break; 996 997 ifr = (struct ifreq *)data; 998 error = ipw_firmware_init(sc, (u_char *)ifr->ifr_data); 999 break; 1000 1001 case SIOCSKILLFW: 1002 /* only super-user can do that! */ 1003 if ((error = suser(curproc->p_ucred, &curproc->p_acflag)) != 0) 1004 break; 1005 1006 ipw_reset(sc); 1007 break; 1008 1009 default: 1010 error = ieee80211_ioctl(&sc->sc_ic, cmd, data); 1011 if (error != ENETRESET) 1012 break; 1013 1014 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1015 (IFF_UP | IFF_RUNNING)) 1016 ipw_init(ifp); 1017 error = 0; 1018 } 1019 1020 splx(s); 1021 return error; 1022 } 1023 1024 static u_int32_t 1025 ipw_read_table1(struct ipw_softc *sc, u_int32_t off) 1026 { 1027 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 1028 } 1029 1030 static void 1031 ipw_write_table1(struct ipw_softc *sc, u_int32_t off, u_int32_t info) 1032 { 1033 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 1034 } 1035 1036 static int 1037 ipw_read_table2(struct ipw_softc *sc, u_int32_t off, void *buf, u_int32_t *len) 1038 { 1039 u_int32_t addr, info; 1040 u_int16_t count, size; 1041 u_int32_t total; 1042 1043 /* addr[4] + count[2] + size[2] */ 1044 addr = MEM_READ_4(sc, sc->table2_base + off); 1045 info = MEM_READ_4(sc, sc->table2_base + off + 4); 1046 1047 count = info >> 16; 1048 size = info & 0xffff; 1049 total = count * size; 1050 1051 if (total > *len) { 1052 *len = total; 1053 return EINVAL; 1054 } 1055 1056 *len = total; 1057 ipw_read_mem_1(sc, addr, buf, total); 1058 1059 return 0; 1060 } 1061 1062 static int 1063 ipw_tx_init(struct ipw_softc *sc) 1064 { 1065 const char *errmsg; 1066 struct ipw_bd *bd; 1067 struct ipw_soft_bd *sbd; 1068 struct ipw_soft_hdr *shdr; 1069 struct ipw_soft_buf *sbuf; 1070 int error, i, nsegs; 1071 1072 /* Allocate transmission buffer descriptors */ 1073 error = bus_dmamap_create(sc->sc_dmat, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, 1074 BUS_DMA_NOWAIT, &sc->tbd_map); 1075 if (error != 0) { 1076 errmsg = "could not create tbd dma map"; 1077 goto fail; 1078 } 1079 1080 error = bus_dmamem_alloc(sc->sc_dmat, IPW_TBD_SZ, PAGE_SIZE, 0, 1081 &sc->tbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 1082 if (error != 0) { 1083 errmsg = "could not allocate tbd dma memory"; 1084 goto fail; 1085 } 1086 1087 error = bus_dmamem_map(sc->sc_dmat, &sc->tbd_seg, nsegs, IPW_TBD_SZ, 1088 (caddr_t *)&sc->tbd_list, BUS_DMA_NOWAIT); 1089 if (error != 0) { 1090 errmsg = "could not map tbd dma memory"; 1091 goto fail; 1092 } 1093 1094 error = bus_dmamap_load(sc->sc_dmat, sc->tbd_map, sc->tbd_list, 1095 IPW_TBD_SZ, NULL, BUS_DMA_NOWAIT); 1096 if (error != 0) { 1097 errmsg = "could not load tbd dma memory"; 1098 goto fail; 1099 } 1100 1101 sc->stbd_list = malloc(IPW_NTBD * sizeof (struct ipw_soft_bd), 1102 M_DEVBUF, M_NOWAIT); 1103 if (sc->stbd_list == NULL) { 1104 errmsg = "could not allocate soft tbd"; 1105 error = ENOMEM; 1106 goto fail; 1107 } 1108 sbd = sc->stbd_list; 1109 bd = sc->tbd_list; 1110 for (i = 0; i < IPW_NTBD; i++, sbd++, bd++) { 1111 sbd->type = IPW_SBD_TYPE_NOASSOC; 1112 sbd->bd = bd; 1113 } 1114 1115 CSR_WRITE_4(sc, IPW_CSR_TX_BD_BASE, sc->tbd_map->dm_segs[0].ds_addr); 1116 CSR_WRITE_4(sc, IPW_CSR_TX_BD_SIZE, IPW_NTBD); 1117 CSR_WRITE_4(sc, IPW_CSR_TX_READ_INDEX, 0); 1118 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, 0); 1119 sc->txold = IPW_NTBD - 1; /* latest bd index ack'ed by firmware */ 1120 sc->txfree = IPW_NTBD; /* number of descriptors free */ 1121 sc->txcur = 0; /* bd index to write to */ 1122 1123 /* Allocate a DMA-able command */ 1124 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_cmd), 1, 1125 sizeof (struct ipw_cmd), 0, BUS_DMA_NOWAIT, &sc->cmd_map); 1126 if (error != 0) { 1127 errmsg = "could not create cmd dma map"; 1128 goto fail; 1129 } 1130 1131 error = bus_dmamem_alloc(sc->sc_dmat, sizeof (struct ipw_cmd), 1132 PAGE_SIZE, 0, &sc->cmd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 1133 if (error != 0) { 1134 errmsg = "could not allocate cmd dma memory"; 1135 goto fail; 1136 } 1137 1138 error = bus_dmamem_map(sc->sc_dmat, &sc->cmd_seg, nsegs, 1139 sizeof (struct ipw_cmd), (caddr_t *)&sc->cmd, BUS_DMA_NOWAIT); 1140 if (error != 0) { 1141 errmsg = "could not map cmd dma memory"; 1142 goto fail; 1143 } 1144 1145 /* Allocate a pool of DMA-able headers */ 1146 sc->shdr_list = malloc(IPW_NDATA * sizeof (struct ipw_soft_hdr), 1147 M_DEVBUF, M_NOWAIT); 1148 if (sc->shdr_list == NULL) { 1149 errmsg = "could not allocate soft hdr"; 1150 error = ENOMEM; 1151 goto fail; 1152 } 1153 TAILQ_INIT(&sc->sc_free_shdr); 1154 for (i = 0, shdr = sc->shdr_list; i < IPW_NDATA; i++, shdr++) { 1155 error = bus_dmamap_create(sc->sc_dmat, 1156 sizeof (struct ipw_soft_hdr), 1, 1157 sizeof (struct ipw_soft_hdr), 0, BUS_DMA_NOWAIT, 1158 &shdr->map); 1159 if (error != 0) { 1160 errmsg = "could not create hdr dma map"; 1161 goto fail; 1162 } 1163 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 1164 } 1165 1166 /* Allocate a pool of DMA-able buffers */ 1167 sc->tx_sbuf_list = malloc(IPW_NDATA * sizeof (struct ipw_soft_buf), 1168 M_DEVBUF, M_NOWAIT); 1169 if (sc->tx_sbuf_list == NULL) { 1170 errmsg = "could not allocate soft txbuf"; 1171 error = ENOMEM; 1172 goto fail; 1173 } 1174 TAILQ_INIT(&sc->sc_free_sbuf); 1175 for (i = 0, sbuf = sc->tx_sbuf_list; i < IPW_NDATA; i++, sbuf++) { 1176 error = bus_dmamap_create(sc->sc_dmat, IPW_NDATA * MCLBYTES, 1177 IPW_NDATA, MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 1178 if (error != 0) { 1179 errmsg = "could not create txbuf dma map"; 1180 goto fail; 1181 } 1182 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 1183 } 1184 1185 return 0; 1186 1187 fail: aprint_error("%s: %s\n", sc->sc_dev.dv_xname, errmsg); 1188 ipw_tx_stop(sc); 1189 1190 return error; 1191 } 1192 1193 static void 1194 ipw_tx_stop(struct ipw_softc *sc) 1195 { 1196 struct ipw_soft_hdr *shdr; 1197 struct ipw_soft_buf *sbuf; 1198 int i; 1199 1200 if (sc->tbd_map != NULL) { 1201 if (sc->tbd_list != NULL) { 1202 bus_dmamap_unload(sc->sc_dmat, sc->tbd_map); 1203 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->tbd_list, 1204 IPW_TBD_SZ); 1205 bus_dmamem_free(sc->sc_dmat, &sc->tbd_seg, 1); 1206 sc->tbd_list = NULL; 1207 } 1208 bus_dmamap_destroy(sc->sc_dmat, sc->tbd_map); 1209 sc->tbd_map = NULL; 1210 } 1211 1212 if (sc->stbd_list != NULL) { 1213 for (i = 0; i < IPW_NTBD; i++) 1214 ipw_release_sbd(sc, &sc->stbd_list[i]); 1215 free(sc->stbd_list, M_DEVBUF); 1216 sc->stbd_list = NULL; 1217 } 1218 1219 if (sc->cmd_map != NULL) { 1220 if (sc->cmd != NULL) { 1221 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->cmd, 1222 sizeof (struct ipw_cmd)); 1223 bus_dmamem_free(sc->sc_dmat, &sc->cmd_seg, 1); 1224 sc->cmd = NULL; 1225 } 1226 bus_dmamap_destroy(sc->sc_dmat, sc->cmd_map); 1227 sc->cmd_map = NULL; 1228 } 1229 1230 if (sc->shdr_list != NULL) { 1231 TAILQ_FOREACH(shdr, &sc->sc_free_shdr, next) 1232 bus_dmamap_destroy(sc->sc_dmat, shdr->map); 1233 free(sc->shdr_list, M_DEVBUF); 1234 sc->shdr_list = NULL; 1235 } 1236 1237 1238 if (sc->tx_sbuf_list != NULL) { 1239 TAILQ_FOREACH(sbuf, &sc->sc_free_sbuf, next) 1240 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 1241 free(sc->tx_sbuf_list, M_DEVBUF); 1242 sc->tx_sbuf_list = NULL; 1243 } 1244 } 1245 1246 static int 1247 ipw_rx_init(struct ipw_softc *sc) 1248 { 1249 const char *errmsg; 1250 struct ipw_bd *bd; 1251 struct ipw_soft_bd *sbd; 1252 struct ipw_soft_buf *sbuf; 1253 int error, i, nsegs; 1254 1255 /* Allocate reception buffer descriptors */ 1256 error = bus_dmamap_create(sc->sc_dmat, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, 1257 BUS_DMA_NOWAIT, &sc->rbd_map); 1258 if (error != 0) { 1259 errmsg = "could not create rbd dma map"; 1260 goto fail; 1261 } 1262 1263 error = bus_dmamem_alloc(sc->sc_dmat, IPW_RBD_SZ, PAGE_SIZE, 0, 1264 &sc->rbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 1265 if (error != 0) { 1266 errmsg = "could not allocate rbd dma memory"; 1267 goto fail; 1268 } 1269 1270 error = bus_dmamem_map(sc->sc_dmat, &sc->rbd_seg, nsegs, IPW_RBD_SZ, 1271 (caddr_t *)&sc->rbd_list, BUS_DMA_NOWAIT); 1272 if (error != 0) { 1273 errmsg = "could not map rbd dma memory"; 1274 goto fail; 1275 } 1276 1277 error = bus_dmamap_load(sc->sc_dmat, sc->rbd_map, sc->rbd_list, 1278 IPW_RBD_SZ, NULL, BUS_DMA_NOWAIT); 1279 if (error != 0) { 1280 errmsg = "could not load rbd dma memory"; 1281 goto fail; 1282 } 1283 1284 sc->srbd_list = malloc(IPW_NRBD * sizeof (struct ipw_soft_bd), 1285 M_DEVBUF, M_NOWAIT); 1286 if (sc->srbd_list == NULL) { 1287 errmsg = "could not allocate soft rbd"; 1288 error = ENOMEM; 1289 goto fail; 1290 } 1291 sbd = sc->srbd_list; 1292 bd = sc->rbd_list; 1293 for (i = 0; i < IPW_NRBD; i++, sbd++, bd++) { 1294 sbd->type = IPW_SBD_TYPE_NOASSOC; 1295 sbd->bd = bd; 1296 } 1297 1298 CSR_WRITE_4(sc, IPW_CSR_RX_BD_BASE, sc->rbd_map->dm_segs[0].ds_addr); 1299 CSR_WRITE_4(sc, IPW_CSR_RX_BD_SIZE, IPW_NRBD); 1300 CSR_WRITE_4(sc, IPW_CSR_RX_READ_INDEX, 0); 1301 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE_INDEX, IPW_NRBD - 1); 1302 sc->rxcur = IPW_NRBD - 1; /* latest bd index I've read */ 1303 1304 /* Allocate status descriptors */ 1305 error = bus_dmamap_create(sc->sc_dmat, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 1306 0, BUS_DMA_NOWAIT, &sc->status_map); 1307 if (error != 0) { 1308 errmsg = "could not create status dma map"; 1309 goto fail; 1310 } 1311 1312 error = bus_dmamem_alloc(sc->sc_dmat, IPW_STATUS_SZ, PAGE_SIZE, 0, 1313 &sc->status_seg, 1, &nsegs, BUS_DMA_NOWAIT); 1314 if (error != 0) { 1315 errmsg = "could not allocate status dma memory"; 1316 goto fail; 1317 } 1318 1319 error = bus_dmamem_map(sc->sc_dmat, &sc->status_seg, nsegs, 1320 IPW_STATUS_SZ, (caddr_t *)&sc->status_list, BUS_DMA_NOWAIT); 1321 if (error != 0) { 1322 errmsg = "could not map status dma memory"; 1323 goto fail; 1324 } 1325 1326 error = bus_dmamap_load(sc->sc_dmat, sc->status_map, sc->status_list, 1327 IPW_STATUS_SZ, NULL, BUS_DMA_NOWAIT); 1328 if (error != 0) { 1329 errmsg = "could not load status dma memory"; 1330 goto fail; 1331 } 1332 1333 CSR_WRITE_4(sc, IPW_CSR_RX_STATUS_BASE, 1334 sc->status_map->dm_segs[0].ds_addr); 1335 1336 sc->rx_sbuf_list = malloc(IPW_NRBD * sizeof (struct ipw_soft_buf), 1337 M_DEVBUF, M_NOWAIT); 1338 if (sc->rx_sbuf_list == NULL) { 1339 errmsg = "could not allocate soft rxbuf"; 1340 error = ENOMEM; 1341 goto fail; 1342 } 1343 1344 sbuf = sc->rx_sbuf_list; 1345 sbd = sc->srbd_list; 1346 for (i = 0; i < IPW_NRBD; i++, sbuf++, sbd++) { 1347 1348 MGETHDR(sbuf->m, M_DONTWAIT, MT_DATA); 1349 if (sbuf->m == NULL) { 1350 errmsg = "could not allocate rx mbuf"; 1351 error = ENOMEM; 1352 goto fail; 1353 } 1354 MCLGET(sbuf->m, M_DONTWAIT); 1355 if (!(sbuf->m->m_flags & M_EXT)) { 1356 m_freem(sbuf->m); 1357 errmsg = "could not allocate rx mbuf cluster"; 1358 error = ENOMEM; 1359 goto fail; 1360 } 1361 1362 error = bus_dmamap_create(sc->sc_dmat, IPW_NRBD * MCLBYTES, 1363 IPW_NRBD, MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 1364 if (error != 0) { 1365 m_freem(sbuf->m); 1366 errmsg = "could not create rxbuf dma map"; 1367 goto fail; 1368 } 1369 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, 1370 mtod(sbuf->m, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 1371 if (error != 0) { 1372 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 1373 m_freem(sbuf->m); 1374 errmsg = "could not map rxbuf dma memory"; 1375 goto fail; 1376 } 1377 sbd->type = IPW_SBD_TYPE_DATA; 1378 sbd->priv = sbuf; 1379 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 1380 sbd->bd->len = htole32(MCLBYTES); 1381 } 1382 1383 return 0; 1384 1385 fail: aprint_error("%s: %s\n", sc->sc_dev.dv_xname, errmsg); 1386 ipw_rx_stop(sc); 1387 1388 return error; 1389 } 1390 1391 static void 1392 ipw_rx_stop(struct ipw_softc *sc) 1393 { 1394 struct ipw_soft_bd *sbd; 1395 struct ipw_soft_buf *sbuf; 1396 int i; 1397 1398 if (sc->rbd_map != NULL) { 1399 if (sc->rbd_list != NULL) { 1400 bus_dmamap_unload(sc->sc_dmat, sc->rbd_map); 1401 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->rbd_list, 1402 IPW_RBD_SZ); 1403 bus_dmamem_free(sc->sc_dmat, &sc->rbd_seg, 1); 1404 sc->rbd_list = NULL; 1405 } 1406 bus_dmamap_destroy(sc->sc_dmat, sc->rbd_map); 1407 sc->rbd_map = NULL; 1408 } 1409 1410 if (sc->status_map != NULL) { 1411 if (sc->status_list != NULL) { 1412 bus_dmamap_unload(sc->sc_dmat, sc->status_map); 1413 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->status_list, 1414 IPW_STATUS_SZ); 1415 bus_dmamem_free(sc->sc_dmat, &sc->status_seg, 1); 1416 sc->status_list = NULL; 1417 } 1418 bus_dmamap_destroy(sc->sc_dmat, sc->status_map); 1419 sc->status_map = NULL; 1420 } 1421 1422 if (sc->srbd_list != NULL) { 1423 for (i = 0, sbd = sc->srbd_list; i < IPW_NRBD; i++, sbd++) { 1424 if (sbd->type == IPW_SBD_TYPE_NOASSOC) 1425 continue; 1426 1427 sbuf = sbd->priv; 1428 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1429 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 1430 m_freem(sbuf->m); 1431 } 1432 free(sc->srbd_list, M_DEVBUF); 1433 sc->srbd_list = NULL; 1434 } 1435 1436 if (sc->rx_sbuf_list != NULL) { 1437 free(sc->rx_sbuf_list, M_DEVBUF); 1438 sc->rx_sbuf_list = NULL; 1439 } 1440 } 1441 1442 static void 1443 ipw_reset(struct ipw_softc *sc) 1444 { 1445 struct ifnet *ifp = &sc->sc_if; 1446 int ntries; 1447 1448 ipw_stop(ifp, 1); 1449 1450 if (sc->flags & IPW_FLAG_FW_INITED) { 1451 ipw_cmd(sc, IPW_CMD_DISABLE_PHY, NULL, 0); 1452 ipw_cmd(sc, IPW_CMD_PREPARE_POWER_DOWN, NULL, 0); 1453 1454 sc->flags &= ~IPW_FLAG_FW_INITED; 1455 } 1456 1457 /* Disable interrupts */ 1458 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1459 1460 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1461 for (ntries = 0; ntries < 5; ntries++) { 1462 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1463 break; 1464 DELAY(10); 1465 } 1466 1467 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 1468 1469 ipw_rx_stop(sc); 1470 ipw_tx_stop(sc); 1471 1472 ifp->if_flags &= ~IFF_UP; 1473 } 1474 1475 static int 1476 ipw_clock_sync(struct ipw_softc *sc) 1477 { 1478 int ntries; 1479 u_int32_t r; 1480 1481 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 1482 for (ntries = 0; ntries < 1000; ntries++) { 1483 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_PRINCETON_RESET) 1484 break; 1485 DELAY(10); 1486 } 1487 if (ntries == 1000) 1488 return EIO; 1489 1490 CSR_WRITE_4(sc, IPW_CSR_CTL, IPW_CTL_INIT_DONE); 1491 for (ntries = 0; ntries < 1000; ntries++) { 1492 if ((r = CSR_READ_4(sc, IPW_CSR_CTL)) & IPW_CTL_CLOCK_READY) 1493 break; 1494 DELAY(200); 1495 } 1496 if (ntries == 1000) 1497 return EIO; 1498 1499 CSR_WRITE_4(sc, IPW_CSR_CTL, r | IPW_CTL_ALLOW_STANDBY); 1500 1501 return 0; 1502 } 1503 1504 static int 1505 ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size) 1506 { 1507 int ntries; 1508 1509 MEM_WRITE_2(sc, 0x220000, 0x0703); 1510 MEM_WRITE_2(sc, 0x220000, 0x0707); 1511 1512 MEM_WRITE_1(sc, 0x210014, 0x72); 1513 MEM_WRITE_1(sc, 0x210014, 0x72); 1514 1515 MEM_WRITE_1(sc, 0x210000, 0x40); 1516 MEM_WRITE_1(sc, 0x210000, 0x00); 1517 MEM_WRITE_1(sc, 0x210000, 0x40); 1518 1519 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1520 1521 MEM_WRITE_1(sc, 0x210000, 0x00); 1522 MEM_WRITE_1(sc, 0x210000, 0x00); 1523 MEM_WRITE_1(sc, 0x210000, 0x80); 1524 1525 MEM_WRITE_2(sc, 0x220000, 0x0703); 1526 MEM_WRITE_2(sc, 0x220000, 0x0707); 1527 1528 MEM_WRITE_1(sc, 0x210014, 0x72); 1529 MEM_WRITE_1(sc, 0x210014, 0x72); 1530 1531 MEM_WRITE_1(sc, 0x210000, 0x00); 1532 MEM_WRITE_1(sc, 0x210000, 0x80); 1533 1534 for (ntries = 0; ntries < 10; ntries++) { 1535 if (MEM_READ_1(sc, 0x210000) & 1) 1536 break; 1537 DELAY(10); 1538 } 1539 if (ntries == 10) 1540 return EIO; 1541 1542 return 0; 1543 } 1544 1545 /* set of macros to handle unaligned little endian data in firmware image */ 1546 #define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1547 #define GETLE16(p) ((p)[0] | (p)[1] << 8) 1548 static int 1549 ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size) 1550 { 1551 u_char *p, *end; 1552 u_int32_t addr; 1553 u_int16_t len; 1554 1555 p = fw; 1556 end = fw + size; 1557 while (p < end) { 1558 if (p + 6 > end) 1559 return EINVAL; 1560 1561 addr = GETLE32(p); 1562 p += 4; 1563 len = GETLE16(p); 1564 p += 2; 1565 1566 if (p + len > end) 1567 return EINVAL; 1568 1569 ipw_write_mem_1(sc, addr, p, len); 1570 p += len; 1571 } 1572 return 0; 1573 } 1574 1575 static int 1576 ipw_firmware_init(struct ipw_softc *sc, u_char *data) 1577 { 1578 struct ieee80211com *ic = &sc->sc_ic; 1579 struct ifnet *ifp = &sc->sc_if; 1580 struct ipw_fw_hdr hdr; 1581 u_int32_t r, len, fw_size, uc_size; 1582 u_char *fw, *uc; 1583 int error; 1584 1585 ipw_reset(sc); 1586 1587 if ((error = copyin(data, &hdr, sizeof hdr)) != 0) 1588 goto fail1; 1589 1590 fw_size = le32toh(hdr.fw_size); 1591 uc_size = le32toh(hdr.uc_size); 1592 data += sizeof hdr; 1593 1594 if ((fw = malloc(fw_size, M_DEVBUF, M_NOWAIT)) == NULL) { 1595 error = ENOMEM; 1596 goto fail1; 1597 } 1598 1599 if ((error = copyin(data, fw, fw_size)) != 0) 1600 goto fail2; 1601 1602 data += fw_size; 1603 1604 if ((uc = malloc(uc_size, M_DEVBUF, M_NOWAIT)) == NULL) { 1605 error = ENOMEM; 1606 goto fail2; 1607 } 1608 1609 if ((error = copyin(data, uc, uc_size)) != 0) 1610 goto fail3; 1611 1612 if ((error = ipw_clock_sync(sc)) != 0) { 1613 aprint_error("%s: clock synchronization failed\n", 1614 sc->sc_dev.dv_xname); 1615 goto fail3; 1616 } 1617 1618 MEM_WRITE_4(sc, 0x003000e0, 0x80000000); 1619 1620 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1621 1622 if ((error = ipw_load_ucode(sc, uc, uc_size)) != 0) { 1623 aprint_error("%s: could not load microcode\n", 1624 sc->sc_dev.dv_xname); 1625 goto fail3; 1626 } 1627 1628 MEM_WRITE_4(sc, 0x003000e0, 0); 1629 1630 if ((error = ipw_clock_sync(sc)) != 0) { 1631 aprint_error("%s: clock synchronization failed\n", 1632 sc->sc_dev.dv_xname); 1633 goto fail3; 1634 } 1635 1636 if ((error = ipw_load_firmware(sc, fw, fw_size))) { 1637 aprint_error("%s: could not load firmware\n", 1638 sc->sc_dev.dv_xname); 1639 goto fail3; 1640 } 1641 1642 ipw_zero_mem_4(sc, 0x0002f200, 196); 1643 ipw_zero_mem_4(sc, 0x0002f610, 8); 1644 ipw_zero_mem_4(sc, 0x0002fa00, 8); 1645 ipw_zero_mem_4(sc, 0x0002fc00, 4); 1646 ipw_zero_mem_4(sc, 0x0002ff80, 32); 1647 1648 if ((error = ipw_rx_init(sc)) != 0) { 1649 aprint_error("%s: could not initialize rx queue\n", 1650 sc->sc_dev.dv_xname); 1651 goto fail3; 1652 } 1653 1654 if ((error = ipw_tx_init(sc)) != 0) { 1655 aprint_error("%s: could not initialize tx queue\n", 1656 sc->sc_dev.dv_xname); 1657 goto fail3; 1658 } 1659 1660 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1661 IPW_IO_LED_OFF); 1662 1663 /* Enable interrupts */ 1664 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1665 1666 /* Let's go! */ 1667 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1668 1669 /* Wait at most 5 seconds for firmware initialization to complete */ 1670 if ((error = tsleep(sc, 0, "ipwinit", 5 * hz)) != 0) { 1671 aprint_error("%s: timeout waiting for firmware initialization " 1672 "to complete\n", sc->sc_dev.dv_xname); 1673 goto fail3; 1674 } 1675 1676 /* Firmware initialization completed */ 1677 sc->flags |= IPW_FLAG_FW_INITED; 1678 1679 free(uc, M_DEVBUF); 1680 free(fw, M_DEVBUF); 1681 1682 r = CSR_READ_4(sc, IPW_CSR_IO); 1683 CSR_WRITE_4(sc, IPW_CSR_IO, r | IPW_IO_GPIO1_MASK | IPW_IO_GPIO3_MASK); 1684 1685 /* Retrieve information tables base addresses */ 1686 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 1687 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 1688 1689 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 1690 1691 /* Retrieve adapter MAC address */ 1692 len = IEEE80211_ADDR_LEN; 1693 ipw_read_table2(sc, IPW_INFO_ADAPTER_MAC, ic->ic_myaddr, &len); 1694 1695 IEEE80211_ADDR_COPY(LLADDR(ifp->if_sadl), ic->ic_myaddr); 1696 1697 return 0; 1698 1699 fail3: free(uc, M_DEVBUF); 1700 fail2: free(fw, M_DEVBUF); 1701 fail1: ipw_reset(sc); 1702 1703 return error; 1704 } 1705 1706 static int 1707 ipw_config(struct ipw_softc *sc) 1708 { 1709 struct ieee80211com *ic = &sc->sc_ic; 1710 struct ifnet *ifp = &sc->sc_if; 1711 struct ipw_security security; 1712 struct ieee80211_key *k; 1713 struct ipw_wep_key wepkey; 1714 struct ipw_scan_options options; 1715 struct ipw_configuration config; 1716 u_int32_t data; 1717 int error, i; 1718 1719 switch (ic->ic_opmode) { 1720 case IEEE80211_M_STA: 1721 case IEEE80211_M_HOSTAP: 1722 data = htole32(IPW_MODE_BSS); 1723 break; 1724 1725 case IEEE80211_M_IBSS: 1726 case IEEE80211_M_AHDEMO: 1727 data = htole32(IPW_MODE_IBSS); 1728 break; 1729 1730 case IEEE80211_M_MONITOR: 1731 data = htole32(IPW_MODE_MONITOR); 1732 break; 1733 } 1734 DPRINTF(("Setting adapter mode to %u\n", data)); 1735 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 1736 if (error != 0) 1737 return error; 1738 1739 if (ic->ic_opmode == IEEE80211_M_IBSS || 1740 ic->ic_opmode == IEEE80211_M_MONITOR) { 1741 data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); 1742 DPRINTF(("Setting adapter channel to %u\n", data)); 1743 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 1744 if (error != 0) 1745 return error; 1746 } 1747 1748 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1749 DPRINTF(("Enabling adapter\n")); 1750 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1751 } 1752 1753 DPRINTF(("Setting adapter MAC to %s\n", ether_sprintf(ic->ic_myaddr))); 1754 IEEE80211_ADDR_COPY(LLADDR(ifp->if_sadl), ic->ic_myaddr); 1755 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 1756 IEEE80211_ADDR_LEN); 1757 if (error != 0) 1758 return error; 1759 1760 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 1761 IPW_CFG_PREAMBLE_LEN | IPW_CFG_802_1x_ENABLE); 1762 if (ic->ic_opmode == IEEE80211_M_IBSS) 1763 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 1764 if (ifp->if_flags & IFF_PROMISC) 1765 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 1766 config.channels = htole32(0x3fff); /* channels 1-14 */ 1767 config.ibss_chan = htole32(0x7ff); 1768 DPRINTF(("Setting adapter configuration 0x%08x\n", config.flags)); 1769 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 1770 if (error != 0) 1771 return error; 1772 1773 data = htole32(0x3); /* 1, 2 */ 1774 DPRINTF(("Setting adapter basic tx rates to 0x%x\n", data)); 1775 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 1776 if (error != 0) 1777 return error; 1778 1779 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 1780 DPRINTF(("Setting adapter tx rates to 0x%x\n", data)); 1781 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 1782 if (error != 0) 1783 return error; 1784 1785 data = htole32(IPW_POWER_MODE_CAM); 1786 DPRINTF(("Setting adapter power mode to %u\n", data)); 1787 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 1788 if (error != 0) 1789 return error; 1790 1791 if (ic->ic_opmode == IEEE80211_M_IBSS) { 1792 data = htole32(ic->ic_bss->ni_txpower); 1793 DPRINTF(("Setting adapter tx power index to %u\n", data)); 1794 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 1795 sizeof data); 1796 if (error != 0) 1797 return error; 1798 } 1799 1800 data = htole32(ic->ic_rtsthreshold); 1801 DPRINTF(("Setting adapter RTS threshold to %u\n", data)); 1802 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 1803 if (error != 0) 1804 return error; 1805 1806 data = htole32(ic->ic_fragthreshold); 1807 DPRINTF(("Setting adapter frag threshold to %u\n", data)); 1808 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 1809 if (error != 0) 1810 return error; 1811 1812 #ifdef IPW_DEBUG 1813 if (ipw_debug > 0) { 1814 printf("Setting adapter ESSID to "); 1815 ieee80211_print_essid(ic->ic_des_essid, ic->ic_des_esslen); 1816 printf("\n"); 1817 } 1818 #endif 1819 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ic->ic_des_essid, 1820 ic->ic_des_esslen); 1821 if (error != 0) 1822 return error; 1823 1824 /* no mandatory BSSID */ 1825 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 1826 if (error != 0) 1827 return error; 1828 1829 if (ic->ic_flags & IEEE80211_F_DESBSSID) { 1830 DPRINTF(("Setting adapter desired BSSID to %s\n", 1831 ether_sprintf(ic->ic_des_bssid))); 1832 error = ipw_cmd(sc, IPW_CMD_SET_DESIRED_BSSID, 1833 ic->ic_des_bssid, IEEE80211_ADDR_LEN); 1834 if (error != 0) 1835 return error; 1836 } 1837 1838 security.authmode = IPW_AUTH_OPEN; 1839 security.ciphers = htole32(IPW_CIPHER_NONE); 1840 security.version = htole16(0); 1841 security.replay_counters_number = 0; 1842 security.unicast_using_group = 0; 1843 DPRINTF(("Setting adapter authmode to %u\n", security.authmode)); 1844 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 1845 sizeof security); 1846 if (error != 0) 1847 return error; 1848 1849 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 1850 k = ic->ic_nw_keys; 1851 for (i = 0; i < IEEE80211_WEP_NKID; i++, k++) { 1852 if (k->wk_keylen == 0) 1853 continue; 1854 1855 wepkey.idx = i; 1856 wepkey.len = k->wk_keylen; 1857 bzero(wepkey.key, sizeof wepkey.key); 1858 bcopy(k->wk_key, wepkey.key, k->wk_keylen); 1859 DPRINTF(("Setting wep key index %d len %d\n", 1860 wepkey.idx, wepkey.len)); 1861 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY, &wepkey, 1862 sizeof wepkey); 1863 if (error != 0) 1864 return error; 1865 } 1866 1867 data = htole32(ic->ic_def_txkey); 1868 DPRINTF(("Setting adapter tx key index to %u\n", data)); 1869 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY_INDEX, &data, 1870 sizeof data); 1871 if (error != 0) 1872 return error; 1873 } 1874 1875 data = htole32((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) ? 0x8 : 0); 1876 DPRINTF(("Setting adapter wep flags to 0x%x\n", data)); 1877 error = ipw_cmd(sc, IPW_CMD_SET_WEP_FLAGS, &data, sizeof data); 1878 if (error != 0) 1879 return error; 1880 1881 if (ic->ic_opmode == IEEE80211_M_IBSS || 1882 ic->ic_opmode == IEEE80211_M_HOSTAP) { 1883 data = htole32(ic->ic_lintval); 1884 DPRINTF(("Setting adapter beacon interval to %u\n", data)); 1885 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 1886 sizeof data); 1887 if (error != 0) 1888 return error; 1889 } 1890 1891 options.flags = htole32(0); 1892 options.channels = htole32(0x3fff); /* scan channels 1-14 */ 1893 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &options, sizeof options); 1894 if (error != 0) 1895 return error; 1896 1897 /* finally, enable adapter (start scanning for an access point) */ 1898 DPRINTF(("Enabling adapter\n")); 1899 error = ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1900 if (error != 0) 1901 return error; 1902 1903 return 0; 1904 } 1905 1906 static int 1907 ipw_init(struct ifnet *ifp) 1908 { 1909 struct ipw_softc *sc = ifp->if_softc; 1910 struct ieee80211com *ic = &sc->sc_ic; 1911 1912 /* exit immediately if firmware has not been ioctl'd */ 1913 if (!(sc->flags & IPW_FLAG_FW_INITED)) { 1914 ifp->if_flags &= ~IFF_UP; 1915 return EIO; 1916 } 1917 1918 ipw_stop(ifp, 0); 1919 1920 if (ipw_config(sc) != 0) { 1921 aprint_error("%s: device configuration failed\n", 1922 sc->sc_dev.dv_xname); 1923 goto fail; 1924 } 1925 1926 ifp->if_flags &= ~IFF_OACTIVE; 1927 ifp->if_flags |= IFF_RUNNING; 1928 1929 ic->ic_bss->ni_chan = ic->ic_channels; 1930 1931 return 0; 1932 1933 fail: ipw_stop(ifp, 0); 1934 1935 return EIO; 1936 } 1937 1938 static void 1939 ipw_stop(struct ifnet *ifp, int disable) 1940 { 1941 struct ipw_softc *sc = ifp->if_softc; 1942 struct ieee80211com *ic = &sc->sc_ic; 1943 1944 if (ifp->if_flags & IFF_RUNNING) { 1945 DPRINTF(("Disabling adapter\n")); 1946 ipw_cmd(sc, IPW_CMD_DISABLE, NULL, 0); 1947 } 1948 1949 ifp->if_timer = 0; 1950 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1951 1952 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1953 } 1954 1955 static void 1956 ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, u_int8_t *datap, 1957 bus_size_t count) 1958 { 1959 for (; count > 0; offset++, datap++, count--) { 1960 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 1961 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 1962 } 1963 } 1964 1965 static void 1966 ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, u_int8_t *datap, 1967 bus_size_t count) 1968 { 1969 for (; count > 0; offset++, datap++, count--) { 1970 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 1971 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 1972 } 1973 } 1974 1975 static void 1976 ipw_zero_mem_4(struct ipw_softc *sc, bus_size_t offset, bus_size_t count) 1977 { 1978 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, offset); 1979 while (count-- > 0) 1980 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_DATA, 0); 1981 } 1982 1983
Indexes created Mon Sep 29 21:09:56 GMT 2025