if_ipw.c revision 1.16.10.2
1 /* $NetBSD: if_ipw.c,v 1.16.10.2 2006/03/10 14:39:02 elad Exp $ */ 2 /* FreeBSD: src/sys/dev/ipw/if_ipw.c,v 1.15 2005/11/13 17:17:40 damien Exp */ 3 4 /*- 5 * Copyright (c) 2004, 2005 6 * Damien Bergamini <damien.bergamini (at) free.fr>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: if_ipw.c,v 1.16.10.2 2006/03/10 14:39:02 elad Exp $"); 33 34 /*- 35 * Intel(R) PRO/Wireless 2100 MiniPCI driver 36 * http://www.intel.com/network/connectivity/products/wireless/prowireless_mobile.htm 37 */ 38 39 #include "bpfilter.h" 40 41 #include <sys/param.h> 42 #include <sys/sockio.h> 43 #include <sys/sysctl.h> 44 #include <sys/mbuf.h> 45 #include <sys/kernel.h> 46 #include <sys/socket.h> 47 #include <sys/systm.h> 48 #include <sys/malloc.h> 49 #include <sys/conf.h> 50 51 #include <machine/bus.h> 52 #include <machine/endian.h> 53 #include <machine/intr.h> 54 55 #include <dev/pci/pcireg.h> 56 #include <dev/pci/pcivar.h> 57 #include <dev/pci/pcidevs.h> 58 59 #if NBPFILTER > 0 60 #include <net/bpf.h> 61 #endif 62 #include <net/if.h> 63 #include <net/if_arp.h> 64 #include <net/if_dl.h> 65 #include <net/if_ether.h> 66 #include <net/if_media.h> 67 #include <net/if_types.h> 68 69 #include <net80211/ieee80211_var.h> 70 #include <net80211/ieee80211_radiotap.h> 71 72 #include <netinet/in.h> 73 #include <netinet/in_systm.h> 74 #include <netinet/in_var.h> 75 #include <netinet/ip.h> 76 77 #include <dev/pci/if_ipwreg.h> 78 #include <dev/pci/if_ipwvar.h> 79 80 #ifdef IPW_DEBUG 81 #define DPRINTF(x) if (ipw_debug > 0) printf x 82 #define DPRINTFN(n, x) if (ipw_debug >= (n)) printf x 83 int ipw_debug = 0; 84 #else 85 #define DPRINTF(x) 86 #define DPRINTFN(n, x) 87 #endif 88 89 static int ipw_dma_alloc(struct ipw_softc *); 90 static void ipw_release(struct ipw_softc *); 91 static int ipw_match(struct device *, struct cfdata *, void *); 92 static void ipw_attach(struct device *, struct device *, void *); 93 static int ipw_detach(struct device *, int); 94 95 static void ipw_shutdown(void *); 96 static int ipw_suspend(struct ipw_softc *); 97 static int ipw_resume(struct ipw_softc *); 98 static void ipw_powerhook(int, void *); 99 100 static int ipw_media_change(struct ifnet *); 101 static void ipw_media_status(struct ifnet *, struct ifmediareq *); 102 static int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 103 static uint16_t ipw_read_prom_word(struct ipw_softc *, uint8_t); 104 static void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 105 static void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 106 static void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 107 struct ipw_soft_bd *, struct ipw_soft_buf *); 108 static void ipw_rx_intr(struct ipw_softc *); 109 static void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 110 static void ipw_tx_intr(struct ipw_softc *); 111 static int ipw_intr(void *); 112 static int ipw_cmd(struct ipw_softc *, uint32_t, void *, uint32_t); 113 static int ipw_tx_start(struct ifnet *, struct mbuf *, 114 struct ieee80211_node *); 115 static void ipw_start(struct ifnet *); 116 static void ipw_watchdog(struct ifnet *); 117 static int ipw_ioctl(struct ifnet *, u_long, caddr_t); 118 static int ipw_get_table1(struct ipw_softc *, uint32_t *); 119 static int ipw_get_radio(struct ipw_softc *, int *); 120 static void ipw_stop_master(struct ipw_softc *); 121 static int ipw_reset(struct ipw_softc *); 122 static int ipw_load_ucode(struct ipw_softc *, u_char *, int); 123 static int ipw_load_firmware(struct ipw_softc *, u_char *, int); 124 static int ipw_cache_firmware(struct ipw_softc *, void *); 125 static void ipw_free_firmware(struct ipw_softc *); 126 static int ipw_config(struct ipw_softc *); 127 static int ipw_init(struct ifnet *); 128 static void ipw_stop(struct ifnet *, int); 129 static uint32_t ipw_read_table1(struct ipw_softc *, uint32_t); 130 static void ipw_write_table1(struct ipw_softc *, uint32_t, uint32_t); 131 static int ipw_read_table2(struct ipw_softc *, uint32_t, void *, uint32_t *); 132 static void ipw_read_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 133 bus_size_t); 134 static void ipw_write_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 135 bus_size_t); 136 137 /* 138 * Supported rates for 802.11b mode (in 500Kbps unit). 139 */ 140 static const struct ieee80211_rateset ipw_rateset_11b = 141 { 4, { 2, 4, 11, 22 } }; 142 143 static inline uint8_t 144 MEM_READ_1(struct ipw_softc *sc, uint32_t addr) 145 { 146 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 147 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); 148 } 149 150 static inline uint32_t 151 MEM_READ_4(struct ipw_softc *sc, uint32_t addr) 152 { 153 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 154 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); 155 } 156 157 CFATTACH_DECL(ipw, sizeof (struct ipw_softc), ipw_match, ipw_attach, 158 ipw_detach, NULL); 159 160 static int 161 ipw_match(struct device *parent, struct cfdata *match, void *aux) 162 { 163 struct pci_attach_args *pa = aux; 164 165 if (PCI_VENDOR (pa->pa_id) == PCI_VENDOR_INTEL && 166 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_PRO_WL_2100) 167 return 1; 168 169 return 0; 170 } 171 172 /* Base Address Register */ 173 #define IPW_PCI_BAR0 0x10 174 175 static void 176 ipw_attach(struct device *parent, struct device *self, void *aux) 177 { 178 struct ipw_softc *sc = (struct ipw_softc *)self; 179 struct ieee80211com *ic = &sc->sc_ic; 180 struct ifnet *ifp = &sc->sc_if; 181 struct pci_attach_args *pa = aux; 182 const char *intrstr; 183 char devinfo[256]; 184 bus_space_tag_t memt; 185 bus_space_handle_t memh; 186 bus_addr_t base; 187 pci_intr_handle_t ih; 188 uint32_t data; 189 uint16_t val; 190 int i, revision, error; 191 192 sc->sc_pct = pa->pa_pc; 193 sc->sc_pcitag = pa->pa_tag; 194 195 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof devinfo); 196 revision = PCI_REVISION(pa->pa_class); 197 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, revision); 198 199 /* enable bus-mastering */ 200 data = pci_conf_read(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG); 201 data |= PCI_COMMAND_MASTER_ENABLE; 202 pci_conf_write(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG, data); 203 204 /* clear device specific PCI configuration register 0x41 */ 205 data = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 206 data &= ~0x0000ff00; 207 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, data); 208 209 /* map the register window */ 210 error = pci_mapreg_map(pa, IPW_PCI_BAR0, PCI_MAPREG_TYPE_MEM | 211 PCI_MAPREG_MEM_TYPE_32BIT, 0, &memt, &memh, &base, &sc->sc_sz); 212 if (error != 0) { 213 aprint_error("%s: could not map memory space\n", 214 sc->sc_dev.dv_xname); 215 return; 216 } 217 218 sc->sc_st = memt; 219 sc->sc_sh = memh; 220 sc->sc_dmat = pa->pa_dmat; 221 222 /* disable interrupts */ 223 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 224 225 if (pci_intr_map(pa, &ih) != 0) { 226 aprint_error("%s: could not map interrupt\n", 227 sc->sc_dev.dv_xname); 228 return; 229 } 230 231 intrstr = pci_intr_string(sc->sc_pct, ih); 232 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, ipw_intr, sc); 233 if (sc->sc_ih == NULL) { 234 aprint_error("%s: could not establish interrupt", 235 sc->sc_dev.dv_xname); 236 if (intrstr != NULL) 237 aprint_error(" at %s", intrstr); 238 aprint_error("\n"); 239 return; 240 } 241 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 242 243 if (ipw_reset(sc) != 0) { 244 aprint_error("%s: could not reset adapter\n", 245 sc->sc_dev.dv_xname); 246 goto fail; 247 } 248 249 if (ipw_dma_alloc(sc) != 0) { 250 aprint_error("%s: could not allocate DMA resources\n", 251 sc->sc_dev.dv_xname); 252 goto fail; 253 } 254 255 ifp->if_softc = sc; 256 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 257 ifp->if_init = ipw_init; 258 ifp->if_stop = ipw_stop; 259 ifp->if_ioctl = ipw_ioctl; 260 ifp->if_start = ipw_start; 261 ifp->if_watchdog = ipw_watchdog; 262 IFQ_SET_READY(&ifp->if_snd); 263 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 264 265 ic->ic_ifp = ifp; 266 ic->ic_phytype = IEEE80211_T_DS; 267 ic->ic_opmode = IEEE80211_M_STA; 268 ic->ic_state = IEEE80211_S_INIT; 269 270 /* set device capabilities */ 271 ic->ic_caps = IEEE80211_C_SHPREAMBLE | IEEE80211_C_TXPMGT | 272 IEEE80211_C_PMGT | IEEE80211_C_IBSS | IEEE80211_C_MONITOR; 273 274 /* read MAC address from EEPROM */ 275 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0); 276 ic->ic_myaddr[0] = val >> 8; 277 ic->ic_myaddr[1] = val & 0xff; 278 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 1); 279 ic->ic_myaddr[2] = val >> 8; 280 ic->ic_myaddr[3] = val & 0xff; 281 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 2); 282 ic->ic_myaddr[4] = val >> 8; 283 ic->ic_myaddr[5] = val & 0xff; 284 285 /* set supported .11b rates */ 286 ic->ic_sup_rates[IEEE80211_MODE_11B] = ipw_rateset_11b; 287 288 /* set supported .11b channels (read from EEPROM) */ 289 if ((val = ipw_read_prom_word(sc, IPW_EEPROM_CHANNEL_LIST)) == 0) 290 val = 0x7ff; /* default to channels 1-11 */ 291 val <<= 1; 292 for (i = 1; i < 16; i++) { 293 if (val & (1 << i)) { 294 ic->ic_channels[i].ic_freq = 295 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 296 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 297 } 298 } 299 300 /* check support for radio transmitter switch in EEPROM */ 301 if (!(ipw_read_prom_word(sc, IPW_EEPROM_RADIO) & 8)) 302 sc->flags |= IPW_FLAG_HAS_RADIO_SWITCH; 303 304 if_attach(ifp); 305 ieee80211_ifattach(ic); 306 307 /* override state transition machine */ 308 sc->sc_newstate = ic->ic_newstate; 309 ic->ic_newstate = ipw_newstate; 310 311 ieee80211_media_init(ic, ipw_media_change, ipw_media_status); 312 313 #if NBPFILTER > 0 314 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 315 sizeof (struct ieee80211_frame) + 64, &sc->sc_drvbpf); 316 317 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 318 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 319 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 320 321 sc->sc_txtap_len = sizeof sc->sc_txtapu; 322 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 323 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 324 #endif 325 326 /* 327 * Add a few sysctl knobs. 328 * XXX: Not yet 329 */ 330 sc->dwelltime = 100; 331 332 /* 333 * Make sure the interface is shutdown during reboot. 334 */ 335 sc->sc_sdhook = shutdownhook_establish(ipw_shutdown, sc); 336 if (sc->sc_sdhook == NULL) 337 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 338 sc->sc_dev.dv_xname); 339 sc->sc_powerhook = powerhook_establish(ipw_powerhook, sc); 340 if (sc->sc_powerhook == NULL) 341 printf("%s: WARNING: unable to establish power hook\n", 342 sc->sc_dev.dv_xname); 343 344 ieee80211_announce(ic); 345 346 return; 347 348 fail: ipw_detach(self, 0); 349 } 350 351 static int 352 ipw_detach(struct device* self, int flags) 353 { 354 struct ipw_softc *sc = (struct ipw_softc *)self; 355 struct ifnet *ifp = &sc->sc_if; 356 357 if (ifp->if_softc) { 358 ipw_stop(ifp, 1); 359 ipw_free_firmware(sc); 360 361 #if NBPFILTER > 0 362 bpfdetach(ifp); 363 #endif 364 ieee80211_ifdetach(&sc->sc_ic); 365 if_detach(ifp); 366 367 ipw_release(sc); 368 } 369 370 if (sc->sc_ih != NULL) { 371 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 372 sc->sc_ih = NULL; 373 } 374 375 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 376 377 return 0; 378 } 379 380 static int 381 ipw_dma_alloc(struct ipw_softc *sc) 382 { 383 struct ipw_soft_bd *sbd; 384 struct ipw_soft_hdr *shdr; 385 struct ipw_soft_buf *sbuf; 386 int error, i, nsegs; 387 388 /* 389 * Allocate and map tx ring. 390 */ 391 error = bus_dmamap_create(sc->sc_dmat, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, 392 BUS_DMA_NOWAIT, &sc->tbd_map); 393 if (error != 0) { 394 aprint_error("%s: could not create tbd dma map\n", 395 sc->sc_dev.dv_xname); 396 goto fail; 397 } 398 399 error = bus_dmamem_alloc(sc->sc_dmat, IPW_TBD_SZ, PAGE_SIZE, 0, 400 &sc->tbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 401 if (error != 0) { 402 aprint_error("%s: could not allocate tbd dma memory\n", 403 sc->sc_dev.dv_xname); 404 goto fail; 405 } 406 407 error = bus_dmamem_map(sc->sc_dmat, &sc->tbd_seg, nsegs, IPW_TBD_SZ, 408 (caddr_t *)&sc->tbd_list, BUS_DMA_NOWAIT); 409 if (error != 0) { 410 aprint_error("%s: could not map tbd dma memory\n", 411 sc->sc_dev.dv_xname); 412 goto fail; 413 } 414 415 error = bus_dmamap_load(sc->sc_dmat, sc->tbd_map, sc->tbd_list, 416 IPW_TBD_SZ, NULL, BUS_DMA_NOWAIT); 417 if (error != 0) { 418 aprint_error("%s: could not load tbd dma memory\n", 419 sc->sc_dev.dv_xname); 420 goto fail; 421 } 422 423 (void)memset(sc->tbd_list, 0, IPW_TBD_SZ); 424 425 /* 426 * Allocate and map rx ring. 427 */ 428 error = bus_dmamap_create(sc->sc_dmat, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, 429 BUS_DMA_NOWAIT, &sc->rbd_map); 430 if (error != 0) { 431 aprint_error("%s: could not create rbd dma map\n", 432 sc->sc_dev.dv_xname); 433 goto fail; 434 } 435 436 error = bus_dmamem_alloc(sc->sc_dmat, IPW_RBD_SZ, PAGE_SIZE, 0, 437 &sc->rbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 438 if (error != 0) { 439 aprint_error("%s: could not allocate rbd dma memory\n", 440 sc->sc_dev.dv_xname); 441 goto fail; 442 } 443 444 error = bus_dmamem_map(sc->sc_dmat, &sc->rbd_seg, nsegs, IPW_RBD_SZ, 445 (caddr_t *)&sc->rbd_list, BUS_DMA_NOWAIT); 446 if (error != 0) { 447 aprint_error("%s: could not map rbd dma memory\n", 448 sc->sc_dev.dv_xname); 449 goto fail; 450 } 451 452 error = bus_dmamap_load(sc->sc_dmat, sc->rbd_map, sc->rbd_list, 453 IPW_RBD_SZ, NULL, BUS_DMA_NOWAIT); 454 if (error != 0) { 455 aprint_error("%s: could not load rbd dma memory\n", 456 sc->sc_dev.dv_xname); 457 goto fail; 458 } 459 460 (void)memset(sc->rbd_list, 0, IPW_RBD_SZ); 461 462 /* 463 * Allocate and map status ring. 464 */ 465 error = bus_dmamap_create(sc->sc_dmat, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 466 0, BUS_DMA_NOWAIT, &sc->status_map); 467 if (error != 0) { 468 aprint_error("%s: could not create status dma map\n", 469 sc->sc_dev.dv_xname); 470 goto fail; 471 } 472 473 error = bus_dmamem_alloc(sc->sc_dmat, IPW_STATUS_SZ, PAGE_SIZE, 0, 474 &sc->status_seg, 1, &nsegs, BUS_DMA_NOWAIT); 475 if (error != 0) { 476 aprint_error("%s: could not allocate status dma memory\n", 477 sc->sc_dev.dv_xname); 478 goto fail; 479 } 480 481 error = bus_dmamem_map(sc->sc_dmat, &sc->status_seg, nsegs, 482 IPW_STATUS_SZ, (caddr_t *)&sc->status_list, BUS_DMA_NOWAIT); 483 if (error != 0) { 484 aprint_error("%s: could not map status dma memory\n", 485 sc->sc_dev.dv_xname); 486 goto fail; 487 } 488 489 error = bus_dmamap_load(sc->sc_dmat, sc->status_map, sc->status_list, 490 IPW_STATUS_SZ, NULL, BUS_DMA_NOWAIT); 491 if (error != 0) { 492 aprint_error("%s: could not load status dma memory\n", 493 sc->sc_dev.dv_xname); 494 goto fail; 495 } 496 497 (void)memset(sc->status_list, 0, IPW_STATUS_SZ); 498 499 /* 500 * Allocate command DMA map. 501 */ 502 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_cmd), 503 1, sizeof (struct ipw_cmd), 0, BUS_DMA_NOWAIT, &sc->cmd_map); 504 if (error != 0) { 505 aprint_error("%s: could not create cmd dma map\n", 506 sc->sc_dev.dv_xname); 507 goto fail; 508 } 509 510 error = bus_dmamem_alloc(sc->sc_dmat, sizeof (struct ipw_cmd), 511 PAGE_SIZE, 0, &sc->cmd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 512 if (error != 0) { 513 aprint_error("%s: could not allocate cmd dma memory\n", 514 sc->sc_dev.dv_xname); 515 goto fail; 516 } 517 518 error = bus_dmamem_map(sc->sc_dmat, &sc->cmd_seg, nsegs, 519 sizeof (struct ipw_cmd), (caddr_t *)&sc->cmd, BUS_DMA_NOWAIT); 520 if (error != 0) { 521 aprint_error("%s: could not map cmd dma memory\n", 522 sc->sc_dev.dv_xname); 523 goto fail; 524 } 525 526 error = bus_dmamap_load(sc->sc_dmat, sc->cmd_map, &sc->cmd, 527 sizeof (struct ipw_cmd), NULL, BUS_DMA_NOWAIT); 528 if (error != 0) { 529 aprint_error("%s: could not map cmd dma memory\n", 530 sc->sc_dev.dv_xname); 531 return error; 532 } 533 534 /* 535 * Allocate and map hdr list. 536 */ 537 538 error = bus_dmamap_create(sc->sc_dmat, 539 IPW_NDATA * sizeof(struct ipw_hdr), 1, 540 sizeof(struct ipw_hdr), 0, BUS_DMA_NOWAIT, 541 &sc->hdr_map); 542 if (error != 0) { 543 aprint_error("%s: could not create hdr dma map\n", 544 sc->sc_dev.dv_xname); 545 goto fail; 546 } 547 548 error = bus_dmamem_alloc(sc->sc_dmat, 549 IPW_NDATA * sizeof(struct ipw_hdr), PAGE_SIZE, 0, &sc->hdr_seg, 550 1, &nsegs, BUS_DMA_NOWAIT); 551 if (error != 0) { 552 aprint_error("%s: could not allocate hdr memory\n", 553 sc->sc_dev.dv_xname); 554 goto fail; 555 } 556 557 error = bus_dmamem_map(sc->sc_dmat, &sc->hdr_seg, nsegs, 558 IPW_NDATA * sizeof(struct ipw_hdr), (caddr_t *)&sc->hdr_list, 559 BUS_DMA_NOWAIT); 560 if (error != 0) { 561 aprint_error("%s: could not map hdr memory\n", 562 sc->sc_dev.dv_xname); 563 goto fail; 564 } 565 566 error = bus_dmamap_load(sc->sc_dmat, sc->hdr_map, sc->hdr_list, 567 IPW_NDATA * sizeof(struct ipw_hdr), NULL, BUS_DMA_NOWAIT); 568 if (error != 0) { 569 aprint_error("%s: could not load hdr memory\n", 570 sc->sc_dev.dv_xname); 571 goto fail; 572 } 573 574 (void)memset(sc->hdr_list, 0, IPW_HDR_SZ); 575 576 /* 577 * Create DMA hdrs tailq. 578 */ 579 TAILQ_INIT(&sc->sc_free_shdr); 580 for (i = 0; i < IPW_NDATA; i++) { 581 shdr = &sc->shdr_list[i]; 582 shdr->hdr = sc->hdr_list + i; 583 shdr->offset = sizeof(struct ipw_hdr) * i; 584 shdr->addr = sc->hdr_map->dm_segs[0].ds_addr + shdr->offset; 585 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 586 } 587 588 /* 589 * Allocate tx buffers DMA maps. 590 */ 591 TAILQ_INIT(&sc->sc_free_sbuf); 592 for (i = 0; i < IPW_NDATA; i++) { 593 sbuf = &sc->tx_sbuf_list[i]; 594 595 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 596 IPW_MAX_NSEG, MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 597 if (error != 0) { 598 aprint_error("%s: could not create txbuf dma map\n", 599 sc->sc_dev.dv_xname); 600 goto fail; 601 } 602 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 603 } 604 605 /* 606 * Initialize tx ring. 607 */ 608 for (i = 0; i < IPW_NTBD; i++) { 609 sbd = &sc->stbd_list[i]; 610 sbd->bd = &sc->tbd_list[i]; 611 sbd->type = IPW_SBD_TYPE_NOASSOC; 612 } 613 614 /* 615 * Pre-allocate rx buffers and DMA maps 616 */ 617 for (i = 0; i < IPW_NRBD; i++) { 618 sbd = &sc->srbd_list[i]; 619 sbuf = &sc->rx_sbuf_list[i]; 620 sbd->bd = &sc->rbd_list[i]; 621 622 MGETHDR(sbuf->m, M_DONTWAIT, MT_DATA); 623 if (sbuf->m == NULL) { 624 aprint_error("%s: could not allocate rx mbuf\n", 625 sc->sc_dev.dv_xname); 626 error = ENOMEM; 627 goto fail; 628 } 629 630 MCLGET(sbuf->m, M_DONTWAIT); 631 if (!(sbuf->m->m_flags & M_EXT)) { 632 m_freem(sbuf->m); 633 aprint_error("%s: could not allocate rx mbuf cluster\n", 634 sc->sc_dev.dv_xname); 635 error = ENOMEM; 636 goto fail; 637 } 638 639 sbuf->m->m_pkthdr.len = sbuf->m->m_len = sbuf->m->m_ext.ext_size; 640 641 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 642 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sbuf->map); 643 if (error != 0) { 644 aprint_error("%s: could not create rxbuf dma map\n", 645 sc->sc_dev.dv_xname); 646 m_freem(sbuf->m); 647 goto fail; 648 } 649 650 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, 651 sbuf->m, BUS_DMA_READ | BUS_DMA_NOWAIT); 652 if (error != 0) { 653 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 654 m_freem(sbuf->m); 655 aprint_error("%s: could not map rxbuf dma memory\n", 656 sc->sc_dev.dv_xname); 657 goto fail; 658 } 659 660 sbd->type = IPW_SBD_TYPE_DATA; 661 sbd->priv = sbuf; 662 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 663 sbd->bd->len = htole32(MCLBYTES); 664 665 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, 666 sbuf->map->dm_mapsize, BUS_DMASYNC_PREREAD); 667 668 } 669 670 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 0, IPW_RBD_SZ, 671 BUS_DMASYNC_PREREAD); 672 673 return 0; 674 675 fail: ipw_release(sc); 676 return error; 677 } 678 679 static void 680 ipw_release(struct ipw_softc *sc) 681 { 682 struct ipw_soft_buf *sbuf; 683 int i; 684 685 if (sc->tbd_map != NULL) { 686 if (sc->tbd_list != NULL) { 687 bus_dmamap_unload(sc->sc_dmat, sc->tbd_map); 688 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->tbd_list, 689 IPW_TBD_SZ); 690 bus_dmamem_free(sc->sc_dmat, &sc->tbd_seg, 1); 691 } 692 bus_dmamap_destroy(sc->sc_dmat, sc->tbd_map); 693 } 694 695 if (sc->rbd_map != NULL) { 696 if (sc->rbd_list != NULL) { 697 bus_dmamap_unload(sc->sc_dmat, sc->rbd_map); 698 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->rbd_list, 699 IPW_RBD_SZ); 700 bus_dmamem_free(sc->sc_dmat, &sc->rbd_seg, 1); 701 } 702 bus_dmamap_destroy(sc->sc_dmat, sc->rbd_map); 703 } 704 705 if (sc->status_map != NULL) { 706 if (sc->status_list != NULL) { 707 bus_dmamap_unload(sc->sc_dmat, sc->status_map); 708 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->status_list, 709 IPW_RBD_SZ); 710 bus_dmamem_free(sc->sc_dmat, &sc->status_seg, 1); 711 } 712 bus_dmamap_destroy(sc->sc_dmat, sc->status_map); 713 } 714 715 for (i = 0; i < IPW_NTBD; i++) 716 ipw_release_sbd(sc, &sc->stbd_list[i]); 717 718 if (sc->cmd_map != NULL) 719 bus_dmamap_destroy(sc->sc_dmat, sc->cmd_map); 720 721 if (sc->hdr_list != NULL) { 722 bus_dmamap_unload(sc->sc_dmat, sc->hdr_map); 723 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->hdr_list, 724 IPW_NDATA * sizeof(struct ipw_hdr)); 725 } 726 if (sc->hdr_map != NULL) { 727 bus_dmamem_free(sc->sc_dmat, &sc->hdr_seg, 1); 728 bus_dmamap_destroy(sc->sc_dmat, sc->hdr_map); 729 } 730 731 for (i = 0; i < IPW_NDATA; i++) 732 bus_dmamap_destroy(sc->sc_dmat, sc->tx_sbuf_list[i].map); 733 734 for (i = 0; i < IPW_NRBD; i++) { 735 sbuf = &sc->rx_sbuf_list[i]; 736 if (sbuf->map != NULL) { 737 if (sbuf->m != NULL) { 738 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 739 m_freem(sbuf->m); 740 } 741 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 742 } 743 } 744 745 } 746 747 static void 748 ipw_shutdown(void *arg) 749 { 750 struct ipw_softc *sc = (struct ipw_softc *)arg; 751 struct ifnet *ifp = sc->sc_ic.ic_ifp; 752 753 ipw_stop(ifp, 1); 754 } 755 756 757 static int 758 ipw_suspend(struct ipw_softc *sc) 759 { 760 struct ifnet *ifp = sc->sc_ic.ic_ifp; 761 762 ipw_stop(ifp, 1); 763 764 return 0; 765 } 766 767 static int 768 ipw_resume(struct ipw_softc *sc) 769 { 770 struct ifnet *ifp = sc->sc_ic.ic_ifp; 771 pcireg_t data; 772 773 /* clear device specific PCI configuration register 0x41 */ 774 data = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 775 data &= ~0x0000ff00; 776 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, data); 777 778 if (ifp->if_flags & IFF_UP) { 779 ipw_init(ifp); 780 if (ifp->if_flags & IFF_RUNNING) 781 ipw_start(ifp); 782 } 783 784 return 0; 785 } 786 787 static void 788 ipw_powerhook(int why, void *arg) 789 { 790 struct ipw_softc *sc = arg; 791 int s; 792 793 s = splnet(); 794 switch (why) { 795 case PWR_SUSPEND: 796 case PWR_STANDBY: 797 ipw_suspend(sc); 798 break; 799 case PWR_RESUME: 800 ipw_resume(sc); 801 break; 802 case PWR_SOFTSUSPEND: 803 case PWR_SOFTSTANDBY: 804 case PWR_SOFTRESUME: 805 break; 806 } 807 splx(s); 808 } 809 810 static int 811 ipw_media_change(struct ifnet *ifp) 812 { 813 int error; 814 815 error = ieee80211_media_change(ifp); 816 if (error != ENETRESET) 817 return error; 818 819 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 820 ipw_init(ifp); 821 822 return 0; 823 } 824 825 /* 826 * The firmware automatically adapts the transmit speed. We report the current 827 * transmit speed here. 828 */ 829 static void 830 ipw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 831 { 832 #define N(a) (sizeof (a) / sizeof (a[0])) 833 struct ipw_softc *sc = ifp->if_softc; 834 struct ieee80211com *ic = &sc->sc_ic; 835 static const struct { 836 uint32_t val; 837 int rate; 838 } rates[] = { 839 { IPW_RATE_DS1, 2 }, 840 { IPW_RATE_DS2, 4 }, 841 { IPW_RATE_DS5, 11 }, 842 { IPW_RATE_DS11, 22 }, 843 }; 844 uint32_t val; 845 int rate, i; 846 847 imr->ifm_status = IFM_AVALID; 848 imr->ifm_active = IFM_IEEE80211; 849 if (ic->ic_state == IEEE80211_S_RUN) 850 imr->ifm_status |= IFM_ACTIVE; 851 852 /* read current transmission rate from adapter */ 853 val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE) & 0xf; 854 855 /* convert ipw rate to 802.11 rate */ 856 for (i = 0; i < N(rates) && rates[i].val != val; i++); 857 rate = (i < N(rates)) ? rates[i].rate : 0; 858 859 imr->ifm_active |= IFM_IEEE80211_11B; 860 imr->ifm_active |= ieee80211_rate2media(ic, rate, IEEE80211_MODE_11B); 861 switch (ic->ic_opmode) { 862 case IEEE80211_M_STA: 863 break; 864 865 case IEEE80211_M_IBSS: 866 imr->ifm_active |= IFM_IEEE80211_ADHOC; 867 break; 868 869 case IEEE80211_M_MONITOR: 870 imr->ifm_active |= IFM_IEEE80211_MONITOR; 871 break; 872 873 case IEEE80211_M_AHDEMO: 874 case IEEE80211_M_HOSTAP: 875 /* should not get there */ 876 break; 877 } 878 #undef N 879 } 880 881 static int 882 ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 883 { 884 struct ifnet *ifp = ic->ic_ifp; 885 struct ipw_softc *sc = ifp->if_softc; 886 struct ieee80211_node *ni; 887 uint8_t macaddr[IEEE80211_ADDR_LEN]; 888 uint32_t len; 889 890 switch (nstate) { 891 case IEEE80211_S_RUN: 892 DELAY(200); /* firmware needs a short delay here */ 893 894 len = IEEE80211_ADDR_LEN; 895 ipw_read_table2(sc, IPW_INFO_CURRENT_BSSID, macaddr, &len); 896 897 ni = ieee80211_find_node(&ic->ic_scan, macaddr); 898 if (ni == NULL) 899 break; 900 901 ieee80211_ref_node(ni); 902 ieee80211_sta_join(ic, ni); 903 ieee80211_node_authorize(ni); 904 905 if (ic->ic_opmode == IEEE80211_M_STA) 906 ieee80211_notify_node_join(ic, ni, 1); 907 break; 908 909 case IEEE80211_S_INIT: 910 case IEEE80211_S_SCAN: 911 case IEEE80211_S_AUTH: 912 case IEEE80211_S_ASSOC: 913 break; 914 } 915 916 ic->ic_state = nstate; 917 return 0; 918 } 919 920 /* 921 * Read 16 bits at address 'addr' from the serial EEPROM. 922 */ 923 static uint16_t 924 ipw_read_prom_word(struct ipw_softc *sc, uint8_t addr) 925 { 926 uint32_t tmp; 927 uint16_t val; 928 int n; 929 930 /* clock C once before the first command */ 931 IPW_EEPROM_CTL(sc, 0); 932 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 933 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 934 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 935 936 /* write start bit (1) */ 937 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 938 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 939 940 /* write READ opcode (10) */ 941 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 942 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 943 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 944 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 945 946 /* write address A7-A0 */ 947 for (n = 7; n >= 0; n--) { 948 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 949 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D)); 950 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 951 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D) | IPW_EEPROM_C); 952 } 953 954 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 955 956 /* read data Q15-Q0 */ 957 val = 0; 958 for (n = 15; n >= 0; n--) { 959 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 960 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 961 tmp = MEM_READ_4(sc, IPW_MEM_EEPROM_CTL); 962 val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n; 963 } 964 965 IPW_EEPROM_CTL(sc, 0); 966 967 /* clear Chip Select and clock C */ 968 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 969 IPW_EEPROM_CTL(sc, 0); 970 IPW_EEPROM_CTL(sc, IPW_EEPROM_C); 971 972 return le16toh(val); 973 } 974 975 static void 976 ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 977 { 978 struct ipw_cmd *cmd; 979 980 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof (struct ipw_cmd), 981 BUS_DMASYNC_POSTREAD); 982 983 cmd = mtod(sbuf->m, struct ipw_cmd *); 984 985 DPRINTFN(2, ("cmd ack'ed (%u, %u, %u, %u, %u)\n", le32toh(cmd->type), 986 le32toh(cmd->subtype), le32toh(cmd->seq), le32toh(cmd->len), 987 le32toh(cmd->status))); 988 989 wakeup(&sc->cmd); 990 } 991 992 static void 993 ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 994 { 995 struct ieee80211com *ic = &sc->sc_ic; 996 struct ifnet *ifp = sc->sc_ic.ic_ifp; 997 uint32_t state; 998 999 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof state, 1000 BUS_DMASYNC_POSTREAD); 1001 1002 state = le32toh(*mtod(sbuf->m, uint32_t *)); 1003 1004 DPRINTFN(2, ("entering state %u\n", state)); 1005 1006 switch (state) { 1007 case IPW_STATE_ASSOCIATED: 1008 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1009 break; 1010 1011 case IPW_STATE_SCANNING: 1012 /* don't leave run state on background scan */ 1013 if (ic->ic_state != IEEE80211_S_RUN) 1014 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1015 1016 ic->ic_flags |= IEEE80211_F_SCAN; 1017 break; 1018 1019 case IPW_STATE_SCAN_COMPLETE: 1020 ieee80211_notify_scan_done(ic); 1021 ic->ic_flags &= ~IEEE80211_F_SCAN; 1022 break; 1023 1024 case IPW_STATE_ASSOCIATION_LOST: 1025 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1026 break; 1027 1028 case IPW_STATE_RADIO_DISABLED: 1029 ic->ic_ifp->if_flags &= ~IFF_UP; 1030 ipw_stop(ifp, 1); 1031 break; 1032 } 1033 } 1034 1035 /* 1036 * XXX: Hack to set the current channel to the value advertised in beacons or 1037 * probe responses. Only used during AP detection. 1038 */ 1039 static void 1040 ipw_fix_channel(struct ieee80211com *ic, struct mbuf *m) 1041 { 1042 struct ieee80211_frame *wh; 1043 uint8_t subtype; 1044 uint8_t *frm, *efrm; 1045 1046 wh = mtod(m, struct ieee80211_frame *); 1047 1048 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_MGT) 1049 return; 1050 1051 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 1052 1053 if (subtype != IEEE80211_FC0_SUBTYPE_BEACON && 1054 subtype != IEEE80211_FC0_SUBTYPE_PROBE_RESP) 1055 return; 1056 1057 frm = (uint8_t *)(wh + 1); 1058 efrm = mtod(m, uint8_t *) + m->m_len; 1059 1060 frm += 12; /* skip tstamp, bintval and capinfo fields */ 1061 while (frm < efrm) { 1062 if (*frm == IEEE80211_ELEMID_DSPARMS) 1063 #if IEEE80211_CHAN_MAX < 255 1064 if (frm[2] <= IEEE80211_CHAN_MAX) 1065 #endif 1066 ic->ic_curchan = &ic->ic_channels[frm[2]]; 1067 1068 frm += frm[1] + 2; 1069 } 1070 } 1071 1072 static void 1073 ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 1074 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 1075 { 1076 struct ieee80211com *ic = &sc->sc_ic; 1077 struct ifnet *ifp = &sc->sc_if; 1078 struct mbuf *mnew, *m; 1079 struct ieee80211_frame *wh; 1080 struct ieee80211_node *ni; 1081 int error; 1082 1083 DPRINTFN(5, ("received frame len=%u, rssi=%u\n", le32toh(status->len), 1084 status->rssi)); 1085 1086 if (le32toh(status->len) < sizeof (struct ieee80211_frame_min) || 1087 le32toh(status->len) > MCLBYTES) 1088 return; 1089 1090 /* 1091 * Try to allocate a new mbuf for this ring element and load it before 1092 * processing the current mbuf. If the ring element cannot be loaded, 1093 * drop the received packet and reuse the old mbuf. In the unlikely 1094 * case that the old mbuf can't be reloaded either, explicitly panic. 1095 */ 1096 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1097 if (mnew == NULL) { 1098 aprint_error("%s: could not allocate rx mbuf\n", 1099 sc->sc_dev.dv_xname); 1100 ifp->if_ierrors++; 1101 return; 1102 } 1103 1104 MCLGET(mnew, M_DONTWAIT); 1105 if (!(mnew->m_flags & M_EXT)) { 1106 aprint_error("%s: could not allocate rx mbuf cluster\n", 1107 sc->sc_dev.dv_xname); 1108 m_freem(mnew); 1109 ifp->if_ierrors++; 1110 return; 1111 } 1112 1113 mnew->m_pkthdr.len = mnew->m_len = mnew->m_ext.ext_size; 1114 1115 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, le32toh(status->len), 1116 BUS_DMASYNC_POSTREAD); 1117 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1118 1119 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, mnew, 1120 BUS_DMA_READ | BUS_DMA_NOWAIT); 1121 if (error != 0) { 1122 aprint_error("%s: could not load rx buf DMA map\n", 1123 sc->sc_dev.dv_xname); 1124 m_freem(mnew); 1125 1126 /* try to reload the old mbuf */ 1127 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, 1128 sbuf->m, BUS_DMA_READ | BUS_DMA_NOWAIT); 1129 if (error != 0) { 1130 /* very unlikely that it will fail... */ 1131 panic("%s: unable to remap rx buf", 1132 sc->sc_dev.dv_xname); 1133 } 1134 ifp->if_ierrors++; 1135 return; 1136 } 1137 1138 /* 1139 * New mbuf successfully loaded, update Rx ring and continue 1140 * processing. 1141 */ 1142 m = sbuf->m; 1143 sbuf->m = mnew; 1144 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 1145 1146 /* finalize mbuf */ 1147 m->m_pkthdr.rcvif = ifp; 1148 m->m_pkthdr.len = m->m_len = le32toh(status->len); 1149 1150 #if NBPFILTER > 0 1151 if (sc->sc_drvbpf != NULL) { 1152 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 1153 1154 tap->wr_flags = 0; 1155 tap->wr_antsignal = status->rssi; 1156 tap->wr_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 1157 tap->wr_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 1158 1159 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 1160 } 1161 #endif 1162 1163 if (ic->ic_state == IEEE80211_S_SCAN) 1164 ipw_fix_channel(ic, m); 1165 1166 wh = mtod(m, struct ieee80211_frame *); 1167 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 1168 1169 /* send the frame to the 802.11 layer */ 1170 ieee80211_input(ic, m, ni, status->rssi, 0); 1171 1172 /* node is no longer needed */ 1173 ieee80211_free_node(ni); 1174 1175 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, 1176 sbuf->map->dm_mapsize, BUS_DMASYNC_PREREAD); 1177 } 1178 1179 static void 1180 ipw_rx_intr(struct ipw_softc *sc) 1181 { 1182 struct ipw_status *status; 1183 struct ipw_soft_bd *sbd; 1184 struct ipw_soft_buf *sbuf; 1185 uint32_t r, i; 1186 1187 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1188 return; 1189 1190 r = CSR_READ_4(sc, IPW_CSR_RX_READ); 1191 1192 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 1193 1194 /* firmware was killed, stop processing received frames */ 1195 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1196 return; 1197 1198 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 1199 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1200 BUS_DMASYNC_POSTREAD); 1201 1202 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 1203 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 1204 BUS_DMASYNC_POSTREAD); 1205 1206 status = &sc->status_list[i]; 1207 sbd = &sc->srbd_list[i]; 1208 sbuf = sbd->priv; 1209 1210 switch (le16toh(status->code) & 0xf) { 1211 case IPW_STATUS_CODE_COMMAND: 1212 ipw_command_intr(sc, sbuf); 1213 break; 1214 1215 case IPW_STATUS_CODE_NEWSTATE: 1216 ipw_newstate_intr(sc, sbuf); 1217 break; 1218 1219 case IPW_STATUS_CODE_DATA_802_3: 1220 case IPW_STATUS_CODE_DATA_802_11: 1221 ipw_data_intr(sc, status, sbd, sbuf); 1222 break; 1223 1224 case IPW_STATUS_CODE_NOTIFICATION: 1225 DPRINTFN(2, ("received notification\n")); 1226 break; 1227 1228 default: 1229 aprint_debug("%s: unknown status code %u\n", 1230 sc->sc_dev.dv_xname, le16toh(status->code)); 1231 } 1232 1233 sbd->bd->flags = 0; 1234 1235 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 1236 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1237 BUS_DMASYNC_PREREAD); 1238 1239 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 1240 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 1241 BUS_DMASYNC_PREREAD); 1242 } 1243 1244 /* Tell the firmware what we have processed */ 1245 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 1246 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 1247 } 1248 1249 static void 1250 ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 1251 { 1252 struct ieee80211com *ic; 1253 struct ipw_soft_hdr *shdr; 1254 struct ipw_soft_buf *sbuf; 1255 1256 switch (sbd->type) { 1257 case IPW_SBD_TYPE_COMMAND: 1258 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 1259 0, sizeof(struct ipw_cmd), BUS_DMASYNC_POSTWRITE); 1260 /* bus_dmamap_unload(sc->sc_dmat, sc->cmd_map); */ 1261 break; 1262 1263 case IPW_SBD_TYPE_HEADER: 1264 shdr = sbd->priv; 1265 bus_dmamap_sync(sc->sc_dmat, sc->hdr_map, 1266 shdr->offset, sizeof(struct ipw_hdr), BUS_DMASYNC_POSTWRITE); 1267 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 1268 break; 1269 1270 case IPW_SBD_TYPE_DATA: 1271 ic = &sc->sc_ic; 1272 sbuf = sbd->priv; 1273 1274 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 1275 0, MCLBYTES, BUS_DMASYNC_POSTWRITE); 1276 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1277 m_freem(sbuf->m); 1278 if (sbuf->ni != NULL) 1279 ieee80211_free_node(sbuf->ni); 1280 /* kill watchdog timer */ 1281 sc->sc_tx_timer = 0; 1282 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 1283 break; 1284 } 1285 sbd->type = IPW_SBD_TYPE_NOASSOC; 1286 } 1287 1288 static void 1289 ipw_tx_intr(struct ipw_softc *sc) 1290 { 1291 struct ifnet *ifp = &sc->sc_if; 1292 struct ipw_soft_bd *sbd; 1293 uint32_t r, i; 1294 1295 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1296 return; 1297 1298 r = CSR_READ_4(sc, IPW_CSR_TX_READ); 1299 1300 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) { 1301 sbd = &sc->stbd_list[i]; 1302 1303 if (sbd->type == IPW_SBD_TYPE_DATA) 1304 ifp->if_opackets++; 1305 1306 ipw_release_sbd(sc, sbd); 1307 sc->txfree++; 1308 } 1309 1310 /* remember what the firmware has processed */ 1311 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 1312 1313 /* Call start() since some buffer descriptors have been released */ 1314 ifp->if_flags &= ~IFF_OACTIVE; 1315 (*ifp->if_start)(ifp); 1316 } 1317 1318 static int 1319 ipw_intr(void *arg) 1320 { 1321 struct ipw_softc *sc = arg; 1322 uint32_t r; 1323 1324 r = CSR_READ_4(sc, IPW_CSR_INTR); 1325 if (r == 0 || r == 0xffffffff) 1326 return 0; 1327 1328 /* Disable interrupts */ 1329 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1330 1331 if (r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR)) { 1332 aprint_error("%s: fatal error\n", 1333 sc->sc_dev.dv_xname); 1334 sc->sc_ic.ic_ifp->if_flags &= ~IFF_UP; 1335 ipw_stop(&sc->sc_if, 1); 1336 } 1337 1338 if (r & IPW_INTR_FW_INIT_DONE) { 1339 if (!(r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR))) 1340 wakeup(sc); 1341 } 1342 1343 if (r & IPW_INTR_RX_TRANSFER) 1344 ipw_rx_intr(sc); 1345 1346 if (r & IPW_INTR_TX_TRANSFER) 1347 ipw_tx_intr(sc); 1348 1349 /* Acknowledge all interrupts */ 1350 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 1351 1352 /* Re-enable interrupts */ 1353 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1354 1355 return 0; 1356 } 1357 1358 /* 1359 * Send a command to the firmware and wait for the acknowledgement. 1360 */ 1361 static int 1362 ipw_cmd(struct ipw_softc *sc, uint32_t type, void *data, uint32_t len) 1363 { 1364 struct ipw_soft_bd *sbd; 1365 1366 sbd = &sc->stbd_list[sc->txcur]; 1367 1368 sc->cmd.type = htole32(type); 1369 sc->cmd.subtype = 0; 1370 sc->cmd.len = htole32(len); 1371 sc->cmd.seq = 0; 1372 1373 (void)memcpy(sc->cmd.data, data, len); 1374 1375 sbd->type = IPW_SBD_TYPE_COMMAND; 1376 sbd->bd->physaddr = htole32(sc->cmd_map->dm_segs[0].ds_addr); 1377 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 1378 sbd->bd->nfrag = 1; 1379 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 1380 IPW_BD_FLAG_TX_LAST_FRAGMENT; 1381 1382 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 0, sizeof (struct ipw_cmd), 1383 BUS_DMASYNC_PREWRITE); 1384 1385 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1386 sc->txcur * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1387 BUS_DMASYNC_PREWRITE); 1388 1389 DPRINTFN(2, ("sending command (%u, %u, %u, %u)\n", type, 0, 0, len)); 1390 1391 /* kick firmware */ 1392 sc->txfree--; 1393 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1394 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1395 1396 /* Wait at most one second for command to complete */ 1397 return tsleep(&sc->cmd, 0, "ipwcmd", hz); 1398 } 1399 1400 static int 1401 ipw_tx_start(struct ifnet *ifp, struct mbuf *m0, struct ieee80211_node *ni) 1402 { 1403 struct ipw_softc *sc = ifp->if_softc; 1404 struct ieee80211com *ic = &sc->sc_ic; 1405 struct ieee80211_frame *wh; 1406 struct ipw_soft_bd *sbd; 1407 struct ipw_soft_hdr *shdr; 1408 struct ipw_soft_buf *sbuf; 1409 struct ieee80211_key *k; 1410 struct mbuf *mnew; 1411 int error, i; 1412 1413 wh = mtod(m0, struct ieee80211_frame *); 1414 1415 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1416 k = ieee80211_crypto_encap(ic, ni, m0); 1417 if (k == NULL) { 1418 m_freem(m0); 1419 return ENOBUFS; 1420 } 1421 1422 /* packet header may have moved, reset our local pointer */ 1423 wh = mtod(m0, struct ieee80211_frame *); 1424 } 1425 1426 #if NBPFILTER > 0 1427 if (sc->sc_drvbpf != NULL) { 1428 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 1429 1430 tap->wt_flags = 0; 1431 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 1432 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 1433 1434 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 1435 } 1436 #endif 1437 1438 shdr = TAILQ_FIRST(&sc->sc_free_shdr); 1439 sbuf = TAILQ_FIRST(&sc->sc_free_sbuf); 1440 KASSERT(shdr != NULL && sbuf != NULL); 1441 1442 shdr->hdr->type = htole32(IPW_HDR_TYPE_SEND); 1443 shdr->hdr->subtype = 0; 1444 shdr->hdr->encrypted = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0; 1445 shdr->hdr->encrypt = 0; 1446 shdr->hdr->keyidx = 0; 1447 shdr->hdr->keysz = 0; 1448 shdr->hdr->fragmentsz = 0; 1449 IEEE80211_ADDR_COPY(shdr->hdr->src_addr, wh->i_addr2); 1450 if (ic->ic_opmode == IEEE80211_M_STA) 1451 IEEE80211_ADDR_COPY(shdr->hdr->dst_addr, wh->i_addr3); 1452 else 1453 IEEE80211_ADDR_COPY(shdr->hdr->dst_addr, wh->i_addr1); 1454 1455 /* trim IEEE802.11 header */ 1456 m_adj(m0, sizeof (struct ieee80211_frame)); 1457 1458 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m0, BUS_DMA_NOWAIT); 1459 if (error != 0 && error != EFBIG) { 1460 aprint_error("%s: could not map mbuf (error %d)\n", 1461 sc->sc_dev.dv_xname, error); 1462 m_freem(m0); 1463 return error; 1464 } 1465 1466 if (error != 0) { 1467 /* too many fragments, linearize */ 1468 1469 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1470 if (mnew == NULL) { 1471 m_freem(m0); 1472 return ENOMEM; 1473 } 1474 1475 M_COPY_PKTHDR(mnew, m0); 1476 1477 /* If the data won't fit in the header, get a cluster */ 1478 if (m0->m_pkthdr.len > MHLEN) { 1479 MCLGET(mnew, M_DONTWAIT); 1480 if (!(mnew->m_flags & M_EXT)) { 1481 m_freem(m0); 1482 m_freem(mnew); 1483 return ENOMEM; 1484 } 1485 } 1486 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(mnew, caddr_t)); 1487 m_freem(m0); 1488 mnew->m_len = mnew->m_pkthdr.len; 1489 m0 = mnew; 1490 1491 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m0, 1492 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1493 if (error != 0) { 1494 aprint_error("%s: could not map mbuf (error %d)\n", 1495 sc->sc_dev.dv_xname, error); 1496 m_freem(m0); 1497 return error; 1498 } 1499 } 1500 1501 TAILQ_REMOVE(&sc->sc_free_sbuf, sbuf, next); 1502 TAILQ_REMOVE(&sc->sc_free_shdr, shdr, next); 1503 1504 sbd = &sc->stbd_list[sc->txcur]; 1505 sbd->type = IPW_SBD_TYPE_HEADER; 1506 sbd->priv = shdr; 1507 sbd->bd->physaddr = htole32(shdr->addr); 1508 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 1509 sbd->bd->nfrag = 1 + sbuf->map->dm_nsegs; 1510 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 1511 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1512 1513 DPRINTFN(5, ("sending tx hdr (%u, %u, %u, %u, )\n", 1514 shdr->hdr->type, shdr->hdr->subtype, shdr->hdr->encrypted, 1515 shdr->hdr->encrypt)); 1516 DPRINTFN(5, ("%s->", ether_sprintf(shdr->hdr->src_addr))); 1517 DPRINTFN(5, ("%s\n", ether_sprintf(shdr->hdr->dst_addr))); 1518 1519 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1520 sc->txcur * sizeof (struct ipw_bd), 1521 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1522 1523 sc->txfree--; 1524 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1525 1526 sbuf->m = m0; 1527 sbuf->ni = ni; 1528 1529 for (i = 0; i < sbuf->map->dm_nsegs; i++) { 1530 sbd = &sc->stbd_list[sc->txcur]; 1531 1532 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[i].ds_addr); 1533 sbd->bd->len = htole32(sbuf->map->dm_segs[i].ds_len); 1534 sbd->bd->nfrag = 0; 1535 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 1536 if (i == sbuf->map->dm_nsegs - 1) { 1537 sbd->type = IPW_SBD_TYPE_DATA; 1538 sbd->priv = sbuf; 1539 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 1540 } else { 1541 sbd->type = IPW_SBD_TYPE_NOASSOC; 1542 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1543 } 1544 1545 DPRINTFN(5, ("sending fragment (%d, %d)\n", i, 1546 (int)sbuf->map->dm_segs[i].ds_len)); 1547 1548 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1549 sc->txcur * sizeof (struct ipw_bd), 1550 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1551 1552 sc->txfree--; 1553 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1554 } 1555 1556 bus_dmamap_sync(sc->sc_dmat, sc->hdr_map, shdr->offset, 1557 sizeof (struct ipw_hdr), BUS_DMASYNC_PREWRITE); 1558 1559 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, MCLBYTES, 1560 BUS_DMASYNC_PREWRITE); 1561 1562 /* Inform firmware about this new packet */ 1563 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1564 1565 return 0; 1566 } 1567 1568 static void 1569 ipw_start(struct ifnet *ifp) 1570 { 1571 struct ipw_softc *sc = ifp->if_softc; 1572 struct ieee80211com *ic = &sc->sc_ic; 1573 struct mbuf *m0; 1574 struct ether_header *eh; 1575 struct ieee80211_node *ni; 1576 1577 1578 if (ic->ic_state != IEEE80211_S_RUN) 1579 return; 1580 1581 for (;;) { 1582 IF_DEQUEUE(&ifp->if_snd, m0); 1583 if (m0 == NULL) 1584 break; 1585 1586 if (sc->txfree < 1 + IPW_MAX_NSEG) { 1587 IF_PREPEND(&ifp->if_snd, m0); 1588 ifp->if_flags |= IFF_OACTIVE; 1589 break; 1590 } 1591 1592 if (m0->m_len < sizeof (struct ether_header) && 1593 (m0 = m_pullup(m0, sizeof (struct ether_header))) == NULL) 1594 continue; 1595 1596 eh = mtod(m0, struct ether_header *); 1597 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1598 if (ni == NULL) { 1599 m_freem(m0); 1600 continue; 1601 } 1602 1603 #if NBPFILTER > 0 1604 if (ifp->if_bpf != NULL) 1605 bpf_mtap(ifp->if_bpf, m0); 1606 #endif 1607 1608 m0 = ieee80211_encap(ic, m0, ni); 1609 if (m0 == NULL) { 1610 ieee80211_free_node(ni); 1611 continue; 1612 } 1613 1614 #if NBPFILTER > 0 1615 if (ic->ic_rawbpf != NULL) 1616 bpf_mtap(ic->ic_rawbpf, m0); 1617 #endif 1618 1619 if (ipw_tx_start(ifp, m0, ni) != 0) { 1620 ieee80211_free_node(ni); 1621 ifp->if_oerrors++; 1622 break; 1623 } 1624 1625 /* start watchdog timer */ 1626 sc->sc_tx_timer = 5; 1627 ifp->if_timer = 1; 1628 } 1629 } 1630 1631 static void 1632 ipw_watchdog(struct ifnet *ifp) 1633 { 1634 struct ipw_softc *sc = ifp->if_softc; 1635 1636 ifp->if_timer = 0; 1637 1638 if (sc->sc_tx_timer > 0) { 1639 if (--sc->sc_tx_timer == 0) { 1640 aprint_error("%s: device timeout\n", 1641 sc->sc_dev.dv_xname); 1642 ifp->if_oerrors++; 1643 ifp->if_flags &= ~IFF_UP; 1644 ipw_stop(ifp, 1); 1645 return; 1646 } 1647 ifp->if_timer = 1; 1648 } 1649 1650 ieee80211_watchdog(&sc->sc_ic); 1651 } 1652 1653 static int 1654 ipw_get_table1(struct ipw_softc *sc, uint32_t *tbl) 1655 { 1656 uint32_t addr, size, i; 1657 1658 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1659 return ENOTTY; 1660 1661 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, sc->table1_base); 1662 1663 size = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 1664 if (suword(tbl, size) != 0) 1665 return EFAULT; 1666 1667 for (i = 1, ++tbl; i < size; i++, tbl++) { 1668 addr = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 1669 if (suword(tbl, MEM_READ_4(sc, addr)) != 0) 1670 return EFAULT; 1671 } 1672 return 0; 1673 } 1674 1675 static int 1676 ipw_get_radio(struct ipw_softc *sc, int *ret) 1677 { 1678 uint32_t addr; 1679 1680 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1681 return ENOTTY; 1682 1683 addr = ipw_read_table1(sc, IPW_INFO_EEPROM_ADDRESS); 1684 if ((MEM_READ_4(sc, addr + 32) >> 24) & 1) { 1685 suword(ret, -1); 1686 return 0; 1687 } 1688 1689 if (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED) 1690 suword(ret, 0); 1691 else 1692 suword(ret, 1); 1693 1694 return 0; 1695 } 1696 1697 static int 1698 ipw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1699 { 1700 #define IS_RUNNING(ifp) \ 1701 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 1702 1703 struct ipw_softc *sc = ifp->if_softc; 1704 struct ieee80211com *ic = &sc->sc_ic; 1705 struct ifreq *ifr = (struct ifreq *)data; 1706 int s, error = 0; 1707 1708 s = splnet(); 1709 1710 switch (cmd) { 1711 case SIOCSIFFLAGS: 1712 if (ifp->if_flags & IFF_UP) { 1713 if (!(ifp->if_flags & IFF_RUNNING)) 1714 ipw_init(ifp); 1715 } else { 1716 if (ifp->if_flags & IFF_RUNNING) 1717 ipw_stop(ifp, 1); 1718 } 1719 break; 1720 1721 case SIOCADDMULTI: 1722 case SIOCDELMULTI: 1723 error = (cmd == SIOCADDMULTI) ? 1724 ether_addmulti(ifr, &sc->sc_ec) : 1725 ether_delmulti(ifr, &sc->sc_ec); 1726 if (error == ENETRESET) { 1727 /* setup multicast filter, etc */ 1728 error = 0; 1729 } 1730 break; 1731 1732 case SIOCGTABLE1: 1733 error = ipw_get_table1(sc, (uint32_t *)ifr->ifr_data); 1734 break; 1735 1736 case SIOCGRADIO: 1737 error = ipw_get_radio(sc, (int *)ifr->ifr_data); 1738 break; 1739 1740 case SIOCSLOADFW: 1741 /* only super-user can do that! */ 1742 if ((error = kauth_authorize_generic(curproc->p_cred, KAUTH_GENERIC_ISSUSER, 1743 &curproc->p_acflag)) != 0) 1744 break; 1745 1746 error = ipw_cache_firmware(sc, ifr->ifr_data); 1747 break; 1748 1749 case SIOCSKILLFW: 1750 /* only super-user can do that! */ 1751 if ((error = kauth_authorize_generic(curproc->p_cred, KAUTH_GENERIC_ISSUSER, 1752 &curproc->p_acflag)) != 0) 1753 break; 1754 1755 ipw_reset(sc); 1756 break; 1757 1758 default: 1759 error = ieee80211_ioctl(&sc->sc_ic, cmd, data); 1760 if (error != ENETRESET) 1761 break; 1762 1763 if (error == ENETRESET) { 1764 if (IS_RUNNING(ifp) && 1765 (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)) 1766 ipw_init(ifp); 1767 error = 0; 1768 } 1769 1770 } 1771 1772 splx(s); 1773 return error; 1774 #undef IS_RUNNING 1775 } 1776 1777 static uint32_t 1778 ipw_read_table1(struct ipw_softc *sc, uint32_t off) 1779 { 1780 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 1781 } 1782 1783 static void 1784 ipw_write_table1(struct ipw_softc *sc, uint32_t off, uint32_t info) 1785 { 1786 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 1787 } 1788 1789 static int 1790 ipw_read_table2(struct ipw_softc *sc, uint32_t off, void *buf, uint32_t *len) 1791 { 1792 uint32_t addr, info; 1793 uint16_t count, size; 1794 uint32_t total; 1795 1796 /* addr[4] + count[2] + size[2] */ 1797 addr = MEM_READ_4(sc, sc->table2_base + off); 1798 info = MEM_READ_4(sc, sc->table2_base + off + 4); 1799 1800 count = info >> 16; 1801 size = info & 0xffff; 1802 total = count * size; 1803 1804 if (total > *len) { 1805 *len = total; 1806 return EINVAL; 1807 } 1808 1809 *len = total; 1810 ipw_read_mem_1(sc, addr, buf, total); 1811 1812 return 0; 1813 } 1814 1815 static void 1816 ipw_stop_master(struct ipw_softc *sc) 1817 { 1818 int ntries; 1819 1820 /* disable interrupts */ 1821 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1822 1823 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1824 for (ntries = 0; ntries < 50; ntries++) { 1825 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1826 break; 1827 DELAY(10); 1828 } 1829 if (ntries == 50) 1830 aprint_error("%s: timeout waiting for master\n", 1831 sc->sc_dev.dv_xname); 1832 1833 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1834 IPW_RST_PRINCETON_RESET); 1835 1836 sc->flags &= ~IPW_FLAG_FW_INITED; 1837 } 1838 1839 static int 1840 ipw_reset(struct ipw_softc *sc) 1841 { 1842 int ntries; 1843 1844 ipw_stop_master(sc); 1845 1846 /* move adapter to D0 state */ 1847 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1848 IPW_CTL_INIT); 1849 1850 /* wait for clock stabilization */ 1851 for (ntries = 0; ntries < 1000; ntries++) { 1852 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY) 1853 break; 1854 DELAY(200); 1855 } 1856 if (ntries == 1000) 1857 return EIO; 1858 1859 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1860 IPW_RST_SW_RESET); 1861 1862 DELAY(10); 1863 1864 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1865 IPW_CTL_INIT); 1866 1867 return 0; 1868 } 1869 1870 /* 1871 * Upload the microcode to the device. 1872 */ 1873 static int 1874 ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size) 1875 { 1876 int ntries; 1877 1878 MEM_WRITE_4(sc, 0x3000e0, 0x80000000); 1879 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1880 1881 MEM_WRITE_2(sc, 0x220000, 0x0703); 1882 MEM_WRITE_2(sc, 0x220000, 0x0707); 1883 1884 MEM_WRITE_1(sc, 0x210014, 0x72); 1885 MEM_WRITE_1(sc, 0x210014, 0x72); 1886 1887 MEM_WRITE_1(sc, 0x210000, 0x40); 1888 MEM_WRITE_1(sc, 0x210000, 0x00); 1889 MEM_WRITE_1(sc, 0x210000, 0x40); 1890 1891 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1892 1893 MEM_WRITE_1(sc, 0x210000, 0x00); 1894 MEM_WRITE_1(sc, 0x210000, 0x00); 1895 MEM_WRITE_1(sc, 0x210000, 0x80); 1896 1897 MEM_WRITE_2(sc, 0x220000, 0x0703); 1898 MEM_WRITE_2(sc, 0x220000, 0x0707); 1899 1900 MEM_WRITE_1(sc, 0x210014, 0x72); 1901 MEM_WRITE_1(sc, 0x210014, 0x72); 1902 1903 MEM_WRITE_1(sc, 0x210000, 0x00); 1904 MEM_WRITE_1(sc, 0x210000, 0x80); 1905 1906 for (ntries = 0; ntries < 10; ntries++) { 1907 if (MEM_READ_1(sc, 0x210000) & 1) 1908 break; 1909 DELAY(10); 1910 } 1911 if (ntries == 10) { 1912 aprint_error("%s: timeout waiting for ucode to initialize\n", 1913 sc->sc_dev.dv_xname); 1914 return EIO; 1915 } 1916 1917 MEM_WRITE_4(sc, 0x3000e0, 0); 1918 1919 return 0; 1920 } 1921 1922 /* set of macros to handle unaligned little endian data in firmware image */ 1923 #define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1924 #define GETLE16(p) ((p)[0] | (p)[1] << 8) 1925 static int 1926 ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size) 1927 { 1928 u_char *p, *end; 1929 uint32_t dst; 1930 uint16_t len; 1931 int error; 1932 1933 p = fw; 1934 end = fw + size; 1935 while (p < end) { 1936 dst = GETLE32(p); p += 4; 1937 len = GETLE16(p); p += 2; 1938 1939 ipw_write_mem_1(sc, dst, p, len); 1940 p += len; 1941 } 1942 1943 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1944 IPW_IO_LED_OFF); 1945 1946 /* enable interrupts */ 1947 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1948 1949 /* kick the firmware */ 1950 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1951 1952 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1953 IPW_CTL_ALLOW_STANDBY); 1954 1955 /* wait at most one second for firmware initialization to complete */ 1956 if ((error = tsleep(sc, 0, "ipwinit", hz)) != 0) { 1957 aprint_error("%s: timeout waiting for firmware initialization " 1958 "to complete\n", sc->sc_dev.dv_xname); 1959 return error; 1960 } 1961 1962 CSR_WRITE_4(sc, IPW_CSR_IO, CSR_READ_4(sc, IPW_CSR_IO) | 1963 IPW_IO_GPIO1_MASK | IPW_IO_GPIO3_MASK); 1964 1965 return 0; 1966 } 1967 1968 /* 1969 * Store firmware into kernel memory so we can download it when we need to, 1970 * e.g when the adapter wakes up from suspend mode. 1971 */ 1972 static int 1973 ipw_cache_firmware(struct ipw_softc *sc, void *data) 1974 { 1975 struct ipw_firmware *fw = &sc->fw; 1976 struct ipw_firmware_hdr hdr; 1977 u_char *p = data; 1978 int error; 1979 1980 ipw_free_firmware(sc); 1981 1982 if ((error = copyin(data, &hdr, sizeof hdr)) != 0) 1983 goto fail1; 1984 1985 fw->main_size = le32toh(hdr.main_size); 1986 fw->ucode_size = le32toh(hdr.ucode_size); 1987 p += sizeof hdr; 1988 1989 fw->main = malloc(fw->main_size, M_DEVBUF, M_NOWAIT); 1990 if (fw->main == NULL) { 1991 error = ENOMEM; 1992 goto fail1; 1993 } 1994 1995 fw->ucode = malloc(fw->ucode_size, M_DEVBUF, M_NOWAIT); 1996 if (fw->ucode == NULL) { 1997 error = ENOMEM; 1998 goto fail2; 1999 } 2000 2001 if ((error = copyin(p, fw->main, fw->main_size)) != 0) 2002 goto fail3; 2003 2004 p += fw->main_size; 2005 if ((error = copyin(p, fw->ucode, fw->ucode_size)) != 0) 2006 goto fail3; 2007 2008 DPRINTF(("Firmware cached: main %u, ucode %u\n", fw->main_size, 2009 fw->ucode_size)); 2010 2011 sc->flags |= IPW_FLAG_FW_CACHED; 2012 2013 return 0; 2014 2015 fail3: free(fw->ucode, M_DEVBUF); 2016 fail2: free(fw->main, M_DEVBUF); 2017 fail1: 2018 return error; 2019 } 2020 2021 static void 2022 ipw_free_firmware(struct ipw_softc *sc) 2023 { 2024 if (!(sc->flags & IPW_FLAG_FW_CACHED)) 2025 return; 2026 2027 free(sc->fw.main, M_DEVBUF); 2028 free(sc->fw.ucode, M_DEVBUF); 2029 2030 sc->flags &= ~IPW_FLAG_FW_CACHED; 2031 } 2032 2033 static int 2034 ipw_config(struct ipw_softc *sc) 2035 { 2036 struct ieee80211com *ic = &sc->sc_ic; 2037 struct ifnet *ifp = &sc->sc_if; 2038 struct ipw_security security; 2039 struct ieee80211_key *k; 2040 struct ipw_wep_key wepkey; 2041 struct ipw_scan_options options; 2042 struct ipw_configuration config; 2043 uint32_t data; 2044 int error, i; 2045 2046 switch (ic->ic_opmode) { 2047 case IEEE80211_M_STA: 2048 case IEEE80211_M_HOSTAP: 2049 data = htole32(IPW_MODE_BSS); 2050 break; 2051 2052 case IEEE80211_M_IBSS: 2053 case IEEE80211_M_AHDEMO: 2054 data = htole32(IPW_MODE_IBSS); 2055 break; 2056 2057 case IEEE80211_M_MONITOR: 2058 data = htole32(IPW_MODE_MONITOR); 2059 break; 2060 } 2061 DPRINTF(("Setting mode to %u\n", le32toh(data))); 2062 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 2063 if (error != 0) 2064 return error; 2065 2066 if (ic->ic_opmode == IEEE80211_M_IBSS || 2067 ic->ic_opmode == IEEE80211_M_MONITOR) { 2068 data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); 2069 DPRINTF(("Setting channel to %u\n", le32toh(data))); 2070 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 2071 if (error != 0) 2072 return error; 2073 } 2074 2075 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2076 DPRINTF(("Enabling adapter\n")); 2077 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 2078 } 2079 2080 DPRINTF(("Setting MAC to %s\n", ether_sprintf(ic->ic_myaddr))); 2081 IEEE80211_ADDR_COPY(LLADDR(ifp->if_sadl), ic->ic_myaddr); 2082 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 2083 IEEE80211_ADDR_LEN); 2084 if (error != 0) 2085 return error; 2086 2087 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 2088 IPW_CFG_PREAMBLE_AUTO | IPW_CFG_802_1x_ENABLE); 2089 2090 if (ic->ic_opmode == IEEE80211_M_IBSS) 2091 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 2092 if (ifp->if_flags & IFF_PROMISC) 2093 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 2094 config.bss_chan = htole32(0x3fff); /* channels 1-14 */ 2095 config.ibss_chan = htole32(0x7ff); /* channels 1-11 */ 2096 DPRINTF(("Setting adapter configuration 0x%08x\n", config.flags)); 2097 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 2098 if (error != 0) 2099 return error; 2100 2101 data = htole32(0x3); /* 1, 2 */ 2102 DPRINTF(("Setting basic tx rates to 0x%x\n", le32toh(data))); 2103 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 2104 if (error != 0) 2105 return error; 2106 2107 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 2108 DPRINTF(("Setting tx rates to 0x%x\n", le32toh(data))); 2109 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 2110 if (error != 0) 2111 return error; 2112 2113 data = htole32(IPW_POWER_MODE_CAM); 2114 DPRINTF(("Setting power mode to %u\n", le32toh(data))); 2115 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 2116 if (error != 0) 2117 return error; 2118 2119 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2120 data = htole32(32); /* default value */ 2121 DPRINTF(("Setting tx power index to %u\n", le32toh(data))); 2122 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 2123 sizeof data); 2124 if (error != 0) 2125 return error; 2126 } 2127 2128 data = htole32(ic->ic_rtsthreshold); 2129 DPRINTF(("Setting RTS threshold to %u\n", le32toh(data))); 2130 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 2131 if (error != 0) 2132 return error; 2133 2134 data = htole32(ic->ic_fragthreshold); 2135 DPRINTF(("Setting frag threshold to %u\n", le32toh(data))); 2136 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 2137 if (error != 0) 2138 return error; 2139 2140 #ifdef IPW_DEBUG 2141 if (ipw_debug > 0) { 2142 printf("Setting ESSID to "); 2143 ieee80211_print_essid(ic->ic_des_essid, ic->ic_des_esslen); 2144 printf("\n"); 2145 } 2146 #endif 2147 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ic->ic_des_essid, 2148 ic->ic_des_esslen); 2149 if (error != 0) 2150 return error; 2151 2152 /* no mandatory BSSID */ 2153 DPRINTF(("Setting mandatory BSSID to null\n")); 2154 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 2155 if (error != 0) 2156 return error; 2157 2158 if (ic->ic_flags & IEEE80211_F_DESBSSID) { 2159 DPRINTF(("Setting desired BSSID to %s\n", 2160 ether_sprintf(ic->ic_des_bssid))); 2161 error = ipw_cmd(sc, IPW_CMD_SET_DESIRED_BSSID, 2162 ic->ic_des_bssid, IEEE80211_ADDR_LEN); 2163 if (error != 0) 2164 return error; 2165 } 2166 2167 (void)memset(&security, 0, sizeof(security)); 2168 security.authmode = (ic->ic_bss->ni_authmode == IEEE80211_AUTH_SHARED) ? 2169 IPW_AUTH_SHARED : IPW_AUTH_OPEN; 2170 security.ciphers = htole32(IPW_CIPHER_NONE); 2171 DPRINTF(("Setting authmode to %u\n", security.authmode)); 2172 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 2173 sizeof security); 2174 if (error != 0) 2175 return error; 2176 2177 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 2178 k = ic->ic_crypto.cs_nw_keys; 2179 for (i = 0; i < IEEE80211_WEP_NKID; i++, k++) { 2180 if (k->wk_keylen == 0) 2181 continue; 2182 2183 wepkey.idx = i; 2184 wepkey.len = k->wk_keylen; 2185 bzero(wepkey.key, sizeof wepkey.key); 2186 bcopy(k->wk_key, wepkey.key, k->wk_keylen); 2187 DPRINTF(("Setting wep key index %u len %u\n", 2188 wepkey.idx, wepkey.len)); 2189 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY, &wepkey, 2190 sizeof wepkey); 2191 if (error != 0) 2192 return error; 2193 } 2194 2195 data = htole32(ic->ic_crypto.cs_def_txkey); 2196 DPRINTF(("Setting tx key index to %u\n", le32toh(data))); 2197 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY_INDEX, &data, 2198 sizeof data); 2199 if (error != 0) 2200 return error; 2201 } 2202 2203 data = htole32((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) ? IPW_WEPON : 0); 2204 DPRINTF(("Setting wep flags to 0x%x\n", le32toh(data))); 2205 error = ipw_cmd(sc, IPW_CMD_SET_WEP_FLAGS, &data, sizeof data); 2206 if (error != 0) 2207 return error; 2208 2209 #if 0 2210 struct ipw_wpa_ie ie; 2211 2212 bzero(&ie, sizeof ie); 2213 ie.len = htole32(sizeof (struct ieee80211_ie_wpa)); 2214 DPRINTF(("Setting wpa ie\n")); 2215 error = ipw_cmd(sc, IPW_CMD_SET_WPA_IE, &ie, sizeof ie); 2216 if (error != 0) 2217 return error; 2218 #endif 2219 2220 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2221 data = htole32(ic->ic_bintval); 2222 DPRINTF(("Setting beacon interval to %u\n", le32toh(data))); 2223 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 2224 sizeof data); 2225 if (error != 0) 2226 return error; 2227 } 2228 2229 options.flags = 0; 2230 options.channels = htole32(0x3fff); /* scan channels 1-14 */ 2231 DPRINTF(("Setting scan options to 0x%x\n", le32toh(options.flags))); 2232 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &options, sizeof options); 2233 if (error != 0) 2234 return error; 2235 2236 /* finally, enable adapter (start scanning for an access point) */ 2237 DPRINTF(("Enabling adapter\n")); 2238 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 2239 } 2240 2241 static int 2242 ipw_init(struct ifnet *ifp) 2243 { 2244 struct ipw_softc *sc = ifp->if_softc; 2245 struct ipw_firmware *fw = &sc->fw; 2246 2247 /* exit immediately if firmware has not been ioctl'd */ 2248 if (!(sc->flags & IPW_FLAG_FW_CACHED)) { 2249 if (!(sc->flags & IPW_FLAG_FW_WARNED)) 2250 aprint_error("%s: Please load firmware\n", 2251 sc->sc_dev.dv_xname); 2252 sc->flags |= IPW_FLAG_FW_WARNED; 2253 ifp->if_flags &= ~IFF_UP; 2254 return EIO; 2255 } 2256 2257 ipw_stop(ifp, 0); 2258 2259 if (ipw_reset(sc) != 0) { 2260 aprint_error("%s: could not reset adapter\n", 2261 sc->sc_dev.dv_xname); 2262 goto fail; 2263 } 2264 2265 if (ipw_load_ucode(sc, fw->ucode, fw->ucode_size) != 0) { 2266 aprint_error("%s: could not load microcode\n", 2267 sc->sc_dev.dv_xname); 2268 goto fail; 2269 } 2270 2271 ipw_stop_master(sc); 2272 2273 /* 2274 * Setup tx, rx and status rings. 2275 */ 2276 sc->txold = IPW_NTBD - 1; 2277 sc->txcur = 0; 2278 sc->txfree = IPW_NTBD - 2; 2279 sc->rxcur = IPW_NRBD - 1; 2280 2281 CSR_WRITE_4(sc, IPW_CSR_TX_BASE, sc->tbd_map->dm_segs[0].ds_addr); 2282 CSR_WRITE_4(sc, IPW_CSR_TX_SIZE, IPW_NTBD); 2283 CSR_WRITE_4(sc, IPW_CSR_TX_READ, 0); 2284 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 2285 2286 CSR_WRITE_4(sc, IPW_CSR_RX_BASE, sc->rbd_map->dm_segs[0].ds_addr); 2287 CSR_WRITE_4(sc, IPW_CSR_RX_SIZE, IPW_NRBD); 2288 CSR_WRITE_4(sc, IPW_CSR_RX_READ, 0); 2289 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 2290 2291 CSR_WRITE_4(sc, IPW_CSR_STATUS_BASE, sc->status_map->dm_segs[0].ds_addr); 2292 2293 if (ipw_load_firmware(sc, fw->main, fw->main_size) != 0) { 2294 aprint_error("%s: could not load firmware\n", 2295 sc->sc_dev.dv_xname); 2296 goto fail; 2297 } 2298 2299 sc->flags |= IPW_FLAG_FW_INITED; 2300 2301 /* retrieve information tables base addresses */ 2302 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 2303 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 2304 2305 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 2306 2307 if (ipw_config(sc) != 0) { 2308 aprint_error("%s: device configuration failed\n", 2309 sc->sc_dev.dv_xname); 2310 goto fail; 2311 } 2312 2313 ifp->if_flags &= ~IFF_OACTIVE; 2314 ifp->if_flags |= IFF_RUNNING; 2315 2316 return 0; 2317 2318 fail: ifp->if_flags &= ~IFF_UP; 2319 ipw_stop(ifp, 0); 2320 2321 return EIO; 2322 } 2323 2324 static void 2325 ipw_stop(struct ifnet *ifp, int disable) 2326 { 2327 struct ipw_softc *sc = ifp->if_softc; 2328 struct ieee80211com *ic = &sc->sc_ic; 2329 int i; 2330 2331 ipw_stop_master(sc); 2332 2333 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 2334 2335 /* 2336 * Release tx buffers. 2337 */ 2338 for (i = 0; i < IPW_NTBD; i++) 2339 ipw_release_sbd(sc, &sc->stbd_list[i]); 2340 2341 sc->sc_tx_timer = 0; 2342 ifp->if_timer = 0; 2343 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2344 2345 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2346 } 2347 2348 static void 2349 ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2350 bus_size_t count) 2351 { 2352 for (; count > 0; offset++, datap++, count--) { 2353 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2354 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 2355 } 2356 } 2357 2358 static void 2359 ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2360 bus_size_t count) 2361 { 2362 for (; count > 0; offset++, datap++, count--) { 2363 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2364 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 2365 } 2366 } 2367
Indexes created Tue Sep 30 17:09:57 GMT 2025