if_ipw.c revision 1.16.12.1
1 /* $NetBSD: if_ipw.c,v 1.16.12.1 2006/05/24 15:50:27 tron Exp $ */ 2 /* FreeBSD: src/sys/dev/ipw/if_ipw.c,v 1.15 2005/11/13 17:17:40 damien Exp */ 3 4 /*- 5 * Copyright (c) 2004, 2005 6 * Damien Bergamini <damien.bergamini (at) free.fr>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: if_ipw.c,v 1.16.12.1 2006/05/24 15:50:27 tron Exp $"); 33 34 /*- 35 * Intel(R) PRO/Wireless 2100 MiniPCI driver 36 * http://www.intel.com/network/connectivity/products/wireless/prowireless_mobile.htm 37 */ 38 39 #include "bpfilter.h" 40 41 #include <sys/param.h> 42 #include <sys/sockio.h> 43 #include <sys/sysctl.h> 44 #include <sys/mbuf.h> 45 #include <sys/kernel.h> 46 #include <sys/socket.h> 47 #include <sys/systm.h> 48 #include <sys/malloc.h> 49 #include <sys/conf.h> 50 51 #include <machine/bus.h> 52 #include <machine/endian.h> 53 #include <machine/intr.h> 54 55 #include <dev/pci/pcireg.h> 56 #include <dev/pci/pcivar.h> 57 #include <dev/pci/pcidevs.h> 58 59 #if NBPFILTER > 0 60 #include <net/bpf.h> 61 #endif 62 #include <net/if.h> 63 #include <net/if_arp.h> 64 #include <net/if_dl.h> 65 #include <net/if_ether.h> 66 #include <net/if_media.h> 67 #include <net/if_types.h> 68 69 #include <net80211/ieee80211_var.h> 70 #include <net80211/ieee80211_radiotap.h> 71 72 #include <netinet/in.h> 73 #include <netinet/in_systm.h> 74 #include <netinet/in_var.h> 75 #include <netinet/ip.h> 76 77 #include <dev/firmload.h> 78 79 #include <dev/pci/if_ipwreg.h> 80 #include <dev/pci/if_ipwvar.h> 81 82 #ifdef IPW_DEBUG 83 #define DPRINTF(x) if (ipw_debug > 0) printf x 84 #define DPRINTFN(n, x) if (ipw_debug >= (n)) printf x 85 int ipw_debug = 0; 86 #else 87 #define DPRINTF(x) 88 #define DPRINTFN(n, x) 89 #endif 90 91 static int ipw_dma_alloc(struct ipw_softc *); 92 static void ipw_release(struct ipw_softc *); 93 static int ipw_match(struct device *, struct cfdata *, void *); 94 static void ipw_attach(struct device *, struct device *, void *); 95 static int ipw_detach(struct device *, int); 96 97 static void ipw_shutdown(void *); 98 static int ipw_suspend(struct ipw_softc *); 99 static int ipw_resume(struct ipw_softc *); 100 static void ipw_powerhook(int, void *); 101 102 static int ipw_media_change(struct ifnet *); 103 static void ipw_media_status(struct ifnet *, struct ifmediareq *); 104 static int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 105 static uint16_t ipw_read_prom_word(struct ipw_softc *, uint8_t); 106 static void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 107 static void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 108 static void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 109 struct ipw_soft_bd *, struct ipw_soft_buf *); 110 static void ipw_rx_intr(struct ipw_softc *); 111 static void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 112 static void ipw_tx_intr(struct ipw_softc *); 113 static int ipw_intr(void *); 114 static int ipw_cmd(struct ipw_softc *, uint32_t, void *, uint32_t); 115 static int ipw_tx_start(struct ifnet *, struct mbuf *, 116 struct ieee80211_node *); 117 static void ipw_start(struct ifnet *); 118 static void ipw_watchdog(struct ifnet *); 119 static int ipw_ioctl(struct ifnet *, u_long, caddr_t); 120 static int ipw_get_table1(struct ipw_softc *, uint32_t *); 121 static int ipw_get_radio(struct ipw_softc *, int *); 122 static void ipw_stop_master(struct ipw_softc *); 123 static int ipw_reset(struct ipw_softc *); 124 static int ipw_load_ucode(struct ipw_softc *, u_char *, int); 125 static int ipw_load_firmware(struct ipw_softc *, u_char *, int); 126 static int ipw_cache_firmware(struct ipw_softc *); 127 static void ipw_free_firmware(struct ipw_softc *); 128 static int ipw_config(struct ipw_softc *); 129 static int ipw_init(struct ifnet *); 130 static void ipw_stop(struct ifnet *, int); 131 static uint32_t ipw_read_table1(struct ipw_softc *, uint32_t); 132 static void ipw_write_table1(struct ipw_softc *, uint32_t, uint32_t); 133 static int ipw_read_table2(struct ipw_softc *, uint32_t, void *, uint32_t *); 134 static void ipw_read_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 135 bus_size_t); 136 static void ipw_write_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 137 bus_size_t); 138 139 /* 140 * Supported rates for 802.11b mode (in 500Kbps unit). 141 */ 142 static const struct ieee80211_rateset ipw_rateset_11b = 143 { 4, { 2, 4, 11, 22 } }; 144 145 static inline uint8_t 146 MEM_READ_1(struct ipw_softc *sc, uint32_t addr) 147 { 148 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 149 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); 150 } 151 152 static inline uint32_t 153 MEM_READ_4(struct ipw_softc *sc, uint32_t addr) 154 { 155 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 156 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); 157 } 158 159 CFATTACH_DECL(ipw, sizeof (struct ipw_softc), ipw_match, ipw_attach, 160 ipw_detach, NULL); 161 162 static int 163 ipw_match(struct device *parent, struct cfdata *match, void *aux) 164 { 165 struct pci_attach_args *pa = aux; 166 167 if (PCI_VENDOR (pa->pa_id) == PCI_VENDOR_INTEL && 168 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_PRO_WL_2100) 169 return 1; 170 171 return 0; 172 } 173 174 /* Base Address Register */ 175 #define IPW_PCI_BAR0 0x10 176 177 static void 178 ipw_attach(struct device *parent, struct device *self, void *aux) 179 { 180 struct ipw_softc *sc = (struct ipw_softc *)self; 181 struct ieee80211com *ic = &sc->sc_ic; 182 struct ifnet *ifp = &sc->sc_if; 183 struct pci_attach_args *pa = aux; 184 const char *intrstr; 185 char devinfo[256]; 186 bus_space_tag_t memt; 187 bus_space_handle_t memh; 188 bus_addr_t base; 189 pci_intr_handle_t ih; 190 uint32_t data; 191 uint16_t val; 192 int i, revision, error; 193 194 sc->sc_pct = pa->pa_pc; 195 sc->sc_pcitag = pa->pa_tag; 196 197 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof devinfo); 198 revision = PCI_REVISION(pa->pa_class); 199 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, revision); 200 201 /* enable bus-mastering */ 202 data = pci_conf_read(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG); 203 data |= PCI_COMMAND_MASTER_ENABLE; 204 pci_conf_write(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG, data); 205 206 /* clear device specific PCI configuration register 0x41 */ 207 data = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 208 data &= ~0x0000ff00; 209 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, data); 210 211 /* map the register window */ 212 error = pci_mapreg_map(pa, IPW_PCI_BAR0, PCI_MAPREG_TYPE_MEM | 213 PCI_MAPREG_MEM_TYPE_32BIT, 0, &memt, &memh, &base, &sc->sc_sz); 214 if (error != 0) { 215 aprint_error("%s: could not map memory space\n", 216 sc->sc_dev.dv_xname); 217 return; 218 } 219 220 sc->sc_st = memt; 221 sc->sc_sh = memh; 222 sc->sc_dmat = pa->pa_dmat; 223 strlcpy(sc->sc_fwname, "ipw2100-1.2.fw", sizeof(sc->sc_fwname)); 224 225 /* disable interrupts */ 226 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 227 228 if (pci_intr_map(pa, &ih) != 0) { 229 aprint_error("%s: could not map interrupt\n", 230 sc->sc_dev.dv_xname); 231 return; 232 } 233 234 intrstr = pci_intr_string(sc->sc_pct, ih); 235 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, ipw_intr, sc); 236 if (sc->sc_ih == NULL) { 237 aprint_error("%s: could not establish interrupt", 238 sc->sc_dev.dv_xname); 239 if (intrstr != NULL) 240 aprint_error(" at %s", intrstr); 241 aprint_error("\n"); 242 return; 243 } 244 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 245 246 if (ipw_reset(sc) != 0) { 247 aprint_error("%s: could not reset adapter\n", 248 sc->sc_dev.dv_xname); 249 goto fail; 250 } 251 252 if (ipw_dma_alloc(sc) != 0) { 253 aprint_error("%s: could not allocate DMA resources\n", 254 sc->sc_dev.dv_xname); 255 goto fail; 256 } 257 258 ifp->if_softc = sc; 259 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 260 ifp->if_init = ipw_init; 261 ifp->if_stop = ipw_stop; 262 ifp->if_ioctl = ipw_ioctl; 263 ifp->if_start = ipw_start; 264 ifp->if_watchdog = ipw_watchdog; 265 IFQ_SET_READY(&ifp->if_snd); 266 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 267 268 ic->ic_ifp = ifp; 269 ic->ic_phytype = IEEE80211_T_DS; 270 ic->ic_opmode = IEEE80211_M_STA; 271 ic->ic_state = IEEE80211_S_INIT; 272 273 /* set device capabilities */ 274 ic->ic_caps = 275 IEEE80211_C_SHPREAMBLE /* short preamble supported */ 276 | IEEE80211_C_TXPMGT /* tx power management */ 277 | IEEE80211_C_IBSS /* ibss mode */ 278 | IEEE80211_C_MONITOR /* monitor mode */ 279 ; 280 281 /* read MAC address from EEPROM */ 282 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0); 283 ic->ic_myaddr[0] = val >> 8; 284 ic->ic_myaddr[1] = val & 0xff; 285 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 1); 286 ic->ic_myaddr[2] = val >> 8; 287 ic->ic_myaddr[3] = val & 0xff; 288 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 2); 289 ic->ic_myaddr[4] = val >> 8; 290 ic->ic_myaddr[5] = val & 0xff; 291 292 /* set supported .11b rates */ 293 ic->ic_sup_rates[IEEE80211_MODE_11B] = ipw_rateset_11b; 294 295 /* set supported .11b channels (read from EEPROM) */ 296 if ((val = ipw_read_prom_word(sc, IPW_EEPROM_CHANNEL_LIST)) == 0) 297 val = 0x7ff; /* default to channels 1-11 */ 298 val <<= 1; 299 for (i = 1; i < 16; i++) { 300 if (val & (1 << i)) { 301 ic->ic_channels[i].ic_freq = 302 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 303 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 304 } 305 } 306 307 /* check support for radio transmitter switch in EEPROM */ 308 if (!(ipw_read_prom_word(sc, IPW_EEPROM_RADIO) & 8)) 309 sc->flags |= IPW_FLAG_HAS_RADIO_SWITCH; 310 311 aprint_normal("%s: 802.11 address %s\n", sc->sc_dev.dv_xname, 312 ether_sprintf(ic->ic_myaddr)); 313 314 if_attach(ifp); 315 ieee80211_ifattach(ic); 316 317 /* override state transition machine */ 318 sc->sc_newstate = ic->ic_newstate; 319 ic->ic_newstate = ipw_newstate; 320 321 ieee80211_media_init(ic, ipw_media_change, ipw_media_status); 322 323 #if NBPFILTER > 0 324 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 325 sizeof (struct ieee80211_frame) + 64, &sc->sc_drvbpf); 326 327 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 328 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 329 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 330 331 sc->sc_txtap_len = sizeof sc->sc_txtapu; 332 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 333 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 334 #endif 335 336 /* 337 * Add a few sysctl knobs. 338 * XXX: Not yet 339 */ 340 sc->dwelltime = 100; 341 342 /* 343 * Make sure the interface is shutdown during reboot. 344 */ 345 sc->sc_sdhook = shutdownhook_establish(ipw_shutdown, sc); 346 if (sc->sc_sdhook == NULL) 347 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 348 sc->sc_dev.dv_xname); 349 sc->sc_powerhook = powerhook_establish(ipw_powerhook, sc); 350 if (sc->sc_powerhook == NULL) 351 printf("%s: WARNING: unable to establish power hook\n", 352 sc->sc_dev.dv_xname); 353 354 ieee80211_announce(ic); 355 356 return; 357 358 fail: ipw_detach(self, 0); 359 } 360 361 static int 362 ipw_detach(struct device* self, int flags) 363 { 364 struct ipw_softc *sc = (struct ipw_softc *)self; 365 struct ifnet *ifp = &sc->sc_if; 366 367 if (ifp->if_softc) { 368 ipw_stop(ifp, 1); 369 ipw_free_firmware(sc); 370 371 #if NBPFILTER > 0 372 bpfdetach(ifp); 373 #endif 374 ieee80211_ifdetach(&sc->sc_ic); 375 if_detach(ifp); 376 377 ipw_release(sc); 378 } 379 380 if (sc->sc_ih != NULL) { 381 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 382 sc->sc_ih = NULL; 383 } 384 385 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 386 387 return 0; 388 } 389 390 static int 391 ipw_dma_alloc(struct ipw_softc *sc) 392 { 393 struct ipw_soft_bd *sbd; 394 struct ipw_soft_hdr *shdr; 395 struct ipw_soft_buf *sbuf; 396 int error, i, nsegs; 397 398 /* 399 * Allocate and map tx ring. 400 */ 401 error = bus_dmamap_create(sc->sc_dmat, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, 402 BUS_DMA_NOWAIT, &sc->tbd_map); 403 if (error != 0) { 404 aprint_error("%s: could not create tbd dma map\n", 405 sc->sc_dev.dv_xname); 406 goto fail; 407 } 408 409 error = bus_dmamem_alloc(sc->sc_dmat, IPW_TBD_SZ, PAGE_SIZE, 0, 410 &sc->tbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 411 if (error != 0) { 412 aprint_error("%s: could not allocate tbd dma memory\n", 413 sc->sc_dev.dv_xname); 414 goto fail; 415 } 416 417 error = bus_dmamem_map(sc->sc_dmat, &sc->tbd_seg, nsegs, IPW_TBD_SZ, 418 (caddr_t *)&sc->tbd_list, BUS_DMA_NOWAIT); 419 if (error != 0) { 420 aprint_error("%s: could not map tbd dma memory\n", 421 sc->sc_dev.dv_xname); 422 goto fail; 423 } 424 425 error = bus_dmamap_load(sc->sc_dmat, sc->tbd_map, sc->tbd_list, 426 IPW_TBD_SZ, NULL, BUS_DMA_NOWAIT); 427 if (error != 0) { 428 aprint_error("%s: could not load tbd dma memory\n", 429 sc->sc_dev.dv_xname); 430 goto fail; 431 } 432 433 (void)memset(sc->tbd_list, 0, IPW_TBD_SZ); 434 435 /* 436 * Allocate and map rx ring. 437 */ 438 error = bus_dmamap_create(sc->sc_dmat, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, 439 BUS_DMA_NOWAIT, &sc->rbd_map); 440 if (error != 0) { 441 aprint_error("%s: could not create rbd dma map\n", 442 sc->sc_dev.dv_xname); 443 goto fail; 444 } 445 446 error = bus_dmamem_alloc(sc->sc_dmat, IPW_RBD_SZ, PAGE_SIZE, 0, 447 &sc->rbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 448 if (error != 0) { 449 aprint_error("%s: could not allocate rbd dma memory\n", 450 sc->sc_dev.dv_xname); 451 goto fail; 452 } 453 454 error = bus_dmamem_map(sc->sc_dmat, &sc->rbd_seg, nsegs, IPW_RBD_SZ, 455 (caddr_t *)&sc->rbd_list, BUS_DMA_NOWAIT); 456 if (error != 0) { 457 aprint_error("%s: could not map rbd dma memory\n", 458 sc->sc_dev.dv_xname); 459 goto fail; 460 } 461 462 error = bus_dmamap_load(sc->sc_dmat, sc->rbd_map, sc->rbd_list, 463 IPW_RBD_SZ, NULL, BUS_DMA_NOWAIT); 464 if (error != 0) { 465 aprint_error("%s: could not load rbd dma memory\n", 466 sc->sc_dev.dv_xname); 467 goto fail; 468 } 469 470 (void)memset(sc->rbd_list, 0, IPW_RBD_SZ); 471 472 /* 473 * Allocate and map status ring. 474 */ 475 error = bus_dmamap_create(sc->sc_dmat, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 476 0, BUS_DMA_NOWAIT, &sc->status_map); 477 if (error != 0) { 478 aprint_error("%s: could not create status dma map\n", 479 sc->sc_dev.dv_xname); 480 goto fail; 481 } 482 483 error = bus_dmamem_alloc(sc->sc_dmat, IPW_STATUS_SZ, PAGE_SIZE, 0, 484 &sc->status_seg, 1, &nsegs, BUS_DMA_NOWAIT); 485 if (error != 0) { 486 aprint_error("%s: could not allocate status dma memory\n", 487 sc->sc_dev.dv_xname); 488 goto fail; 489 } 490 491 error = bus_dmamem_map(sc->sc_dmat, &sc->status_seg, nsegs, 492 IPW_STATUS_SZ, (caddr_t *)&sc->status_list, BUS_DMA_NOWAIT); 493 if (error != 0) { 494 aprint_error("%s: could not map status dma memory\n", 495 sc->sc_dev.dv_xname); 496 goto fail; 497 } 498 499 error = bus_dmamap_load(sc->sc_dmat, sc->status_map, sc->status_list, 500 IPW_STATUS_SZ, NULL, BUS_DMA_NOWAIT); 501 if (error != 0) { 502 aprint_error("%s: could not load status dma memory\n", 503 sc->sc_dev.dv_xname); 504 goto fail; 505 } 506 507 (void)memset(sc->status_list, 0, IPW_STATUS_SZ); 508 509 /* 510 * Allocate command DMA map. 511 */ 512 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_cmd), 513 1, sizeof (struct ipw_cmd), 0, BUS_DMA_NOWAIT, &sc->cmd_map); 514 if (error != 0) { 515 aprint_error("%s: could not create cmd dma map\n", 516 sc->sc_dev.dv_xname); 517 goto fail; 518 } 519 520 error = bus_dmamem_alloc(sc->sc_dmat, sizeof (struct ipw_cmd), 521 PAGE_SIZE, 0, &sc->cmd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 522 if (error != 0) { 523 aprint_error("%s: could not allocate cmd dma memory\n", 524 sc->sc_dev.dv_xname); 525 goto fail; 526 } 527 528 error = bus_dmamem_map(sc->sc_dmat, &sc->cmd_seg, nsegs, 529 sizeof (struct ipw_cmd), (caddr_t *)&sc->cmd, BUS_DMA_NOWAIT); 530 if (error != 0) { 531 aprint_error("%s: could not map cmd dma memory\n", 532 sc->sc_dev.dv_xname); 533 goto fail; 534 } 535 536 error = bus_dmamap_load(sc->sc_dmat, sc->cmd_map, &sc->cmd, 537 sizeof (struct ipw_cmd), NULL, BUS_DMA_NOWAIT); 538 if (error != 0) { 539 aprint_error("%s: could not map cmd dma memory\n", 540 sc->sc_dev.dv_xname); 541 return error; 542 } 543 544 /* 545 * Allocate and map hdr list. 546 */ 547 548 error = bus_dmamap_create(sc->sc_dmat, 549 IPW_NDATA * sizeof(struct ipw_hdr), 1, 550 sizeof(struct ipw_hdr), 0, BUS_DMA_NOWAIT, 551 &sc->hdr_map); 552 if (error != 0) { 553 aprint_error("%s: could not create hdr dma map\n", 554 sc->sc_dev.dv_xname); 555 goto fail; 556 } 557 558 error = bus_dmamem_alloc(sc->sc_dmat, 559 IPW_NDATA * sizeof(struct ipw_hdr), PAGE_SIZE, 0, &sc->hdr_seg, 560 1, &nsegs, BUS_DMA_NOWAIT); 561 if (error != 0) { 562 aprint_error("%s: could not allocate hdr memory\n", 563 sc->sc_dev.dv_xname); 564 goto fail; 565 } 566 567 error = bus_dmamem_map(sc->sc_dmat, &sc->hdr_seg, nsegs, 568 IPW_NDATA * sizeof(struct ipw_hdr), (caddr_t *)&sc->hdr_list, 569 BUS_DMA_NOWAIT); 570 if (error != 0) { 571 aprint_error("%s: could not map hdr memory\n", 572 sc->sc_dev.dv_xname); 573 goto fail; 574 } 575 576 error = bus_dmamap_load(sc->sc_dmat, sc->hdr_map, sc->hdr_list, 577 IPW_NDATA * sizeof(struct ipw_hdr), NULL, BUS_DMA_NOWAIT); 578 if (error != 0) { 579 aprint_error("%s: could not load hdr memory\n", 580 sc->sc_dev.dv_xname); 581 goto fail; 582 } 583 584 (void)memset(sc->hdr_list, 0, IPW_HDR_SZ); 585 586 /* 587 * Create DMA hdrs tailq. 588 */ 589 TAILQ_INIT(&sc->sc_free_shdr); 590 for (i = 0; i < IPW_NDATA; i++) { 591 shdr = &sc->shdr_list[i]; 592 shdr->hdr = sc->hdr_list + i; 593 shdr->offset = sizeof(struct ipw_hdr) * i; 594 shdr->addr = sc->hdr_map->dm_segs[0].ds_addr + shdr->offset; 595 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 596 } 597 598 /* 599 * Allocate tx buffers DMA maps. 600 */ 601 TAILQ_INIT(&sc->sc_free_sbuf); 602 for (i = 0; i < IPW_NDATA; i++) { 603 sbuf = &sc->tx_sbuf_list[i]; 604 605 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 606 IPW_MAX_NSEG, MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 607 if (error != 0) { 608 aprint_error("%s: could not create txbuf dma map\n", 609 sc->sc_dev.dv_xname); 610 goto fail; 611 } 612 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 613 } 614 615 /* 616 * Initialize tx ring. 617 */ 618 for (i = 0; i < IPW_NTBD; i++) { 619 sbd = &sc->stbd_list[i]; 620 sbd->bd = &sc->tbd_list[i]; 621 sbd->type = IPW_SBD_TYPE_NOASSOC; 622 } 623 624 /* 625 * Pre-allocate rx buffers and DMA maps 626 */ 627 for (i = 0; i < IPW_NRBD; i++) { 628 sbd = &sc->srbd_list[i]; 629 sbuf = &sc->rx_sbuf_list[i]; 630 sbd->bd = &sc->rbd_list[i]; 631 632 MGETHDR(sbuf->m, M_DONTWAIT, MT_DATA); 633 if (sbuf->m == NULL) { 634 aprint_error("%s: could not allocate rx mbuf\n", 635 sc->sc_dev.dv_xname); 636 error = ENOMEM; 637 goto fail; 638 } 639 640 MCLGET(sbuf->m, M_DONTWAIT); 641 if (!(sbuf->m->m_flags & M_EXT)) { 642 m_freem(sbuf->m); 643 aprint_error("%s: could not allocate rx mbuf cluster\n", 644 sc->sc_dev.dv_xname); 645 error = ENOMEM; 646 goto fail; 647 } 648 649 sbuf->m->m_pkthdr.len = sbuf->m->m_len = sbuf->m->m_ext.ext_size; 650 651 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 652 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sbuf->map); 653 if (error != 0) { 654 aprint_error("%s: could not create rxbuf dma map\n", 655 sc->sc_dev.dv_xname); 656 m_freem(sbuf->m); 657 goto fail; 658 } 659 660 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, 661 sbuf->m, BUS_DMA_READ | BUS_DMA_NOWAIT); 662 if (error != 0) { 663 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 664 m_freem(sbuf->m); 665 aprint_error("%s: could not map rxbuf dma memory\n", 666 sc->sc_dev.dv_xname); 667 goto fail; 668 } 669 670 sbd->type = IPW_SBD_TYPE_DATA; 671 sbd->priv = sbuf; 672 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 673 sbd->bd->len = htole32(MCLBYTES); 674 675 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, 676 sbuf->map->dm_mapsize, BUS_DMASYNC_PREREAD); 677 678 } 679 680 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 0, IPW_RBD_SZ, 681 BUS_DMASYNC_PREREAD); 682 683 return 0; 684 685 fail: ipw_release(sc); 686 return error; 687 } 688 689 static void 690 ipw_release(struct ipw_softc *sc) 691 { 692 struct ipw_soft_buf *sbuf; 693 int i; 694 695 if (sc->tbd_map != NULL) { 696 if (sc->tbd_list != NULL) { 697 bus_dmamap_unload(sc->sc_dmat, sc->tbd_map); 698 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->tbd_list, 699 IPW_TBD_SZ); 700 bus_dmamem_free(sc->sc_dmat, &sc->tbd_seg, 1); 701 } 702 bus_dmamap_destroy(sc->sc_dmat, sc->tbd_map); 703 } 704 705 if (sc->rbd_map != NULL) { 706 if (sc->rbd_list != NULL) { 707 bus_dmamap_unload(sc->sc_dmat, sc->rbd_map); 708 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->rbd_list, 709 IPW_RBD_SZ); 710 bus_dmamem_free(sc->sc_dmat, &sc->rbd_seg, 1); 711 } 712 bus_dmamap_destroy(sc->sc_dmat, sc->rbd_map); 713 } 714 715 if (sc->status_map != NULL) { 716 if (sc->status_list != NULL) { 717 bus_dmamap_unload(sc->sc_dmat, sc->status_map); 718 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->status_list, 719 IPW_RBD_SZ); 720 bus_dmamem_free(sc->sc_dmat, &sc->status_seg, 1); 721 } 722 bus_dmamap_destroy(sc->sc_dmat, sc->status_map); 723 } 724 725 for (i = 0; i < IPW_NTBD; i++) 726 ipw_release_sbd(sc, &sc->stbd_list[i]); 727 728 if (sc->cmd_map != NULL) 729 bus_dmamap_destroy(sc->sc_dmat, sc->cmd_map); 730 731 if (sc->hdr_list != NULL) { 732 bus_dmamap_unload(sc->sc_dmat, sc->hdr_map); 733 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->hdr_list, 734 IPW_NDATA * sizeof(struct ipw_hdr)); 735 } 736 if (sc->hdr_map != NULL) { 737 bus_dmamem_free(sc->sc_dmat, &sc->hdr_seg, 1); 738 bus_dmamap_destroy(sc->sc_dmat, sc->hdr_map); 739 } 740 741 for (i = 0; i < IPW_NDATA; i++) 742 bus_dmamap_destroy(sc->sc_dmat, sc->tx_sbuf_list[i].map); 743 744 for (i = 0; i < IPW_NRBD; i++) { 745 sbuf = &sc->rx_sbuf_list[i]; 746 if (sbuf->map != NULL) { 747 if (sbuf->m != NULL) { 748 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 749 m_freem(sbuf->m); 750 } 751 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 752 } 753 } 754 755 } 756 757 static void 758 ipw_shutdown(void *arg) 759 { 760 struct ipw_softc *sc = (struct ipw_softc *)arg; 761 struct ifnet *ifp = sc->sc_ic.ic_ifp; 762 763 ipw_stop(ifp, 1); 764 } 765 766 767 static int 768 ipw_suspend(struct ipw_softc *sc) 769 { 770 struct ifnet *ifp = sc->sc_ic.ic_ifp; 771 772 ipw_stop(ifp, 1); 773 774 return 0; 775 } 776 777 static int 778 ipw_resume(struct ipw_softc *sc) 779 { 780 struct ifnet *ifp = sc->sc_ic.ic_ifp; 781 pcireg_t data; 782 783 /* clear device specific PCI configuration register 0x41 */ 784 data = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 785 data &= ~0x0000ff00; 786 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, data); 787 788 if (ifp->if_flags & IFF_UP) { 789 ipw_init(ifp); 790 if (ifp->if_flags & IFF_RUNNING) 791 ipw_start(ifp); 792 } 793 794 return 0; 795 } 796 797 static void 798 ipw_powerhook(int why, void *arg) 799 { 800 struct ipw_softc *sc = arg; 801 int s; 802 803 s = splnet(); 804 switch (why) { 805 case PWR_SUSPEND: 806 case PWR_STANDBY: 807 ipw_suspend(sc); 808 break; 809 case PWR_RESUME: 810 ipw_resume(sc); 811 break; 812 case PWR_SOFTSUSPEND: 813 case PWR_SOFTSTANDBY: 814 case PWR_SOFTRESUME: 815 break; 816 } 817 splx(s); 818 } 819 820 static int 821 ipw_media_change(struct ifnet *ifp) 822 { 823 int error; 824 825 error = ieee80211_media_change(ifp); 826 if (error != ENETRESET) 827 return error; 828 829 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 830 ipw_init(ifp); 831 832 return 0; 833 } 834 835 /* 836 * The firmware automatically adapts the transmit speed. We report the current 837 * transmit speed here. 838 */ 839 static void 840 ipw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 841 { 842 #define N(a) (sizeof (a) / sizeof (a[0])) 843 struct ipw_softc *sc = ifp->if_softc; 844 struct ieee80211com *ic = &sc->sc_ic; 845 static const struct { 846 uint32_t val; 847 int rate; 848 } rates[] = { 849 { IPW_RATE_DS1, 2 }, 850 { IPW_RATE_DS2, 4 }, 851 { IPW_RATE_DS5, 11 }, 852 { IPW_RATE_DS11, 22 }, 853 }; 854 uint32_t val; 855 int rate, i; 856 857 imr->ifm_status = IFM_AVALID; 858 imr->ifm_active = IFM_IEEE80211; 859 if (ic->ic_state == IEEE80211_S_RUN) 860 imr->ifm_status |= IFM_ACTIVE; 861 862 /* read current transmission rate from adapter */ 863 val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE) & 0xf; 864 865 /* convert ipw rate to 802.11 rate */ 866 for (i = 0; i < N(rates) && rates[i].val != val; i++); 867 rate = (i < N(rates)) ? rates[i].rate : 0; 868 869 imr->ifm_active |= IFM_IEEE80211_11B; 870 imr->ifm_active |= ieee80211_rate2media(ic, rate, IEEE80211_MODE_11B); 871 switch (ic->ic_opmode) { 872 case IEEE80211_M_STA: 873 break; 874 875 case IEEE80211_M_IBSS: 876 imr->ifm_active |= IFM_IEEE80211_ADHOC; 877 break; 878 879 case IEEE80211_M_MONITOR: 880 imr->ifm_active |= IFM_IEEE80211_MONITOR; 881 break; 882 883 case IEEE80211_M_AHDEMO: 884 case IEEE80211_M_HOSTAP: 885 /* should not get there */ 886 break; 887 } 888 #undef N 889 } 890 891 static int 892 ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 893 { 894 struct ifnet *ifp = ic->ic_ifp; 895 struct ipw_softc *sc = ifp->if_softc; 896 struct ieee80211_node *ni; 897 uint8_t macaddr[IEEE80211_ADDR_LEN]; 898 uint32_t len; 899 900 switch (nstate) { 901 case IEEE80211_S_RUN: 902 DELAY(200); /* firmware needs a short delay here */ 903 904 len = IEEE80211_ADDR_LEN; 905 ipw_read_table2(sc, IPW_INFO_CURRENT_BSSID, macaddr, &len); 906 907 ni = ieee80211_find_node(&ic->ic_scan, macaddr); 908 if (ni == NULL) 909 break; 910 911 ieee80211_ref_node(ni); 912 ieee80211_sta_join(ic, ni); 913 ieee80211_node_authorize(ni); 914 915 if (ic->ic_opmode == IEEE80211_M_STA) 916 ieee80211_notify_node_join(ic, ni, 1); 917 break; 918 919 case IEEE80211_S_INIT: 920 case IEEE80211_S_SCAN: 921 case IEEE80211_S_AUTH: 922 case IEEE80211_S_ASSOC: 923 break; 924 } 925 926 ic->ic_state = nstate; 927 return 0; 928 } 929 930 /* 931 * Read 16 bits at address 'addr' from the serial EEPROM. 932 */ 933 static uint16_t 934 ipw_read_prom_word(struct ipw_softc *sc, uint8_t addr) 935 { 936 uint32_t tmp; 937 uint16_t val; 938 int n; 939 940 /* clock C once before the first command */ 941 IPW_EEPROM_CTL(sc, 0); 942 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 943 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 944 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 945 946 /* write start bit (1) */ 947 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 948 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 949 950 /* write READ opcode (10) */ 951 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 952 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 953 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 954 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 955 956 /* write address A7-A0 */ 957 for (n = 7; n >= 0; n--) { 958 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 959 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D)); 960 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 961 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D) | IPW_EEPROM_C); 962 } 963 964 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 965 966 /* read data Q15-Q0 */ 967 val = 0; 968 for (n = 15; n >= 0; n--) { 969 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 970 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 971 tmp = MEM_READ_4(sc, IPW_MEM_EEPROM_CTL); 972 val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n; 973 } 974 975 IPW_EEPROM_CTL(sc, 0); 976 977 /* clear Chip Select and clock C */ 978 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 979 IPW_EEPROM_CTL(sc, 0); 980 IPW_EEPROM_CTL(sc, IPW_EEPROM_C); 981 982 return le16toh(val); 983 } 984 985 static void 986 ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 987 { 988 struct ipw_cmd *cmd; 989 990 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof (struct ipw_cmd), 991 BUS_DMASYNC_POSTREAD); 992 993 cmd = mtod(sbuf->m, struct ipw_cmd *); 994 995 DPRINTFN(2, ("cmd ack'ed (%u, %u, %u, %u, %u)\n", le32toh(cmd->type), 996 le32toh(cmd->subtype), le32toh(cmd->seq), le32toh(cmd->len), 997 le32toh(cmd->status))); 998 999 wakeup(&sc->cmd); 1000 } 1001 1002 static void 1003 ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 1004 { 1005 struct ieee80211com *ic = &sc->sc_ic; 1006 struct ifnet *ifp = sc->sc_ic.ic_ifp; 1007 uint32_t state; 1008 1009 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof state, 1010 BUS_DMASYNC_POSTREAD); 1011 1012 state = le32toh(*mtod(sbuf->m, uint32_t *)); 1013 1014 DPRINTFN(2, ("entering state %u\n", state)); 1015 1016 switch (state) { 1017 case IPW_STATE_ASSOCIATED: 1018 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1019 break; 1020 1021 case IPW_STATE_SCANNING: 1022 /* don't leave run state on background scan */ 1023 if (ic->ic_state != IEEE80211_S_RUN) 1024 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1025 1026 ic->ic_flags |= IEEE80211_F_SCAN; 1027 break; 1028 1029 case IPW_STATE_SCAN_COMPLETE: 1030 ieee80211_notify_scan_done(ic); 1031 ic->ic_flags &= ~IEEE80211_F_SCAN; 1032 break; 1033 1034 case IPW_STATE_ASSOCIATION_LOST: 1035 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1036 break; 1037 1038 case IPW_STATE_RADIO_DISABLED: 1039 ic->ic_ifp->if_flags &= ~IFF_UP; 1040 ipw_stop(ifp, 1); 1041 break; 1042 } 1043 } 1044 1045 /* 1046 * XXX: Hack to set the current channel to the value advertised in beacons or 1047 * probe responses. Only used during AP detection. 1048 */ 1049 static void 1050 ipw_fix_channel(struct ieee80211com *ic, struct mbuf *m) 1051 { 1052 struct ieee80211_frame *wh; 1053 uint8_t subtype; 1054 uint8_t *frm, *efrm; 1055 1056 wh = mtod(m, struct ieee80211_frame *); 1057 1058 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_MGT) 1059 return; 1060 1061 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 1062 1063 if (subtype != IEEE80211_FC0_SUBTYPE_BEACON && 1064 subtype != IEEE80211_FC0_SUBTYPE_PROBE_RESP) 1065 return; 1066 1067 frm = (uint8_t *)(wh + 1); 1068 efrm = mtod(m, uint8_t *) + m->m_len; 1069 1070 frm += 12; /* skip tstamp, bintval and capinfo fields */ 1071 while (frm < efrm) { 1072 if (*frm == IEEE80211_ELEMID_DSPARMS) 1073 #if IEEE80211_CHAN_MAX < 255 1074 if (frm[2] <= IEEE80211_CHAN_MAX) 1075 #endif 1076 ic->ic_curchan = &ic->ic_channels[frm[2]]; 1077 1078 frm += frm[1] + 2; 1079 } 1080 } 1081 1082 static void 1083 ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 1084 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 1085 { 1086 struct ieee80211com *ic = &sc->sc_ic; 1087 struct ifnet *ifp = &sc->sc_if; 1088 struct mbuf *mnew, *m; 1089 struct ieee80211_frame *wh; 1090 struct ieee80211_node *ni; 1091 int error; 1092 1093 DPRINTFN(5, ("received frame len=%u, rssi=%u\n", le32toh(status->len), 1094 status->rssi)); 1095 1096 if (le32toh(status->len) < sizeof (struct ieee80211_frame_min) || 1097 le32toh(status->len) > MCLBYTES) 1098 return; 1099 1100 /* 1101 * Try to allocate a new mbuf for this ring element and load it before 1102 * processing the current mbuf. If the ring element cannot be loaded, 1103 * drop the received packet and reuse the old mbuf. In the unlikely 1104 * case that the old mbuf can't be reloaded either, explicitly panic. 1105 */ 1106 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1107 if (mnew == NULL) { 1108 aprint_error("%s: could not allocate rx mbuf\n", 1109 sc->sc_dev.dv_xname); 1110 ifp->if_ierrors++; 1111 return; 1112 } 1113 1114 MCLGET(mnew, M_DONTWAIT); 1115 if (!(mnew->m_flags & M_EXT)) { 1116 aprint_error("%s: could not allocate rx mbuf cluster\n", 1117 sc->sc_dev.dv_xname); 1118 m_freem(mnew); 1119 ifp->if_ierrors++; 1120 return; 1121 } 1122 1123 mnew->m_pkthdr.len = mnew->m_len = mnew->m_ext.ext_size; 1124 1125 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, le32toh(status->len), 1126 BUS_DMASYNC_POSTREAD); 1127 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1128 1129 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, mnew, 1130 BUS_DMA_READ | BUS_DMA_NOWAIT); 1131 if (error != 0) { 1132 aprint_error("%s: could not load rx buf DMA map\n", 1133 sc->sc_dev.dv_xname); 1134 m_freem(mnew); 1135 1136 /* try to reload the old mbuf */ 1137 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, 1138 sbuf->m, BUS_DMA_READ | BUS_DMA_NOWAIT); 1139 if (error != 0) { 1140 /* very unlikely that it will fail... */ 1141 panic("%s: unable to remap rx buf", 1142 sc->sc_dev.dv_xname); 1143 } 1144 ifp->if_ierrors++; 1145 return; 1146 } 1147 1148 /* 1149 * New mbuf successfully loaded, update Rx ring and continue 1150 * processing. 1151 */ 1152 m = sbuf->m; 1153 sbuf->m = mnew; 1154 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 1155 1156 /* finalize mbuf */ 1157 m->m_pkthdr.rcvif = ifp; 1158 m->m_pkthdr.len = m->m_len = le32toh(status->len); 1159 1160 #if NBPFILTER > 0 1161 if (sc->sc_drvbpf != NULL) { 1162 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 1163 1164 tap->wr_flags = 0; 1165 tap->wr_antsignal = status->rssi; 1166 tap->wr_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 1167 tap->wr_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 1168 1169 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 1170 } 1171 #endif 1172 1173 if (ic->ic_state == IEEE80211_S_SCAN) 1174 ipw_fix_channel(ic, m); 1175 1176 wh = mtod(m, struct ieee80211_frame *); 1177 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 1178 1179 /* send the frame to the 802.11 layer */ 1180 ieee80211_input(ic, m, ni, status->rssi, 0); 1181 1182 /* node is no longer needed */ 1183 ieee80211_free_node(ni); 1184 1185 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, 1186 sbuf->map->dm_mapsize, BUS_DMASYNC_PREREAD); 1187 } 1188 1189 static void 1190 ipw_rx_intr(struct ipw_softc *sc) 1191 { 1192 struct ipw_status *status; 1193 struct ipw_soft_bd *sbd; 1194 struct ipw_soft_buf *sbuf; 1195 uint32_t r, i; 1196 1197 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1198 return; 1199 1200 r = CSR_READ_4(sc, IPW_CSR_RX_READ); 1201 1202 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 1203 1204 /* firmware was killed, stop processing received frames */ 1205 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1206 return; 1207 1208 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 1209 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1210 BUS_DMASYNC_POSTREAD); 1211 1212 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 1213 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 1214 BUS_DMASYNC_POSTREAD); 1215 1216 status = &sc->status_list[i]; 1217 sbd = &sc->srbd_list[i]; 1218 sbuf = sbd->priv; 1219 1220 switch (le16toh(status->code) & 0xf) { 1221 case IPW_STATUS_CODE_COMMAND: 1222 ipw_command_intr(sc, sbuf); 1223 break; 1224 1225 case IPW_STATUS_CODE_NEWSTATE: 1226 ipw_newstate_intr(sc, sbuf); 1227 break; 1228 1229 case IPW_STATUS_CODE_DATA_802_3: 1230 case IPW_STATUS_CODE_DATA_802_11: 1231 ipw_data_intr(sc, status, sbd, sbuf); 1232 break; 1233 1234 case IPW_STATUS_CODE_NOTIFICATION: 1235 DPRINTFN(2, ("received notification\n")); 1236 break; 1237 1238 default: 1239 aprint_error("%s: unknown status code %u\n", 1240 sc->sc_dev.dv_xname, le16toh(status->code)); 1241 } 1242 1243 sbd->bd->flags = 0; 1244 1245 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 1246 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1247 BUS_DMASYNC_PREREAD); 1248 1249 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 1250 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 1251 BUS_DMASYNC_PREREAD); 1252 } 1253 1254 /* Tell the firmware what we have processed */ 1255 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 1256 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 1257 } 1258 1259 static void 1260 ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 1261 { 1262 struct ieee80211com *ic; 1263 struct ipw_soft_hdr *shdr; 1264 struct ipw_soft_buf *sbuf; 1265 1266 switch (sbd->type) { 1267 case IPW_SBD_TYPE_COMMAND: 1268 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 1269 0, sizeof(struct ipw_cmd), BUS_DMASYNC_POSTWRITE); 1270 /* bus_dmamap_unload(sc->sc_dmat, sc->cmd_map); */ 1271 break; 1272 1273 case IPW_SBD_TYPE_HEADER: 1274 shdr = sbd->priv; 1275 bus_dmamap_sync(sc->sc_dmat, sc->hdr_map, 1276 shdr->offset, sizeof(struct ipw_hdr), BUS_DMASYNC_POSTWRITE); 1277 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 1278 break; 1279 1280 case IPW_SBD_TYPE_DATA: 1281 ic = &sc->sc_ic; 1282 sbuf = sbd->priv; 1283 1284 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 1285 0, MCLBYTES, BUS_DMASYNC_POSTWRITE); 1286 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1287 m_freem(sbuf->m); 1288 if (sbuf->ni != NULL) 1289 ieee80211_free_node(sbuf->ni); 1290 /* kill watchdog timer */ 1291 sc->sc_tx_timer = 0; 1292 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 1293 break; 1294 } 1295 sbd->type = IPW_SBD_TYPE_NOASSOC; 1296 } 1297 1298 static void 1299 ipw_tx_intr(struct ipw_softc *sc) 1300 { 1301 struct ifnet *ifp = &sc->sc_if; 1302 struct ipw_soft_bd *sbd; 1303 uint32_t r, i; 1304 1305 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1306 return; 1307 1308 r = CSR_READ_4(sc, IPW_CSR_TX_READ); 1309 1310 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) { 1311 sbd = &sc->stbd_list[i]; 1312 1313 if (sbd->type == IPW_SBD_TYPE_DATA) 1314 ifp->if_opackets++; 1315 1316 ipw_release_sbd(sc, sbd); 1317 sc->txfree++; 1318 } 1319 1320 /* remember what the firmware has processed */ 1321 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 1322 1323 /* Call start() since some buffer descriptors have been released */ 1324 ifp->if_flags &= ~IFF_OACTIVE; 1325 (*ifp->if_start)(ifp); 1326 } 1327 1328 static int 1329 ipw_intr(void *arg) 1330 { 1331 struct ipw_softc *sc = arg; 1332 uint32_t r; 1333 1334 r = CSR_READ_4(sc, IPW_CSR_INTR); 1335 if (r == 0 || r == 0xffffffff) 1336 return 0; 1337 1338 /* Disable interrupts */ 1339 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1340 1341 if (r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR)) { 1342 aprint_error("%s: fatal error\n", 1343 sc->sc_dev.dv_xname); 1344 sc->sc_ic.ic_ifp->if_flags &= ~IFF_UP; 1345 ipw_stop(&sc->sc_if, 1); 1346 } 1347 1348 if (r & IPW_INTR_FW_INIT_DONE) { 1349 if (!(r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR))) 1350 wakeup(sc); 1351 } 1352 1353 if (r & IPW_INTR_RX_TRANSFER) 1354 ipw_rx_intr(sc); 1355 1356 if (r & IPW_INTR_TX_TRANSFER) 1357 ipw_tx_intr(sc); 1358 1359 /* Acknowledge all interrupts */ 1360 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 1361 1362 /* Re-enable interrupts */ 1363 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1364 1365 return 0; 1366 } 1367 1368 /* 1369 * Send a command to the firmware and wait for the acknowledgement. 1370 */ 1371 static int 1372 ipw_cmd(struct ipw_softc *sc, uint32_t type, void *data, uint32_t len) 1373 { 1374 struct ipw_soft_bd *sbd; 1375 1376 sbd = &sc->stbd_list[sc->txcur]; 1377 1378 sc->cmd.type = htole32(type); 1379 sc->cmd.subtype = 0; 1380 sc->cmd.len = htole32(len); 1381 sc->cmd.seq = 0; 1382 1383 (void)memcpy(sc->cmd.data, data, len); 1384 1385 sbd->type = IPW_SBD_TYPE_COMMAND; 1386 sbd->bd->physaddr = htole32(sc->cmd_map->dm_segs[0].ds_addr); 1387 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 1388 sbd->bd->nfrag = 1; 1389 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 1390 IPW_BD_FLAG_TX_LAST_FRAGMENT; 1391 1392 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 0, sizeof (struct ipw_cmd), 1393 BUS_DMASYNC_PREWRITE); 1394 1395 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1396 sc->txcur * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1397 BUS_DMASYNC_PREWRITE); 1398 1399 DPRINTFN(2, ("sending command (%u, %u, %u, %u)\n", type, 0, 0, len)); 1400 1401 /* kick firmware */ 1402 sc->txfree--; 1403 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1404 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1405 1406 /* Wait at most one second for command to complete */ 1407 return tsleep(&sc->cmd, 0, "ipwcmd", hz); 1408 } 1409 1410 static int 1411 ipw_tx_start(struct ifnet *ifp, struct mbuf *m0, struct ieee80211_node *ni) 1412 { 1413 struct ipw_softc *sc = ifp->if_softc; 1414 struct ieee80211com *ic = &sc->sc_ic; 1415 struct ieee80211_frame *wh; 1416 struct ipw_soft_bd *sbd; 1417 struct ipw_soft_hdr *shdr; 1418 struct ipw_soft_buf *sbuf; 1419 struct ieee80211_key *k; 1420 struct mbuf *mnew; 1421 int error, i; 1422 1423 wh = mtod(m0, struct ieee80211_frame *); 1424 1425 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1426 k = ieee80211_crypto_encap(ic, ni, m0); 1427 if (k == NULL) { 1428 m_freem(m0); 1429 return ENOBUFS; 1430 } 1431 1432 /* packet header may have moved, reset our local pointer */ 1433 wh = mtod(m0, struct ieee80211_frame *); 1434 } 1435 1436 #if NBPFILTER > 0 1437 if (sc->sc_drvbpf != NULL) { 1438 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 1439 1440 tap->wt_flags = 0; 1441 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 1442 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 1443 1444 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 1445 } 1446 #endif 1447 1448 shdr = TAILQ_FIRST(&sc->sc_free_shdr); 1449 sbuf = TAILQ_FIRST(&sc->sc_free_sbuf); 1450 KASSERT(shdr != NULL && sbuf != NULL); 1451 1452 shdr->hdr->type = htole32(IPW_HDR_TYPE_SEND); 1453 shdr->hdr->subtype = 0; 1454 shdr->hdr->encrypted = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0; 1455 shdr->hdr->encrypt = 0; 1456 shdr->hdr->keyidx = 0; 1457 shdr->hdr->keysz = 0; 1458 shdr->hdr->fragmentsz = 0; 1459 IEEE80211_ADDR_COPY(shdr->hdr->src_addr, wh->i_addr2); 1460 if (ic->ic_opmode == IEEE80211_M_STA) 1461 IEEE80211_ADDR_COPY(shdr->hdr->dst_addr, wh->i_addr3); 1462 else 1463 IEEE80211_ADDR_COPY(shdr->hdr->dst_addr, wh->i_addr1); 1464 1465 /* trim IEEE802.11 header */ 1466 m_adj(m0, sizeof (struct ieee80211_frame)); 1467 1468 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m0, BUS_DMA_NOWAIT); 1469 if (error != 0 && error != EFBIG) { 1470 aprint_error("%s: could not map mbuf (error %d)\n", 1471 sc->sc_dev.dv_xname, error); 1472 m_freem(m0); 1473 return error; 1474 } 1475 1476 if (error != 0) { 1477 /* too many fragments, linearize */ 1478 1479 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1480 if (mnew == NULL) { 1481 m_freem(m0); 1482 return ENOMEM; 1483 } 1484 1485 M_COPY_PKTHDR(mnew, m0); 1486 1487 /* If the data won't fit in the header, get a cluster */ 1488 if (m0->m_pkthdr.len > MHLEN) { 1489 MCLGET(mnew, M_DONTWAIT); 1490 if (!(mnew->m_flags & M_EXT)) { 1491 m_freem(m0); 1492 m_freem(mnew); 1493 return ENOMEM; 1494 } 1495 } 1496 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(mnew, caddr_t)); 1497 m_freem(m0); 1498 mnew->m_len = mnew->m_pkthdr.len; 1499 m0 = mnew; 1500 1501 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m0, 1502 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1503 if (error != 0) { 1504 aprint_error("%s: could not map mbuf (error %d)\n", 1505 sc->sc_dev.dv_xname, error); 1506 m_freem(m0); 1507 return error; 1508 } 1509 } 1510 1511 TAILQ_REMOVE(&sc->sc_free_sbuf, sbuf, next); 1512 TAILQ_REMOVE(&sc->sc_free_shdr, shdr, next); 1513 1514 sbd = &sc->stbd_list[sc->txcur]; 1515 sbd->type = IPW_SBD_TYPE_HEADER; 1516 sbd->priv = shdr; 1517 sbd->bd->physaddr = htole32(shdr->addr); 1518 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 1519 sbd->bd->nfrag = 1 + sbuf->map->dm_nsegs; 1520 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 1521 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1522 1523 DPRINTFN(5, ("sending tx hdr (%u, %u, %u, %u, )\n", 1524 shdr->hdr->type, shdr->hdr->subtype, shdr->hdr->encrypted, 1525 shdr->hdr->encrypt)); 1526 DPRINTFN(5, ("%s->", ether_sprintf(shdr->hdr->src_addr))); 1527 DPRINTFN(5, ("%s\n", ether_sprintf(shdr->hdr->dst_addr))); 1528 1529 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1530 sc->txcur * sizeof (struct ipw_bd), 1531 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1532 1533 sc->txfree--; 1534 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1535 1536 sbuf->m = m0; 1537 sbuf->ni = ni; 1538 1539 for (i = 0; i < sbuf->map->dm_nsegs; i++) { 1540 sbd = &sc->stbd_list[sc->txcur]; 1541 1542 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[i].ds_addr); 1543 sbd->bd->len = htole32(sbuf->map->dm_segs[i].ds_len); 1544 sbd->bd->nfrag = 0; 1545 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 1546 if (i == sbuf->map->dm_nsegs - 1) { 1547 sbd->type = IPW_SBD_TYPE_DATA; 1548 sbd->priv = sbuf; 1549 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 1550 } else { 1551 sbd->type = IPW_SBD_TYPE_NOASSOC; 1552 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1553 } 1554 1555 DPRINTFN(5, ("sending fragment (%d, %d)\n", i, 1556 (int)sbuf->map->dm_segs[i].ds_len)); 1557 1558 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1559 sc->txcur * sizeof (struct ipw_bd), 1560 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1561 1562 sc->txfree--; 1563 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1564 } 1565 1566 bus_dmamap_sync(sc->sc_dmat, sc->hdr_map, shdr->offset, 1567 sizeof (struct ipw_hdr), BUS_DMASYNC_PREWRITE); 1568 1569 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, MCLBYTES, 1570 BUS_DMASYNC_PREWRITE); 1571 1572 /* Inform firmware about this new packet */ 1573 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1574 1575 return 0; 1576 } 1577 1578 static void 1579 ipw_start(struct ifnet *ifp) 1580 { 1581 struct ipw_softc *sc = ifp->if_softc; 1582 struct ieee80211com *ic = &sc->sc_ic; 1583 struct mbuf *m0; 1584 struct ether_header *eh; 1585 struct ieee80211_node *ni; 1586 1587 1588 if (ic->ic_state != IEEE80211_S_RUN) 1589 return; 1590 1591 for (;;) { 1592 IF_DEQUEUE(&ifp->if_snd, m0); 1593 if (m0 == NULL) 1594 break; 1595 1596 if (sc->txfree < 1 + IPW_MAX_NSEG) { 1597 IF_PREPEND(&ifp->if_snd, m0); 1598 ifp->if_flags |= IFF_OACTIVE; 1599 break; 1600 } 1601 1602 if (m0->m_len < sizeof (struct ether_header) && 1603 (m0 = m_pullup(m0, sizeof (struct ether_header))) == NULL) 1604 continue; 1605 1606 eh = mtod(m0, struct ether_header *); 1607 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1608 if (ni == NULL) { 1609 m_freem(m0); 1610 continue; 1611 } 1612 1613 #if NBPFILTER > 0 1614 if (ifp->if_bpf != NULL) 1615 bpf_mtap(ifp->if_bpf, m0); 1616 #endif 1617 1618 m0 = ieee80211_encap(ic, m0, ni); 1619 if (m0 == NULL) { 1620 ieee80211_free_node(ni); 1621 continue; 1622 } 1623 1624 #if NBPFILTER > 0 1625 if (ic->ic_rawbpf != NULL) 1626 bpf_mtap(ic->ic_rawbpf, m0); 1627 #endif 1628 1629 if (ipw_tx_start(ifp, m0, ni) != 0) { 1630 ieee80211_free_node(ni); 1631 ifp->if_oerrors++; 1632 break; 1633 } 1634 1635 /* start watchdog timer */ 1636 sc->sc_tx_timer = 5; 1637 ifp->if_timer = 1; 1638 } 1639 } 1640 1641 static void 1642 ipw_watchdog(struct ifnet *ifp) 1643 { 1644 struct ipw_softc *sc = ifp->if_softc; 1645 1646 ifp->if_timer = 0; 1647 1648 if (sc->sc_tx_timer > 0) { 1649 if (--sc->sc_tx_timer == 0) { 1650 aprint_error("%s: device timeout\n", 1651 sc->sc_dev.dv_xname); 1652 ifp->if_oerrors++; 1653 ifp->if_flags &= ~IFF_UP; 1654 ipw_stop(ifp, 1); 1655 return; 1656 } 1657 ifp->if_timer = 1; 1658 } 1659 1660 ieee80211_watchdog(&sc->sc_ic); 1661 } 1662 1663 static int 1664 ipw_get_table1(struct ipw_softc *sc, uint32_t *tbl) 1665 { 1666 uint32_t addr, size, i; 1667 1668 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1669 return ENOTTY; 1670 1671 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, sc->table1_base); 1672 1673 size = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 1674 if (suword(tbl, size) != 0) 1675 return EFAULT; 1676 1677 for (i = 1, ++tbl; i < size; i++, tbl++) { 1678 addr = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 1679 if (suword(tbl, MEM_READ_4(sc, addr)) != 0) 1680 return EFAULT; 1681 } 1682 return 0; 1683 } 1684 1685 static int 1686 ipw_get_radio(struct ipw_softc *sc, int *ret) 1687 { 1688 uint32_t addr; 1689 1690 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1691 return ENOTTY; 1692 1693 addr = ipw_read_table1(sc, IPW_INFO_EEPROM_ADDRESS); 1694 if ((MEM_READ_4(sc, addr + 32) >> 24) & 1) { 1695 suword(ret, -1); 1696 return 0; 1697 } 1698 1699 if (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED) 1700 suword(ret, 0); 1701 else 1702 suword(ret, 1); 1703 1704 return 0; 1705 } 1706 1707 static int 1708 ipw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1709 { 1710 #define IS_RUNNING(ifp) \ 1711 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 1712 1713 struct ipw_softc *sc = ifp->if_softc; 1714 struct ieee80211com *ic = &sc->sc_ic; 1715 struct ifreq *ifr = (struct ifreq *)data; 1716 int s, error = 0; 1717 1718 s = splnet(); 1719 1720 switch (cmd) { 1721 case SIOCSIFFLAGS: 1722 if (ifp->if_flags & IFF_UP) { 1723 if (!(ifp->if_flags & IFF_RUNNING)) 1724 ipw_init(ifp); 1725 } else { 1726 if (ifp->if_flags & IFF_RUNNING) 1727 ipw_stop(ifp, 1); 1728 } 1729 break; 1730 1731 case SIOCADDMULTI: 1732 case SIOCDELMULTI: 1733 error = (cmd == SIOCADDMULTI) ? 1734 ether_addmulti(ifr, &sc->sc_ec) : 1735 ether_delmulti(ifr, &sc->sc_ec); 1736 if (error == ENETRESET) { 1737 /* setup multicast filter, etc */ 1738 error = 0; 1739 } 1740 break; 1741 1742 case SIOCGTABLE1: 1743 error = ipw_get_table1(sc, (uint32_t *)ifr->ifr_data); 1744 break; 1745 1746 case SIOCGRADIO: 1747 error = ipw_get_radio(sc, (int *)ifr->ifr_data); 1748 break; 1749 1750 case SIOCSIFMEDIA: 1751 if (ifr->ifr_media & IFM_IEEE80211_ADHOC) 1752 strlcpy(sc->sc_fwname, "ipw2100-1.2-i.fw", 1753 sizeof(sc->sc_fwname)); 1754 else if (ifr->ifr_media & IFM_IEEE80211_MONITOR) 1755 strlcpy(sc->sc_fwname, "ipw2100-1.2-p.fw", 1756 sizeof(sc->sc_fwname)); 1757 else 1758 strlcpy(sc->sc_fwname, "ipw2100-1.2.fw", 1759 sizeof(sc->sc_fwname)); 1760 1761 ipw_free_firmware(sc); 1762 /* FALLTRHOUGH */ 1763 default: 1764 error = ieee80211_ioctl(&sc->sc_ic, cmd, data); 1765 if (error != ENETRESET) 1766 break; 1767 1768 if (error == ENETRESET) { 1769 if (IS_RUNNING(ifp) && 1770 (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)) 1771 ipw_init(ifp); 1772 error = 0; 1773 } 1774 1775 } 1776 1777 splx(s); 1778 return error; 1779 #undef IS_RUNNING 1780 } 1781 1782 static uint32_t 1783 ipw_read_table1(struct ipw_softc *sc, uint32_t off) 1784 { 1785 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 1786 } 1787 1788 static void 1789 ipw_write_table1(struct ipw_softc *sc, uint32_t off, uint32_t info) 1790 { 1791 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 1792 } 1793 1794 static int 1795 ipw_read_table2(struct ipw_softc *sc, uint32_t off, void *buf, uint32_t *len) 1796 { 1797 uint32_t addr, info; 1798 uint16_t count, size; 1799 uint32_t total; 1800 1801 /* addr[4] + count[2] + size[2] */ 1802 addr = MEM_READ_4(sc, sc->table2_base + off); 1803 info = MEM_READ_4(sc, sc->table2_base + off + 4); 1804 1805 count = info >> 16; 1806 size = info & 0xffff; 1807 total = count * size; 1808 1809 if (total > *len) { 1810 *len = total; 1811 return EINVAL; 1812 } 1813 1814 *len = total; 1815 ipw_read_mem_1(sc, addr, buf, total); 1816 1817 return 0; 1818 } 1819 1820 static void 1821 ipw_stop_master(struct ipw_softc *sc) 1822 { 1823 int ntries; 1824 1825 /* disable interrupts */ 1826 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1827 1828 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1829 for (ntries = 0; ntries < 50; ntries++) { 1830 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1831 break; 1832 DELAY(10); 1833 } 1834 if (ntries == 50) 1835 aprint_error("%s: timeout waiting for master\n", 1836 sc->sc_dev.dv_xname); 1837 1838 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1839 IPW_RST_PRINCETON_RESET); 1840 1841 sc->flags &= ~IPW_FLAG_FW_INITED; 1842 } 1843 1844 static int 1845 ipw_reset(struct ipw_softc *sc) 1846 { 1847 int ntries; 1848 1849 ipw_stop_master(sc); 1850 1851 /* move adapter to D0 state */ 1852 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1853 IPW_CTL_INIT); 1854 1855 /* wait for clock stabilization */ 1856 for (ntries = 0; ntries < 1000; ntries++) { 1857 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY) 1858 break; 1859 DELAY(200); 1860 } 1861 if (ntries == 1000) 1862 return EIO; 1863 1864 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1865 IPW_RST_SW_RESET); 1866 1867 DELAY(10); 1868 1869 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1870 IPW_CTL_INIT); 1871 1872 return 0; 1873 } 1874 1875 /* 1876 * Upload the microcode to the device. 1877 */ 1878 static int 1879 ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size) 1880 { 1881 int ntries; 1882 1883 MEM_WRITE_4(sc, 0x3000e0, 0x80000000); 1884 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1885 1886 MEM_WRITE_2(sc, 0x220000, 0x0703); 1887 MEM_WRITE_2(sc, 0x220000, 0x0707); 1888 1889 MEM_WRITE_1(sc, 0x210014, 0x72); 1890 MEM_WRITE_1(sc, 0x210014, 0x72); 1891 1892 MEM_WRITE_1(sc, 0x210000, 0x40); 1893 MEM_WRITE_1(sc, 0x210000, 0x00); 1894 MEM_WRITE_1(sc, 0x210000, 0x40); 1895 1896 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1897 1898 MEM_WRITE_1(sc, 0x210000, 0x00); 1899 MEM_WRITE_1(sc, 0x210000, 0x00); 1900 MEM_WRITE_1(sc, 0x210000, 0x80); 1901 1902 MEM_WRITE_2(sc, 0x220000, 0x0703); 1903 MEM_WRITE_2(sc, 0x220000, 0x0707); 1904 1905 MEM_WRITE_1(sc, 0x210014, 0x72); 1906 MEM_WRITE_1(sc, 0x210014, 0x72); 1907 1908 MEM_WRITE_1(sc, 0x210000, 0x00); 1909 MEM_WRITE_1(sc, 0x210000, 0x80); 1910 1911 for (ntries = 0; ntries < 10; ntries++) { 1912 if (MEM_READ_1(sc, 0x210000) & 1) 1913 break; 1914 DELAY(10); 1915 } 1916 if (ntries == 10) { 1917 aprint_error("%s: timeout waiting for ucode to initialize\n", 1918 sc->sc_dev.dv_xname); 1919 return EIO; 1920 } 1921 1922 MEM_WRITE_4(sc, 0x3000e0, 0); 1923 1924 return 0; 1925 } 1926 1927 /* set of macros to handle unaligned little endian data in firmware image */ 1928 #define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1929 #define GETLE16(p) ((p)[0] | (p)[1] << 8) 1930 static int 1931 ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size) 1932 { 1933 u_char *p, *end; 1934 uint32_t dst; 1935 uint16_t len; 1936 int error; 1937 1938 p = fw; 1939 end = fw + size; 1940 while (p < end) { 1941 dst = GETLE32(p); p += 4; 1942 len = GETLE16(p); p += 2; 1943 1944 ipw_write_mem_1(sc, dst, p, len); 1945 p += len; 1946 } 1947 1948 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1949 IPW_IO_LED_OFF); 1950 1951 /* enable interrupts */ 1952 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1953 1954 /* kick the firmware */ 1955 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1956 1957 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1958 IPW_CTL_ALLOW_STANDBY); 1959 1960 /* wait at most one second for firmware initialization to complete */ 1961 if ((error = tsleep(sc, 0, "ipwinit", hz)) != 0) { 1962 aprint_error("%s: timeout waiting for firmware initialization " 1963 "to complete\n", sc->sc_dev.dv_xname); 1964 return error; 1965 } 1966 1967 CSR_WRITE_4(sc, IPW_CSR_IO, CSR_READ_4(sc, IPW_CSR_IO) | 1968 IPW_IO_GPIO1_MASK | IPW_IO_GPIO3_MASK); 1969 1970 return 0; 1971 } 1972 1973 /* 1974 * Store firmware into kernel memory so we can download it when we need to, 1975 * e.g when the adapter wakes up from suspend mode. 1976 */ 1977 static int 1978 ipw_cache_firmware(struct ipw_softc *sc) 1979 { 1980 struct ipw_firmware *fw = &sc->fw; 1981 struct ipw_firmware_hdr hdr; 1982 firmware_handle_t fwh; 1983 off_t fwsz, p; 1984 int error; 1985 1986 ipw_free_firmware(sc); 1987 1988 if ((error = firmware_open("if_ipw", sc->sc_fwname, &fwh)) != 0) 1989 goto fail0; 1990 1991 fwsz = firmware_get_size(fwh); 1992 1993 if (fwsz < sizeof(hdr)) 1994 goto fail2; 1995 1996 if ((error = firmware_read(fwh, 0, &hdr, sizeof(hdr))) != 0) 1997 goto fail2; 1998 1999 fw->main_size = le32toh(hdr.main_size); 2000 fw->ucode_size = le32toh(hdr.ucode_size); 2001 2002 fw->main = firmware_malloc(fw->main_size); 2003 if (fw->main == NULL) { 2004 error = ENOMEM; 2005 goto fail1; 2006 } 2007 2008 fw->ucode = firmware_malloc(fw->ucode_size); 2009 if (fw->ucode == NULL) { 2010 error = ENOMEM; 2011 goto fail2; 2012 } 2013 2014 p = sizeof(hdr); 2015 if ((error = firmware_read(fwh, p, fw->main, fw->main_size)) != 0) 2016 goto fail3; 2017 2018 if ((error = firmware_read(fwh, p, fw->main, fw->main_size)) != 0) 2019 goto fail3; 2020 2021 p += fw->main_size; 2022 if ((error = firmware_read(fwh, p, fw->ucode, fw->ucode_size)) != 0) 2023 goto fail3; 2024 2025 DPRINTF(("Firmware cached: main %u, ucode %u\n", fw->main_size, 2026 fw->ucode_size)); 2027 2028 sc->flags |= IPW_FLAG_FW_CACHED; 2029 2030 return 0; 2031 2032 fail3: firmware_free(fw->ucode, 0); 2033 fail2: firmware_free(fw->main, 0); 2034 fail1: firmware_close(fwh); 2035 fail0: 2036 return error; 2037 } 2038 2039 static void 2040 ipw_free_firmware(struct ipw_softc *sc) 2041 { 2042 if (!(sc->flags & IPW_FLAG_FW_CACHED)) 2043 return; 2044 2045 firmware_free(sc->fw.main, 0); 2046 firmware_free(sc->fw.ucode, 0); 2047 2048 sc->flags &= ~IPW_FLAG_FW_CACHED; 2049 } 2050 2051 static int 2052 ipw_config(struct ipw_softc *sc) 2053 { 2054 struct ieee80211com *ic = &sc->sc_ic; 2055 struct ifnet *ifp = &sc->sc_if; 2056 struct ipw_security security; 2057 struct ieee80211_key *k; 2058 struct ipw_wep_key wepkey; 2059 struct ipw_scan_options options; 2060 struct ipw_configuration config; 2061 uint32_t data; 2062 int error, i; 2063 2064 switch (ic->ic_opmode) { 2065 case IEEE80211_M_STA: 2066 case IEEE80211_M_HOSTAP: 2067 data = htole32(IPW_MODE_BSS); 2068 break; 2069 2070 case IEEE80211_M_IBSS: 2071 case IEEE80211_M_AHDEMO: 2072 data = htole32(IPW_MODE_IBSS); 2073 break; 2074 2075 case IEEE80211_M_MONITOR: 2076 data = htole32(IPW_MODE_MONITOR); 2077 break; 2078 } 2079 DPRINTF(("Setting mode to %u\n", le32toh(data))); 2080 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 2081 if (error != 0) 2082 return error; 2083 2084 if (ic->ic_opmode == IEEE80211_M_IBSS || 2085 ic->ic_opmode == IEEE80211_M_MONITOR) { 2086 data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); 2087 DPRINTF(("Setting channel to %u\n", le32toh(data))); 2088 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 2089 if (error != 0) 2090 return error; 2091 } 2092 2093 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2094 DPRINTF(("Enabling adapter\n")); 2095 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 2096 } 2097 2098 DPRINTF(("Setting MAC to %s\n", ether_sprintf(ic->ic_myaddr))); 2099 IEEE80211_ADDR_COPY(LLADDR(ifp->if_sadl), ic->ic_myaddr); 2100 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 2101 IEEE80211_ADDR_LEN); 2102 if (error != 0) 2103 return error; 2104 2105 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 2106 IPW_CFG_PREAMBLE_AUTO | IPW_CFG_802_1x_ENABLE); 2107 2108 if (ic->ic_opmode == IEEE80211_M_IBSS) 2109 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 2110 if (ifp->if_flags & IFF_PROMISC) 2111 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 2112 config.bss_chan = htole32(0x3fff); /* channels 1-14 */ 2113 config.ibss_chan = htole32(0x7ff); /* channels 1-11 */ 2114 DPRINTF(("Setting adapter configuration 0x%08x\n", config.flags)); 2115 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 2116 if (error != 0) 2117 return error; 2118 2119 data = htole32(0x3); /* 1, 2 */ 2120 DPRINTF(("Setting basic tx rates to 0x%x\n", le32toh(data))); 2121 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 2122 if (error != 0) 2123 return error; 2124 2125 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 2126 DPRINTF(("Setting tx rates to 0x%x\n", le32toh(data))); 2127 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 2128 if (error != 0) 2129 return error; 2130 2131 data = htole32(IPW_POWER_MODE_CAM); 2132 DPRINTF(("Setting power mode to %u\n", le32toh(data))); 2133 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 2134 if (error != 0) 2135 return error; 2136 2137 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2138 data = htole32(32); /* default value */ 2139 DPRINTF(("Setting tx power index to %u\n", le32toh(data))); 2140 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 2141 sizeof data); 2142 if (error != 0) 2143 return error; 2144 } 2145 2146 data = htole32(ic->ic_rtsthreshold); 2147 DPRINTF(("Setting RTS threshold to %u\n", le32toh(data))); 2148 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 2149 if (error != 0) 2150 return error; 2151 2152 data = htole32(ic->ic_fragthreshold); 2153 DPRINTF(("Setting frag threshold to %u\n", le32toh(data))); 2154 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 2155 if (error != 0) 2156 return error; 2157 2158 #ifdef IPW_DEBUG 2159 if (ipw_debug > 0) { 2160 printf("Setting ESSID to "); 2161 ieee80211_print_essid(ic->ic_des_essid, ic->ic_des_esslen); 2162 printf("\n"); 2163 } 2164 #endif 2165 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ic->ic_des_essid, 2166 ic->ic_des_esslen); 2167 if (error != 0) 2168 return error; 2169 2170 /* no mandatory BSSID */ 2171 DPRINTF(("Setting mandatory BSSID to null\n")); 2172 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 2173 if (error != 0) 2174 return error; 2175 2176 if (ic->ic_flags & IEEE80211_F_DESBSSID) { 2177 DPRINTF(("Setting desired BSSID to %s\n", 2178 ether_sprintf(ic->ic_des_bssid))); 2179 error = ipw_cmd(sc, IPW_CMD_SET_DESIRED_BSSID, 2180 ic->ic_des_bssid, IEEE80211_ADDR_LEN); 2181 if (error != 0) 2182 return error; 2183 } 2184 2185 (void)memset(&security, 0, sizeof(security)); 2186 security.authmode = (ic->ic_bss->ni_authmode == IEEE80211_AUTH_SHARED) ? 2187 IPW_AUTH_SHARED : IPW_AUTH_OPEN; 2188 security.ciphers = htole32(IPW_CIPHER_NONE); 2189 DPRINTF(("Setting authmode to %u\n", security.authmode)); 2190 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 2191 sizeof security); 2192 if (error != 0) 2193 return error; 2194 2195 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 2196 k = ic->ic_crypto.cs_nw_keys; 2197 for (i = 0; i < IEEE80211_WEP_NKID; i++, k++) { 2198 if (k->wk_keylen == 0) 2199 continue; 2200 2201 wepkey.idx = i; 2202 wepkey.len = k->wk_keylen; 2203 memset(wepkey.key, 0, sizeof(wepkey.key)); 2204 memcpy(wepkey.key, k->wk_key, k->wk_keylen); 2205 DPRINTF(("Setting wep key index %u len %u\n", 2206 wepkey.idx, wepkey.len)); 2207 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY, &wepkey, 2208 sizeof wepkey); 2209 if (error != 0) 2210 return error; 2211 } 2212 2213 data = htole32(ic->ic_crypto.cs_def_txkey); 2214 DPRINTF(("Setting tx key index to %u\n", le32toh(data))); 2215 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY_INDEX, &data, 2216 sizeof data); 2217 if (error != 0) 2218 return error; 2219 } 2220 2221 data = htole32((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) ? IPW_WEPON : 0); 2222 DPRINTF(("Setting wep flags to 0x%x\n", le32toh(data))); 2223 error = ipw_cmd(sc, IPW_CMD_SET_WEP_FLAGS, &data, sizeof data); 2224 if (error != 0) 2225 return error; 2226 2227 #if 0 2228 struct ipw_wpa_ie ie; 2229 2230 memset(&ie, 0 sizeof(ie)); 2231 ie.len = htole32(sizeof (struct ieee80211_ie_wpa)); 2232 DPRINTF(("Setting wpa ie\n")); 2233 error = ipw_cmd(sc, IPW_CMD_SET_WPA_IE, &ie, sizeof ie); 2234 if (error != 0) 2235 return error; 2236 #endif 2237 2238 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2239 data = htole32(ic->ic_bintval); 2240 DPRINTF(("Setting beacon interval to %u\n", le32toh(data))); 2241 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 2242 sizeof data); 2243 if (error != 0) 2244 return error; 2245 } 2246 2247 options.flags = 0; 2248 options.channels = htole32(0x3fff); /* scan channels 1-14 */ 2249 DPRINTF(("Setting scan options to 0x%x\n", le32toh(options.flags))); 2250 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &options, sizeof options); 2251 if (error != 0) 2252 return error; 2253 2254 /* finally, enable adapter (start scanning for an access point) */ 2255 DPRINTF(("Enabling adapter\n")); 2256 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 2257 } 2258 2259 static int 2260 ipw_init(struct ifnet *ifp) 2261 { 2262 struct ipw_softc *sc = ifp->if_softc; 2263 struct ipw_firmware *fw = &sc->fw; 2264 2265 if (!(sc->flags & IPW_FLAG_FW_CACHED)) { 2266 if (ipw_cache_firmware(sc) != 0) { 2267 aprint_error("%s: could not cache the firmware (%s)\n", 2268 sc->sc_dev.dv_xname, sc->sc_fwname); 2269 goto fail; 2270 } 2271 } 2272 2273 ipw_stop(ifp, 0); 2274 2275 if (ipw_reset(sc) != 0) { 2276 aprint_error("%s: could not reset adapter\n", 2277 sc->sc_dev.dv_xname); 2278 goto fail; 2279 } 2280 2281 if (ipw_load_ucode(sc, fw->ucode, fw->ucode_size) != 0) { 2282 aprint_error("%s: could not load microcode\n", 2283 sc->sc_dev.dv_xname); 2284 goto fail; 2285 } 2286 2287 ipw_stop_master(sc); 2288 2289 /* 2290 * Setup tx, rx and status rings. 2291 */ 2292 sc->txold = IPW_NTBD - 1; 2293 sc->txcur = 0; 2294 sc->txfree = IPW_NTBD - 2; 2295 sc->rxcur = IPW_NRBD - 1; 2296 2297 CSR_WRITE_4(sc, IPW_CSR_TX_BASE, sc->tbd_map->dm_segs[0].ds_addr); 2298 CSR_WRITE_4(sc, IPW_CSR_TX_SIZE, IPW_NTBD); 2299 CSR_WRITE_4(sc, IPW_CSR_TX_READ, 0); 2300 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 2301 2302 CSR_WRITE_4(sc, IPW_CSR_RX_BASE, sc->rbd_map->dm_segs[0].ds_addr); 2303 CSR_WRITE_4(sc, IPW_CSR_RX_SIZE, IPW_NRBD); 2304 CSR_WRITE_4(sc, IPW_CSR_RX_READ, 0); 2305 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 2306 2307 CSR_WRITE_4(sc, IPW_CSR_STATUS_BASE, sc->status_map->dm_segs[0].ds_addr); 2308 2309 if (ipw_load_firmware(sc, fw->main, fw->main_size) != 0) { 2310 aprint_error("%s: could not load firmware\n", 2311 sc->sc_dev.dv_xname); 2312 goto fail; 2313 } 2314 2315 sc->flags |= IPW_FLAG_FW_INITED; 2316 2317 /* retrieve information tables base addresses */ 2318 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 2319 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 2320 2321 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 2322 2323 if (ipw_config(sc) != 0) { 2324 aprint_error("%s: device configuration failed\n", 2325 sc->sc_dev.dv_xname); 2326 goto fail; 2327 } 2328 2329 ifp->if_flags &= ~IFF_OACTIVE; 2330 ifp->if_flags |= IFF_RUNNING; 2331 2332 return 0; 2333 2334 fail: ifp->if_flags &= ~IFF_UP; 2335 ipw_stop(ifp, 0); 2336 2337 return EIO; 2338 } 2339 2340 static void 2341 ipw_stop(struct ifnet *ifp, int disable) 2342 { 2343 struct ipw_softc *sc = ifp->if_softc; 2344 struct ieee80211com *ic = &sc->sc_ic; 2345 int i; 2346 2347 ipw_stop_master(sc); 2348 2349 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 2350 2351 /* 2352 * Release tx buffers. 2353 */ 2354 for (i = 0; i < IPW_NTBD; i++) 2355 ipw_release_sbd(sc, &sc->stbd_list[i]); 2356 2357 sc->sc_tx_timer = 0; 2358 ifp->if_timer = 0; 2359 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2360 2361 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2362 } 2363 2364 static void 2365 ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2366 bus_size_t count) 2367 { 2368 for (; count > 0; offset++, datap++, count--) { 2369 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2370 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 2371 } 2372 } 2373 2374 static void 2375 ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2376 bus_size_t count) 2377 { 2378 for (; count > 0; offset++, datap++, count--) { 2379 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2380 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 2381 } 2382 } 2383
Indexes created Tue Sep 30 17:09:57 GMT 2025