if_ipw.c revision 1.19
1 /* $NetBSD: if_ipw.c,v 1.19 2006/04/17 20:57:24 rpaulo Exp $ */ 2 /* FreeBSD: src/sys/dev/ipw/if_ipw.c,v 1.15 2005/11/13 17:17:40 damien Exp */ 3 4 /*- 5 * Copyright (c) 2004, 2005 6 * Damien Bergamini <damien.bergamini (at) free.fr>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: if_ipw.c,v 1.19 2006/04/17 20:57:24 rpaulo Exp $"); 33 34 /*- 35 * Intel(R) PRO/Wireless 2100 MiniPCI driver 36 * http://www.intel.com/network/connectivity/products/wireless/prowireless_mobile.htm 37 */ 38 39 #include "bpfilter.h" 40 41 #include <sys/param.h> 42 #include <sys/sockio.h> 43 #include <sys/sysctl.h> 44 #include <sys/mbuf.h> 45 #include <sys/kernel.h> 46 #include <sys/socket.h> 47 #include <sys/systm.h> 48 #include <sys/malloc.h> 49 #include <sys/conf.h> 50 51 #include <machine/bus.h> 52 #include <machine/endian.h> 53 #include <machine/intr.h> 54 55 #include <dev/pci/pcireg.h> 56 #include <dev/pci/pcivar.h> 57 #include <dev/pci/pcidevs.h> 58 59 #if NBPFILTER > 0 60 #include <net/bpf.h> 61 #endif 62 #include <net/if.h> 63 #include <net/if_arp.h> 64 #include <net/if_dl.h> 65 #include <net/if_ether.h> 66 #include <net/if_media.h> 67 #include <net/if_types.h> 68 69 #include <net80211/ieee80211_var.h> 70 #include <net80211/ieee80211_radiotap.h> 71 72 #include <netinet/in.h> 73 #include <netinet/in_systm.h> 74 #include <netinet/in_var.h> 75 #include <netinet/ip.h> 76 77 #include <dev/firmload.h> 78 79 #include <dev/pci/if_ipwreg.h> 80 #include <dev/pci/if_ipwvar.h> 81 82 #ifdef IPW_DEBUG 83 #define DPRINTF(x) if (ipw_debug > 0) printf x 84 #define DPRINTFN(n, x) if (ipw_debug >= (n)) printf x 85 int ipw_debug = 0; 86 #else 87 #define DPRINTF(x) 88 #define DPRINTFN(n, x) 89 #endif 90 91 static int ipw_dma_alloc(struct ipw_softc *); 92 static void ipw_release(struct ipw_softc *); 93 static int ipw_match(struct device *, struct cfdata *, void *); 94 static void ipw_attach(struct device *, struct device *, void *); 95 static int ipw_detach(struct device *, int); 96 97 static void ipw_shutdown(void *); 98 static int ipw_suspend(struct ipw_softc *); 99 static int ipw_resume(struct ipw_softc *); 100 static void ipw_powerhook(int, void *); 101 102 static int ipw_media_change(struct ifnet *); 103 static void ipw_media_status(struct ifnet *, struct ifmediareq *); 104 static int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 105 static uint16_t ipw_read_prom_word(struct ipw_softc *, uint8_t); 106 static void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 107 static void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 108 static void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 109 struct ipw_soft_bd *, struct ipw_soft_buf *); 110 static void ipw_rx_intr(struct ipw_softc *); 111 static void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 112 static void ipw_tx_intr(struct ipw_softc *); 113 static int ipw_intr(void *); 114 static int ipw_cmd(struct ipw_softc *, uint32_t, void *, uint32_t); 115 static int ipw_tx_start(struct ifnet *, struct mbuf *, 116 struct ieee80211_node *); 117 static void ipw_start(struct ifnet *); 118 static void ipw_watchdog(struct ifnet *); 119 static int ipw_ioctl(struct ifnet *, u_long, caddr_t); 120 static int ipw_get_table1(struct ipw_softc *, uint32_t *); 121 static int ipw_get_radio(struct ipw_softc *, int *); 122 static void ipw_stop_master(struct ipw_softc *); 123 static int ipw_reset(struct ipw_softc *); 124 static int ipw_load_ucode(struct ipw_softc *, u_char *, int); 125 static int ipw_load_firmware(struct ipw_softc *, u_char *, int); 126 static int ipw_cache_firmware(struct ipw_softc *); 127 static void ipw_free_firmware(struct ipw_softc *); 128 static int ipw_config(struct ipw_softc *); 129 static int ipw_init(struct ifnet *); 130 static void ipw_stop(struct ifnet *, int); 131 static uint32_t ipw_read_table1(struct ipw_softc *, uint32_t); 132 static void ipw_write_table1(struct ipw_softc *, uint32_t, uint32_t); 133 static int ipw_read_table2(struct ipw_softc *, uint32_t, void *, uint32_t *); 134 static void ipw_read_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 135 bus_size_t); 136 static void ipw_write_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 137 bus_size_t); 138 139 /* 140 * Supported rates for 802.11b mode (in 500Kbps unit). 141 */ 142 static const struct ieee80211_rateset ipw_rateset_11b = 143 { 4, { 2, 4, 11, 22 } }; 144 145 static inline uint8_t 146 MEM_READ_1(struct ipw_softc *sc, uint32_t addr) 147 { 148 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 149 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); 150 } 151 152 static inline uint32_t 153 MEM_READ_4(struct ipw_softc *sc, uint32_t addr) 154 { 155 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 156 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); 157 } 158 159 CFATTACH_DECL(ipw, sizeof (struct ipw_softc), ipw_match, ipw_attach, 160 ipw_detach, NULL); 161 162 static int 163 ipw_match(struct device *parent, struct cfdata *match, void *aux) 164 { 165 struct pci_attach_args *pa = aux; 166 167 if (PCI_VENDOR (pa->pa_id) == PCI_VENDOR_INTEL && 168 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_PRO_WL_2100) 169 return 1; 170 171 return 0; 172 } 173 174 /* Base Address Register */ 175 #define IPW_PCI_BAR0 0x10 176 177 static void 178 ipw_attach(struct device *parent, struct device *self, void *aux) 179 { 180 struct ipw_softc *sc = (struct ipw_softc *)self; 181 struct ieee80211com *ic = &sc->sc_ic; 182 struct ifnet *ifp = &sc->sc_if; 183 struct pci_attach_args *pa = aux; 184 const char *intrstr; 185 char devinfo[256]; 186 bus_space_tag_t memt; 187 bus_space_handle_t memh; 188 bus_addr_t base; 189 pci_intr_handle_t ih; 190 uint32_t data; 191 uint16_t val; 192 int i, revision, error; 193 194 sc->sc_pct = pa->pa_pc; 195 sc->sc_pcitag = pa->pa_tag; 196 197 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof devinfo); 198 revision = PCI_REVISION(pa->pa_class); 199 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, revision); 200 201 /* enable bus-mastering */ 202 data = pci_conf_read(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG); 203 data |= PCI_COMMAND_MASTER_ENABLE; 204 pci_conf_write(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG, data); 205 206 /* clear device specific PCI configuration register 0x41 */ 207 data = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 208 data &= ~0x0000ff00; 209 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, data); 210 211 /* map the register window */ 212 error = pci_mapreg_map(pa, IPW_PCI_BAR0, PCI_MAPREG_TYPE_MEM | 213 PCI_MAPREG_MEM_TYPE_32BIT, 0, &memt, &memh, &base, &sc->sc_sz); 214 if (error != 0) { 215 aprint_error("%s: could not map memory space\n", 216 sc->sc_dev.dv_xname); 217 return; 218 } 219 220 sc->sc_st = memt; 221 sc->sc_sh = memh; 222 sc->sc_dmat = pa->pa_dmat; 223 strncpy(sc->sc_fwname, "ipw2100-1.2.fw", 24); 224 225 /* disable interrupts */ 226 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 227 228 if (pci_intr_map(pa, &ih) != 0) { 229 aprint_error("%s: could not map interrupt\n", 230 sc->sc_dev.dv_xname); 231 return; 232 } 233 234 intrstr = pci_intr_string(sc->sc_pct, ih); 235 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, ipw_intr, sc); 236 if (sc->sc_ih == NULL) { 237 aprint_error("%s: could not establish interrupt", 238 sc->sc_dev.dv_xname); 239 if (intrstr != NULL) 240 aprint_error(" at %s", intrstr); 241 aprint_error("\n"); 242 return; 243 } 244 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 245 246 if (ipw_reset(sc) != 0) { 247 aprint_error("%s: could not reset adapter\n", 248 sc->sc_dev.dv_xname); 249 goto fail; 250 } 251 252 if (ipw_dma_alloc(sc) != 0) { 253 aprint_error("%s: could not allocate DMA resources\n", 254 sc->sc_dev.dv_xname); 255 goto fail; 256 } 257 258 ifp->if_softc = sc; 259 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 260 ifp->if_init = ipw_init; 261 ifp->if_stop = ipw_stop; 262 ifp->if_ioctl = ipw_ioctl; 263 ifp->if_start = ipw_start; 264 ifp->if_watchdog = ipw_watchdog; 265 IFQ_SET_READY(&ifp->if_snd); 266 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 267 268 ic->ic_ifp = ifp; 269 ic->ic_phytype = IEEE80211_T_DS; 270 ic->ic_opmode = IEEE80211_M_STA; 271 ic->ic_state = IEEE80211_S_INIT; 272 273 /* set device capabilities */ 274 ic->ic_caps = IEEE80211_C_SHPREAMBLE | IEEE80211_C_TXPMGT | 275 IEEE80211_C_PMGT | IEEE80211_C_IBSS | IEEE80211_C_MONITOR; 276 277 /* read MAC address from EEPROM */ 278 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0); 279 ic->ic_myaddr[0] = val >> 8; 280 ic->ic_myaddr[1] = val & 0xff; 281 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 1); 282 ic->ic_myaddr[2] = val >> 8; 283 ic->ic_myaddr[3] = val & 0xff; 284 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 2); 285 ic->ic_myaddr[4] = val >> 8; 286 ic->ic_myaddr[5] = val & 0xff; 287 288 /* set supported .11b rates */ 289 ic->ic_sup_rates[IEEE80211_MODE_11B] = ipw_rateset_11b; 290 291 /* set supported .11b channels (read from EEPROM) */ 292 if ((val = ipw_read_prom_word(sc, IPW_EEPROM_CHANNEL_LIST)) == 0) 293 val = 0x7ff; /* default to channels 1-11 */ 294 val <<= 1; 295 for (i = 1; i < 16; i++) { 296 if (val & (1 << i)) { 297 ic->ic_channels[i].ic_freq = 298 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 299 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 300 } 301 } 302 303 /* check support for radio transmitter switch in EEPROM */ 304 if (!(ipw_read_prom_word(sc, IPW_EEPROM_RADIO) & 8)) 305 sc->flags |= IPW_FLAG_HAS_RADIO_SWITCH; 306 307 if_attach(ifp); 308 ieee80211_ifattach(ic); 309 310 /* override state transition machine */ 311 sc->sc_newstate = ic->ic_newstate; 312 ic->ic_newstate = ipw_newstate; 313 314 ieee80211_media_init(ic, ipw_media_change, ipw_media_status); 315 316 #if NBPFILTER > 0 317 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 318 sizeof (struct ieee80211_frame) + 64, &sc->sc_drvbpf); 319 320 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 321 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 322 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 323 324 sc->sc_txtap_len = sizeof sc->sc_txtapu; 325 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 326 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 327 #endif 328 329 /* 330 * Add a few sysctl knobs. 331 * XXX: Not yet 332 */ 333 sc->dwelltime = 100; 334 335 /* 336 * Make sure the interface is shutdown during reboot. 337 */ 338 sc->sc_sdhook = shutdownhook_establish(ipw_shutdown, sc); 339 if (sc->sc_sdhook == NULL) 340 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 341 sc->sc_dev.dv_xname); 342 sc->sc_powerhook = powerhook_establish(ipw_powerhook, sc); 343 if (sc->sc_powerhook == NULL) 344 printf("%s: WARNING: unable to establish power hook\n", 345 sc->sc_dev.dv_xname); 346 347 ieee80211_announce(ic); 348 349 return; 350 351 fail: ipw_detach(self, 0); 352 } 353 354 static int 355 ipw_detach(struct device* self, int flags) 356 { 357 struct ipw_softc *sc = (struct ipw_softc *)self; 358 struct ifnet *ifp = &sc->sc_if; 359 360 if (ifp->if_softc) { 361 ipw_stop(ifp, 1); 362 ipw_free_firmware(sc); 363 364 #if NBPFILTER > 0 365 bpfdetach(ifp); 366 #endif 367 ieee80211_ifdetach(&sc->sc_ic); 368 if_detach(ifp); 369 370 ipw_release(sc); 371 } 372 373 if (sc->sc_ih != NULL) { 374 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 375 sc->sc_ih = NULL; 376 } 377 378 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 379 380 return 0; 381 } 382 383 static int 384 ipw_dma_alloc(struct ipw_softc *sc) 385 { 386 struct ipw_soft_bd *sbd; 387 struct ipw_soft_hdr *shdr; 388 struct ipw_soft_buf *sbuf; 389 int error, i, nsegs; 390 391 /* 392 * Allocate and map tx ring. 393 */ 394 error = bus_dmamap_create(sc->sc_dmat, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, 395 BUS_DMA_NOWAIT, &sc->tbd_map); 396 if (error != 0) { 397 aprint_error("%s: could not create tbd dma map\n", 398 sc->sc_dev.dv_xname); 399 goto fail; 400 } 401 402 error = bus_dmamem_alloc(sc->sc_dmat, IPW_TBD_SZ, PAGE_SIZE, 0, 403 &sc->tbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 404 if (error != 0) { 405 aprint_error("%s: could not allocate tbd dma memory\n", 406 sc->sc_dev.dv_xname); 407 goto fail; 408 } 409 410 error = bus_dmamem_map(sc->sc_dmat, &sc->tbd_seg, nsegs, IPW_TBD_SZ, 411 (caddr_t *)&sc->tbd_list, BUS_DMA_NOWAIT); 412 if (error != 0) { 413 aprint_error("%s: could not map tbd dma memory\n", 414 sc->sc_dev.dv_xname); 415 goto fail; 416 } 417 418 error = bus_dmamap_load(sc->sc_dmat, sc->tbd_map, sc->tbd_list, 419 IPW_TBD_SZ, NULL, BUS_DMA_NOWAIT); 420 if (error != 0) { 421 aprint_error("%s: could not load tbd dma memory\n", 422 sc->sc_dev.dv_xname); 423 goto fail; 424 } 425 426 (void)memset(sc->tbd_list, 0, IPW_TBD_SZ); 427 428 /* 429 * Allocate and map rx ring. 430 */ 431 error = bus_dmamap_create(sc->sc_dmat, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, 432 BUS_DMA_NOWAIT, &sc->rbd_map); 433 if (error != 0) { 434 aprint_error("%s: could not create rbd dma map\n", 435 sc->sc_dev.dv_xname); 436 goto fail; 437 } 438 439 error = bus_dmamem_alloc(sc->sc_dmat, IPW_RBD_SZ, PAGE_SIZE, 0, 440 &sc->rbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 441 if (error != 0) { 442 aprint_error("%s: could not allocate rbd dma memory\n", 443 sc->sc_dev.dv_xname); 444 goto fail; 445 } 446 447 error = bus_dmamem_map(sc->sc_dmat, &sc->rbd_seg, nsegs, IPW_RBD_SZ, 448 (caddr_t *)&sc->rbd_list, BUS_DMA_NOWAIT); 449 if (error != 0) { 450 aprint_error("%s: could not map rbd dma memory\n", 451 sc->sc_dev.dv_xname); 452 goto fail; 453 } 454 455 error = bus_dmamap_load(sc->sc_dmat, sc->rbd_map, sc->rbd_list, 456 IPW_RBD_SZ, NULL, BUS_DMA_NOWAIT); 457 if (error != 0) { 458 aprint_error("%s: could not load rbd dma memory\n", 459 sc->sc_dev.dv_xname); 460 goto fail; 461 } 462 463 (void)memset(sc->rbd_list, 0, IPW_RBD_SZ); 464 465 /* 466 * Allocate and map status ring. 467 */ 468 error = bus_dmamap_create(sc->sc_dmat, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 469 0, BUS_DMA_NOWAIT, &sc->status_map); 470 if (error != 0) { 471 aprint_error("%s: could not create status dma map\n", 472 sc->sc_dev.dv_xname); 473 goto fail; 474 } 475 476 error = bus_dmamem_alloc(sc->sc_dmat, IPW_STATUS_SZ, PAGE_SIZE, 0, 477 &sc->status_seg, 1, &nsegs, BUS_DMA_NOWAIT); 478 if (error != 0) { 479 aprint_error("%s: could not allocate status dma memory\n", 480 sc->sc_dev.dv_xname); 481 goto fail; 482 } 483 484 error = bus_dmamem_map(sc->sc_dmat, &sc->status_seg, nsegs, 485 IPW_STATUS_SZ, (caddr_t *)&sc->status_list, BUS_DMA_NOWAIT); 486 if (error != 0) { 487 aprint_error("%s: could not map status dma memory\n", 488 sc->sc_dev.dv_xname); 489 goto fail; 490 } 491 492 error = bus_dmamap_load(sc->sc_dmat, sc->status_map, sc->status_list, 493 IPW_STATUS_SZ, NULL, BUS_DMA_NOWAIT); 494 if (error != 0) { 495 aprint_error("%s: could not load status dma memory\n", 496 sc->sc_dev.dv_xname); 497 goto fail; 498 } 499 500 (void)memset(sc->status_list, 0, IPW_STATUS_SZ); 501 502 /* 503 * Allocate command DMA map. 504 */ 505 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_cmd), 506 1, sizeof (struct ipw_cmd), 0, BUS_DMA_NOWAIT, &sc->cmd_map); 507 if (error != 0) { 508 aprint_error("%s: could not create cmd dma map\n", 509 sc->sc_dev.dv_xname); 510 goto fail; 511 } 512 513 error = bus_dmamem_alloc(sc->sc_dmat, sizeof (struct ipw_cmd), 514 PAGE_SIZE, 0, &sc->cmd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 515 if (error != 0) { 516 aprint_error("%s: could not allocate cmd dma memory\n", 517 sc->sc_dev.dv_xname); 518 goto fail; 519 } 520 521 error = bus_dmamem_map(sc->sc_dmat, &sc->cmd_seg, nsegs, 522 sizeof (struct ipw_cmd), (caddr_t *)&sc->cmd, BUS_DMA_NOWAIT); 523 if (error != 0) { 524 aprint_error("%s: could not map cmd dma memory\n", 525 sc->sc_dev.dv_xname); 526 goto fail; 527 } 528 529 error = bus_dmamap_load(sc->sc_dmat, sc->cmd_map, &sc->cmd, 530 sizeof (struct ipw_cmd), NULL, BUS_DMA_NOWAIT); 531 if (error != 0) { 532 aprint_error("%s: could not map cmd dma memory\n", 533 sc->sc_dev.dv_xname); 534 return error; 535 } 536 537 /* 538 * Allocate and map hdr list. 539 */ 540 541 error = bus_dmamap_create(sc->sc_dmat, 542 IPW_NDATA * sizeof(struct ipw_hdr), 1, 543 sizeof(struct ipw_hdr), 0, BUS_DMA_NOWAIT, 544 &sc->hdr_map); 545 if (error != 0) { 546 aprint_error("%s: could not create hdr dma map\n", 547 sc->sc_dev.dv_xname); 548 goto fail; 549 } 550 551 error = bus_dmamem_alloc(sc->sc_dmat, 552 IPW_NDATA * sizeof(struct ipw_hdr), PAGE_SIZE, 0, &sc->hdr_seg, 553 1, &nsegs, BUS_DMA_NOWAIT); 554 if (error != 0) { 555 aprint_error("%s: could not allocate hdr memory\n", 556 sc->sc_dev.dv_xname); 557 goto fail; 558 } 559 560 error = bus_dmamem_map(sc->sc_dmat, &sc->hdr_seg, nsegs, 561 IPW_NDATA * sizeof(struct ipw_hdr), (caddr_t *)&sc->hdr_list, 562 BUS_DMA_NOWAIT); 563 if (error != 0) { 564 aprint_error("%s: could not map hdr memory\n", 565 sc->sc_dev.dv_xname); 566 goto fail; 567 } 568 569 error = bus_dmamap_load(sc->sc_dmat, sc->hdr_map, sc->hdr_list, 570 IPW_NDATA * sizeof(struct ipw_hdr), NULL, BUS_DMA_NOWAIT); 571 if (error != 0) { 572 aprint_error("%s: could not load hdr memory\n", 573 sc->sc_dev.dv_xname); 574 goto fail; 575 } 576 577 (void)memset(sc->hdr_list, 0, IPW_HDR_SZ); 578 579 /* 580 * Create DMA hdrs tailq. 581 */ 582 TAILQ_INIT(&sc->sc_free_shdr); 583 for (i = 0; i < IPW_NDATA; i++) { 584 shdr = &sc->shdr_list[i]; 585 shdr->hdr = sc->hdr_list + i; 586 shdr->offset = sizeof(struct ipw_hdr) * i; 587 shdr->addr = sc->hdr_map->dm_segs[0].ds_addr + shdr->offset; 588 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 589 } 590 591 /* 592 * Allocate tx buffers DMA maps. 593 */ 594 TAILQ_INIT(&sc->sc_free_sbuf); 595 for (i = 0; i < IPW_NDATA; i++) { 596 sbuf = &sc->tx_sbuf_list[i]; 597 598 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 599 IPW_MAX_NSEG, MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 600 if (error != 0) { 601 aprint_error("%s: could not create txbuf dma map\n", 602 sc->sc_dev.dv_xname); 603 goto fail; 604 } 605 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 606 } 607 608 /* 609 * Initialize tx ring. 610 */ 611 for (i = 0; i < IPW_NTBD; i++) { 612 sbd = &sc->stbd_list[i]; 613 sbd->bd = &sc->tbd_list[i]; 614 sbd->type = IPW_SBD_TYPE_NOASSOC; 615 } 616 617 /* 618 * Pre-allocate rx buffers and DMA maps 619 */ 620 for (i = 0; i < IPW_NRBD; i++) { 621 sbd = &sc->srbd_list[i]; 622 sbuf = &sc->rx_sbuf_list[i]; 623 sbd->bd = &sc->rbd_list[i]; 624 625 MGETHDR(sbuf->m, M_DONTWAIT, MT_DATA); 626 if (sbuf->m == NULL) { 627 aprint_error("%s: could not allocate rx mbuf\n", 628 sc->sc_dev.dv_xname); 629 error = ENOMEM; 630 goto fail; 631 } 632 633 MCLGET(sbuf->m, M_DONTWAIT); 634 if (!(sbuf->m->m_flags & M_EXT)) { 635 m_freem(sbuf->m); 636 aprint_error("%s: could not allocate rx mbuf cluster\n", 637 sc->sc_dev.dv_xname); 638 error = ENOMEM; 639 goto fail; 640 } 641 642 sbuf->m->m_pkthdr.len = sbuf->m->m_len = sbuf->m->m_ext.ext_size; 643 644 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 645 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sbuf->map); 646 if (error != 0) { 647 aprint_error("%s: could not create rxbuf dma map\n", 648 sc->sc_dev.dv_xname); 649 m_freem(sbuf->m); 650 goto fail; 651 } 652 653 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, 654 sbuf->m, BUS_DMA_READ | BUS_DMA_NOWAIT); 655 if (error != 0) { 656 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 657 m_freem(sbuf->m); 658 aprint_error("%s: could not map rxbuf dma memory\n", 659 sc->sc_dev.dv_xname); 660 goto fail; 661 } 662 663 sbd->type = IPW_SBD_TYPE_DATA; 664 sbd->priv = sbuf; 665 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 666 sbd->bd->len = htole32(MCLBYTES); 667 668 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, 669 sbuf->map->dm_mapsize, BUS_DMASYNC_PREREAD); 670 671 } 672 673 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 0, IPW_RBD_SZ, 674 BUS_DMASYNC_PREREAD); 675 676 return 0; 677 678 fail: ipw_release(sc); 679 return error; 680 } 681 682 static void 683 ipw_release(struct ipw_softc *sc) 684 { 685 struct ipw_soft_buf *sbuf; 686 int i; 687 688 if (sc->tbd_map != NULL) { 689 if (sc->tbd_list != NULL) { 690 bus_dmamap_unload(sc->sc_dmat, sc->tbd_map); 691 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->tbd_list, 692 IPW_TBD_SZ); 693 bus_dmamem_free(sc->sc_dmat, &sc->tbd_seg, 1); 694 } 695 bus_dmamap_destroy(sc->sc_dmat, sc->tbd_map); 696 } 697 698 if (sc->rbd_map != NULL) { 699 if (sc->rbd_list != NULL) { 700 bus_dmamap_unload(sc->sc_dmat, sc->rbd_map); 701 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->rbd_list, 702 IPW_RBD_SZ); 703 bus_dmamem_free(sc->sc_dmat, &sc->rbd_seg, 1); 704 } 705 bus_dmamap_destroy(sc->sc_dmat, sc->rbd_map); 706 } 707 708 if (sc->status_map != NULL) { 709 if (sc->status_list != NULL) { 710 bus_dmamap_unload(sc->sc_dmat, sc->status_map); 711 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->status_list, 712 IPW_RBD_SZ); 713 bus_dmamem_free(sc->sc_dmat, &sc->status_seg, 1); 714 } 715 bus_dmamap_destroy(sc->sc_dmat, sc->status_map); 716 } 717 718 for (i = 0; i < IPW_NTBD; i++) 719 ipw_release_sbd(sc, &sc->stbd_list[i]); 720 721 if (sc->cmd_map != NULL) 722 bus_dmamap_destroy(sc->sc_dmat, sc->cmd_map); 723 724 if (sc->hdr_list != NULL) { 725 bus_dmamap_unload(sc->sc_dmat, sc->hdr_map); 726 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->hdr_list, 727 IPW_NDATA * sizeof(struct ipw_hdr)); 728 } 729 if (sc->hdr_map != NULL) { 730 bus_dmamem_free(sc->sc_dmat, &sc->hdr_seg, 1); 731 bus_dmamap_destroy(sc->sc_dmat, sc->hdr_map); 732 } 733 734 for (i = 0; i < IPW_NDATA; i++) 735 bus_dmamap_destroy(sc->sc_dmat, sc->tx_sbuf_list[i].map); 736 737 for (i = 0; i < IPW_NRBD; i++) { 738 sbuf = &sc->rx_sbuf_list[i]; 739 if (sbuf->map != NULL) { 740 if (sbuf->m != NULL) { 741 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 742 m_freem(sbuf->m); 743 } 744 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 745 } 746 } 747 748 } 749 750 static void 751 ipw_shutdown(void *arg) 752 { 753 struct ipw_softc *sc = (struct ipw_softc *)arg; 754 struct ifnet *ifp = sc->sc_ic.ic_ifp; 755 756 ipw_stop(ifp, 1); 757 } 758 759 760 static int 761 ipw_suspend(struct ipw_softc *sc) 762 { 763 struct ifnet *ifp = sc->sc_ic.ic_ifp; 764 765 ipw_stop(ifp, 1); 766 767 return 0; 768 } 769 770 static int 771 ipw_resume(struct ipw_softc *sc) 772 { 773 struct ifnet *ifp = sc->sc_ic.ic_ifp; 774 pcireg_t data; 775 776 /* clear device specific PCI configuration register 0x41 */ 777 data = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 778 data &= ~0x0000ff00; 779 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, data); 780 781 if (ifp->if_flags & IFF_UP) { 782 ipw_init(ifp); 783 if (ifp->if_flags & IFF_RUNNING) 784 ipw_start(ifp); 785 } 786 787 return 0; 788 } 789 790 static void 791 ipw_powerhook(int why, void *arg) 792 { 793 struct ipw_softc *sc = arg; 794 int s; 795 796 s = splnet(); 797 switch (why) { 798 case PWR_SUSPEND: 799 case PWR_STANDBY: 800 ipw_suspend(sc); 801 break; 802 case PWR_RESUME: 803 ipw_resume(sc); 804 break; 805 case PWR_SOFTSUSPEND: 806 case PWR_SOFTSTANDBY: 807 case PWR_SOFTRESUME: 808 break; 809 } 810 splx(s); 811 } 812 813 static int 814 ipw_media_change(struct ifnet *ifp) 815 { 816 int error; 817 818 error = ieee80211_media_change(ifp); 819 if (error != ENETRESET) 820 return error; 821 822 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 823 ipw_init(ifp); 824 825 return 0; 826 } 827 828 /* 829 * The firmware automatically adapts the transmit speed. We report the current 830 * transmit speed here. 831 */ 832 static void 833 ipw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 834 { 835 #define N(a) (sizeof (a) / sizeof (a[0])) 836 struct ipw_softc *sc = ifp->if_softc; 837 struct ieee80211com *ic = &sc->sc_ic; 838 static const struct { 839 uint32_t val; 840 int rate; 841 } rates[] = { 842 { IPW_RATE_DS1, 2 }, 843 { IPW_RATE_DS2, 4 }, 844 { IPW_RATE_DS5, 11 }, 845 { IPW_RATE_DS11, 22 }, 846 }; 847 uint32_t val; 848 int rate, i; 849 850 imr->ifm_status = IFM_AVALID; 851 imr->ifm_active = IFM_IEEE80211; 852 if (ic->ic_state == IEEE80211_S_RUN) 853 imr->ifm_status |= IFM_ACTIVE; 854 855 /* read current transmission rate from adapter */ 856 val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE) & 0xf; 857 858 /* convert ipw rate to 802.11 rate */ 859 for (i = 0; i < N(rates) && rates[i].val != val; i++); 860 rate = (i < N(rates)) ? rates[i].rate : 0; 861 862 imr->ifm_active |= IFM_IEEE80211_11B; 863 imr->ifm_active |= ieee80211_rate2media(ic, rate, IEEE80211_MODE_11B); 864 switch (ic->ic_opmode) { 865 case IEEE80211_M_STA: 866 break; 867 868 case IEEE80211_M_IBSS: 869 imr->ifm_active |= IFM_IEEE80211_ADHOC; 870 break; 871 872 case IEEE80211_M_MONITOR: 873 imr->ifm_active |= IFM_IEEE80211_MONITOR; 874 break; 875 876 case IEEE80211_M_AHDEMO: 877 case IEEE80211_M_HOSTAP: 878 /* should not get there */ 879 break; 880 } 881 #undef N 882 } 883 884 static int 885 ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 886 { 887 struct ifnet *ifp = ic->ic_ifp; 888 struct ipw_softc *sc = ifp->if_softc; 889 struct ieee80211_node *ni; 890 uint8_t macaddr[IEEE80211_ADDR_LEN]; 891 uint32_t len; 892 893 switch (nstate) { 894 case IEEE80211_S_RUN: 895 DELAY(200); /* firmware needs a short delay here */ 896 897 len = IEEE80211_ADDR_LEN; 898 ipw_read_table2(sc, IPW_INFO_CURRENT_BSSID, macaddr, &len); 899 900 ni = ieee80211_find_node(&ic->ic_scan, macaddr); 901 if (ni == NULL) 902 break; 903 904 ieee80211_ref_node(ni); 905 ieee80211_sta_join(ic, ni); 906 ieee80211_node_authorize(ni); 907 908 if (ic->ic_opmode == IEEE80211_M_STA) 909 ieee80211_notify_node_join(ic, ni, 1); 910 break; 911 912 case IEEE80211_S_INIT: 913 case IEEE80211_S_SCAN: 914 case IEEE80211_S_AUTH: 915 case IEEE80211_S_ASSOC: 916 break; 917 } 918 919 ic->ic_state = nstate; 920 return 0; 921 } 922 923 /* 924 * Read 16 bits at address 'addr' from the serial EEPROM. 925 */ 926 static uint16_t 927 ipw_read_prom_word(struct ipw_softc *sc, uint8_t addr) 928 { 929 uint32_t tmp; 930 uint16_t val; 931 int n; 932 933 /* clock C once before the first command */ 934 IPW_EEPROM_CTL(sc, 0); 935 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 936 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 937 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 938 939 /* write start bit (1) */ 940 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 941 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 942 943 /* write READ opcode (10) */ 944 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 945 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 946 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 947 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 948 949 /* write address A7-A0 */ 950 for (n = 7; n >= 0; n--) { 951 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 952 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D)); 953 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 954 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D) | IPW_EEPROM_C); 955 } 956 957 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 958 959 /* read data Q15-Q0 */ 960 val = 0; 961 for (n = 15; n >= 0; n--) { 962 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 963 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 964 tmp = MEM_READ_4(sc, IPW_MEM_EEPROM_CTL); 965 val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n; 966 } 967 968 IPW_EEPROM_CTL(sc, 0); 969 970 /* clear Chip Select and clock C */ 971 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 972 IPW_EEPROM_CTL(sc, 0); 973 IPW_EEPROM_CTL(sc, IPW_EEPROM_C); 974 975 return le16toh(val); 976 } 977 978 static void 979 ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 980 { 981 struct ipw_cmd *cmd; 982 983 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof (struct ipw_cmd), 984 BUS_DMASYNC_POSTREAD); 985 986 cmd = mtod(sbuf->m, struct ipw_cmd *); 987 988 DPRINTFN(2, ("cmd ack'ed (%u, %u, %u, %u, %u)\n", le32toh(cmd->type), 989 le32toh(cmd->subtype), le32toh(cmd->seq), le32toh(cmd->len), 990 le32toh(cmd->status))); 991 992 wakeup(&sc->cmd); 993 } 994 995 static void 996 ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 997 { 998 struct ieee80211com *ic = &sc->sc_ic; 999 struct ifnet *ifp = sc->sc_ic.ic_ifp; 1000 uint32_t state; 1001 1002 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof state, 1003 BUS_DMASYNC_POSTREAD); 1004 1005 state = le32toh(*mtod(sbuf->m, uint32_t *)); 1006 1007 DPRINTFN(2, ("entering state %u\n", state)); 1008 1009 switch (state) { 1010 case IPW_STATE_ASSOCIATED: 1011 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1012 break; 1013 1014 case IPW_STATE_SCANNING: 1015 /* don't leave run state on background scan */ 1016 if (ic->ic_state != IEEE80211_S_RUN) 1017 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1018 1019 ic->ic_flags |= IEEE80211_F_SCAN; 1020 break; 1021 1022 case IPW_STATE_SCAN_COMPLETE: 1023 ieee80211_notify_scan_done(ic); 1024 ic->ic_flags &= ~IEEE80211_F_SCAN; 1025 break; 1026 1027 case IPW_STATE_ASSOCIATION_LOST: 1028 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1029 break; 1030 1031 case IPW_STATE_RADIO_DISABLED: 1032 ic->ic_ifp->if_flags &= ~IFF_UP; 1033 ipw_stop(ifp, 1); 1034 break; 1035 } 1036 } 1037 1038 /* 1039 * XXX: Hack to set the current channel to the value advertised in beacons or 1040 * probe responses. Only used during AP detection. 1041 */ 1042 static void 1043 ipw_fix_channel(struct ieee80211com *ic, struct mbuf *m) 1044 { 1045 struct ieee80211_frame *wh; 1046 uint8_t subtype; 1047 uint8_t *frm, *efrm; 1048 1049 wh = mtod(m, struct ieee80211_frame *); 1050 1051 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_MGT) 1052 return; 1053 1054 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 1055 1056 if (subtype != IEEE80211_FC0_SUBTYPE_BEACON && 1057 subtype != IEEE80211_FC0_SUBTYPE_PROBE_RESP) 1058 return; 1059 1060 frm = (uint8_t *)(wh + 1); 1061 efrm = mtod(m, uint8_t *) + m->m_len; 1062 1063 frm += 12; /* skip tstamp, bintval and capinfo fields */ 1064 while (frm < efrm) { 1065 if (*frm == IEEE80211_ELEMID_DSPARMS) 1066 #if IEEE80211_CHAN_MAX < 255 1067 if (frm[2] <= IEEE80211_CHAN_MAX) 1068 #endif 1069 ic->ic_curchan = &ic->ic_channels[frm[2]]; 1070 1071 frm += frm[1] + 2; 1072 } 1073 } 1074 1075 static void 1076 ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 1077 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 1078 { 1079 struct ieee80211com *ic = &sc->sc_ic; 1080 struct ifnet *ifp = &sc->sc_if; 1081 struct mbuf *mnew, *m; 1082 struct ieee80211_frame *wh; 1083 struct ieee80211_node *ni; 1084 int error; 1085 1086 DPRINTFN(5, ("received frame len=%u, rssi=%u\n", le32toh(status->len), 1087 status->rssi)); 1088 1089 if (le32toh(status->len) < sizeof (struct ieee80211_frame_min) || 1090 le32toh(status->len) > MCLBYTES) 1091 return; 1092 1093 /* 1094 * Try to allocate a new mbuf for this ring element and load it before 1095 * processing the current mbuf. If the ring element cannot be loaded, 1096 * drop the received packet and reuse the old mbuf. In the unlikely 1097 * case that the old mbuf can't be reloaded either, explicitly panic. 1098 */ 1099 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1100 if (mnew == NULL) { 1101 aprint_error("%s: could not allocate rx mbuf\n", 1102 sc->sc_dev.dv_xname); 1103 ifp->if_ierrors++; 1104 return; 1105 } 1106 1107 MCLGET(mnew, M_DONTWAIT); 1108 if (!(mnew->m_flags & M_EXT)) { 1109 aprint_error("%s: could not allocate rx mbuf cluster\n", 1110 sc->sc_dev.dv_xname); 1111 m_freem(mnew); 1112 ifp->if_ierrors++; 1113 return; 1114 } 1115 1116 mnew->m_pkthdr.len = mnew->m_len = mnew->m_ext.ext_size; 1117 1118 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, le32toh(status->len), 1119 BUS_DMASYNC_POSTREAD); 1120 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1121 1122 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, mnew, 1123 BUS_DMA_READ | BUS_DMA_NOWAIT); 1124 if (error != 0) { 1125 aprint_error("%s: could not load rx buf DMA map\n", 1126 sc->sc_dev.dv_xname); 1127 m_freem(mnew); 1128 1129 /* try to reload the old mbuf */ 1130 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, 1131 sbuf->m, BUS_DMA_READ | BUS_DMA_NOWAIT); 1132 if (error != 0) { 1133 /* very unlikely that it will fail... */ 1134 panic("%s: unable to remap rx buf", 1135 sc->sc_dev.dv_xname); 1136 } 1137 ifp->if_ierrors++; 1138 return; 1139 } 1140 1141 /* 1142 * New mbuf successfully loaded, update Rx ring and continue 1143 * processing. 1144 */ 1145 m = sbuf->m; 1146 sbuf->m = mnew; 1147 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 1148 1149 /* finalize mbuf */ 1150 m->m_pkthdr.rcvif = ifp; 1151 m->m_pkthdr.len = m->m_len = le32toh(status->len); 1152 1153 #if NBPFILTER > 0 1154 if (sc->sc_drvbpf != NULL) { 1155 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 1156 1157 tap->wr_flags = 0; 1158 tap->wr_antsignal = status->rssi; 1159 tap->wr_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 1160 tap->wr_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 1161 1162 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 1163 } 1164 #endif 1165 1166 if (ic->ic_state == IEEE80211_S_SCAN) 1167 ipw_fix_channel(ic, m); 1168 1169 wh = mtod(m, struct ieee80211_frame *); 1170 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 1171 1172 /* send the frame to the 802.11 layer */ 1173 ieee80211_input(ic, m, ni, status->rssi, 0); 1174 1175 /* node is no longer needed */ 1176 ieee80211_free_node(ni); 1177 1178 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, 1179 sbuf->map->dm_mapsize, BUS_DMASYNC_PREREAD); 1180 } 1181 1182 static void 1183 ipw_rx_intr(struct ipw_softc *sc) 1184 { 1185 struct ipw_status *status; 1186 struct ipw_soft_bd *sbd; 1187 struct ipw_soft_buf *sbuf; 1188 uint32_t r, i; 1189 1190 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1191 return; 1192 1193 r = CSR_READ_4(sc, IPW_CSR_RX_READ); 1194 1195 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 1196 1197 /* firmware was killed, stop processing received frames */ 1198 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1199 return; 1200 1201 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 1202 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1203 BUS_DMASYNC_POSTREAD); 1204 1205 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 1206 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 1207 BUS_DMASYNC_POSTREAD); 1208 1209 status = &sc->status_list[i]; 1210 sbd = &sc->srbd_list[i]; 1211 sbuf = sbd->priv; 1212 1213 switch (le16toh(status->code) & 0xf) { 1214 case IPW_STATUS_CODE_COMMAND: 1215 ipw_command_intr(sc, sbuf); 1216 break; 1217 1218 case IPW_STATUS_CODE_NEWSTATE: 1219 ipw_newstate_intr(sc, sbuf); 1220 break; 1221 1222 case IPW_STATUS_CODE_DATA_802_3: 1223 case IPW_STATUS_CODE_DATA_802_11: 1224 ipw_data_intr(sc, status, sbd, sbuf); 1225 break; 1226 1227 case IPW_STATUS_CODE_NOTIFICATION: 1228 DPRINTFN(2, ("received notification\n")); 1229 break; 1230 1231 default: 1232 aprint_debug("%s: unknown status code %u\n", 1233 sc->sc_dev.dv_xname, le16toh(status->code)); 1234 } 1235 1236 sbd->bd->flags = 0; 1237 1238 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 1239 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1240 BUS_DMASYNC_PREREAD); 1241 1242 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 1243 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 1244 BUS_DMASYNC_PREREAD); 1245 } 1246 1247 /* Tell the firmware what we have processed */ 1248 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 1249 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 1250 } 1251 1252 static void 1253 ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 1254 { 1255 struct ieee80211com *ic; 1256 struct ipw_soft_hdr *shdr; 1257 struct ipw_soft_buf *sbuf; 1258 1259 switch (sbd->type) { 1260 case IPW_SBD_TYPE_COMMAND: 1261 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 1262 0, sizeof(struct ipw_cmd), BUS_DMASYNC_POSTWRITE); 1263 /* bus_dmamap_unload(sc->sc_dmat, sc->cmd_map); */ 1264 break; 1265 1266 case IPW_SBD_TYPE_HEADER: 1267 shdr = sbd->priv; 1268 bus_dmamap_sync(sc->sc_dmat, sc->hdr_map, 1269 shdr->offset, sizeof(struct ipw_hdr), BUS_DMASYNC_POSTWRITE); 1270 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 1271 break; 1272 1273 case IPW_SBD_TYPE_DATA: 1274 ic = &sc->sc_ic; 1275 sbuf = sbd->priv; 1276 1277 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 1278 0, MCLBYTES, BUS_DMASYNC_POSTWRITE); 1279 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1280 m_freem(sbuf->m); 1281 if (sbuf->ni != NULL) 1282 ieee80211_free_node(sbuf->ni); 1283 /* kill watchdog timer */ 1284 sc->sc_tx_timer = 0; 1285 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 1286 break; 1287 } 1288 sbd->type = IPW_SBD_TYPE_NOASSOC; 1289 } 1290 1291 static void 1292 ipw_tx_intr(struct ipw_softc *sc) 1293 { 1294 struct ifnet *ifp = &sc->sc_if; 1295 struct ipw_soft_bd *sbd; 1296 uint32_t r, i; 1297 1298 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1299 return; 1300 1301 r = CSR_READ_4(sc, IPW_CSR_TX_READ); 1302 1303 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) { 1304 sbd = &sc->stbd_list[i]; 1305 1306 if (sbd->type == IPW_SBD_TYPE_DATA) 1307 ifp->if_opackets++; 1308 1309 ipw_release_sbd(sc, sbd); 1310 sc->txfree++; 1311 } 1312 1313 /* remember what the firmware has processed */ 1314 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 1315 1316 /* Call start() since some buffer descriptors have been released */ 1317 ifp->if_flags &= ~IFF_OACTIVE; 1318 (*ifp->if_start)(ifp); 1319 } 1320 1321 static int 1322 ipw_intr(void *arg) 1323 { 1324 struct ipw_softc *sc = arg; 1325 uint32_t r; 1326 1327 r = CSR_READ_4(sc, IPW_CSR_INTR); 1328 if (r == 0 || r == 0xffffffff) 1329 return 0; 1330 1331 /* Disable interrupts */ 1332 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1333 1334 if (r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR)) { 1335 aprint_error("%s: fatal error\n", 1336 sc->sc_dev.dv_xname); 1337 sc->sc_ic.ic_ifp->if_flags &= ~IFF_UP; 1338 ipw_stop(&sc->sc_if, 1); 1339 } 1340 1341 if (r & IPW_INTR_FW_INIT_DONE) { 1342 if (!(r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR))) 1343 wakeup(sc); 1344 } 1345 1346 if (r & IPW_INTR_RX_TRANSFER) 1347 ipw_rx_intr(sc); 1348 1349 if (r & IPW_INTR_TX_TRANSFER) 1350 ipw_tx_intr(sc); 1351 1352 /* Acknowledge all interrupts */ 1353 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 1354 1355 /* Re-enable interrupts */ 1356 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1357 1358 return 0; 1359 } 1360 1361 /* 1362 * Send a command to the firmware and wait for the acknowledgement. 1363 */ 1364 static int 1365 ipw_cmd(struct ipw_softc *sc, uint32_t type, void *data, uint32_t len) 1366 { 1367 struct ipw_soft_bd *sbd; 1368 1369 sbd = &sc->stbd_list[sc->txcur]; 1370 1371 sc->cmd.type = htole32(type); 1372 sc->cmd.subtype = 0; 1373 sc->cmd.len = htole32(len); 1374 sc->cmd.seq = 0; 1375 1376 (void)memcpy(sc->cmd.data, data, len); 1377 1378 sbd->type = IPW_SBD_TYPE_COMMAND; 1379 sbd->bd->physaddr = htole32(sc->cmd_map->dm_segs[0].ds_addr); 1380 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 1381 sbd->bd->nfrag = 1; 1382 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 1383 IPW_BD_FLAG_TX_LAST_FRAGMENT; 1384 1385 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 0, sizeof (struct ipw_cmd), 1386 BUS_DMASYNC_PREWRITE); 1387 1388 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1389 sc->txcur * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1390 BUS_DMASYNC_PREWRITE); 1391 1392 DPRINTFN(2, ("sending command (%u, %u, %u, %u)\n", type, 0, 0, len)); 1393 1394 /* kick firmware */ 1395 sc->txfree--; 1396 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1397 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1398 1399 /* Wait at most one second for command to complete */ 1400 return tsleep(&sc->cmd, 0, "ipwcmd", hz); 1401 } 1402 1403 static int 1404 ipw_tx_start(struct ifnet *ifp, struct mbuf *m0, struct ieee80211_node *ni) 1405 { 1406 struct ipw_softc *sc = ifp->if_softc; 1407 struct ieee80211com *ic = &sc->sc_ic; 1408 struct ieee80211_frame *wh; 1409 struct ipw_soft_bd *sbd; 1410 struct ipw_soft_hdr *shdr; 1411 struct ipw_soft_buf *sbuf; 1412 struct ieee80211_key *k; 1413 struct mbuf *mnew; 1414 int error, i; 1415 1416 wh = mtod(m0, struct ieee80211_frame *); 1417 1418 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1419 k = ieee80211_crypto_encap(ic, ni, m0); 1420 if (k == NULL) { 1421 m_freem(m0); 1422 return ENOBUFS; 1423 } 1424 1425 /* packet header may have moved, reset our local pointer */ 1426 wh = mtod(m0, struct ieee80211_frame *); 1427 } 1428 1429 #if NBPFILTER > 0 1430 if (sc->sc_drvbpf != NULL) { 1431 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 1432 1433 tap->wt_flags = 0; 1434 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 1435 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 1436 1437 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 1438 } 1439 #endif 1440 1441 shdr = TAILQ_FIRST(&sc->sc_free_shdr); 1442 sbuf = TAILQ_FIRST(&sc->sc_free_sbuf); 1443 KASSERT(shdr != NULL && sbuf != NULL); 1444 1445 shdr->hdr->type = htole32(IPW_HDR_TYPE_SEND); 1446 shdr->hdr->subtype = 0; 1447 shdr->hdr->encrypted = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0; 1448 shdr->hdr->encrypt = 0; 1449 shdr->hdr->keyidx = 0; 1450 shdr->hdr->keysz = 0; 1451 shdr->hdr->fragmentsz = 0; 1452 IEEE80211_ADDR_COPY(shdr->hdr->src_addr, wh->i_addr2); 1453 if (ic->ic_opmode == IEEE80211_M_STA) 1454 IEEE80211_ADDR_COPY(shdr->hdr->dst_addr, wh->i_addr3); 1455 else 1456 IEEE80211_ADDR_COPY(shdr->hdr->dst_addr, wh->i_addr1); 1457 1458 /* trim IEEE802.11 header */ 1459 m_adj(m0, sizeof (struct ieee80211_frame)); 1460 1461 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m0, BUS_DMA_NOWAIT); 1462 if (error != 0 && error != EFBIG) { 1463 aprint_error("%s: could not map mbuf (error %d)\n", 1464 sc->sc_dev.dv_xname, error); 1465 m_freem(m0); 1466 return error; 1467 } 1468 1469 if (error != 0) { 1470 /* too many fragments, linearize */ 1471 1472 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1473 if (mnew == NULL) { 1474 m_freem(m0); 1475 return ENOMEM; 1476 } 1477 1478 M_COPY_PKTHDR(mnew, m0); 1479 1480 /* If the data won't fit in the header, get a cluster */ 1481 if (m0->m_pkthdr.len > MHLEN) { 1482 MCLGET(mnew, M_DONTWAIT); 1483 if (!(mnew->m_flags & M_EXT)) { 1484 m_freem(m0); 1485 m_freem(mnew); 1486 return ENOMEM; 1487 } 1488 } 1489 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(mnew, caddr_t)); 1490 m_freem(m0); 1491 mnew->m_len = mnew->m_pkthdr.len; 1492 m0 = mnew; 1493 1494 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m0, 1495 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1496 if (error != 0) { 1497 aprint_error("%s: could not map mbuf (error %d)\n", 1498 sc->sc_dev.dv_xname, error); 1499 m_freem(m0); 1500 return error; 1501 } 1502 } 1503 1504 TAILQ_REMOVE(&sc->sc_free_sbuf, sbuf, next); 1505 TAILQ_REMOVE(&sc->sc_free_shdr, shdr, next); 1506 1507 sbd = &sc->stbd_list[sc->txcur]; 1508 sbd->type = IPW_SBD_TYPE_HEADER; 1509 sbd->priv = shdr; 1510 sbd->bd->physaddr = htole32(shdr->addr); 1511 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 1512 sbd->bd->nfrag = 1 + sbuf->map->dm_nsegs; 1513 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 1514 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1515 1516 DPRINTFN(5, ("sending tx hdr (%u, %u, %u, %u, )\n", 1517 shdr->hdr->type, shdr->hdr->subtype, shdr->hdr->encrypted, 1518 shdr->hdr->encrypt)); 1519 DPRINTFN(5, ("%s->", ether_sprintf(shdr->hdr->src_addr))); 1520 DPRINTFN(5, ("%s\n", ether_sprintf(shdr->hdr->dst_addr))); 1521 1522 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1523 sc->txcur * sizeof (struct ipw_bd), 1524 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1525 1526 sc->txfree--; 1527 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1528 1529 sbuf->m = m0; 1530 sbuf->ni = ni; 1531 1532 for (i = 0; i < sbuf->map->dm_nsegs; i++) { 1533 sbd = &sc->stbd_list[sc->txcur]; 1534 1535 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[i].ds_addr); 1536 sbd->bd->len = htole32(sbuf->map->dm_segs[i].ds_len); 1537 sbd->bd->nfrag = 0; 1538 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 1539 if (i == sbuf->map->dm_nsegs - 1) { 1540 sbd->type = IPW_SBD_TYPE_DATA; 1541 sbd->priv = sbuf; 1542 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 1543 } else { 1544 sbd->type = IPW_SBD_TYPE_NOASSOC; 1545 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1546 } 1547 1548 DPRINTFN(5, ("sending fragment (%d, %d)\n", i, 1549 (int)sbuf->map->dm_segs[i].ds_len)); 1550 1551 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1552 sc->txcur * sizeof (struct ipw_bd), 1553 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1554 1555 sc->txfree--; 1556 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1557 } 1558 1559 bus_dmamap_sync(sc->sc_dmat, sc->hdr_map, shdr->offset, 1560 sizeof (struct ipw_hdr), BUS_DMASYNC_PREWRITE); 1561 1562 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, MCLBYTES, 1563 BUS_DMASYNC_PREWRITE); 1564 1565 /* Inform firmware about this new packet */ 1566 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1567 1568 return 0; 1569 } 1570 1571 static void 1572 ipw_start(struct ifnet *ifp) 1573 { 1574 struct ipw_softc *sc = ifp->if_softc; 1575 struct ieee80211com *ic = &sc->sc_ic; 1576 struct mbuf *m0; 1577 struct ether_header *eh; 1578 struct ieee80211_node *ni; 1579 1580 1581 if (ic->ic_state != IEEE80211_S_RUN) 1582 return; 1583 1584 for (;;) { 1585 IF_DEQUEUE(&ifp->if_snd, m0); 1586 if (m0 == NULL) 1587 break; 1588 1589 if (sc->txfree < 1 + IPW_MAX_NSEG) { 1590 IF_PREPEND(&ifp->if_snd, m0); 1591 ifp->if_flags |= IFF_OACTIVE; 1592 break; 1593 } 1594 1595 if (m0->m_len < sizeof (struct ether_header) && 1596 (m0 = m_pullup(m0, sizeof (struct ether_header))) == NULL) 1597 continue; 1598 1599 eh = mtod(m0, struct ether_header *); 1600 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1601 if (ni == NULL) { 1602 m_freem(m0); 1603 continue; 1604 } 1605 1606 #if NBPFILTER > 0 1607 if (ifp->if_bpf != NULL) 1608 bpf_mtap(ifp->if_bpf, m0); 1609 #endif 1610 1611 m0 = ieee80211_encap(ic, m0, ni); 1612 if (m0 == NULL) { 1613 ieee80211_free_node(ni); 1614 continue; 1615 } 1616 1617 #if NBPFILTER > 0 1618 if (ic->ic_rawbpf != NULL) 1619 bpf_mtap(ic->ic_rawbpf, m0); 1620 #endif 1621 1622 if (ipw_tx_start(ifp, m0, ni) != 0) { 1623 ieee80211_free_node(ni); 1624 ifp->if_oerrors++; 1625 break; 1626 } 1627 1628 /* start watchdog timer */ 1629 sc->sc_tx_timer = 5; 1630 ifp->if_timer = 1; 1631 } 1632 } 1633 1634 static void 1635 ipw_watchdog(struct ifnet *ifp) 1636 { 1637 struct ipw_softc *sc = ifp->if_softc; 1638 1639 ifp->if_timer = 0; 1640 1641 if (sc->sc_tx_timer > 0) { 1642 if (--sc->sc_tx_timer == 0) { 1643 aprint_error("%s: device timeout\n", 1644 sc->sc_dev.dv_xname); 1645 ifp->if_oerrors++; 1646 ifp->if_flags &= ~IFF_UP; 1647 ipw_stop(ifp, 1); 1648 return; 1649 } 1650 ifp->if_timer = 1; 1651 } 1652 1653 ieee80211_watchdog(&sc->sc_ic); 1654 } 1655 1656 static int 1657 ipw_get_table1(struct ipw_softc *sc, uint32_t *tbl) 1658 { 1659 uint32_t addr, size, i; 1660 1661 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1662 return ENOTTY; 1663 1664 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, sc->table1_base); 1665 1666 size = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 1667 if (suword(tbl, size) != 0) 1668 return EFAULT; 1669 1670 for (i = 1, ++tbl; i < size; i++, tbl++) { 1671 addr = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 1672 if (suword(tbl, MEM_READ_4(sc, addr)) != 0) 1673 return EFAULT; 1674 } 1675 return 0; 1676 } 1677 1678 static int 1679 ipw_get_radio(struct ipw_softc *sc, int *ret) 1680 { 1681 uint32_t addr; 1682 1683 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1684 return ENOTTY; 1685 1686 addr = ipw_read_table1(sc, IPW_INFO_EEPROM_ADDRESS); 1687 if ((MEM_READ_4(sc, addr + 32) >> 24) & 1) { 1688 suword(ret, -1); 1689 return 0; 1690 } 1691 1692 if (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED) 1693 suword(ret, 0); 1694 else 1695 suword(ret, 1); 1696 1697 return 0; 1698 } 1699 1700 static int 1701 ipw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1702 { 1703 #define IS_RUNNING(ifp) \ 1704 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 1705 1706 struct ipw_softc *sc = ifp->if_softc; 1707 struct ieee80211com *ic = &sc->sc_ic; 1708 struct ifreq *ifr = (struct ifreq *)data; 1709 int s, error = 0; 1710 1711 s = splnet(); 1712 1713 switch (cmd) { 1714 case SIOCSIFFLAGS: 1715 if (ifp->if_flags & IFF_UP) { 1716 if (!(ifp->if_flags & IFF_RUNNING)) 1717 ipw_init(ifp); 1718 } else { 1719 if (ifp->if_flags & IFF_RUNNING) 1720 ipw_stop(ifp, 1); 1721 } 1722 break; 1723 1724 case SIOCADDMULTI: 1725 case SIOCDELMULTI: 1726 error = (cmd == SIOCADDMULTI) ? 1727 ether_addmulti(ifr, &sc->sc_ec) : 1728 ether_delmulti(ifr, &sc->sc_ec); 1729 if (error == ENETRESET) { 1730 /* setup multicast filter, etc */ 1731 error = 0; 1732 } 1733 break; 1734 1735 case SIOCGTABLE1: 1736 error = ipw_get_table1(sc, (uint32_t *)ifr->ifr_data); 1737 break; 1738 1739 case SIOCGRADIO: 1740 error = ipw_get_radio(sc, (int *)ifr->ifr_data); 1741 break; 1742 1743 case SIOCSIFMEDIA: 1744 if (ifr->ifr_media & IFM_IEEE80211_ADHOC) 1745 strncpy(sc->sc_fwname, "ipw2100-1.2-i.fw", 24); 1746 else if (ifr->ifr_media & IFM_IEEE80211_MONITOR) 1747 strncpy(sc->sc_fwname, "ipw2100-1.2-p.fw", 24); 1748 else 1749 strncpy(sc->sc_fwname, "ipw2100-1.2.fw", 24); 1750 1751 ipw_free_firmware(sc); 1752 /* FALLTRHOUGH */ 1753 default: 1754 error = ieee80211_ioctl(&sc->sc_ic, cmd, data); 1755 if (error != ENETRESET) 1756 break; 1757 1758 if (error == ENETRESET) { 1759 if (IS_RUNNING(ifp) && 1760 (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)) 1761 ipw_init(ifp); 1762 error = 0; 1763 } 1764 1765 } 1766 1767 splx(s); 1768 return error; 1769 #undef IS_RUNNING 1770 } 1771 1772 static uint32_t 1773 ipw_read_table1(struct ipw_softc *sc, uint32_t off) 1774 { 1775 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 1776 } 1777 1778 static void 1779 ipw_write_table1(struct ipw_softc *sc, uint32_t off, uint32_t info) 1780 { 1781 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 1782 } 1783 1784 static int 1785 ipw_read_table2(struct ipw_softc *sc, uint32_t off, void *buf, uint32_t *len) 1786 { 1787 uint32_t addr, info; 1788 uint16_t count, size; 1789 uint32_t total; 1790 1791 /* addr[4] + count[2] + size[2] */ 1792 addr = MEM_READ_4(sc, sc->table2_base + off); 1793 info = MEM_READ_4(sc, sc->table2_base + off + 4); 1794 1795 count = info >> 16; 1796 size = info & 0xffff; 1797 total = count * size; 1798 1799 if (total > *len) { 1800 *len = total; 1801 return EINVAL; 1802 } 1803 1804 *len = total; 1805 ipw_read_mem_1(sc, addr, buf, total); 1806 1807 return 0; 1808 } 1809 1810 static void 1811 ipw_stop_master(struct ipw_softc *sc) 1812 { 1813 int ntries; 1814 1815 /* disable interrupts */ 1816 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1817 1818 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1819 for (ntries = 0; ntries < 50; ntries++) { 1820 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1821 break; 1822 DELAY(10); 1823 } 1824 if (ntries == 50) 1825 aprint_error("%s: timeout waiting for master\n", 1826 sc->sc_dev.dv_xname); 1827 1828 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1829 IPW_RST_PRINCETON_RESET); 1830 1831 sc->flags &= ~IPW_FLAG_FW_INITED; 1832 } 1833 1834 static int 1835 ipw_reset(struct ipw_softc *sc) 1836 { 1837 int ntries; 1838 1839 ipw_stop_master(sc); 1840 1841 /* move adapter to D0 state */ 1842 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1843 IPW_CTL_INIT); 1844 1845 /* wait for clock stabilization */ 1846 for (ntries = 0; ntries < 1000; ntries++) { 1847 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY) 1848 break; 1849 DELAY(200); 1850 } 1851 if (ntries == 1000) 1852 return EIO; 1853 1854 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1855 IPW_RST_SW_RESET); 1856 1857 DELAY(10); 1858 1859 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1860 IPW_CTL_INIT); 1861 1862 return 0; 1863 } 1864 1865 /* 1866 * Upload the microcode to the device. 1867 */ 1868 static int 1869 ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size) 1870 { 1871 int ntries; 1872 1873 MEM_WRITE_4(sc, 0x3000e0, 0x80000000); 1874 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1875 1876 MEM_WRITE_2(sc, 0x220000, 0x0703); 1877 MEM_WRITE_2(sc, 0x220000, 0x0707); 1878 1879 MEM_WRITE_1(sc, 0x210014, 0x72); 1880 MEM_WRITE_1(sc, 0x210014, 0x72); 1881 1882 MEM_WRITE_1(sc, 0x210000, 0x40); 1883 MEM_WRITE_1(sc, 0x210000, 0x00); 1884 MEM_WRITE_1(sc, 0x210000, 0x40); 1885 1886 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1887 1888 MEM_WRITE_1(sc, 0x210000, 0x00); 1889 MEM_WRITE_1(sc, 0x210000, 0x00); 1890 MEM_WRITE_1(sc, 0x210000, 0x80); 1891 1892 MEM_WRITE_2(sc, 0x220000, 0x0703); 1893 MEM_WRITE_2(sc, 0x220000, 0x0707); 1894 1895 MEM_WRITE_1(sc, 0x210014, 0x72); 1896 MEM_WRITE_1(sc, 0x210014, 0x72); 1897 1898 MEM_WRITE_1(sc, 0x210000, 0x00); 1899 MEM_WRITE_1(sc, 0x210000, 0x80); 1900 1901 for (ntries = 0; ntries < 10; ntries++) { 1902 if (MEM_READ_1(sc, 0x210000) & 1) 1903 break; 1904 DELAY(10); 1905 } 1906 if (ntries == 10) { 1907 aprint_error("%s: timeout waiting for ucode to initialize\n", 1908 sc->sc_dev.dv_xname); 1909 return EIO; 1910 } 1911 1912 MEM_WRITE_4(sc, 0x3000e0, 0); 1913 1914 return 0; 1915 } 1916 1917 /* set of macros to handle unaligned little endian data in firmware image */ 1918 #define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1919 #define GETLE16(p) ((p)[0] | (p)[1] << 8) 1920 static int 1921 ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size) 1922 { 1923 u_char *p, *end; 1924 uint32_t dst; 1925 uint16_t len; 1926 int error; 1927 1928 p = fw; 1929 end = fw + size; 1930 while (p < end) { 1931 dst = GETLE32(p); p += 4; 1932 len = GETLE16(p); p += 2; 1933 1934 ipw_write_mem_1(sc, dst, p, len); 1935 p += len; 1936 } 1937 1938 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1939 IPW_IO_LED_OFF); 1940 1941 /* enable interrupts */ 1942 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1943 1944 /* kick the firmware */ 1945 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1946 1947 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1948 IPW_CTL_ALLOW_STANDBY); 1949 1950 /* wait at most one second for firmware initialization to complete */ 1951 if ((error = tsleep(sc, 0, "ipwinit", hz)) != 0) { 1952 aprint_error("%s: timeout waiting for firmware initialization " 1953 "to complete\n", sc->sc_dev.dv_xname); 1954 return error; 1955 } 1956 1957 CSR_WRITE_4(sc, IPW_CSR_IO, CSR_READ_4(sc, IPW_CSR_IO) | 1958 IPW_IO_GPIO1_MASK | IPW_IO_GPIO3_MASK); 1959 1960 return 0; 1961 } 1962 1963 /* 1964 * Store firmware into kernel memory so we can download it when we need to, 1965 * e.g when the adapter wakes up from suspend mode. 1966 */ 1967 static int 1968 ipw_cache_firmware(struct ipw_softc *sc) 1969 { 1970 struct ipw_firmware *fw = &sc->fw; 1971 struct ipw_firmware_hdr hdr; 1972 firmware_handle_t fwh; 1973 off_t fwsz, p; 1974 int error; 1975 1976 ipw_free_firmware(sc); 1977 1978 if ((error = firmware_open("if_ipw", sc->sc_fwname, &fwh)) != 0) 1979 goto fail0; 1980 1981 fwsz = firmware_get_size(fwh); 1982 1983 if (fwsz < sizeof(hdr)) 1984 goto fail2; 1985 1986 if ((error = firmware_read(fwh, 0, &hdr, sizeof(hdr))) != 0) 1987 goto fail2; 1988 1989 fw->main_size = le32toh(hdr.main_size); 1990 fw->ucode_size = le32toh(hdr.ucode_size); 1991 1992 fw->main = firmware_malloc(fw->main_size); 1993 if (fw->main == NULL) { 1994 error = ENOMEM; 1995 goto fail1; 1996 } 1997 1998 fw->ucode = firmware_malloc(fw->ucode_size); 1999 if (fw->ucode == NULL) { 2000 error = ENOMEM; 2001 goto fail2; 2002 } 2003 2004 p = sizeof(hdr); 2005 if ((error = firmware_read(fwh, p, fw->main, fw->main_size)) != 0) 2006 goto fail3; 2007 2008 if ((error = firmware_read(fwh, p, fw->main, fw->main_size)) != 0) 2009 goto fail3; 2010 2011 p += fw->main_size; 2012 if ((error = firmware_read(fwh, p, fw->ucode, fw->ucode_size)) != 0) 2013 goto fail3; 2014 2015 DPRINTF(("Firmware cached: main %u, ucode %u\n", fw->main_size, 2016 fw->ucode_size)); 2017 2018 sc->flags |= IPW_FLAG_FW_CACHED; 2019 2020 return 0; 2021 2022 fail3: firmware_free(fw->ucode, 0); 2023 fail2: firmware_free(fw->main, 0); 2024 fail1: firmware_close(fwh); 2025 fail0: 2026 return error; 2027 } 2028 2029 static void 2030 ipw_free_firmware(struct ipw_softc *sc) 2031 { 2032 if (!(sc->flags & IPW_FLAG_FW_CACHED)) 2033 return; 2034 2035 firmware_free(sc->fw.main, 0); 2036 firmware_free(sc->fw.ucode, 0); 2037 2038 sc->flags &= ~IPW_FLAG_FW_CACHED; 2039 } 2040 2041 static int 2042 ipw_config(struct ipw_softc *sc) 2043 { 2044 struct ieee80211com *ic = &sc->sc_ic; 2045 struct ifnet *ifp = &sc->sc_if; 2046 struct ipw_security security; 2047 struct ieee80211_key *k; 2048 struct ipw_wep_key wepkey; 2049 struct ipw_scan_options options; 2050 struct ipw_configuration config; 2051 uint32_t data; 2052 int error, i; 2053 2054 switch (ic->ic_opmode) { 2055 case IEEE80211_M_STA: 2056 case IEEE80211_M_HOSTAP: 2057 data = htole32(IPW_MODE_BSS); 2058 break; 2059 2060 case IEEE80211_M_IBSS: 2061 case IEEE80211_M_AHDEMO: 2062 data = htole32(IPW_MODE_IBSS); 2063 break; 2064 2065 case IEEE80211_M_MONITOR: 2066 data = htole32(IPW_MODE_MONITOR); 2067 break; 2068 } 2069 DPRINTF(("Setting mode to %u\n", le32toh(data))); 2070 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 2071 if (error != 0) 2072 return error; 2073 2074 if (ic->ic_opmode == IEEE80211_M_IBSS || 2075 ic->ic_opmode == IEEE80211_M_MONITOR) { 2076 data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); 2077 DPRINTF(("Setting channel to %u\n", le32toh(data))); 2078 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 2079 if (error != 0) 2080 return error; 2081 } 2082 2083 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2084 DPRINTF(("Enabling adapter\n")); 2085 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 2086 } 2087 2088 DPRINTF(("Setting MAC to %s\n", ether_sprintf(ic->ic_myaddr))); 2089 IEEE80211_ADDR_COPY(LLADDR(ifp->if_sadl), ic->ic_myaddr); 2090 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 2091 IEEE80211_ADDR_LEN); 2092 if (error != 0) 2093 return error; 2094 2095 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 2096 IPW_CFG_PREAMBLE_AUTO | IPW_CFG_802_1x_ENABLE); 2097 2098 if (ic->ic_opmode == IEEE80211_M_IBSS) 2099 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 2100 if (ifp->if_flags & IFF_PROMISC) 2101 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 2102 config.bss_chan = htole32(0x3fff); /* channels 1-14 */ 2103 config.ibss_chan = htole32(0x7ff); /* channels 1-11 */ 2104 DPRINTF(("Setting adapter configuration 0x%08x\n", config.flags)); 2105 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 2106 if (error != 0) 2107 return error; 2108 2109 data = htole32(0x3); /* 1, 2 */ 2110 DPRINTF(("Setting basic tx rates to 0x%x\n", le32toh(data))); 2111 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 2112 if (error != 0) 2113 return error; 2114 2115 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 2116 DPRINTF(("Setting tx rates to 0x%x\n", le32toh(data))); 2117 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 2118 if (error != 0) 2119 return error; 2120 2121 data = htole32(IPW_POWER_MODE_CAM); 2122 DPRINTF(("Setting power mode to %u\n", le32toh(data))); 2123 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 2124 if (error != 0) 2125 return error; 2126 2127 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2128 data = htole32(32); /* default value */ 2129 DPRINTF(("Setting tx power index to %u\n", le32toh(data))); 2130 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 2131 sizeof data); 2132 if (error != 0) 2133 return error; 2134 } 2135 2136 data = htole32(ic->ic_rtsthreshold); 2137 DPRINTF(("Setting RTS threshold to %u\n", le32toh(data))); 2138 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 2139 if (error != 0) 2140 return error; 2141 2142 data = htole32(ic->ic_fragthreshold); 2143 DPRINTF(("Setting frag threshold to %u\n", le32toh(data))); 2144 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 2145 if (error != 0) 2146 return error; 2147 2148 #ifdef IPW_DEBUG 2149 if (ipw_debug > 0) { 2150 printf("Setting ESSID to "); 2151 ieee80211_print_essid(ic->ic_des_essid, ic->ic_des_esslen); 2152 printf("\n"); 2153 } 2154 #endif 2155 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ic->ic_des_essid, 2156 ic->ic_des_esslen); 2157 if (error != 0) 2158 return error; 2159 2160 /* no mandatory BSSID */ 2161 DPRINTF(("Setting mandatory BSSID to null\n")); 2162 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 2163 if (error != 0) 2164 return error; 2165 2166 if (ic->ic_flags & IEEE80211_F_DESBSSID) { 2167 DPRINTF(("Setting desired BSSID to %s\n", 2168 ether_sprintf(ic->ic_des_bssid))); 2169 error = ipw_cmd(sc, IPW_CMD_SET_DESIRED_BSSID, 2170 ic->ic_des_bssid, IEEE80211_ADDR_LEN); 2171 if (error != 0) 2172 return error; 2173 } 2174 2175 (void)memset(&security, 0, sizeof(security)); 2176 security.authmode = (ic->ic_bss->ni_authmode == IEEE80211_AUTH_SHARED) ? 2177 IPW_AUTH_SHARED : IPW_AUTH_OPEN; 2178 security.ciphers = htole32(IPW_CIPHER_NONE); 2179 DPRINTF(("Setting authmode to %u\n", security.authmode)); 2180 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 2181 sizeof security); 2182 if (error != 0) 2183 return error; 2184 2185 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 2186 k = ic->ic_crypto.cs_nw_keys; 2187 for (i = 0; i < IEEE80211_WEP_NKID; i++, k++) { 2188 if (k->wk_keylen == 0) 2189 continue; 2190 2191 wepkey.idx = i; 2192 wepkey.len = k->wk_keylen; 2193 bzero(wepkey.key, sizeof wepkey.key); 2194 bcopy(k->wk_key, wepkey.key, k->wk_keylen); 2195 DPRINTF(("Setting wep key index %u len %u\n", 2196 wepkey.idx, wepkey.len)); 2197 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY, &wepkey, 2198 sizeof wepkey); 2199 if (error != 0) 2200 return error; 2201 } 2202 2203 data = htole32(ic->ic_crypto.cs_def_txkey); 2204 DPRINTF(("Setting tx key index to %u\n", le32toh(data))); 2205 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY_INDEX, &data, 2206 sizeof data); 2207 if (error != 0) 2208 return error; 2209 } 2210 2211 data = htole32((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) ? IPW_WEPON : 0); 2212 DPRINTF(("Setting wep flags to 0x%x\n", le32toh(data))); 2213 error = ipw_cmd(sc, IPW_CMD_SET_WEP_FLAGS, &data, sizeof data); 2214 if (error != 0) 2215 return error; 2216 2217 #if 0 2218 struct ipw_wpa_ie ie; 2219 2220 bzero(&ie, sizeof ie); 2221 ie.len = htole32(sizeof (struct ieee80211_ie_wpa)); 2222 DPRINTF(("Setting wpa ie\n")); 2223 error = ipw_cmd(sc, IPW_CMD_SET_WPA_IE, &ie, sizeof ie); 2224 if (error != 0) 2225 return error; 2226 #endif 2227 2228 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2229 data = htole32(ic->ic_bintval); 2230 DPRINTF(("Setting beacon interval to %u\n", le32toh(data))); 2231 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 2232 sizeof data); 2233 if (error != 0) 2234 return error; 2235 } 2236 2237 options.flags = 0; 2238 options.channels = htole32(0x3fff); /* scan channels 1-14 */ 2239 DPRINTF(("Setting scan options to 0x%x\n", le32toh(options.flags))); 2240 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &options, sizeof options); 2241 if (error != 0) 2242 return error; 2243 2244 /* finally, enable adapter (start scanning for an access point) */ 2245 DPRINTF(("Enabling adapter\n")); 2246 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 2247 } 2248 2249 static int 2250 ipw_init(struct ifnet *ifp) 2251 { 2252 struct ipw_softc *sc = ifp->if_softc; 2253 struct ipw_firmware *fw = &sc->fw; 2254 2255 if (!(sc->flags & IPW_FLAG_FW_CACHED)) { 2256 if (ipw_cache_firmware(sc) != 0) { 2257 aprint_error("%s: could not cache the firmware (%s)\n", 2258 sc->sc_dev.dv_xname, sc->sc_fwname); 2259 goto fail; 2260 } 2261 } 2262 2263 ipw_stop(ifp, 0); 2264 2265 if (ipw_reset(sc) != 0) { 2266 aprint_error("%s: could not reset adapter\n", 2267 sc->sc_dev.dv_xname); 2268 goto fail; 2269 } 2270 2271 if (ipw_load_ucode(sc, fw->ucode, fw->ucode_size) != 0) { 2272 aprint_error("%s: could not load microcode\n", 2273 sc->sc_dev.dv_xname); 2274 goto fail; 2275 } 2276 2277 ipw_stop_master(sc); 2278 2279 /* 2280 * Setup tx, rx and status rings. 2281 */ 2282 sc->txold = IPW_NTBD - 1; 2283 sc->txcur = 0; 2284 sc->txfree = IPW_NTBD - 2; 2285 sc->rxcur = IPW_NRBD - 1; 2286 2287 CSR_WRITE_4(sc, IPW_CSR_TX_BASE, sc->tbd_map->dm_segs[0].ds_addr); 2288 CSR_WRITE_4(sc, IPW_CSR_TX_SIZE, IPW_NTBD); 2289 CSR_WRITE_4(sc, IPW_CSR_TX_READ, 0); 2290 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 2291 2292 CSR_WRITE_4(sc, IPW_CSR_RX_BASE, sc->rbd_map->dm_segs[0].ds_addr); 2293 CSR_WRITE_4(sc, IPW_CSR_RX_SIZE, IPW_NRBD); 2294 CSR_WRITE_4(sc, IPW_CSR_RX_READ, 0); 2295 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 2296 2297 CSR_WRITE_4(sc, IPW_CSR_STATUS_BASE, sc->status_map->dm_segs[0].ds_addr); 2298 2299 if (ipw_load_firmware(sc, fw->main, fw->main_size) != 0) { 2300 aprint_error("%s: could not load firmware\n", 2301 sc->sc_dev.dv_xname); 2302 goto fail; 2303 } 2304 2305 sc->flags |= IPW_FLAG_FW_INITED; 2306 2307 /* retrieve information tables base addresses */ 2308 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 2309 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 2310 2311 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 2312 2313 if (ipw_config(sc) != 0) { 2314 aprint_error("%s: device configuration failed\n", 2315 sc->sc_dev.dv_xname); 2316 goto fail; 2317 } 2318 2319 ifp->if_flags &= ~IFF_OACTIVE; 2320 ifp->if_flags |= IFF_RUNNING; 2321 2322 return 0; 2323 2324 fail: ifp->if_flags &= ~IFF_UP; 2325 ipw_stop(ifp, 0); 2326 2327 return EIO; 2328 } 2329 2330 static void 2331 ipw_stop(struct ifnet *ifp, int disable) 2332 { 2333 struct ipw_softc *sc = ifp->if_softc; 2334 struct ieee80211com *ic = &sc->sc_ic; 2335 int i; 2336 2337 ipw_stop_master(sc); 2338 2339 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 2340 2341 /* 2342 * Release tx buffers. 2343 */ 2344 for (i = 0; i < IPW_NTBD; i++) 2345 ipw_release_sbd(sc, &sc->stbd_list[i]); 2346 2347 sc->sc_tx_timer = 0; 2348 ifp->if_timer = 0; 2349 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2350 2351 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2352 } 2353 2354 static void 2355 ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2356 bus_size_t count) 2357 { 2358 for (; count > 0; offset++, datap++, count--) { 2359 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2360 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 2361 } 2362 } 2363 2364 static void 2365 ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2366 bus_size_t count) 2367 { 2368 for (; count > 0; offset++, datap++, count--) { 2369 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2370 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 2371 } 2372 } 2373
Indexes created Tue Sep 30 20:09:53 GMT 2025