if_ipw.c revision 1.2.2.2
1 /* $NetBSD: if_ipw.c,v 1.2.2.2 2004/08/25 06:58:05 skrll Exp $ */ 2 /* Id: if_ipw.c,v 1.1.2.7 2004/08/20 11:20:11 damien Exp */ 3 4 /*- 5 * Copyright (c) 2004 6 * Damien Bergamini <damien.bergamini (at) free.fr>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: if_ipw.c,v 1.2.2.2 2004/08/25 06:58:05 skrll Exp $"); 33 34 /*- 35 * Intel(R) PRO/Wireless 2100 MiniPCI driver 36 * http://www.intel.com/products/mobiletechnology/prowireless.htm 37 */ 38 39 #include "bpfilter.h" 40 41 #include <sys/param.h> 42 #include <sys/sockio.h> 43 #include <sys/sysctl.h> 44 #include <sys/mbuf.h> 45 #include <sys/kernel.h> 46 #include <sys/socket.h> 47 #include <sys/systm.h> 48 #include <sys/malloc.h> 49 #include <sys/conf.h> 50 51 #include <machine/bus.h> 52 #include <machine/endian.h> 53 #include <machine/intr.h> 54 55 #include <dev/pci/pcireg.h> 56 #include <dev/pci/pcivar.h> 57 #include <dev/pci/pcidevs.h> 58 59 #if NBPFILTER > 0 60 #include <net/bpf.h> 61 #endif 62 #include <net/if.h> 63 #include <net/if_arp.h> 64 #include <net/if_dl.h> 65 #include <net/if_ether.h> 66 #include <net/if_media.h> 67 #include <net/if_types.h> 68 69 #include <net80211/ieee80211_var.h> 70 71 #include <netinet/in.h> 72 #include <netinet/in_systm.h> 73 #include <netinet/in_var.h> 74 #include <netinet/ip.h> 75 76 #include "if_ipwreg.h" 77 #include "if_ipwvar.h" 78 79 static int ipw_match(struct device *, struct cfdata *, void *); 80 static void ipw_attach(struct device *, struct device *, void *); 81 static int ipw_detach(struct device *, int); 82 static int ipw_media_change(struct ifnet *); 83 static int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 84 static void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 85 static void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 86 static void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 87 struct ipw_soft_bd *, struct ipw_soft_buf *); 88 static void ipw_notification_intr(struct ipw_softc *, struct ipw_soft_buf *); 89 static void ipw_rx_intr(struct ipw_softc *); 90 static void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 91 static void ipw_tx_intr(struct ipw_softc *); 92 static int ipw_intr(void *); 93 static int ipw_cmd(struct ipw_softc *, u_int32_t, void *, u_int32_t); 94 static int ipw_tx_start(struct ifnet *, struct mbuf *, struct ieee80211_node *); 95 static void ipw_start(struct ifnet *); 96 static void ipw_watchdog(struct ifnet *); 97 static int ipw_get_table1(struct ipw_softc *, u_int32_t *); 98 static int ipw_get_radio(struct ipw_softc *, int *); 99 static int ipw_ioctl(struct ifnet *, u_long, caddr_t); 100 static u_int32_t ipw_read_table1(struct ipw_softc *, u_int32_t); 101 static void ipw_write_table1(struct ipw_softc *, u_int32_t, u_int32_t); 102 static int ipw_read_table2(struct ipw_softc *, u_int32_t, void *, u_int32_t *); 103 static int ipw_tx_init(struct ipw_softc *); 104 static void ipw_tx_stop(struct ipw_softc *); 105 static int ipw_rx_init(struct ipw_softc *); 106 static void ipw_rx_stop(struct ipw_softc *); 107 static void ipw_reset(struct ipw_softc *); 108 static int ipw_clock_sync(struct ipw_softc *); 109 static int ipw_load_ucode(struct ipw_softc *, u_char *, int); 110 static int ipw_load_firmware(struct ipw_softc *, u_char *, int); 111 static int ipw_firmware_init(struct ipw_softc *, u_char *); 112 static int ipw_config(struct ipw_softc *); 113 static int ipw_init(struct ifnet *); 114 static void ipw_stop(struct ifnet *, int); 115 static void ipw_read_mem_1(struct ipw_softc *, bus_size_t, u_int8_t *, 116 bus_size_t); 117 static void ipw_write_mem_1(struct ipw_softc *, bus_size_t, u_int8_t *, 118 bus_size_t); 119 static void ipw_zero_mem_4(struct ipw_softc *, bus_size_t, bus_size_t); 120 121 static inline u_int8_t MEM_READ_1(struct ipw_softc *sc, u_int32_t addr) 122 { 123 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 124 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); 125 } 126 127 static inline u_int16_t MEM_READ_2(struct ipw_softc *sc, u_int32_t addr) 128 { 129 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 130 return CSR_READ_2(sc, IPW_CSR_INDIRECT_DATA); 131 } 132 133 static inline u_int32_t MEM_READ_4(struct ipw_softc *sc, u_int32_t addr) 134 { 135 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 136 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); 137 } 138 139 #ifdef IPW_DEBUG 140 #define DPRINTF(x) if (ipw_debug > 0) printf x 141 #define DPRINTFN(n, x) if (ipw_debug >= (n)) printf x 142 int ipw_debug = 0; 143 #else 144 #define DPRINTF(x) 145 #define DPRINTFN(n, x) 146 #endif 147 148 CFATTACH_DECL(ipw, sizeof (struct ipw_softc), ipw_match, ipw_attach, 149 ipw_detach, NULL); 150 151 static int 152 ipw_match(struct device *parent, struct cfdata *match, void *aux) 153 { 154 struct pci_attach_args *pa = aux; 155 156 if (PCI_VENDOR (pa->pa_id) == PCI_VENDOR_INTEL && 157 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_PRO_WL_2100) 158 return 1; 159 160 return 0; 161 } 162 163 /* Base Address Register */ 164 #define IPW_PCI_BAR0 0x10 165 166 static void 167 ipw_attach(struct device *parent, struct device *self, void *aux) 168 { 169 struct ipw_softc *sc = (struct ipw_softc *)self; 170 struct ieee80211com *ic = &sc->sc_ic; 171 struct ifnet *ifp = &ic->ic_if; 172 struct ieee80211_rateset *rs; 173 struct pci_attach_args *pa = aux; 174 const char *intrstr; 175 char devinfo[256]; 176 bus_space_tag_t memt; 177 bus_space_handle_t memh; 178 bus_addr_t base; 179 pci_intr_handle_t ih; 180 u_int32_t data; 181 int i, revision, error; 182 183 sc->sc_pct = pa->pa_pc; 184 185 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof devinfo); 186 revision = PCI_REVISION(pa->pa_class); 187 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, revision); 188 189 /* enable bus-mastering */ 190 data = pci_conf_read(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG); 191 data |= PCI_COMMAND_MASTER_ENABLE; 192 pci_conf_write(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG, data); 193 194 /* map the register window */ 195 error = pci_mapreg_map(pa, IPW_PCI_BAR0, PCI_MAPREG_TYPE_MEM | 196 PCI_MAPREG_MEM_TYPE_32BIT, 0, &memt, &memh, &base, &sc->sc_sz); 197 if (error != 0) { 198 aprint_error("%s: could not map memory space\n", 199 sc->sc_dev.dv_xname); 200 return; 201 } 202 203 sc->sc_st = memt; 204 sc->sc_sh = memh; 205 sc->sc_dmat = pa->pa_dmat; 206 207 /* disable interrupts */ 208 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 209 210 if (pci_intr_map(pa, &ih) != 0) { 211 aprint_error("%s: could not map interrupt\n", 212 sc->sc_dev.dv_xname); 213 return; 214 } 215 216 intrstr = pci_intr_string(sc->sc_pct, ih); 217 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, ipw_intr, sc); 218 if (sc->sc_ih == NULL) { 219 aprint_error("%s: could not establish interrupt", 220 sc->sc_dev.dv_xname); 221 if (intrstr != NULL) 222 aprint_error(" at %s", intrstr); 223 aprint_error("\n"); 224 return; 225 } 226 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 227 228 ic->ic_phytype = IEEE80211_T_DS; 229 ic->ic_opmode = IEEE80211_M_STA; 230 ic->ic_state = IEEE80211_S_INIT; 231 232 /* set device capabilities */ 233 ic->ic_caps = IEEE80211_C_IBSS | IEEE80211_C_MONITOR | 234 IEEE80211_C_PMGT | IEEE80211_C_TXPMGT | IEEE80211_C_WEP; 235 236 /* set supported 11.b rates */ 237 rs = &ic->ic_sup_rates[IEEE80211_MODE_11B]; 238 rs->rs_nrates = 4; 239 rs->rs_rates[0] = 2; /* 1Mbps */ 240 rs->rs_rates[1] = 4; /* 2Mbps */ 241 rs->rs_rates[2] = 11; /* 5.5Mbps */ 242 rs->rs_rates[3] = 22; /* 11Mbps */ 243 244 /* set supported 11.b channels (1 through 14) */ 245 for (i = 1; i <= 14; i++) { 246 ic->ic_channels[i].ic_freq = 247 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 248 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 249 } 250 251 ic->ic_ibss_chan = &ic->ic_channels[0]; 252 253 ifp->if_softc = sc; 254 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 255 ifp->if_init = ipw_init; 256 ifp->if_stop = ipw_stop; 257 ifp->if_ioctl = ipw_ioctl; 258 ifp->if_start = ipw_start; 259 ifp->if_watchdog = ipw_watchdog; 260 IFQ_SET_READY(&ifp->if_snd); 261 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 262 263 if_attach(ifp); 264 ieee80211_ifattach(ifp); 265 /* override state transition machine */ 266 sc->sc_newstate = ic->ic_newstate; 267 ic->ic_newstate = ipw_newstate; 268 269 ieee80211_media_init(ifp, ipw_media_change, ieee80211_media_status); 270 } 271 272 static int 273 ipw_detach(struct device* self, int flags) 274 { 275 struct ipw_softc *sc = (struct ipw_softc *)self; 276 struct ifnet *ifp = &sc->sc_ic.ic_if; 277 278 ipw_reset(sc); 279 280 ieee80211_ifdetach(ifp); 281 if_detach(ifp); 282 283 if (sc->sc_ih != NULL) { 284 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 285 sc->sc_ih = NULL; 286 } 287 288 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 289 290 return 0; 291 } 292 293 static int 294 ipw_media_change(struct ifnet *ifp) 295 { 296 int error; 297 298 error = ieee80211_media_change(ifp); 299 if (error != ENETRESET) 300 return error; 301 302 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 303 ipw_init(ifp); 304 305 return 0; 306 } 307 308 static int 309 ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 310 { 311 struct ifnet *ifp = &ic->ic_if; 312 struct ipw_softc *sc = ifp->if_softc; 313 struct ieee80211_node *ni = ic->ic_bss; 314 u_int32_t val, len; 315 316 switch (nstate) { 317 case IEEE80211_S_INIT: 318 break; 319 320 case IEEE80211_S_RUN: 321 len = IEEE80211_NWID_LEN; 322 ipw_read_table2(sc, IPW_INFO_CURRENT_SSID, ni->ni_essid, &len); 323 ni->ni_esslen = len; 324 325 val = ipw_read_table1(sc, IPW_INFO_CURRENT_CHANNEL); 326 ni->ni_chan = &ic->ic_channels[val]; 327 328 DELAY(100); /* firmware needs a short delay here */ 329 330 len = IEEE80211_ADDR_LEN; 331 ipw_read_table2(sc, IPW_INFO_CURRENT_BSSID, ni->ni_bssid, &len); 332 break; 333 334 case IEEE80211_S_SCAN: 335 case IEEE80211_S_AUTH: 336 case IEEE80211_S_ASSOC: 337 break; 338 } 339 340 ic->ic_state = nstate; 341 return 0; 342 } 343 344 static void 345 ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 346 { 347 struct ipw_cmd *cmd; 348 349 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof (struct ipw_cmd), 350 BUS_DMASYNC_POSTREAD); 351 352 cmd = mtod(sbuf->m, struct ipw_cmd *); 353 354 DPRINTFN(2, ("RX!CMD!%u!%u!%u!%u!%u\n", 355 le32toh(cmd->type), le32toh(cmd->subtype), le32toh(cmd->seq), 356 le32toh(cmd->len), le32toh(cmd->status))); 357 358 /* 359 * Wake up processes waiting for command ack. In the case of the 360 * IPW_CMD_DISABLE command, wake up the process only when the adapter 361 * enters the IPW_STATE_DISABLED state. This is notified in 362 * ipw_newstate_intr(). 363 */ 364 if (le32toh(cmd->type) != IPW_CMD_DISABLE) 365 wakeup(sc->cmd); 366 } 367 368 static void 369 ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 370 { 371 struct ieee80211com *ic = &sc->sc_ic; 372 u_int32_t state; 373 374 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof state, 375 BUS_DMASYNC_POSTREAD); 376 377 state = le32toh(*mtod(sbuf->m, u_int32_t *)); 378 379 DPRINTFN(2, ("RX!NEWSTATE!%u\n", state)); 380 381 switch (state) { 382 case IPW_STATE_ASSOCIATED: 383 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 384 break; 385 386 case IPW_STATE_SCANNING: 387 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 388 break; 389 390 case IPW_STATE_ASSOCIATION_LOST: 391 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 392 break; 393 394 case IPW_STATE_DISABLED: 395 wakeup(sc->cmd); 396 break; 397 398 case IPW_STATE_RADIO_DISABLED: 399 /* XXX should turn the interface down */ 400 break; 401 } 402 } 403 404 static void 405 ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 406 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 407 { 408 struct ieee80211com *ic = &sc->sc_ic; 409 struct ifnet *ifp = &ic->ic_if; 410 struct mbuf *m; 411 struct ieee80211_frame *wh; 412 struct ieee80211_node *ni; 413 int error; 414 415 DPRINTFN(5, ("RX!DATA!%u!%u\n", le32toh(status->len), status->rssi)); 416 417 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, le32toh(status->len), 418 BUS_DMASYNC_POSTREAD); 419 420 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 421 422 /* Finalize mbuf */ 423 m = sbuf->m; 424 m->m_pkthdr.rcvif = ifp; 425 m->m_pkthdr.len = m->m_len = le32toh(status->len); 426 427 wh = mtod(m, struct ieee80211_frame *); 428 429 if (ic->ic_opmode != IEEE80211_M_STA) { 430 ni = ieee80211_find_node(ic, wh->i_addr2); 431 if (ni == NULL) 432 ni = ieee80211_ref_node(ic->ic_bss); 433 } else 434 ni = ieee80211_ref_node(ic->ic_bss); 435 436 /* Send it up to the upper layer */ 437 ieee80211_input(ifp, m, ni, status->rssi, 0/*rstamp*/); 438 439 ieee80211_release_node(ic, ni); 440 441 MGETHDR(m, M_DONTWAIT, MT_DATA); 442 if (m == NULL) { 443 aprint_error("%s: could not allocate rx mbuf\n", 444 sc->sc_dev.dv_xname); 445 return; 446 } 447 MCLGET(m, M_DONTWAIT); 448 if (!(m->m_flags & M_EXT)) { 449 m_freem(m); 450 aprint_error("%s: could not allocate rx mbuf cluster\n", 451 sc->sc_dev.dv_xname); 452 return; 453 } 454 455 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, mtod(m, void *), 456 MCLBYTES, NULL, BUS_DMA_NOWAIT); 457 if (error != 0) { 458 aprint_error("%s: could not map rxbuf dma memory\n", 459 sc->sc_dev.dv_xname); 460 m_freem(m); 461 return; 462 } 463 464 sbuf->m = m; 465 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 466 } 467 468 static void 469 ipw_notification_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 470 { 471 DPRINTFN(2, ("RX!NOTIFICATION\n")); 472 } 473 474 static void 475 ipw_rx_intr(struct ipw_softc *sc) 476 { 477 struct ipw_status *status; 478 struct ipw_soft_bd *sbd; 479 struct ipw_soft_buf *sbuf; 480 u_int32_t r, i; 481 482 r = CSR_READ_4(sc, IPW_CSR_RX_READ_INDEX); 483 484 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 485 486 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 487 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 488 BUS_DMASYNC_POSTREAD); 489 490 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 491 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 492 BUS_DMASYNC_POSTREAD); 493 494 status = &sc->status_list[i]; 495 sbd = &sc->srbd_list[i]; 496 sbuf = sbd->priv; 497 498 switch (le16toh(status->code) & 0xf) { 499 case IPW_STATUS_CODE_COMMAND: 500 ipw_command_intr(sc, sbuf); 501 break; 502 503 case IPW_STATUS_CODE_NEWSTATE: 504 ipw_newstate_intr(sc, sbuf); 505 break; 506 507 case IPW_STATUS_CODE_DATA_802_3: 508 case IPW_STATUS_CODE_DATA_802_11: 509 ipw_data_intr(sc, status, sbd, sbuf); 510 break; 511 512 case IPW_STATUS_CODE_NOTIFICATION: 513 ipw_notification_intr(sc, sbuf); 514 break; 515 516 default: 517 aprint_debug("%s: unknown status code %u\n", 518 sc->sc_dev.dv_xname, le16toh(status->code)); 519 } 520 sbd->bd->flags = 0; 521 522 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 523 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 524 BUS_DMASYNC_PREWRITE); 525 } 526 527 /* Tell the firmware what we have processed */ 528 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 529 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE_INDEX, sc->rxcur); 530 } 531 532 static void 533 ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 534 { 535 struct ieee80211com *ic; 536 struct ipw_soft_hdr *shdr; 537 struct ipw_soft_buf *sbuf; 538 539 switch (sbd->type) { 540 case IPW_SBD_TYPE_COMMAND: 541 bus_dmamap_unload(sc->sc_dmat, sc->cmd_map); 542 break; 543 544 case IPW_SBD_TYPE_HEADER: 545 shdr = sbd->priv; 546 bus_dmamap_unload(sc->sc_dmat, shdr->map); 547 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 548 break; 549 550 case IPW_SBD_TYPE_DATA: 551 ic = &sc->sc_ic; 552 sbuf = sbd->priv; 553 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 554 m_freem(sbuf->m); 555 if (sbuf->ni != NULL) 556 ieee80211_release_node(ic, sbuf->ni); 557 /* kill watchdog timer */ 558 sc->sc_tx_timer = 0; 559 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 560 break; 561 } 562 sbd->type = IPW_SBD_TYPE_NOASSOC; 563 } 564 565 static void 566 ipw_tx_intr(struct ipw_softc *sc) 567 { 568 struct ifnet *ifp = &sc->sc_ic.ic_if; 569 u_int32_t r, i; 570 571 r = CSR_READ_4(sc, IPW_CSR_TX_READ_INDEX); 572 573 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) 574 ipw_release_sbd(sc, &sc->stbd_list[i]); 575 576 /* Remember what the firmware has processed */ 577 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 578 579 /* Call start() since some buffer descriptors have been released */ 580 ifp->if_flags &= ~IFF_OACTIVE; 581 (*ifp->if_start)(ifp); 582 } 583 584 static int 585 ipw_intr(void *arg) 586 { 587 struct ipw_softc *sc = arg; 588 u_int32_t r; 589 590 if ((r = CSR_READ_4(sc, IPW_CSR_INTR)) == 0) 591 return 0; 592 593 /* Disable interrupts */ 594 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 595 596 DPRINTFN(8, ("INTR!0x%08x\n", r)); 597 598 if (r & IPW_INTR_RX_TRANSFER) 599 ipw_rx_intr(sc); 600 601 if (r & IPW_INTR_TX_TRANSFER) 602 ipw_tx_intr(sc); 603 604 if (r & IPW_INTR_FW_INIT_DONE) { 605 if (!(r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR))) 606 wakeup(sc); 607 } 608 609 /* Acknowledge interrupts */ 610 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 611 612 /* Re-enable interrupts */ 613 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 614 615 return 0; 616 } 617 618 static int 619 ipw_cmd(struct ipw_softc *sc, u_int32_t type, void *data, u_int32_t len) 620 { 621 struct ipw_soft_bd *sbd; 622 int error; 623 624 sbd = &sc->stbd_list[sc->txcur]; 625 626 error = bus_dmamap_load(sc->sc_dmat, sc->cmd_map, sc->cmd, 627 sizeof (struct ipw_cmd), NULL, BUS_DMA_NOWAIT); 628 if (error != 0) { 629 aprint_error("%s: could not map cmd dma memory\n", 630 sc->sc_dev.dv_xname); 631 return error; 632 } 633 634 sc->cmd->type = htole32(type); 635 sc->cmd->subtype = htole32(0); 636 sc->cmd->len = htole32(len); 637 sc->cmd->seq = htole32(0); 638 if (data != NULL) 639 bcopy(data, sc->cmd->data, len); 640 641 sbd->type = IPW_SBD_TYPE_COMMAND; 642 sbd->bd->physaddr = htole32(sc->cmd_map->dm_segs[0].ds_addr); 643 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 644 sbd->bd->nfrag = 1; 645 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 646 IPW_BD_FLAG_TX_LAST_FRAGMENT; 647 648 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 0, sizeof (struct ipw_cmd), 649 BUS_DMASYNC_PREWRITE); 650 651 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 652 sc->txcur * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 653 BUS_DMASYNC_PREWRITE); 654 655 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 656 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, sc->txcur); 657 658 DPRINTFN(2, ("TX!CMD!%u!%u!%u!%u\n", type, 0, 0, len)); 659 660 /* Wait at most two seconds for command to complete */ 661 return tsleep(sc->cmd, 0, "ipwcmd", 2 * hz); 662 } 663 664 static int 665 ipw_tx_start(struct ifnet *ifp, struct mbuf *m, struct ieee80211_node *ni) 666 { 667 struct ipw_softc *sc = ifp->if_softc; 668 struct ieee80211com *ic = &sc->sc_ic; 669 struct ieee80211_frame *wh; 670 struct ipw_soft_bd *sbd; 671 struct ipw_soft_hdr *shdr; 672 struct ipw_soft_buf *sbuf; 673 int error, i; 674 675 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 676 m = ieee80211_wep_crypt(ifp, m, 1); 677 if (m == NULL) 678 return ENOBUFS; 679 } 680 681 wh = mtod(m, struct ieee80211_frame *); 682 683 shdr = TAILQ_FIRST(&sc->sc_free_shdr); 684 sbuf = TAILQ_FIRST(&sc->sc_free_sbuf); 685 686 shdr->hdr.type = htole32(IPW_HDR_TYPE_SEND); 687 shdr->hdr.subtype = htole32(0); 688 shdr->hdr.encrypted = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0; 689 shdr->hdr.encrypt = 0; 690 shdr->hdr.keyidx = 0; 691 shdr->hdr.keysz = 0; 692 shdr->hdr.fragmentsz = htole16(0); 693 IEEE80211_ADDR_COPY(shdr->hdr.src_addr, wh->i_addr2); 694 if (ic->ic_opmode == IEEE80211_M_STA) 695 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr3); 696 else 697 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr1); 698 699 /* trim IEEE802.11 header */ 700 m_adj(m, sizeof (struct ieee80211_frame)); 701 702 /* 703 * We need to map the mbuf first to know how many buffer descriptors 704 * are needed for this transfer. 705 */ 706 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m, BUS_DMA_NOWAIT); 707 if (error != 0) { 708 aprint_error("%s: could not map mbuf (error %d)\n", 709 sc->sc_dev.dv_xname, error); 710 m_freem(m); 711 return error; 712 } 713 714 error = bus_dmamap_load(sc->sc_dmat, shdr->map, &shdr->hdr, 715 sizeof (struct ipw_hdr), NULL, BUS_DMA_NOWAIT); 716 if (error != 0) { 717 aprint_error("%s: could not map hdr (error %d)\n", 718 sc->sc_dev.dv_xname, error); 719 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 720 m_freem(m); 721 return error; 722 } 723 724 TAILQ_REMOVE(&sc->sc_free_sbuf, sbuf, next); 725 TAILQ_REMOVE(&sc->sc_free_shdr, shdr, next); 726 727 sbd = &sc->stbd_list[sc->txcur]; 728 sbd->type = IPW_SBD_TYPE_HEADER; 729 sbd->priv = shdr; 730 sbd->bd->physaddr = htole32(shdr->map->dm_segs[0].ds_addr); 731 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 732 sbd->bd->nfrag = 1 + sbuf->map->dm_nsegs; 733 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 734 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 735 736 DPRINTFN(5, ("TX!HDR!%u!%u!%u!%u\n", shdr->hdr.type, shdr->hdr.subtype, 737 shdr->hdr.encrypted, shdr->hdr.encrypt)); 738 DPRINTFN(5, ("!%s", ether_sprintf(shdr->hdr.src_addr))); 739 DPRINTFN(5, ("!%s\n", ether_sprintf(shdr->hdr.dst_addr))); 740 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 741 742 sbuf->m = m; 743 sbuf->ni = ni; 744 745 for (i = 0; i < sbuf->map->dm_nsegs; i++) { 746 sbd = &sc->stbd_list[sc->txcur]; 747 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[i].ds_addr); 748 sbd->bd->len = htole32(sbuf->map->dm_segs[i].ds_len); 749 sbd->bd->nfrag = 0; /* used only in first bd */ 750 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 751 if (i == sbuf->map->dm_nsegs - 1) { 752 sbd->type = IPW_SBD_TYPE_DATA; 753 sbd->priv = sbuf; 754 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 755 } else { 756 sbd->type = IPW_SBD_TYPE_NOASSOC; 757 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 758 } 759 760 DPRINTFN(5, ("TX!FRAG!%d!%ld\n", i, 761 sbuf->map->dm_segs[i].ds_len)); 762 763 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 764 sc->txcur * sizeof (struct ipw_bd), 765 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 766 767 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 768 } 769 770 bus_dmamap_sync(sc->sc_dmat, shdr->map, 0, sizeof (struct ipw_hdr), 771 BUS_DMASYNC_PREWRITE); 772 773 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, MCLBYTES, 774 BUS_DMASYNC_PREWRITE); 775 776 /* Inform firmware about this new packet */ 777 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, sc->txcur); 778 779 return 0; 780 } 781 782 static void 783 ipw_start(struct ifnet *ifp) 784 { 785 struct ipw_softc *sc = ifp->if_softc; 786 struct ieee80211com *ic = &sc->sc_ic; 787 struct mbuf *m; 788 struct ieee80211_node *ni; 789 790 for (;;) { 791 IF_DEQUEUE(&ifp->if_snd, m); 792 if (m == NULL) 793 break; 794 795 #if NBPFILTER > 0 796 if (ifp->if_bpf != NULL) 797 bpf_mtap(ifp->if_bpf, m); 798 #endif 799 800 m = ieee80211_encap(ifp, m, &ni); 801 if (m == NULL) 802 continue; 803 804 #if NBPFILTER > 0 805 if (ic->ic_rawbpf != NULL) 806 bpf_mtap(ic->ic_rawbpf, m); 807 #endif 808 809 if (ipw_tx_start(ifp, m, ni) != 0) { 810 if (ni != NULL) 811 ieee80211_release_node(ic, ni); 812 break; 813 } 814 815 /* start watchdog timer */ 816 sc->sc_tx_timer = 5; 817 ifp->if_timer = 1; 818 } 819 } 820 821 static void 822 ipw_watchdog(struct ifnet *ifp) 823 { 824 struct ipw_softc *sc = ifp->if_softc; 825 826 ifp->if_timer = 0; 827 828 if (sc->sc_tx_timer > 0) { 829 if (--sc->sc_tx_timer == 0) { 830 aprint_error("%s: device timeout\n", 831 sc->sc_dev.dv_xname); 832 #ifdef notyet 833 ipw_init(ifp); 834 #endif 835 return; 836 } 837 ifp->if_timer = 1; 838 } 839 840 ieee80211_watchdog(ifp); 841 } 842 843 static int 844 ipw_get_table1(struct ipw_softc *sc, u_int32_t *tbl) 845 { 846 u_int32_t addr, size, i; 847 848 if (!(sc->flags & IPW_FLAG_FW_INITED)) 849 return ENOTTY; 850 851 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, sc->table1_base); 852 853 size = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 854 if (suword(tbl, size) != 0) 855 return EFAULT; 856 857 for (i = 1, ++tbl; i < size; i++, tbl++) { 858 addr = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 859 if (suword(tbl, MEM_READ_4(sc, addr)) != 0) 860 return EFAULT; 861 } 862 return 0; 863 } 864 865 static int 866 ipw_get_radio(struct ipw_softc *sc, int *ret) 867 { 868 u_int32_t addr; 869 870 if (!(sc->flags & IPW_FLAG_FW_INITED)) 871 return ENOTTY; 872 873 addr = ipw_read_table1(sc, IPW_INFO_EEPROM_ADDRESS); 874 if ((MEM_READ_4(sc, addr + 32) >> 24) & 1) { 875 suword(ret, -1); 876 return 0; 877 } 878 879 if (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED) 880 suword(ret, 0); 881 else 882 suword(ret, 1); 883 884 return 0; 885 } 886 887 static int 888 ipw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 889 { 890 struct ipw_softc *sc = ifp->if_softc; 891 struct ifreq *ifr; 892 int s, error = 0; 893 894 s = splnet(); 895 896 switch (cmd) { 897 case SIOCSIFFLAGS: 898 if (ifp->if_flags & IFF_UP) { 899 if (!(ifp->if_flags & IFF_RUNNING)) 900 ipw_init(ifp); 901 } else { 902 if (ifp->if_flags & IFF_RUNNING) 903 ipw_stop(ifp, 1); 904 } 905 break; 906 907 case SIOCGTABLE1: 908 ifr = (struct ifreq *)data; 909 error = ipw_get_table1(sc, (u_int32_t *)ifr->ifr_data); 910 break; 911 912 case SIOCGRADIO: 913 ifr = (struct ifreq *)data; 914 error = ipw_get_radio(sc, (int *)ifr->ifr_data); 915 break; 916 917 case SIOCSLOADFW: 918 /* only super-user can do that! */ 919 if ((error = suser(curproc->p_ucred, &curproc->p_acflag)) != 0) 920 break; 921 922 ifr = (struct ifreq *)data; 923 error = ipw_firmware_init(sc, (u_char *)ifr->ifr_data); 924 break; 925 926 case SIOCSKILLFW: 927 /* only super-user can do that! */ 928 if ((error = suser(curproc->p_ucred, &curproc->p_acflag)) != 0) 929 break; 930 931 ipw_reset(sc); 932 break; 933 934 default: 935 error = ieee80211_ioctl(ifp, cmd, data); 936 if (error != ENETRESET) 937 break; 938 939 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 940 (IFF_UP | IFF_RUNNING)) 941 ipw_init(ifp); 942 error = 0; 943 } 944 945 splx(s); 946 return error; 947 } 948 949 static u_int32_t 950 ipw_read_table1(struct ipw_softc *sc, u_int32_t off) 951 { 952 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 953 } 954 955 static void 956 ipw_write_table1(struct ipw_softc *sc, u_int32_t off, u_int32_t info) 957 { 958 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 959 } 960 961 static int 962 ipw_read_table2(struct ipw_softc *sc, u_int32_t off, void *buf, u_int32_t *len) 963 { 964 u_int32_t addr, info; 965 u_int16_t count, size; 966 u_int32_t total; 967 968 /* addr[4] + count[2] + size[2] */ 969 addr = MEM_READ_4(sc, sc->table2_base + off); 970 info = MEM_READ_4(sc, sc->table2_base + off + 4); 971 972 count = info >> 16; 973 size = info & 0xffff; 974 total = count * size; 975 976 if (total > *len) { 977 *len = total; 978 return EINVAL; 979 } 980 981 *len = total; 982 ipw_read_mem_1(sc, addr, buf, total); 983 984 return 0; 985 } 986 987 static int 988 ipw_tx_init(struct ipw_softc *sc) 989 { 990 char *errmsg; 991 struct ipw_bd *bd; 992 struct ipw_soft_bd *sbd; 993 struct ipw_soft_hdr *shdr; 994 struct ipw_soft_buf *sbuf; 995 int error, i, nsegs; 996 997 /* Allocate transmission buffer descriptors */ 998 error = bus_dmamap_create(sc->sc_dmat, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, 999 BUS_DMA_NOWAIT, &sc->tbd_map); 1000 if (error != 0) { 1001 errmsg = "could not create tbd dma map"; 1002 goto fail; 1003 } 1004 1005 error = bus_dmamem_alloc(sc->sc_dmat, IPW_TBD_SZ, PAGE_SIZE, 0, 1006 &sc->tbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 1007 if (error != 0) { 1008 errmsg = "could not allocate tbd dma memory"; 1009 goto fail; 1010 } 1011 1012 error = bus_dmamem_map(sc->sc_dmat, &sc->tbd_seg, nsegs, IPW_TBD_SZ, 1013 (caddr_t *)&sc->tbd_list, BUS_DMA_NOWAIT); 1014 if (error != 0) { 1015 errmsg = "could not map tbd dma memory"; 1016 goto fail; 1017 } 1018 1019 error = bus_dmamap_load(sc->sc_dmat, sc->tbd_map, sc->tbd_list, 1020 IPW_TBD_SZ, NULL, BUS_DMA_NOWAIT); 1021 if (error != 0) { 1022 errmsg = "could not load tbd dma memory"; 1023 goto fail; 1024 } 1025 1026 sc->stbd_list = malloc(IPW_NTBD * sizeof (struct ipw_soft_bd), 1027 M_DEVBUF, M_NOWAIT); 1028 if (sc->stbd_list == NULL) { 1029 errmsg = "could not allocate soft tbd"; 1030 error = ENOMEM; 1031 goto fail; 1032 } 1033 sbd = sc->stbd_list; 1034 bd = sc->tbd_list; 1035 for (i = 0; i < IPW_NTBD; i++, sbd++, bd++) { 1036 sbd->type = IPW_SBD_TYPE_NOASSOC; 1037 sbd->bd = bd; 1038 } 1039 1040 CSR_WRITE_4(sc, IPW_CSR_TX_BD_BASE, sc->tbd_map->dm_segs[0].ds_addr); 1041 CSR_WRITE_4(sc, IPW_CSR_TX_BD_SIZE, IPW_NTBD); 1042 CSR_WRITE_4(sc, IPW_CSR_TX_READ_INDEX, 0); 1043 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, 0); 1044 sc->txold = IPW_NTBD - 1; /* latest bd index ack'ed by firmware */ 1045 sc->txcur = 0; /* bd index to write to */ 1046 1047 /* Allocate a DMA-able command */ 1048 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_cmd), 1, 1049 sizeof (struct ipw_cmd), 0, BUS_DMA_NOWAIT, &sc->cmd_map); 1050 if (error != 0) { 1051 errmsg = "could not create cmd dma map"; 1052 goto fail; 1053 } 1054 1055 error = bus_dmamem_alloc(sc->sc_dmat, sizeof (struct ipw_cmd), 1056 PAGE_SIZE, 0, &sc->cmd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 1057 if (error != 0) { 1058 errmsg = "could not allocate cmd dma memory"; 1059 goto fail; 1060 } 1061 1062 error = bus_dmamem_map(sc->sc_dmat, &sc->cmd_seg, nsegs, 1063 sizeof (struct ipw_cmd), (caddr_t *)&sc->cmd, BUS_DMA_NOWAIT); 1064 if (error != 0) { 1065 errmsg = "could not map cmd dma memory"; 1066 goto fail; 1067 } 1068 1069 /* Allocate a pool of DMA-able headers */ 1070 sc->shdr_list = malloc(IPW_NDATA * sizeof (struct ipw_soft_hdr), 1071 M_DEVBUF, M_NOWAIT); 1072 if (sc->shdr_list == NULL) { 1073 errmsg = "could not allocate soft hdr"; 1074 error = ENOMEM; 1075 goto fail; 1076 } 1077 TAILQ_INIT(&sc->sc_free_shdr); 1078 for (i = 0, shdr = sc->shdr_list; i < IPW_NDATA; i++, shdr++) { 1079 error = bus_dmamap_create(sc->sc_dmat, 1080 sizeof (struct ipw_soft_hdr), 1, 1081 sizeof (struct ipw_soft_hdr), 0, BUS_DMA_NOWAIT, 1082 &shdr->map); 1083 if (error != 0) { 1084 errmsg = "could not create hdr dma map"; 1085 goto fail; 1086 } 1087 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 1088 } 1089 1090 /* Allocate a pool of DMA-able buffers */ 1091 sc->tx_sbuf_list = malloc(IPW_NDATA * sizeof (struct ipw_soft_buf), 1092 M_DEVBUF, M_NOWAIT); 1093 if (sc->tx_sbuf_list == NULL) { 1094 errmsg = "could not allocate soft txbuf"; 1095 error = ENOMEM; 1096 goto fail; 1097 } 1098 TAILQ_INIT(&sc->sc_free_sbuf); 1099 for (i = 0, sbuf = sc->tx_sbuf_list; i < IPW_NDATA; i++, sbuf++) { 1100 error = bus_dmamap_create(sc->sc_dmat, IPW_NDATA * MCLBYTES, 1101 IPW_NDATA, MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 1102 if (error != 0) { 1103 errmsg = "could not create txbuf dma map"; 1104 goto fail; 1105 } 1106 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 1107 } 1108 1109 return 0; 1110 1111 fail: aprint_error("%s: %s\n", sc->sc_dev.dv_xname, errmsg); 1112 ipw_tx_stop(sc); 1113 1114 return error; 1115 } 1116 1117 static void 1118 ipw_tx_stop(struct ipw_softc *sc) 1119 { 1120 struct ipw_soft_hdr *shdr; 1121 struct ipw_soft_buf *sbuf; 1122 int i; 1123 1124 if (sc->tbd_map != NULL) { 1125 if (sc->tbd_list != NULL) { 1126 bus_dmamap_unload(sc->sc_dmat, sc->tbd_map); 1127 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->tbd_list, 1128 IPW_TBD_SZ); 1129 bus_dmamem_free(sc->sc_dmat, &sc->tbd_seg, 1); 1130 sc->tbd_list = NULL; 1131 } 1132 bus_dmamap_destroy(sc->sc_dmat, sc->tbd_map); 1133 sc->tbd_map = NULL; 1134 } 1135 1136 if (sc->stbd_list != NULL) { 1137 for (i = 0; i < IPW_NTBD; i++) 1138 ipw_release_sbd(sc, &sc->stbd_list[i]); 1139 free(sc->stbd_list, M_DEVBUF); 1140 sc->stbd_list = NULL; 1141 } 1142 1143 if (sc->cmd_map != NULL) { 1144 if (sc->cmd != NULL) { 1145 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->cmd, 1146 sizeof (struct ipw_cmd)); 1147 bus_dmamem_free(sc->sc_dmat, &sc->cmd_seg, 1); 1148 sc->cmd = NULL; 1149 } 1150 bus_dmamap_destroy(sc->sc_dmat, sc->cmd_map); 1151 sc->cmd_map = NULL; 1152 } 1153 1154 if (sc->shdr_list != NULL) { 1155 TAILQ_FOREACH(shdr, &sc->sc_free_shdr, next) 1156 bus_dmamap_destroy(sc->sc_dmat, shdr->map); 1157 free(sc->shdr_list, M_DEVBUF); 1158 sc->shdr_list = NULL; 1159 } 1160 1161 1162 if (sc->tx_sbuf_list != NULL) { 1163 TAILQ_FOREACH(sbuf, &sc->sc_free_sbuf, next) 1164 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 1165 free(sc->tx_sbuf_list, M_DEVBUF); 1166 sc->tx_sbuf_list = NULL; 1167 } 1168 } 1169 1170 static int 1171 ipw_rx_init(struct ipw_softc *sc) 1172 { 1173 char *errmsg; 1174 struct ipw_bd *bd; 1175 struct ipw_soft_bd *sbd; 1176 struct ipw_soft_buf *sbuf; 1177 int error, i, nsegs; 1178 1179 /* Allocate reception buffer descriptors */ 1180 error = bus_dmamap_create(sc->sc_dmat, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, 1181 BUS_DMA_NOWAIT, &sc->rbd_map); 1182 if (error != 0) { 1183 errmsg = "could not create rbd dma map"; 1184 goto fail; 1185 } 1186 1187 error = bus_dmamem_alloc(sc->sc_dmat, IPW_RBD_SZ, PAGE_SIZE, 0, 1188 &sc->rbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 1189 if (error != 0) { 1190 errmsg = "could not allocate rbd dma memory"; 1191 goto fail; 1192 } 1193 1194 error = bus_dmamem_map(sc->sc_dmat, &sc->rbd_seg, nsegs, IPW_RBD_SZ, 1195 (caddr_t *)&sc->rbd_list, BUS_DMA_NOWAIT); 1196 if (error != 0) { 1197 errmsg = "could not map rbd dma memory"; 1198 goto fail; 1199 } 1200 1201 error = bus_dmamap_load(sc->sc_dmat, sc->rbd_map, sc->rbd_list, 1202 IPW_RBD_SZ, NULL, BUS_DMA_NOWAIT); 1203 if (error != 0) { 1204 errmsg = "could not load rbd dma memory"; 1205 goto fail; 1206 } 1207 1208 sc->srbd_list = malloc(IPW_NRBD * sizeof (struct ipw_soft_bd), 1209 M_DEVBUF, M_NOWAIT); 1210 if (sc->srbd_list == NULL) { 1211 errmsg = "could not allocate soft rbd"; 1212 error = ENOMEM; 1213 goto fail; 1214 } 1215 sbd = sc->srbd_list; 1216 bd = sc->rbd_list; 1217 for (i = 0; i < IPW_NRBD; i++, sbd++, bd++) { 1218 sbd->type = IPW_SBD_TYPE_NOASSOC; 1219 sbd->bd = bd; 1220 } 1221 1222 CSR_WRITE_4(sc, IPW_CSR_RX_BD_BASE, sc->rbd_map->dm_segs[0].ds_addr); 1223 CSR_WRITE_4(sc, IPW_CSR_RX_BD_SIZE, IPW_NRBD); 1224 CSR_WRITE_4(sc, IPW_CSR_RX_READ_INDEX, 0); 1225 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE_INDEX, IPW_NRBD - 1); 1226 sc->rxcur = IPW_NRBD - 1; /* latest bd index I've read */ 1227 1228 /* Allocate status descriptors */ 1229 error = bus_dmamap_create(sc->sc_dmat, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 1230 0, BUS_DMA_NOWAIT, &sc->status_map); 1231 if (error != 0) { 1232 errmsg = "could not create status dma map"; 1233 goto fail; 1234 } 1235 1236 error = bus_dmamem_alloc(sc->sc_dmat, IPW_STATUS_SZ, PAGE_SIZE, 0, 1237 &sc->status_seg, 1, &nsegs, BUS_DMA_NOWAIT); 1238 if (error != 0) { 1239 errmsg = "could not allocate status dma memory"; 1240 goto fail; 1241 } 1242 1243 error = bus_dmamem_map(sc->sc_dmat, &sc->status_seg, nsegs, 1244 IPW_STATUS_SZ, (caddr_t *)&sc->status_list, BUS_DMA_NOWAIT); 1245 if (error != 0) { 1246 errmsg = "could not map status dma memory"; 1247 goto fail; 1248 } 1249 1250 error = bus_dmamap_load(sc->sc_dmat, sc->status_map, sc->status_list, 1251 IPW_STATUS_SZ, NULL, BUS_DMA_NOWAIT); 1252 if (error != 0) { 1253 errmsg = "could not load status dma memory"; 1254 goto fail; 1255 } 1256 1257 CSR_WRITE_4(sc, IPW_CSR_RX_STATUS_BASE, 1258 sc->status_map->dm_segs[0].ds_addr); 1259 1260 sc->rx_sbuf_list = malloc(IPW_NRBD * sizeof (struct ipw_soft_buf), 1261 M_DEVBUF, M_NOWAIT); 1262 if (sc->rx_sbuf_list == NULL) { 1263 errmsg = "could not allocate soft rxbuf"; 1264 error = ENOMEM; 1265 goto fail; 1266 } 1267 1268 sbuf = sc->rx_sbuf_list; 1269 sbd = sc->srbd_list; 1270 for (i = 0; i < IPW_NRBD; i++, sbuf++, sbd++) { 1271 1272 MGETHDR(sbuf->m, M_DONTWAIT, MT_DATA); 1273 if (sbuf->m == NULL) { 1274 errmsg = "could not allocate rx mbuf"; 1275 error = ENOMEM; 1276 goto fail; 1277 } 1278 MCLGET(sbuf->m, M_DONTWAIT); 1279 if (!(sbuf->m->m_flags & M_EXT)) { 1280 m_freem(sbuf->m); 1281 errmsg = "could not allocate rx mbuf cluster"; 1282 error = ENOMEM; 1283 goto fail; 1284 } 1285 1286 error = bus_dmamap_create(sc->sc_dmat, IPW_NRBD * MCLBYTES, 1287 IPW_NRBD, MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 1288 if (error != 0) { 1289 m_freem(sbuf->m); 1290 errmsg = "could not create rxbuf dma map"; 1291 goto fail; 1292 } 1293 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, 1294 mtod(sbuf->m, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 1295 if (error != 0) { 1296 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 1297 m_freem(sbuf->m); 1298 errmsg = "could not map rxbuf dma memory"; 1299 goto fail; 1300 } 1301 sbd->type = IPW_SBD_TYPE_DATA; 1302 sbd->priv = sbuf; 1303 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 1304 sbd->bd->len = htole32(MCLBYTES); 1305 } 1306 1307 return 0; 1308 1309 fail: aprint_error("%s: %s\n", sc->sc_dev.dv_xname, errmsg); 1310 ipw_rx_stop(sc); 1311 1312 return error; 1313 } 1314 1315 static void 1316 ipw_rx_stop(struct ipw_softc *sc) 1317 { 1318 struct ipw_soft_bd *sbd; 1319 struct ipw_soft_buf *sbuf; 1320 int i; 1321 1322 if (sc->rbd_map != NULL) { 1323 if (sc->rbd_list != NULL) { 1324 bus_dmamap_unload(sc->sc_dmat, sc->rbd_map); 1325 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->rbd_list, 1326 IPW_RBD_SZ); 1327 bus_dmamem_free(sc->sc_dmat, &sc->rbd_seg, 1); 1328 sc->rbd_list = NULL; 1329 } 1330 bus_dmamap_destroy(sc->sc_dmat, sc->rbd_map); 1331 sc->rbd_map = NULL; 1332 } 1333 1334 if (sc->status_map != NULL) { 1335 if (sc->status_list != NULL) { 1336 bus_dmamap_unload(sc->sc_dmat, sc->status_map); 1337 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->status_list, 1338 IPW_STATUS_SZ); 1339 bus_dmamem_free(sc->sc_dmat, &sc->status_seg, 1); 1340 sc->status_list = NULL; 1341 } 1342 bus_dmamap_destroy(sc->sc_dmat, sc->status_map); 1343 sc->status_map = NULL; 1344 } 1345 1346 if (sc->srbd_list != NULL) { 1347 for (i = 0, sbd = sc->srbd_list; i < IPW_NRBD; i++, sbd++) { 1348 if (sbd->type == IPW_SBD_TYPE_NOASSOC) 1349 continue; 1350 1351 sbuf = sbd->priv; 1352 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1353 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 1354 m_freem(sbuf->m); 1355 } 1356 free(sc->srbd_list, M_DEVBUF); 1357 sc->srbd_list = NULL; 1358 } 1359 1360 if (sc->rx_sbuf_list != NULL) { 1361 free(sc->rx_sbuf_list, M_DEVBUF); 1362 sc->rx_sbuf_list = NULL; 1363 } 1364 } 1365 1366 static void 1367 ipw_reset(struct ipw_softc *sc) 1368 { 1369 struct ifnet *ifp = &sc->sc_ic.ic_if; 1370 int ntries; 1371 1372 ipw_stop(ifp, 1); 1373 1374 if (sc->flags & IPW_FLAG_FW_INITED) { 1375 ipw_cmd(sc, IPW_CMD_DISABLE_PHY, NULL, 0); 1376 ipw_cmd(sc, IPW_CMD_PREPARE_POWER_DOWN, NULL, 0); 1377 1378 sc->flags &= ~IPW_FLAG_FW_INITED; 1379 } 1380 1381 /* Disable interrupts */ 1382 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1383 1384 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1385 for (ntries = 0; ntries < 5; ntries++) { 1386 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1387 break; 1388 DELAY(10); 1389 } 1390 1391 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 1392 1393 ipw_rx_stop(sc); 1394 ipw_tx_stop(sc); 1395 1396 ifp->if_flags &= ~IFF_UP; 1397 } 1398 1399 static int 1400 ipw_clock_sync(struct ipw_softc *sc) 1401 { 1402 int ntries; 1403 u_int32_t r; 1404 1405 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 1406 for (ntries = 0; ntries < 1000; ntries++) { 1407 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_PRINCETON_RESET) 1408 break; 1409 DELAY(10); 1410 } 1411 if (ntries == 1000) 1412 return EIO; 1413 1414 CSR_WRITE_4(sc, IPW_CSR_CTL, IPW_CTL_INIT_DONE); 1415 for (ntries = 0; ntries < 1000; ntries++) { 1416 if ((r = CSR_READ_4(sc, IPW_CSR_CTL)) & IPW_CTL_CLOCK_READY) 1417 break; 1418 DELAY(200); 1419 } 1420 if (ntries == 1000) 1421 return EIO; 1422 1423 CSR_WRITE_4(sc, IPW_CSR_CTL, r | IPW_CTL_ALLOW_STANDBY); 1424 1425 return 0; 1426 } 1427 1428 static int 1429 ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size) 1430 { 1431 int ntries; 1432 1433 MEM_WRITE_2(sc, 0x220000, 0x0703); 1434 MEM_WRITE_2(sc, 0x220000, 0x0707); 1435 1436 MEM_WRITE_1(sc, 0x210014, 0x72); 1437 MEM_WRITE_1(sc, 0x210014, 0x72); 1438 1439 MEM_WRITE_1(sc, 0x210000, 0x40); 1440 MEM_WRITE_1(sc, 0x210000, 0x00); 1441 MEM_WRITE_1(sc, 0x210000, 0x40); 1442 1443 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1444 1445 MEM_WRITE_1(sc, 0x210000, 0x00); 1446 MEM_WRITE_1(sc, 0x210000, 0x00); 1447 MEM_WRITE_1(sc, 0x210000, 0x80); 1448 1449 MEM_WRITE_2(sc, 0x220000, 0x0703); 1450 MEM_WRITE_2(sc, 0x220000, 0x0707); 1451 1452 MEM_WRITE_1(sc, 0x210014, 0x72); 1453 MEM_WRITE_1(sc, 0x210014, 0x72); 1454 1455 MEM_WRITE_1(sc, 0x210000, 0x00); 1456 MEM_WRITE_1(sc, 0x210000, 0x80); 1457 1458 for (ntries = 0; ntries < 10; ntries++) { 1459 if (MEM_READ_1(sc, 0x210000) & 1) 1460 break; 1461 DELAY(10); 1462 } 1463 if (ntries == 10) 1464 return EIO; 1465 1466 return 0; 1467 } 1468 1469 /* set of macros to handle unaligned little endian data in firmware image */ 1470 #define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1471 #define GETLE16(p) ((p)[0] | (p)[1] << 8) 1472 static int 1473 ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size) 1474 { 1475 u_char *p, *end; 1476 u_int32_t addr; 1477 u_int16_t len; 1478 1479 p = fw; 1480 end = fw + size; 1481 while (p < end) { 1482 if (p + 6 > end) 1483 return EINVAL; 1484 1485 addr = GETLE32(p); 1486 p += 4; 1487 len = GETLE16(p); 1488 p += 2; 1489 1490 if (p + len > end) 1491 return EINVAL; 1492 1493 ipw_write_mem_1(sc, addr, p, len); 1494 p += len; 1495 } 1496 return 0; 1497 } 1498 1499 static int 1500 ipw_firmware_init(struct ipw_softc *sc, u_char *data) 1501 { 1502 struct ieee80211com *ic = &sc->sc_ic; 1503 struct ifnet *ifp = &ic->ic_if; 1504 struct ipw_fw_hdr hdr; 1505 u_int32_t r, len, fw_size, uc_size; 1506 u_char *fw, *uc; 1507 int error; 1508 1509 ipw_reset(sc); 1510 1511 if ((error = copyin(data, &hdr, sizeof hdr)) != 0) 1512 goto fail1; 1513 1514 fw_size = le32toh(hdr.fw_size); 1515 uc_size = le32toh(hdr.uc_size); 1516 data += sizeof hdr; 1517 1518 if ((fw = malloc(fw_size, M_DEVBUF, M_NOWAIT)) == NULL) { 1519 error = ENOMEM; 1520 goto fail1; 1521 } 1522 1523 if ((error = copyin(data, fw, fw_size)) != 0) 1524 goto fail2; 1525 1526 data += fw_size; 1527 1528 if ((uc = malloc(uc_size, M_DEVBUF, M_NOWAIT)) == NULL) { 1529 error = ENOMEM; 1530 goto fail2; 1531 } 1532 1533 if ((error = copyin(data, uc, uc_size)) != 0) 1534 goto fail3; 1535 1536 if ((error = ipw_clock_sync(sc)) != 0) { 1537 aprint_error("%s: clock synchronization failed\n", 1538 sc->sc_dev.dv_xname); 1539 goto fail3; 1540 } 1541 1542 MEM_WRITE_4(sc, 0x003000e0, 0x80000000); 1543 1544 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1545 1546 if ((error = ipw_load_ucode(sc, uc, uc_size)) != 0) { 1547 aprint_error("%s: could not load microcode\n", 1548 sc->sc_dev.dv_xname); 1549 goto fail3; 1550 } 1551 1552 MEM_WRITE_4(sc, 0x003000e0, 0); 1553 1554 if ((error = ipw_clock_sync(sc)) != 0) { 1555 aprint_error("%s: clock synchronization failed\n", 1556 sc->sc_dev.dv_xname); 1557 goto fail3; 1558 } 1559 1560 if ((error = ipw_load_firmware(sc, fw, fw_size))) { 1561 aprint_error("%s: could not load firmware\n", 1562 sc->sc_dev.dv_xname); 1563 goto fail3; 1564 } 1565 1566 ipw_zero_mem_4(sc, 0x0002f200, 196); 1567 ipw_zero_mem_4(sc, 0x0002f610, 8); 1568 ipw_zero_mem_4(sc, 0x0002fa00, 8); 1569 ipw_zero_mem_4(sc, 0x0002fc00, 4); 1570 ipw_zero_mem_4(sc, 0x0002ff80, 32); 1571 1572 if ((error = ipw_rx_init(sc)) != 0) { 1573 aprint_error("%s: could not initialize rx queue\n", 1574 sc->sc_dev.dv_xname); 1575 goto fail3; 1576 } 1577 1578 if ((error = ipw_tx_init(sc)) != 0) { 1579 aprint_error("%s: could not initialize tx queue\n", 1580 sc->sc_dev.dv_xname); 1581 goto fail3; 1582 } 1583 1584 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1585 IPW_IO_LED_OFF); 1586 1587 /* Enable interrupts */ 1588 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1589 1590 /* Let's go! */ 1591 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1592 1593 /* Wait at most 5 seconds for firmware initialization to complete */ 1594 if ((error = tsleep(sc, 0, "ipwinit", 5 * hz)) != 0) { 1595 aprint_error("%s: timeout waiting for firmware initialization " 1596 "to complete\n", sc->sc_dev.dv_xname); 1597 goto fail3; 1598 } 1599 1600 /* Firmware initialization completed */ 1601 sc->flags |= IPW_FLAG_FW_INITED; 1602 1603 free(uc, M_DEVBUF); 1604 free(fw, M_DEVBUF); 1605 1606 r = CSR_READ_4(sc, IPW_CSR_IO); 1607 CSR_WRITE_4(sc, IPW_CSR_IO, r | IPW_IO_GPIO1_MASK | IPW_IO_GPIO3_MASK); 1608 1609 /* Retrieve information tables base addresses */ 1610 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 1611 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 1612 1613 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 1614 1615 /* Retrieve adapter MAC address */ 1616 len = IEEE80211_ADDR_LEN; 1617 ipw_read_table2(sc, IPW_INFO_ADAPTER_MAC, ic->ic_myaddr, &len); 1618 1619 IEEE80211_ADDR_COPY(LLADDR(ifp->if_sadl), ic->ic_myaddr); 1620 1621 return 0; 1622 1623 fail3: free(uc, M_DEVBUF); 1624 fail2: free(fw, M_DEVBUF); 1625 fail1: ipw_reset(sc); 1626 1627 return error; 1628 } 1629 1630 static int 1631 ipw_config(struct ipw_softc *sc) 1632 { 1633 struct ieee80211com *ic = &sc->sc_ic; 1634 struct ifnet *ifp = &ic->ic_if; 1635 struct ipw_security security; 1636 struct ieee80211_wepkey *k; 1637 struct ipw_wep_key wepkey; 1638 struct ipw_scan_options options; 1639 struct ipw_configuration config; 1640 u_int32_t data; 1641 int error, i; 1642 1643 DPRINTF(("Setting adapter MAC to %s\n", ether_sprintf(ic->ic_myaddr))); 1644 IEEE80211_ADDR_COPY(LLADDR(ifp->if_sadl), ic->ic_myaddr); 1645 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 1646 IEEE80211_ADDR_LEN); 1647 if (error != 0) 1648 return error; 1649 1650 switch (ic->ic_opmode) { 1651 case IEEE80211_M_STA: 1652 case IEEE80211_M_HOSTAP: 1653 data = htole32(IPW_MODE_BSS); 1654 break; 1655 1656 case IEEE80211_M_IBSS: 1657 case IEEE80211_M_AHDEMO: 1658 data = htole32(IPW_MODE_IBSS); 1659 break; 1660 1661 case IEEE80211_M_MONITOR: 1662 data = htole32(IPW_MODE_MONITOR); 1663 break; 1664 } 1665 DPRINTF(("Setting adapter mode to %u\n", data)); 1666 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 1667 if (error != 0) 1668 return error; 1669 1670 if (ic->ic_opmode == IEEE80211_M_IBSS || 1671 ic->ic_opmode == IEEE80211_M_MONITOR) { 1672 data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); 1673 DPRINTF(("Setting adapter channel to %u\n", data)); 1674 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 1675 if (error != 0) 1676 return error; 1677 } 1678 1679 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 1680 IPW_CFG_PREAMBLE_LEN | IPW_CFG_802_1x_ENABLE); 1681 if (ic->ic_opmode == IEEE80211_M_IBSS) 1682 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 1683 if (ifp->if_flags & IFF_PROMISC) 1684 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 1685 config.channels = htole32(0x3fff); /* channels 1-14 */ 1686 config.ibss_chan = htole32(0x7ff); 1687 DPRINTF(("Setting adapter configuration 0x%08x\n", config.flags)); 1688 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 1689 if (error != 0) 1690 return error; 1691 1692 data = htole32(0x3); /* 1, 2 */ 1693 DPRINTF(("Setting adapter basic tx rates to 0x%x\n", data)); 1694 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 1695 if (error != 0) 1696 return error; 1697 1698 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 1699 DPRINTF(("Setting adapter tx rates to 0x%x\n", data)); 1700 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 1701 if (error != 0) 1702 return error; 1703 1704 data = htole32(IPW_POWER_MODE_CAM); 1705 DPRINTF(("Setting adapter power mode to %u\n", data)); 1706 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 1707 if (error != 0) 1708 return error; 1709 1710 if (ic->ic_opmode == IEEE80211_M_IBSS) { 1711 data = htole32(ic->ic_txpower); 1712 DPRINTF(("Setting adapter tx power index to %u\n", data)); 1713 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 1714 sizeof data); 1715 if (error != 0) 1716 return error; 1717 } 1718 1719 data = htole32(ic->ic_rtsthreshold); 1720 DPRINTF(("Setting adapter RTS threshold to %u\n", data)); 1721 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 1722 if (error != 0) 1723 return error; 1724 1725 data = htole32(ic->ic_fragthreshold); 1726 DPRINTF(("Setting adapter frag threshold to %u\n", data)); 1727 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 1728 if (error != 0) 1729 return error; 1730 1731 #ifdef IPW_DEBUG 1732 if (ipw_debug > 0) { 1733 printf("Setting adapter ESSID to "); 1734 ieee80211_print_essid(ic->ic_des_essid, ic->ic_des_esslen); 1735 printf("\n"); 1736 } 1737 #endif 1738 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ic->ic_des_essid, 1739 ic->ic_des_esslen); 1740 if (error != 0) 1741 return error; 1742 1743 /* no mandatory BSSID */ 1744 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 1745 if (error != 0) 1746 return error; 1747 1748 if (ic->ic_flags & IEEE80211_F_DESBSSID) { 1749 DPRINTF(("Setting adapter desired BSSID to %s\n", 1750 ether_sprintf(ic->ic_des_bssid))); 1751 error = ipw_cmd(sc, IPW_CMD_SET_DESIRED_BSSID, 1752 ic->ic_des_bssid, IEEE80211_ADDR_LEN); 1753 if (error != 0) 1754 return error; 1755 } 1756 1757 security.authmode = IPW_AUTH_OPEN; 1758 security.ciphers = htole32(IPW_CIPHER_NONE); 1759 security.version = htole16(0); 1760 security.replay_counters_number = 0; 1761 security.unicast_using_group = 0; 1762 DPRINTF(("Setting adapter authmode to %u\n", security.authmode)); 1763 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 1764 sizeof security); 1765 if (error != 0) 1766 return error; 1767 1768 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 1769 k = ic->ic_nw_keys; 1770 for (i = 0; i < IEEE80211_WEP_NKID; i++, k++) { 1771 if (k->wk_len == 0) 1772 continue; 1773 1774 wepkey.idx = i; 1775 wepkey.len = k->wk_len; 1776 bzero(wepkey.key, sizeof wepkey.key); 1777 bcopy(k->wk_key, wepkey.key, k->wk_len); 1778 DPRINTF(("Setting wep key index %d len %d\n", 1779 wepkey.idx, wepkey.len)); 1780 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY, &wepkey, 1781 sizeof wepkey); 1782 if (error != 0) 1783 return error; 1784 } 1785 1786 data = htole32(ic->ic_wep_txkey); 1787 DPRINTF(("Setting adapter tx key index to %u\n", data)); 1788 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY_INDEX, &data, 1789 sizeof data); 1790 if (error != 0) 1791 return error; 1792 } 1793 1794 data = htole32((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) ? 0x8 : 0); 1795 DPRINTF(("Setting adapter wep flags to 0x%x\n", data)); 1796 error = ipw_cmd(sc, IPW_CMD_SET_WEP_FLAGS, &data, sizeof data); 1797 if (error != 0) 1798 return error; 1799 1800 if (ic->ic_opmode == IEEE80211_M_IBSS || 1801 ic->ic_opmode == IEEE80211_M_HOSTAP) { 1802 data = htole32(ic->ic_lintval); 1803 DPRINTF(("Setting adapter beacon interval to %u\n", data)); 1804 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 1805 sizeof data); 1806 if (error != 0) 1807 return error; 1808 } 1809 1810 options.flags = htole32(0); 1811 options.channels = htole32(0x3fff); /* scan channels 1-14 */ 1812 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &options, sizeof options); 1813 if (error != 0) 1814 return error; 1815 1816 /* finally, enable adapter (start scanning for an access point) */ 1817 DPRINTF(("Enabling adapter\n")); 1818 error = ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1819 if (error != 0) 1820 return error; 1821 1822 return 0; 1823 } 1824 1825 static int 1826 ipw_init(struct ifnet *ifp) 1827 { 1828 struct ipw_softc *sc = ifp->if_softc; 1829 struct ieee80211com *ic = &sc->sc_ic; 1830 1831 /* exit immediately if firmware has not been ioctl'd */ 1832 if (!(sc->flags & IPW_FLAG_FW_INITED)) { 1833 ifp->if_flags &= ~IFF_UP; 1834 return EIO; 1835 } 1836 1837 ipw_stop(ifp, 0); 1838 1839 if (ipw_config(sc) != 0) { 1840 aprint_error("%s: device configuration failed\n", 1841 sc->sc_dev.dv_xname); 1842 goto fail; 1843 } 1844 1845 ifp->if_flags &= ~IFF_OACTIVE; 1846 ifp->if_flags |= IFF_RUNNING; 1847 1848 ic->ic_bss->ni_chan = ic->ic_channels; 1849 1850 return 0; 1851 1852 fail: ipw_stop(ifp, 0); 1853 1854 return EIO; 1855 } 1856 1857 static void 1858 ipw_stop(struct ifnet *ifp, int disable) 1859 { 1860 struct ipw_softc *sc = ifp->if_softc; 1861 struct ieee80211com *ic = &sc->sc_ic; 1862 1863 if (ifp->if_flags & IFF_RUNNING) { 1864 DPRINTF(("Disabling adapter\n")); 1865 ipw_cmd(sc, IPW_CMD_DISABLE, NULL, 0); 1866 } 1867 1868 ifp->if_timer = 0; 1869 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1870 1871 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1872 } 1873 1874 static void 1875 ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, u_int8_t *datap, 1876 bus_size_t count) 1877 { 1878 for (; count > 0; offset++, datap++, count--) { 1879 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 1880 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 1881 } 1882 } 1883 1884 static void 1885 ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, u_int8_t *datap, 1886 bus_size_t count) 1887 { 1888 for (; count > 0; offset++, datap++, count--) { 1889 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 1890 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 1891 } 1892 } 1893 1894 static void 1895 ipw_zero_mem_4(struct ipw_softc *sc, bus_size_t offset, bus_size_t count) 1896 { 1897 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, offset); 1898 while (count-- > 0) 1899 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_DATA, 0); 1900 } 1901 1902 #ifdef IPW_AS_LKM 1903 1904 #include <sys/lkm.h> 1905 #include <lkm/dev/pcilkm/pcilkm.h> 1906 1907 MOD_MISC("ipw"); 1908 1909 PCILKM_DECLARE(ipw, DV_DULL, NULL); 1910 1911 #endif 1912
Indexes created Tue Sep 30 20:09:53 GMT 2025