if_ipw.c revision 1.2.2.7
1 /* $NetBSD: if_ipw.c,v 1.2.2.7 2005/11/10 14:06:01 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 5 * Damien Bergamini <damien.bergamini (at) free.fr>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: if_ipw.c,v 1.2.2.7 2005/11/10 14:06:01 skrll Exp $"); 32 33 /*- 34 * Intel(R) PRO/Wireless 2100 MiniPCI driver 35 * http://www.intel.com/products/mobiletechnology/prowireless.htm 36 */ 37 38 #include "bpfilter.h" 39 40 #include <sys/param.h> 41 #include <sys/sockio.h> 42 #include <sys/sysctl.h> 43 #include <sys/mbuf.h> 44 #include <sys/kernel.h> 45 #include <sys/socket.h> 46 #include <sys/systm.h> 47 #include <sys/malloc.h> 48 #include <sys/conf.h> 49 50 #include <machine/bus.h> 51 #include <machine/endian.h> 52 #include <machine/intr.h> 53 54 #include <dev/pci/pcireg.h> 55 #include <dev/pci/pcivar.h> 56 #include <dev/pci/pcidevs.h> 57 58 #if NBPFILTER > 0 59 #include <net/bpf.h> 60 #endif 61 #include <net/if.h> 62 #include <net/if_arp.h> 63 #include <net/if_dl.h> 64 #include <net/if_ether.h> 65 #include <net/if_media.h> 66 #include <net/if_types.h> 67 68 #include <net80211/ieee80211_var.h> 69 #include <net80211/ieee80211_radiotap.h> 70 71 #include <netinet/in.h> 72 #include <netinet/in_systm.h> 73 #include <netinet/in_var.h> 74 #include <netinet/ip.h> 75 76 #include <dev/pci/if_ipwreg.h> 77 #include <dev/pci/if_ipwvar.h> 78 79 static int ipw_match(struct device *, struct cfdata *, void *); 80 static void ipw_attach(struct device *, struct device *, void *); 81 static int ipw_detach(struct device *, int); 82 static int ipw_media_change(struct ifnet *); 83 static int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 84 static void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 85 static void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 86 static void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 87 struct ipw_soft_bd *, struct ipw_soft_buf *); 88 static void ipw_notification_intr(struct ipw_softc *, struct ipw_soft_buf *); 89 static void ipw_rx_intr(struct ipw_softc *); 90 static void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 91 static void ipw_tx_intr(struct ipw_softc *); 92 static int ipw_intr(void *); 93 static int ipw_cmd(struct ipw_softc *, u_int32_t, void *, u_int32_t); 94 static int ipw_tx_start(struct ifnet *, struct mbuf *, struct ieee80211_node *); 95 static void ipw_start(struct ifnet *); 96 static void ipw_watchdog(struct ifnet *); 97 static int ipw_get_table1(struct ipw_softc *, u_int32_t *); 98 static int ipw_get_radio(struct ipw_softc *, int *); 99 static int ipw_ioctl(struct ifnet *, u_long, caddr_t); 100 static u_int32_t ipw_read_table1(struct ipw_softc *, u_int32_t); 101 static void ipw_write_table1(struct ipw_softc *, u_int32_t, u_int32_t); 102 static int ipw_read_table2(struct ipw_softc *, u_int32_t, void *, u_int32_t *); 103 static int ipw_tx_init(struct ipw_softc *); 104 static void ipw_tx_stop(struct ipw_softc *); 105 static int ipw_rx_init(struct ipw_softc *); 106 static void ipw_rx_stop(struct ipw_softc *); 107 static void ipw_reset(struct ipw_softc *); 108 static int ipw_clock_sync(struct ipw_softc *); 109 static int ipw_load_ucode(struct ipw_softc *, u_char *, int); 110 static int ipw_load_firmware(struct ipw_softc *, u_char *, int); 111 static int ipw_firmware_init(struct ipw_softc *, u_char *); 112 static int ipw_config(struct ipw_softc *); 113 static int ipw_init(struct ifnet *); 114 static void ipw_stop(struct ifnet *, int); 115 static void ipw_read_mem_1(struct ipw_softc *, bus_size_t, u_int8_t *, 116 bus_size_t); 117 static void ipw_write_mem_1(struct ipw_softc *, bus_size_t, u_int8_t *, 118 bus_size_t); 119 static void ipw_zero_mem_4(struct ipw_softc *, bus_size_t, bus_size_t); 120 121 static inline u_int8_t MEM_READ_1(struct ipw_softc *sc, u_int32_t addr) 122 { 123 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 124 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); 125 } 126 127 static inline u_int16_t MEM_READ_2(struct ipw_softc *sc, u_int32_t addr) 128 { 129 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 130 return CSR_READ_2(sc, IPW_CSR_INDIRECT_DATA); 131 } 132 133 static inline u_int32_t MEM_READ_4(struct ipw_softc *sc, u_int32_t addr) 134 { 135 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 136 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); 137 } 138 139 #ifdef IPW_DEBUG 140 #define DPRINTF(x) if (ipw_debug > 0) printf x 141 #define DPRINTFN(n, x) if (ipw_debug >= (n)) printf x 142 int ipw_debug = 0; 143 #else 144 #define DPRINTF(x) 145 #define DPRINTFN(n, x) 146 #endif 147 148 CFATTACH_DECL(ipw, sizeof (struct ipw_softc), ipw_match, ipw_attach, 149 ipw_detach, NULL); 150 151 static int 152 ipw_match(struct device *parent, struct cfdata *match, void *aux) 153 { 154 struct pci_attach_args *pa = aux; 155 156 if (PCI_VENDOR (pa->pa_id) == PCI_VENDOR_INTEL && 157 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_PRO_WL_2100) 158 return 1; 159 160 return 0; 161 } 162 163 /* Base Address Register */ 164 #define IPW_PCI_BAR0 0x10 165 166 static void 167 ipw_attach(struct device *parent, struct device *self, void *aux) 168 { 169 struct ipw_softc *sc = (struct ipw_softc *)self; 170 struct ieee80211com *ic = &sc->sc_ic; 171 struct ifnet *ifp = &sc->sc_if; 172 struct ieee80211_rateset *rs; 173 struct pci_attach_args *pa = aux; 174 const char *intrstr; 175 char devinfo[256]; 176 bus_space_tag_t memt; 177 bus_space_handle_t memh; 178 bus_addr_t base; 179 pci_intr_handle_t ih; 180 u_int32_t data; 181 int i, revision, error; 182 183 sc->sc_pct = pa->pa_pc; 184 185 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof devinfo); 186 revision = PCI_REVISION(pa->pa_class); 187 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, revision); 188 189 /* enable bus-mastering */ 190 data = pci_conf_read(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG); 191 data |= PCI_COMMAND_MASTER_ENABLE; 192 pci_conf_write(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG, data); 193 194 /* map the register window */ 195 error = pci_mapreg_map(pa, IPW_PCI_BAR0, PCI_MAPREG_TYPE_MEM | 196 PCI_MAPREG_MEM_TYPE_32BIT, 0, &memt, &memh, &base, &sc->sc_sz); 197 if (error != 0) { 198 aprint_error("%s: could not map memory space\n", 199 sc->sc_dev.dv_xname); 200 return; 201 } 202 203 sc->sc_st = memt; 204 sc->sc_sh = memh; 205 sc->sc_dmat = pa->pa_dmat; 206 207 /* disable interrupts */ 208 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 209 210 if (pci_intr_map(pa, &ih) != 0) { 211 aprint_error("%s: could not map interrupt\n", 212 sc->sc_dev.dv_xname); 213 return; 214 } 215 216 intrstr = pci_intr_string(sc->sc_pct, ih); 217 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, ipw_intr, sc); 218 if (sc->sc_ih == NULL) { 219 aprint_error("%s: could not establish interrupt", 220 sc->sc_dev.dv_xname); 221 if (intrstr != NULL) 222 aprint_error(" at %s", intrstr); 223 aprint_error("\n"); 224 return; 225 } 226 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 227 228 ic->ic_ifp = ifp; 229 ic->ic_phytype = IEEE80211_T_DS; 230 ic->ic_opmode = IEEE80211_M_STA; 231 ic->ic_state = IEEE80211_S_INIT; 232 233 /* set device capabilities */ 234 ic->ic_caps = IEEE80211_C_IBSS | IEEE80211_C_MONITOR | 235 IEEE80211_C_PMGT | IEEE80211_C_TXPMGT | IEEE80211_C_WEP; 236 237 /* set supported 11.b rates */ 238 rs = &ic->ic_sup_rates[IEEE80211_MODE_11B]; 239 rs->rs_nrates = 4; 240 rs->rs_rates[0] = 2; /* 1Mbps */ 241 rs->rs_rates[1] = 4; /* 2Mbps */ 242 rs->rs_rates[2] = 11; /* 5.5Mbps */ 243 rs->rs_rates[3] = 22; /* 11Mbps */ 244 245 /* set supported 11.b channels (1 through 14) */ 246 for (i = 1; i <= 14; i++) { 247 ic->ic_channels[i].ic_freq = 248 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 249 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 250 } 251 252 ic->ic_ibss_chan = &ic->ic_channels[0]; 253 254 ifp->if_softc = sc; 255 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 256 ifp->if_init = ipw_init; 257 ifp->if_stop = ipw_stop; 258 ifp->if_ioctl = ipw_ioctl; 259 ifp->if_start = ipw_start; 260 ifp->if_watchdog = ipw_watchdog; 261 IFQ_SET_READY(&ifp->if_snd); 262 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 263 264 if_attach(ifp); 265 ieee80211_ifattach(ic); 266 /* override state transition machine */ 267 sc->sc_newstate = ic->ic_newstate; 268 ic->ic_newstate = ipw_newstate; 269 270 ieee80211_media_init(ic, ipw_media_change, ieee80211_media_status); 271 272 #if NBPFILTER > 0 273 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 274 sizeof (struct ieee80211_frame) + 64, &sc->sc_drvbpf); 275 276 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 277 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 278 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 279 280 sc->sc_txtap_len = sizeof sc->sc_txtapu; 281 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 282 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 283 #endif 284 } 285 286 static int 287 ipw_detach(struct device* self, int flags) 288 { 289 struct ipw_softc *sc = (struct ipw_softc *)self; 290 struct ifnet *ifp = &sc->sc_if; 291 292 ipw_reset(sc); 293 294 #if NBPFILTER > 0 295 bpfdetach(ifp); 296 #endif 297 ieee80211_ifdetach(&sc->sc_ic); 298 if_detach(ifp); 299 300 if (sc->sc_ih != NULL) { 301 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 302 sc->sc_ih = NULL; 303 } 304 305 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 306 307 return 0; 308 } 309 310 static int 311 ipw_media_change(struct ifnet *ifp) 312 { 313 int error; 314 315 error = ieee80211_media_change(ifp); 316 if (error != ENETRESET) 317 return error; 318 319 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 320 ipw_init(ifp); 321 322 return 0; 323 } 324 325 static int 326 ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 327 { 328 struct ifnet *ifp = ic->ic_ifp; 329 struct ipw_softc *sc = ifp->if_softc; 330 struct ieee80211_node *ni = ic->ic_bss; 331 u_int32_t val, len; 332 333 switch (nstate) { 334 case IEEE80211_S_INIT: 335 break; 336 337 case IEEE80211_S_RUN: 338 len = IEEE80211_NWID_LEN; 339 ipw_read_table2(sc, IPW_INFO_CURRENT_SSID, ni->ni_essid, &len); 340 ni->ni_esslen = len; 341 342 val = ipw_read_table1(sc, IPW_INFO_CURRENT_CHANNEL); 343 ni->ni_chan = &ic->ic_channels[val]; 344 345 DELAY(100); /* firmware needs a short delay here */ 346 347 len = IEEE80211_ADDR_LEN; 348 ipw_read_table2(sc, IPW_INFO_CURRENT_BSSID, ni->ni_bssid, &len); 349 break; 350 351 case IEEE80211_S_SCAN: 352 case IEEE80211_S_AUTH: 353 case IEEE80211_S_ASSOC: 354 break; 355 } 356 357 ic->ic_state = nstate; 358 return 0; 359 } 360 361 static void 362 ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 363 { 364 struct ipw_cmd *cmd; 365 366 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof (struct ipw_cmd), 367 BUS_DMASYNC_POSTREAD); 368 369 cmd = mtod(sbuf->m, struct ipw_cmd *); 370 371 DPRINTFN(2, ("RX!CMD!%u!%u!%u!%u!%u\n", 372 le32toh(cmd->type), le32toh(cmd->subtype), le32toh(cmd->seq), 373 le32toh(cmd->len), le32toh(cmd->status))); 374 375 /* 376 * Wake up processes waiting for command ack. In the case of the 377 * IPW_CMD_DISABLE command, wake up the process only when the adapter 378 * enters the IPW_STATE_DISABLED state. This is notified in 379 * ipw_newstate_intr(). 380 */ 381 if (le32toh(cmd->type) != IPW_CMD_DISABLE) 382 wakeup(sc->cmd); 383 } 384 385 static void 386 ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 387 { 388 struct ieee80211com *ic = &sc->sc_ic; 389 u_int32_t state; 390 391 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof state, 392 BUS_DMASYNC_POSTREAD); 393 394 state = le32toh(*mtod(sbuf->m, u_int32_t *)); 395 396 DPRINTFN(2, ("RX!NEWSTATE!%u\n", state)); 397 398 switch (state) { 399 case IPW_STATE_ASSOCIATED: 400 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 401 break; 402 403 case IPW_STATE_SCANNING: 404 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 405 break; 406 407 case IPW_STATE_ASSOCIATION_LOST: 408 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 409 break; 410 411 case IPW_STATE_DISABLED: 412 wakeup(sc->cmd); 413 break; 414 415 case IPW_STATE_RADIO_DISABLED: 416 /* XXX should turn the interface down */ 417 break; 418 } 419 } 420 421 static void 422 ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 423 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 424 { 425 struct ieee80211com *ic = &sc->sc_ic; 426 struct ifnet *ifp = &sc->sc_if; 427 struct mbuf *m; 428 struct ieee80211_frame_min *wh; 429 struct ieee80211_node *ni; 430 int error; 431 432 DPRINTFN(5, ("RX!DATA!%u!%u\n", le32toh(status->len), status->rssi)); 433 434 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, le32toh(status->len), 435 BUS_DMASYNC_POSTREAD); 436 437 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 438 439 /* Finalize mbuf */ 440 m = sbuf->m; 441 m->m_pkthdr.rcvif = ifp; 442 m->m_pkthdr.len = m->m_len = le32toh(status->len); 443 444 #if NBPFILTER > 0 445 if (sc->sc_drvbpf != NULL) { 446 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 447 448 tap->wr_flags = 0; 449 tap->wr_antsignal = status->rssi; 450 tap->wr_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 451 tap->wr_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 452 453 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 454 } 455 #endif 456 457 wh = mtod(m, struct ieee80211_frame_min *); 458 459 ni = ieee80211_find_rxnode(ic, wh); 460 461 /* Send it up to the upper layer */ 462 ieee80211_input(ic, m, ni, status->rssi, 0/*rstamp*/); 463 464 ieee80211_free_node(ni); 465 466 MGETHDR(m, M_DONTWAIT, MT_DATA); 467 if (m == NULL) { 468 aprint_error("%s: could not allocate rx mbuf\n", 469 sc->sc_dev.dv_xname); 470 return; 471 } 472 MCLGET(m, M_DONTWAIT); 473 if (!(m->m_flags & M_EXT)) { 474 m_freem(m); 475 aprint_error("%s: could not allocate rx mbuf cluster\n", 476 sc->sc_dev.dv_xname); 477 return; 478 } 479 480 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, mtod(m, void *), 481 MCLBYTES, NULL, BUS_DMA_NOWAIT); 482 if (error != 0) { 483 aprint_error("%s: could not map rxbuf dma memory\n", 484 sc->sc_dev.dv_xname); 485 m_freem(m); 486 return; 487 } 488 489 sbuf->m = m; 490 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 491 } 492 493 static void 494 ipw_notification_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 495 { 496 DPRINTFN(2, ("RX!NOTIFICATION\n")); 497 } 498 499 static void 500 ipw_rx_intr(struct ipw_softc *sc) 501 { 502 struct ipw_status *status; 503 struct ipw_soft_bd *sbd; 504 struct ipw_soft_buf *sbuf; 505 u_int32_t r, i; 506 507 r = CSR_READ_4(sc, IPW_CSR_RX_READ_INDEX); 508 509 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 510 511 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 512 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 513 BUS_DMASYNC_POSTREAD); 514 515 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 516 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 517 BUS_DMASYNC_POSTREAD); 518 519 status = &sc->status_list[i]; 520 sbd = &sc->srbd_list[i]; 521 sbuf = sbd->priv; 522 523 switch (le16toh(status->code) & 0xf) { 524 case IPW_STATUS_CODE_COMMAND: 525 ipw_command_intr(sc, sbuf); 526 break; 527 528 case IPW_STATUS_CODE_NEWSTATE: 529 ipw_newstate_intr(sc, sbuf); 530 break; 531 532 case IPW_STATUS_CODE_DATA_802_3: 533 case IPW_STATUS_CODE_DATA_802_11: 534 ipw_data_intr(sc, status, sbd, sbuf); 535 break; 536 537 case IPW_STATUS_CODE_NOTIFICATION: 538 ipw_notification_intr(sc, sbuf); 539 break; 540 541 default: 542 aprint_debug("%s: unknown status code %u\n", 543 sc->sc_dev.dv_xname, le16toh(status->code)); 544 } 545 sbd->bd->flags = 0; 546 547 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 548 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 549 BUS_DMASYNC_PREWRITE); 550 } 551 552 /* Tell the firmware what we have processed */ 553 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 554 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE_INDEX, sc->rxcur); 555 } 556 557 static void 558 ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 559 { 560 struct ieee80211com *ic; 561 struct ipw_soft_hdr *shdr; 562 struct ipw_soft_buf *sbuf; 563 564 switch (sbd->type) { 565 case IPW_SBD_TYPE_COMMAND: 566 bus_dmamap_unload(sc->sc_dmat, sc->cmd_map); 567 break; 568 569 case IPW_SBD_TYPE_HEADER: 570 shdr = sbd->priv; 571 bus_dmamap_unload(sc->sc_dmat, shdr->map); 572 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 573 break; 574 575 case IPW_SBD_TYPE_DATA: 576 ic = &sc->sc_ic; 577 sbuf = sbd->priv; 578 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 579 m_freem(sbuf->m); 580 if (sbuf->ni != NULL) 581 ieee80211_free_node(sbuf->ni); 582 /* kill watchdog timer */ 583 sc->sc_tx_timer = 0; 584 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 585 break; 586 } 587 ++sc->txfree; 588 sbd->type = IPW_SBD_TYPE_NOASSOC; 589 } 590 591 static void 592 ipw_tx_intr(struct ipw_softc *sc) 593 { 594 struct ifnet *ifp = &sc->sc_if; 595 u_int32_t r, i; 596 597 r = CSR_READ_4(sc, IPW_CSR_TX_READ_INDEX); 598 599 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) 600 ipw_release_sbd(sc, &sc->stbd_list[i]); 601 602 /* Remember what the firmware has processed */ 603 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 604 605 /* Call start() since some buffer descriptors have been released */ 606 ifp->if_flags &= ~IFF_OACTIVE; 607 (*ifp->if_start)(ifp); 608 } 609 610 static int 611 ipw_intr(void *arg) 612 { 613 struct ipw_softc *sc = arg; 614 u_int32_t r; 615 616 if ((r = CSR_READ_4(sc, IPW_CSR_INTR)) == 0) 617 return 0; 618 619 /* Disable interrupts */ 620 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 621 622 DPRINTFN(8, ("INTR!0x%08x\n", r)); 623 624 if (r & IPW_INTR_RX_TRANSFER) 625 ipw_rx_intr(sc); 626 627 if (r & IPW_INTR_TX_TRANSFER) 628 ipw_tx_intr(sc); 629 630 if (r & IPW_INTR_FW_INIT_DONE) { 631 if (!(r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR))) 632 wakeup(sc); 633 } 634 635 /* Acknowledge interrupts */ 636 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 637 638 /* Re-enable interrupts */ 639 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 640 641 return 0; 642 } 643 644 static int 645 ipw_cmd(struct ipw_softc *sc, u_int32_t type, void *data, u_int32_t len) 646 { 647 struct ipw_soft_bd *sbd; 648 int error; 649 650 #ifdef DIAGNOSTIC 651 KASSERT(sc->txfree != 0); 652 #endif /* DIAGNOSTIC */ 653 654 sbd = &sc->stbd_list[sc->txcur]; 655 656 error = bus_dmamap_load(sc->sc_dmat, sc->cmd_map, sc->cmd, 657 sizeof (struct ipw_cmd), NULL, BUS_DMA_NOWAIT); 658 if (error != 0) { 659 aprint_error("%s: could not map cmd dma memory\n", 660 sc->sc_dev.dv_xname); 661 return error; 662 } 663 664 sc->cmd->type = htole32(type); 665 sc->cmd->subtype = htole32(0); 666 sc->cmd->len = htole32(len); 667 sc->cmd->seq = htole32(0); 668 if (data != NULL) 669 bcopy(data, sc->cmd->data, len); 670 671 sbd->type = IPW_SBD_TYPE_COMMAND; 672 sbd->bd->physaddr = htole32(sc->cmd_map->dm_segs[0].ds_addr); 673 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 674 sbd->bd->nfrag = 1; 675 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 676 IPW_BD_FLAG_TX_LAST_FRAGMENT; 677 678 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 0, sizeof (struct ipw_cmd), 679 BUS_DMASYNC_PREWRITE); 680 681 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 682 sc->txcur * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 683 BUS_DMASYNC_PREWRITE); 684 685 --sc->txfree; 686 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 687 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, sc->txcur); 688 689 DPRINTFN(2, ("TX!CMD!%u!%u!%u!%u\n", type, 0, 0, len)); 690 691 /* Wait at most two seconds for command to complete */ 692 return tsleep(sc->cmd, 0, "ipwcmd", 2 * hz); 693 } 694 695 /* Check that descriptors are available to transmit one packet. 696 * Always reserve one transmit-buffer descriptor for ipw_cmd. 697 */ 698 static __inline int 699 ipw_tx_ready(struct ipw_softc *sc) 700 { 701 return !TAILQ_EMPTY(&sc->sc_free_shdr) && 702 !TAILQ_EMPTY(&sc->sc_free_sbuf) && sc->txfree > 1; 703 } 704 705 /* Must not be called unless ipw_tx_ready(sc). */ 706 static int 707 ipw_tx_start(struct ifnet *ifp, struct mbuf *m, struct ieee80211_node *ni) 708 { 709 struct ipw_softc *sc = ifp->if_softc; 710 struct ieee80211com *ic = &sc->sc_ic; 711 struct ieee80211_frame *wh; 712 struct ieee80211_key *k; 713 struct ipw_soft_bd *sbd; 714 struct ipw_soft_hdr *shdr; 715 struct ipw_soft_buf *sbuf; 716 int error, i, iswep; 717 718 #ifdef DIAGNOSTIC 719 KASSERT(ipw_tx_ready(sc)); 720 #endif 721 722 wh = mtod(m, struct ieee80211_frame *); 723 724 iswep = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0; 725 726 if (iswep && (k = ieee80211_crypto_encap(ic, ni, m)) == NULL) { 727 m_freem(m); 728 return EIO; 729 } 730 731 #if NBPFILTER > 0 732 if (sc->sc_drvbpf != NULL) { 733 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 734 735 tap->wt_flags = 0; 736 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 737 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 738 739 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m); 740 } 741 #endif 742 743 shdr = TAILQ_FIRST(&sc->sc_free_shdr); 744 sbuf = TAILQ_FIRST(&sc->sc_free_sbuf); 745 746 shdr->hdr.type = htole32(IPW_HDR_TYPE_SEND); 747 shdr->hdr.subtype = htole32(0); 748 shdr->hdr.encrypted = iswep; 749 shdr->hdr.encrypt = 0; 750 shdr->hdr.keyidx = 0; 751 shdr->hdr.keysz = 0; 752 shdr->hdr.fragmentsz = htole16(0); 753 IEEE80211_ADDR_COPY(shdr->hdr.src_addr, wh->i_addr2); 754 if (ic->ic_opmode == IEEE80211_M_STA) 755 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr3); 756 else 757 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr1); 758 759 /* trim IEEE802.11 header */ 760 m_adj(m, sizeof (struct ieee80211_frame)); 761 762 /* 763 * We need to map the mbuf first to know how many buffer descriptors 764 * are needed for this transfer. 765 */ 766 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m, BUS_DMA_NOWAIT); 767 if (error != 0) { 768 aprint_error("%s: could not map mbuf (error %d)\n", 769 sc->sc_dev.dv_xname, error); 770 m_freem(m); 771 return error; 772 } 773 774 error = bus_dmamap_load(sc->sc_dmat, shdr->map, &shdr->hdr, 775 sizeof (struct ipw_hdr), NULL, BUS_DMA_NOWAIT); 776 if (error != 0) { 777 aprint_error("%s: could not map hdr (error %d)\n", 778 sc->sc_dev.dv_xname, error); 779 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 780 m_freem(m); 781 return error; 782 } 783 784 TAILQ_REMOVE(&sc->sc_free_sbuf, sbuf, next); 785 TAILQ_REMOVE(&sc->sc_free_shdr, shdr, next); 786 787 sbd = &sc->stbd_list[sc->txcur]; 788 sbd->type = IPW_SBD_TYPE_HEADER; 789 sbd->priv = shdr; 790 sbd->bd->physaddr = htole32(shdr->map->dm_segs[0].ds_addr); 791 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 792 sbd->bd->nfrag = 1 + sbuf->map->dm_nsegs; 793 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 794 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 795 796 DPRINTFN(5, ("TX!HDR!%u!%u!%u!%u\n", shdr->hdr.type, shdr->hdr.subtype, 797 shdr->hdr.encrypted, shdr->hdr.encrypt)); 798 DPRINTFN(5, ("!%s", ether_sprintf(shdr->hdr.src_addr))); 799 DPRINTFN(5, ("!%s\n", ether_sprintf(shdr->hdr.dst_addr))); 800 801 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 802 sc->txcur * sizeof (struct ipw_bd), 803 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 804 805 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 806 --sc->txfree; 807 808 sbuf->m = m; 809 sbuf->ni = ni; 810 811 for (i = 0; i < sbuf->map->dm_nsegs; i++) { 812 sbd = &sc->stbd_list[sc->txcur]; 813 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[i].ds_addr); 814 sbd->bd->len = htole32(sbuf->map->dm_segs[i].ds_len); 815 sbd->bd->nfrag = 0; /* used only in first bd */ 816 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 817 if (i == sbuf->map->dm_nsegs - 1) { 818 sbd->type = IPW_SBD_TYPE_DATA; 819 sbd->priv = sbuf; 820 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 821 } else { 822 sbd->type = IPW_SBD_TYPE_NOASSOC; 823 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 824 } 825 826 DPRINTFN(5, ("TX!FRAG!%d!%ld\n", i, 827 sbuf->map->dm_segs[i].ds_len)); 828 829 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 830 sc->txcur * sizeof (struct ipw_bd), 831 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 832 833 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 834 } 835 836 bus_dmamap_sync(sc->sc_dmat, shdr->map, 0, sizeof (struct ipw_hdr), 837 BUS_DMASYNC_PREWRITE); 838 839 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, MCLBYTES, 840 BUS_DMASYNC_PREWRITE); 841 842 /* Inform firmware about this new packet */ 843 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, sc->txcur); 844 845 return 0; 846 } 847 848 static void 849 ipw_start(struct ifnet *ifp) 850 { 851 struct ipw_softc *sc = ifp->if_softc; 852 struct ieee80211com *ic = &sc->sc_ic; 853 struct mbuf *m; 854 struct ieee80211_node *ni; 855 856 for (;;) { 857 if (!ipw_tx_ready(sc)) { 858 DPRINTFN(2, ("%s: no tx descriptors\n", ifp->if_xname)); 859 ifp->if_flags |= IFF_OACTIVE; 860 break; 861 } 862 IFQ_DEQUEUE(&ifp->if_snd, m); 863 if (m == NULL) 864 break; 865 866 #if NBPFILTER > 0 867 if (ifp->if_bpf != NULL) 868 bpf_mtap(ifp->if_bpf, m); 869 #endif 870 871 ni = ieee80211_find_txnode(ic, 872 mtod(m, struct ether_header *)->ether_dhost); 873 if (ni == NULL) { 874 /* NB: ieee80211_find_txnode does stat+msg */ 875 continue; 876 } 877 m = ieee80211_encap(ic, m, ni); 878 if (m == NULL) 879 continue; 880 881 #if NBPFILTER > 0 882 if (ic->ic_rawbpf != NULL) 883 bpf_mtap(ic->ic_rawbpf, m); 884 #endif 885 886 if (ipw_tx_start(ifp, m, ni) != 0) { 887 if (ni != NULL) 888 ieee80211_free_node(ni); 889 break; 890 } 891 892 /* start watchdog timer */ 893 sc->sc_tx_timer = 5; 894 ifp->if_timer = 1; 895 } 896 } 897 898 static void 899 ipw_watchdog(struct ifnet *ifp) 900 { 901 struct ipw_softc *sc = ifp->if_softc; 902 903 ifp->if_timer = 0; 904 905 if (sc->sc_tx_timer > 0) { 906 if (--sc->sc_tx_timer == 0) { 907 aprint_error("%s: device timeout\n", 908 sc->sc_dev.dv_xname); 909 #ifdef notyet 910 ipw_init(ifp); 911 #endif 912 return; 913 } 914 ifp->if_timer = 1; 915 } 916 917 ieee80211_watchdog(&sc->sc_ic); 918 } 919 920 static int 921 ipw_get_table1(struct ipw_softc *sc, u_int32_t *tbl) 922 { 923 u_int32_t addr, size, i; 924 925 if (!(sc->flags & IPW_FLAG_FW_INITED)) 926 return ENOTTY; 927 928 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, sc->table1_base); 929 930 size = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 931 if (suword(tbl, size) != 0) 932 return EFAULT; 933 934 for (i = 1, ++tbl; i < size; i++, tbl++) { 935 addr = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 936 if (suword(tbl, MEM_READ_4(sc, addr)) != 0) 937 return EFAULT; 938 } 939 return 0; 940 } 941 942 static int 943 ipw_get_radio(struct ipw_softc *sc, int *ret) 944 { 945 u_int32_t addr; 946 947 if (!(sc->flags & IPW_FLAG_FW_INITED)) 948 return ENOTTY; 949 950 addr = ipw_read_table1(sc, IPW_INFO_EEPROM_ADDRESS); 951 if ((MEM_READ_4(sc, addr + 32) >> 24) & 1) { 952 suword(ret, -1); 953 return 0; 954 } 955 956 if (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED) 957 suword(ret, 0); 958 else 959 suword(ret, 1); 960 961 return 0; 962 } 963 964 static int 965 ipw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 966 { 967 struct ipw_softc *sc = ifp->if_softc; 968 struct ifreq *ifr; 969 int s, error = 0; 970 971 s = splnet(); 972 973 switch (cmd) { 974 case SIOCSIFFLAGS: 975 if (ifp->if_flags & IFF_UP) { 976 if (!(ifp->if_flags & IFF_RUNNING)) 977 ipw_init(ifp); 978 } else { 979 if (ifp->if_flags & IFF_RUNNING) 980 ipw_stop(ifp, 1); 981 } 982 break; 983 984 case SIOCGTABLE1: 985 ifr = (struct ifreq *)data; 986 error = ipw_get_table1(sc, (u_int32_t *)ifr->ifr_data); 987 break; 988 989 case SIOCGRADIO: 990 ifr = (struct ifreq *)data; 991 error = ipw_get_radio(sc, (int *)ifr->ifr_data); 992 break; 993 994 case SIOCSLOADFW: 995 /* only super-user can do that! */ 996 if ((error = suser(curproc->p_ucred, &curproc->p_acflag)) != 0) 997 break; 998 999 ifr = (struct ifreq *)data; 1000 error = ipw_firmware_init(sc, (u_char *)ifr->ifr_data); 1001 break; 1002 1003 case SIOCSKILLFW: 1004 /* only super-user can do that! */ 1005 if ((error = suser(curproc->p_ucred, &curproc->p_acflag)) != 0) 1006 break; 1007 1008 ipw_reset(sc); 1009 break; 1010 1011 default: 1012 error = ieee80211_ioctl(&sc->sc_ic, cmd, data); 1013 if (error != ENETRESET) 1014 break; 1015 1016 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1017 (IFF_UP | IFF_RUNNING)) 1018 ipw_init(ifp); 1019 error = 0; 1020 } 1021 1022 splx(s); 1023 return error; 1024 } 1025 1026 static u_int32_t 1027 ipw_read_table1(struct ipw_softc *sc, u_int32_t off) 1028 { 1029 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 1030 } 1031 1032 static void 1033 ipw_write_table1(struct ipw_softc *sc, u_int32_t off, u_int32_t info) 1034 { 1035 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 1036 } 1037 1038 static int 1039 ipw_read_table2(struct ipw_softc *sc, u_int32_t off, void *buf, u_int32_t *len) 1040 { 1041 u_int32_t addr, info; 1042 u_int16_t count, size; 1043 u_int32_t total; 1044 1045 /* addr[4] + count[2] + size[2] */ 1046 addr = MEM_READ_4(sc, sc->table2_base + off); 1047 info = MEM_READ_4(sc, sc->table2_base + off + 4); 1048 1049 count = info >> 16; 1050 size = info & 0xffff; 1051 total = count * size; 1052 1053 if (total > *len) { 1054 *len = total; 1055 return EINVAL; 1056 } 1057 1058 *len = total; 1059 ipw_read_mem_1(sc, addr, buf, total); 1060 1061 return 0; 1062 } 1063 1064 static int 1065 ipw_tx_init(struct ipw_softc *sc) 1066 { 1067 const char *errmsg; 1068 struct ipw_bd *bd; 1069 struct ipw_soft_bd *sbd; 1070 struct ipw_soft_hdr *shdr; 1071 struct ipw_soft_buf *sbuf; 1072 int error, i, nsegs; 1073 1074 /* Allocate transmission buffer descriptors */ 1075 error = bus_dmamap_create(sc->sc_dmat, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, 1076 BUS_DMA_NOWAIT, &sc->tbd_map); 1077 if (error != 0) { 1078 errmsg = "could not create tbd dma map"; 1079 goto fail; 1080 } 1081 1082 error = bus_dmamem_alloc(sc->sc_dmat, IPW_TBD_SZ, PAGE_SIZE, 0, 1083 &sc->tbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 1084 if (error != 0) { 1085 errmsg = "could not allocate tbd dma memory"; 1086 goto fail; 1087 } 1088 1089 error = bus_dmamem_map(sc->sc_dmat, &sc->tbd_seg, nsegs, IPW_TBD_SZ, 1090 (caddr_t *)&sc->tbd_list, BUS_DMA_NOWAIT); 1091 if (error != 0) { 1092 errmsg = "could not map tbd dma memory"; 1093 goto fail; 1094 } 1095 1096 error = bus_dmamap_load(sc->sc_dmat, sc->tbd_map, sc->tbd_list, 1097 IPW_TBD_SZ, NULL, BUS_DMA_NOWAIT); 1098 if (error != 0) { 1099 errmsg = "could not load tbd dma memory"; 1100 goto fail; 1101 } 1102 1103 sc->stbd_list = malloc(IPW_NTBD * sizeof (struct ipw_soft_bd), 1104 M_DEVBUF, M_NOWAIT); 1105 if (sc->stbd_list == NULL) { 1106 errmsg = "could not allocate soft tbd"; 1107 error = ENOMEM; 1108 goto fail; 1109 } 1110 sbd = sc->stbd_list; 1111 bd = sc->tbd_list; 1112 for (i = 0; i < IPW_NTBD; i++, sbd++, bd++) { 1113 sbd->type = IPW_SBD_TYPE_NOASSOC; 1114 sbd->bd = bd; 1115 } 1116 1117 CSR_WRITE_4(sc, IPW_CSR_TX_BD_BASE, sc->tbd_map->dm_segs[0].ds_addr); 1118 CSR_WRITE_4(sc, IPW_CSR_TX_BD_SIZE, IPW_NTBD); 1119 CSR_WRITE_4(sc, IPW_CSR_TX_READ_INDEX, 0); 1120 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, 0); 1121 sc->txold = IPW_NTBD - 1; /* latest bd index ack'ed by firmware */ 1122 sc->txfree = IPW_NTBD; /* number of descriptors free */ 1123 sc->txcur = 0; /* bd index to write to */ 1124 1125 /* Allocate a DMA-able command */ 1126 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_cmd), 1, 1127 sizeof (struct ipw_cmd), 0, BUS_DMA_NOWAIT, &sc->cmd_map); 1128 if (error != 0) { 1129 errmsg = "could not create cmd dma map"; 1130 goto fail; 1131 } 1132 1133 error = bus_dmamem_alloc(sc->sc_dmat, sizeof (struct ipw_cmd), 1134 PAGE_SIZE, 0, &sc->cmd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 1135 if (error != 0) { 1136 errmsg = "could not allocate cmd dma memory"; 1137 goto fail; 1138 } 1139 1140 error = bus_dmamem_map(sc->sc_dmat, &sc->cmd_seg, nsegs, 1141 sizeof (struct ipw_cmd), (caddr_t *)&sc->cmd, BUS_DMA_NOWAIT); 1142 if (error != 0) { 1143 errmsg = "could not map cmd dma memory"; 1144 goto fail; 1145 } 1146 1147 /* Allocate a pool of DMA-able headers */ 1148 sc->shdr_list = malloc(IPW_NDATA * sizeof (struct ipw_soft_hdr), 1149 M_DEVBUF, M_NOWAIT); 1150 if (sc->shdr_list == NULL) { 1151 errmsg = "could not allocate soft hdr"; 1152 error = ENOMEM; 1153 goto fail; 1154 } 1155 TAILQ_INIT(&sc->sc_free_shdr); 1156 for (i = 0, shdr = sc->shdr_list; i < IPW_NDATA; i++, shdr++) { 1157 error = bus_dmamap_create(sc->sc_dmat, 1158 sizeof (struct ipw_soft_hdr), 1, 1159 sizeof (struct ipw_soft_hdr), 0, BUS_DMA_NOWAIT, 1160 &shdr->map); 1161 if (error != 0) { 1162 errmsg = "could not create hdr dma map"; 1163 goto fail; 1164 } 1165 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 1166 } 1167 1168 /* Allocate a pool of DMA-able buffers */ 1169 sc->tx_sbuf_list = malloc(IPW_NDATA * sizeof (struct ipw_soft_buf), 1170 M_DEVBUF, M_NOWAIT); 1171 if (sc->tx_sbuf_list == NULL) { 1172 errmsg = "could not allocate soft txbuf"; 1173 error = ENOMEM; 1174 goto fail; 1175 } 1176 TAILQ_INIT(&sc->sc_free_sbuf); 1177 for (i = 0, sbuf = sc->tx_sbuf_list; i < IPW_NDATA; i++, sbuf++) { 1178 error = bus_dmamap_create(sc->sc_dmat, IPW_NDATA * MCLBYTES, 1179 IPW_NDATA, MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 1180 if (error != 0) { 1181 errmsg = "could not create txbuf dma map"; 1182 goto fail; 1183 } 1184 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 1185 } 1186 1187 return 0; 1188 1189 fail: aprint_error("%s: %s\n", sc->sc_dev.dv_xname, errmsg); 1190 ipw_tx_stop(sc); 1191 1192 return error; 1193 } 1194 1195 static void 1196 ipw_tx_stop(struct ipw_softc *sc) 1197 { 1198 struct ipw_soft_hdr *shdr; 1199 struct ipw_soft_buf *sbuf; 1200 int i; 1201 1202 if (sc->tbd_map != NULL) { 1203 if (sc->tbd_list != NULL) { 1204 bus_dmamap_unload(sc->sc_dmat, sc->tbd_map); 1205 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->tbd_list, 1206 IPW_TBD_SZ); 1207 bus_dmamem_free(sc->sc_dmat, &sc->tbd_seg, 1); 1208 sc->tbd_list = NULL; 1209 } 1210 bus_dmamap_destroy(sc->sc_dmat, sc->tbd_map); 1211 sc->tbd_map = NULL; 1212 } 1213 1214 if (sc->stbd_list != NULL) { 1215 for (i = 0; i < IPW_NTBD; i++) 1216 ipw_release_sbd(sc, &sc->stbd_list[i]); 1217 free(sc->stbd_list, M_DEVBUF); 1218 sc->stbd_list = NULL; 1219 } 1220 1221 if (sc->cmd_map != NULL) { 1222 if (sc->cmd != NULL) { 1223 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->cmd, 1224 sizeof (struct ipw_cmd)); 1225 bus_dmamem_free(sc->sc_dmat, &sc->cmd_seg, 1); 1226 sc->cmd = NULL; 1227 } 1228 bus_dmamap_destroy(sc->sc_dmat, sc->cmd_map); 1229 sc->cmd_map = NULL; 1230 } 1231 1232 if (sc->shdr_list != NULL) { 1233 TAILQ_FOREACH(shdr, &sc->sc_free_shdr, next) 1234 bus_dmamap_destroy(sc->sc_dmat, shdr->map); 1235 free(sc->shdr_list, M_DEVBUF); 1236 sc->shdr_list = NULL; 1237 } 1238 1239 1240 if (sc->tx_sbuf_list != NULL) { 1241 TAILQ_FOREACH(sbuf, &sc->sc_free_sbuf, next) 1242 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 1243 free(sc->tx_sbuf_list, M_DEVBUF); 1244 sc->tx_sbuf_list = NULL; 1245 } 1246 } 1247 1248 static int 1249 ipw_rx_init(struct ipw_softc *sc) 1250 { 1251 const char *errmsg; 1252 struct ipw_bd *bd; 1253 struct ipw_soft_bd *sbd; 1254 struct ipw_soft_buf *sbuf; 1255 int error, i, nsegs; 1256 1257 /* Allocate reception buffer descriptors */ 1258 error = bus_dmamap_create(sc->sc_dmat, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, 1259 BUS_DMA_NOWAIT, &sc->rbd_map); 1260 if (error != 0) { 1261 errmsg = "could not create rbd dma map"; 1262 goto fail; 1263 } 1264 1265 error = bus_dmamem_alloc(sc->sc_dmat, IPW_RBD_SZ, PAGE_SIZE, 0, 1266 &sc->rbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 1267 if (error != 0) { 1268 errmsg = "could not allocate rbd dma memory"; 1269 goto fail; 1270 } 1271 1272 error = bus_dmamem_map(sc->sc_dmat, &sc->rbd_seg, nsegs, IPW_RBD_SZ, 1273 (caddr_t *)&sc->rbd_list, BUS_DMA_NOWAIT); 1274 if (error != 0) { 1275 errmsg = "could not map rbd dma memory"; 1276 goto fail; 1277 } 1278 1279 error = bus_dmamap_load(sc->sc_dmat, sc->rbd_map, sc->rbd_list, 1280 IPW_RBD_SZ, NULL, BUS_DMA_NOWAIT); 1281 if (error != 0) { 1282 errmsg = "could not load rbd dma memory"; 1283 goto fail; 1284 } 1285 1286 sc->srbd_list = malloc(IPW_NRBD * sizeof (struct ipw_soft_bd), 1287 M_DEVBUF, M_NOWAIT); 1288 if (sc->srbd_list == NULL) { 1289 errmsg = "could not allocate soft rbd"; 1290 error = ENOMEM; 1291 goto fail; 1292 } 1293 sbd = sc->srbd_list; 1294 bd = sc->rbd_list; 1295 for (i = 0; i < IPW_NRBD; i++, sbd++, bd++) { 1296 sbd->type = IPW_SBD_TYPE_NOASSOC; 1297 sbd->bd = bd; 1298 } 1299 1300 CSR_WRITE_4(sc, IPW_CSR_RX_BD_BASE, sc->rbd_map->dm_segs[0].ds_addr); 1301 CSR_WRITE_4(sc, IPW_CSR_RX_BD_SIZE, IPW_NRBD); 1302 CSR_WRITE_4(sc, IPW_CSR_RX_READ_INDEX, 0); 1303 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE_INDEX, IPW_NRBD - 1); 1304 sc->rxcur = IPW_NRBD - 1; /* latest bd index I've read */ 1305 1306 /* Allocate status descriptors */ 1307 error = bus_dmamap_create(sc->sc_dmat, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 1308 0, BUS_DMA_NOWAIT, &sc->status_map); 1309 if (error != 0) { 1310 errmsg = "could not create status dma map"; 1311 goto fail; 1312 } 1313 1314 error = bus_dmamem_alloc(sc->sc_dmat, IPW_STATUS_SZ, PAGE_SIZE, 0, 1315 &sc->status_seg, 1, &nsegs, BUS_DMA_NOWAIT); 1316 if (error != 0) { 1317 errmsg = "could not allocate status dma memory"; 1318 goto fail; 1319 } 1320 1321 error = bus_dmamem_map(sc->sc_dmat, &sc->status_seg, nsegs, 1322 IPW_STATUS_SZ, (caddr_t *)&sc->status_list, BUS_DMA_NOWAIT); 1323 if (error != 0) { 1324 errmsg = "could not map status dma memory"; 1325 goto fail; 1326 } 1327 1328 error = bus_dmamap_load(sc->sc_dmat, sc->status_map, sc->status_list, 1329 IPW_STATUS_SZ, NULL, BUS_DMA_NOWAIT); 1330 if (error != 0) { 1331 errmsg = "could not load status dma memory"; 1332 goto fail; 1333 } 1334 1335 CSR_WRITE_4(sc, IPW_CSR_RX_STATUS_BASE, 1336 sc->status_map->dm_segs[0].ds_addr); 1337 1338 sc->rx_sbuf_list = malloc(IPW_NRBD * sizeof (struct ipw_soft_buf), 1339 M_DEVBUF, M_NOWAIT); 1340 if (sc->rx_sbuf_list == NULL) { 1341 errmsg = "could not allocate soft rxbuf"; 1342 error = ENOMEM; 1343 goto fail; 1344 } 1345 1346 sbuf = sc->rx_sbuf_list; 1347 sbd = sc->srbd_list; 1348 for (i = 0; i < IPW_NRBD; i++, sbuf++, sbd++) { 1349 1350 MGETHDR(sbuf->m, M_DONTWAIT, MT_DATA); 1351 if (sbuf->m == NULL) { 1352 errmsg = "could not allocate rx mbuf"; 1353 error = ENOMEM; 1354 goto fail; 1355 } 1356 MCLGET(sbuf->m, M_DONTWAIT); 1357 if (!(sbuf->m->m_flags & M_EXT)) { 1358 m_freem(sbuf->m); 1359 errmsg = "could not allocate rx mbuf cluster"; 1360 error = ENOMEM; 1361 goto fail; 1362 } 1363 1364 error = bus_dmamap_create(sc->sc_dmat, IPW_NRBD * MCLBYTES, 1365 IPW_NRBD, MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 1366 if (error != 0) { 1367 m_freem(sbuf->m); 1368 errmsg = "could not create rxbuf dma map"; 1369 goto fail; 1370 } 1371 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, 1372 mtod(sbuf->m, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 1373 if (error != 0) { 1374 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 1375 m_freem(sbuf->m); 1376 errmsg = "could not map rxbuf dma memory"; 1377 goto fail; 1378 } 1379 sbd->type = IPW_SBD_TYPE_DATA; 1380 sbd->priv = sbuf; 1381 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 1382 sbd->bd->len = htole32(MCLBYTES); 1383 } 1384 1385 return 0; 1386 1387 fail: aprint_error("%s: %s\n", sc->sc_dev.dv_xname, errmsg); 1388 ipw_rx_stop(sc); 1389 1390 return error; 1391 } 1392 1393 static void 1394 ipw_rx_stop(struct ipw_softc *sc) 1395 { 1396 struct ipw_soft_bd *sbd; 1397 struct ipw_soft_buf *sbuf; 1398 int i; 1399 1400 if (sc->rbd_map != NULL) { 1401 if (sc->rbd_list != NULL) { 1402 bus_dmamap_unload(sc->sc_dmat, sc->rbd_map); 1403 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->rbd_list, 1404 IPW_RBD_SZ); 1405 bus_dmamem_free(sc->sc_dmat, &sc->rbd_seg, 1); 1406 sc->rbd_list = NULL; 1407 } 1408 bus_dmamap_destroy(sc->sc_dmat, sc->rbd_map); 1409 sc->rbd_map = NULL; 1410 } 1411 1412 if (sc->status_map != NULL) { 1413 if (sc->status_list != NULL) { 1414 bus_dmamap_unload(sc->sc_dmat, sc->status_map); 1415 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->status_list, 1416 IPW_STATUS_SZ); 1417 bus_dmamem_free(sc->sc_dmat, &sc->status_seg, 1); 1418 sc->status_list = NULL; 1419 } 1420 bus_dmamap_destroy(sc->sc_dmat, sc->status_map); 1421 sc->status_map = NULL; 1422 } 1423 1424 if (sc->srbd_list != NULL) { 1425 for (i = 0, sbd = sc->srbd_list; i < IPW_NRBD; i++, sbd++) { 1426 if (sbd->type == IPW_SBD_TYPE_NOASSOC) 1427 continue; 1428 1429 sbuf = sbd->priv; 1430 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1431 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 1432 m_freem(sbuf->m); 1433 } 1434 free(sc->srbd_list, M_DEVBUF); 1435 sc->srbd_list = NULL; 1436 } 1437 1438 if (sc->rx_sbuf_list != NULL) { 1439 free(sc->rx_sbuf_list, M_DEVBUF); 1440 sc->rx_sbuf_list = NULL; 1441 } 1442 } 1443 1444 static void 1445 ipw_reset(struct ipw_softc *sc) 1446 { 1447 struct ifnet *ifp = &sc->sc_if; 1448 int ntries; 1449 1450 ipw_stop(ifp, 1); 1451 1452 if (sc->flags & IPW_FLAG_FW_INITED) { 1453 ipw_cmd(sc, IPW_CMD_DISABLE_PHY, NULL, 0); 1454 ipw_cmd(sc, IPW_CMD_PREPARE_POWER_DOWN, NULL, 0); 1455 1456 sc->flags &= ~IPW_FLAG_FW_INITED; 1457 } 1458 1459 /* Disable interrupts */ 1460 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1461 1462 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1463 for (ntries = 0; ntries < 5; ntries++) { 1464 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1465 break; 1466 DELAY(10); 1467 } 1468 1469 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 1470 1471 ipw_rx_stop(sc); 1472 ipw_tx_stop(sc); 1473 1474 ifp->if_flags &= ~IFF_UP; 1475 } 1476 1477 static int 1478 ipw_clock_sync(struct ipw_softc *sc) 1479 { 1480 int ntries; 1481 u_int32_t r; 1482 1483 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 1484 for (ntries = 0; ntries < 1000; ntries++) { 1485 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_PRINCETON_RESET) 1486 break; 1487 DELAY(10); 1488 } 1489 if (ntries == 1000) 1490 return EIO; 1491 1492 CSR_WRITE_4(sc, IPW_CSR_CTL, IPW_CTL_INIT_DONE); 1493 for (ntries = 0; ntries < 1000; ntries++) { 1494 if ((r = CSR_READ_4(sc, IPW_CSR_CTL)) & IPW_CTL_CLOCK_READY) 1495 break; 1496 DELAY(200); 1497 } 1498 if (ntries == 1000) 1499 return EIO; 1500 1501 CSR_WRITE_4(sc, IPW_CSR_CTL, r | IPW_CTL_ALLOW_STANDBY); 1502 1503 return 0; 1504 } 1505 1506 static int 1507 ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size) 1508 { 1509 int ntries; 1510 1511 MEM_WRITE_2(sc, 0x220000, 0x0703); 1512 MEM_WRITE_2(sc, 0x220000, 0x0707); 1513 1514 MEM_WRITE_1(sc, 0x210014, 0x72); 1515 MEM_WRITE_1(sc, 0x210014, 0x72); 1516 1517 MEM_WRITE_1(sc, 0x210000, 0x40); 1518 MEM_WRITE_1(sc, 0x210000, 0x00); 1519 MEM_WRITE_1(sc, 0x210000, 0x40); 1520 1521 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1522 1523 MEM_WRITE_1(sc, 0x210000, 0x00); 1524 MEM_WRITE_1(sc, 0x210000, 0x00); 1525 MEM_WRITE_1(sc, 0x210000, 0x80); 1526 1527 MEM_WRITE_2(sc, 0x220000, 0x0703); 1528 MEM_WRITE_2(sc, 0x220000, 0x0707); 1529 1530 MEM_WRITE_1(sc, 0x210014, 0x72); 1531 MEM_WRITE_1(sc, 0x210014, 0x72); 1532 1533 MEM_WRITE_1(sc, 0x210000, 0x00); 1534 MEM_WRITE_1(sc, 0x210000, 0x80); 1535 1536 for (ntries = 0; ntries < 10; ntries++) { 1537 if (MEM_READ_1(sc, 0x210000) & 1) 1538 break; 1539 DELAY(10); 1540 } 1541 if (ntries == 10) 1542 return EIO; 1543 1544 return 0; 1545 } 1546 1547 /* set of macros to handle unaligned little endian data in firmware image */ 1548 #define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1549 #define GETLE16(p) ((p)[0] | (p)[1] << 8) 1550 static int 1551 ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size) 1552 { 1553 u_char *p, *end; 1554 u_int32_t addr; 1555 u_int16_t len; 1556 1557 p = fw; 1558 end = fw + size; 1559 while (p < end) { 1560 if (p + 6 > end) 1561 return EINVAL; 1562 1563 addr = GETLE32(p); 1564 p += 4; 1565 len = GETLE16(p); 1566 p += 2; 1567 1568 if (p + len > end) 1569 return EINVAL; 1570 1571 ipw_write_mem_1(sc, addr, p, len); 1572 p += len; 1573 } 1574 return 0; 1575 } 1576 1577 static int 1578 ipw_firmware_init(struct ipw_softc *sc, u_char *data) 1579 { 1580 struct ieee80211com *ic = &sc->sc_ic; 1581 struct ifnet *ifp = &sc->sc_if; 1582 struct ipw_fw_hdr hdr; 1583 u_int32_t r, len, fw_size, uc_size; 1584 u_char *fw, *uc; 1585 int error; 1586 1587 ipw_reset(sc); 1588 1589 if ((error = copyin(data, &hdr, sizeof hdr)) != 0) 1590 goto fail1; 1591 1592 fw_size = le32toh(hdr.fw_size); 1593 uc_size = le32toh(hdr.uc_size); 1594 data += sizeof hdr; 1595 1596 if ((fw = malloc(fw_size, M_DEVBUF, M_NOWAIT)) == NULL) { 1597 error = ENOMEM; 1598 goto fail1; 1599 } 1600 1601 if ((error = copyin(data, fw, fw_size)) != 0) 1602 goto fail2; 1603 1604 data += fw_size; 1605 1606 if ((uc = malloc(uc_size, M_DEVBUF, M_NOWAIT)) == NULL) { 1607 error = ENOMEM; 1608 goto fail2; 1609 } 1610 1611 if ((error = copyin(data, uc, uc_size)) != 0) 1612 goto fail3; 1613 1614 if ((error = ipw_clock_sync(sc)) != 0) { 1615 aprint_error("%s: clock synchronization failed\n", 1616 sc->sc_dev.dv_xname); 1617 goto fail3; 1618 } 1619 1620 MEM_WRITE_4(sc, 0x003000e0, 0x80000000); 1621 1622 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1623 1624 if ((error = ipw_load_ucode(sc, uc, uc_size)) != 0) { 1625 aprint_error("%s: could not load microcode\n", 1626 sc->sc_dev.dv_xname); 1627 goto fail3; 1628 } 1629 1630 MEM_WRITE_4(sc, 0x003000e0, 0); 1631 1632 if ((error = ipw_clock_sync(sc)) != 0) { 1633 aprint_error("%s: clock synchronization failed\n", 1634 sc->sc_dev.dv_xname); 1635 goto fail3; 1636 } 1637 1638 if ((error = ipw_load_firmware(sc, fw, fw_size))) { 1639 aprint_error("%s: could not load firmware\n", 1640 sc->sc_dev.dv_xname); 1641 goto fail3; 1642 } 1643 1644 ipw_zero_mem_4(sc, 0x0002f200, 196); 1645 ipw_zero_mem_4(sc, 0x0002f610, 8); 1646 ipw_zero_mem_4(sc, 0x0002fa00, 8); 1647 ipw_zero_mem_4(sc, 0x0002fc00, 4); 1648 ipw_zero_mem_4(sc, 0x0002ff80, 32); 1649 1650 if ((error = ipw_rx_init(sc)) != 0) { 1651 aprint_error("%s: could not initialize rx queue\n", 1652 sc->sc_dev.dv_xname); 1653 goto fail3; 1654 } 1655 1656 if ((error = ipw_tx_init(sc)) != 0) { 1657 aprint_error("%s: could not initialize tx queue\n", 1658 sc->sc_dev.dv_xname); 1659 goto fail3; 1660 } 1661 1662 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1663 IPW_IO_LED_OFF); 1664 1665 /* Enable interrupts */ 1666 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1667 1668 /* Let's go! */ 1669 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1670 1671 /* Wait at most 5 seconds for firmware initialization to complete */ 1672 if ((error = tsleep(sc, 0, "ipwinit", 5 * hz)) != 0) { 1673 aprint_error("%s: timeout waiting for firmware initialization " 1674 "to complete\n", sc->sc_dev.dv_xname); 1675 goto fail3; 1676 } 1677 1678 /* Firmware initialization completed */ 1679 sc->flags |= IPW_FLAG_FW_INITED; 1680 1681 free(uc, M_DEVBUF); 1682 free(fw, M_DEVBUF); 1683 1684 r = CSR_READ_4(sc, IPW_CSR_IO); 1685 CSR_WRITE_4(sc, IPW_CSR_IO, r | IPW_IO_GPIO1_MASK | IPW_IO_GPIO3_MASK); 1686 1687 /* Retrieve information tables base addresses */ 1688 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 1689 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 1690 1691 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 1692 1693 /* Retrieve adapter MAC address */ 1694 len = IEEE80211_ADDR_LEN; 1695 ipw_read_table2(sc, IPW_INFO_ADAPTER_MAC, ic->ic_myaddr, &len); 1696 1697 IEEE80211_ADDR_COPY(LLADDR(ifp->if_sadl), ic->ic_myaddr); 1698 1699 return 0; 1700 1701 fail3: free(uc, M_DEVBUF); 1702 fail2: free(fw, M_DEVBUF); 1703 fail1: ipw_reset(sc); 1704 1705 return error; 1706 } 1707 1708 static int 1709 ipw_config(struct ipw_softc *sc) 1710 { 1711 struct ieee80211com *ic = &sc->sc_ic; 1712 struct ifnet *ifp = &sc->sc_if; 1713 struct ipw_security security; 1714 struct ieee80211_key *k; 1715 struct ipw_wep_key wepkey; 1716 struct ipw_scan_options options; 1717 struct ipw_configuration config; 1718 u_int32_t data; 1719 int error, i; 1720 1721 switch (ic->ic_opmode) { 1722 case IEEE80211_M_STA: 1723 case IEEE80211_M_HOSTAP: 1724 data = htole32(IPW_MODE_BSS); 1725 break; 1726 1727 case IEEE80211_M_IBSS: 1728 case IEEE80211_M_AHDEMO: 1729 data = htole32(IPW_MODE_IBSS); 1730 break; 1731 1732 case IEEE80211_M_MONITOR: 1733 data = htole32(IPW_MODE_MONITOR); 1734 break; 1735 } 1736 DPRINTF(("Setting adapter mode to %u\n", data)); 1737 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 1738 if (error != 0) 1739 return error; 1740 1741 if (ic->ic_opmode == IEEE80211_M_IBSS || 1742 ic->ic_opmode == IEEE80211_M_MONITOR) { 1743 data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); 1744 DPRINTF(("Setting adapter channel to %u\n", data)); 1745 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 1746 if (error != 0) 1747 return error; 1748 } 1749 1750 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1751 DPRINTF(("Enabling adapter\n")); 1752 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1753 } 1754 1755 DPRINTF(("Setting adapter MAC to %s\n", ether_sprintf(ic->ic_myaddr))); 1756 IEEE80211_ADDR_COPY(LLADDR(ifp->if_sadl), ic->ic_myaddr); 1757 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 1758 IEEE80211_ADDR_LEN); 1759 if (error != 0) 1760 return error; 1761 1762 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 1763 IPW_CFG_PREAMBLE_LEN | IPW_CFG_802_1x_ENABLE); 1764 if (ic->ic_opmode == IEEE80211_M_IBSS) 1765 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 1766 if (ifp->if_flags & IFF_PROMISC) 1767 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 1768 config.channels = htole32(0x3fff); /* channels 1-14 */ 1769 config.ibss_chan = htole32(0x7ff); 1770 DPRINTF(("Setting adapter configuration 0x%08x\n", config.flags)); 1771 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 1772 if (error != 0) 1773 return error; 1774 1775 data = htole32(0x3); /* 1, 2 */ 1776 DPRINTF(("Setting adapter basic tx rates to 0x%x\n", data)); 1777 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 1778 if (error != 0) 1779 return error; 1780 1781 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 1782 DPRINTF(("Setting adapter tx rates to 0x%x\n", data)); 1783 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 1784 if (error != 0) 1785 return error; 1786 1787 data = htole32(IPW_POWER_MODE_CAM); 1788 DPRINTF(("Setting adapter power mode to %u\n", data)); 1789 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 1790 if (error != 0) 1791 return error; 1792 1793 if (ic->ic_opmode == IEEE80211_M_IBSS) { 1794 data = htole32(ic->ic_bss->ni_txpower); 1795 DPRINTF(("Setting adapter tx power index to %u\n", data)); 1796 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 1797 sizeof data); 1798 if (error != 0) 1799 return error; 1800 } 1801 1802 data = htole32(ic->ic_rtsthreshold); 1803 DPRINTF(("Setting adapter RTS threshold to %u\n", data)); 1804 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 1805 if (error != 0) 1806 return error; 1807 1808 data = htole32(ic->ic_fragthreshold); 1809 DPRINTF(("Setting adapter frag threshold to %u\n", data)); 1810 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 1811 if (error != 0) 1812 return error; 1813 1814 #ifdef IPW_DEBUG 1815 if (ipw_debug > 0) { 1816 printf("Setting adapter ESSID to "); 1817 ieee80211_print_essid(ic->ic_des_essid, ic->ic_des_esslen); 1818 printf("\n"); 1819 } 1820 #endif 1821 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ic->ic_des_essid, 1822 ic->ic_des_esslen); 1823 if (error != 0) 1824 return error; 1825 1826 /* no mandatory BSSID */ 1827 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 1828 if (error != 0) 1829 return error; 1830 1831 if (ic->ic_flags & IEEE80211_F_DESBSSID) { 1832 DPRINTF(("Setting adapter desired BSSID to %s\n", 1833 ether_sprintf(ic->ic_des_bssid))); 1834 error = ipw_cmd(sc, IPW_CMD_SET_DESIRED_BSSID, 1835 ic->ic_des_bssid, IEEE80211_ADDR_LEN); 1836 if (error != 0) 1837 return error; 1838 } 1839 1840 security.authmode = IPW_AUTH_OPEN; 1841 security.ciphers = htole32(IPW_CIPHER_NONE); 1842 security.version = htole16(0); 1843 security.replay_counters_number = 0; 1844 security.unicast_using_group = 0; 1845 DPRINTF(("Setting adapter authmode to %u\n", security.authmode)); 1846 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 1847 sizeof security); 1848 if (error != 0) 1849 return error; 1850 1851 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 1852 k = ic->ic_nw_keys; 1853 for (i = 0; i < IEEE80211_WEP_NKID; i++, k++) { 1854 if (k->wk_keylen == 0) 1855 continue; 1856 1857 wepkey.idx = i; 1858 wepkey.len = k->wk_keylen; 1859 bzero(wepkey.key, sizeof wepkey.key); 1860 bcopy(k->wk_key, wepkey.key, k->wk_keylen); 1861 DPRINTF(("Setting wep key index %d len %d\n", 1862 wepkey.idx, wepkey.len)); 1863 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY, &wepkey, 1864 sizeof wepkey); 1865 if (error != 0) 1866 return error; 1867 } 1868 1869 data = htole32(ic->ic_def_txkey); 1870 DPRINTF(("Setting adapter tx key index to %u\n", data)); 1871 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY_INDEX, &data, 1872 sizeof data); 1873 if (error != 0) 1874 return error; 1875 } 1876 1877 data = htole32((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) ? 0x8 : 0); 1878 DPRINTF(("Setting adapter wep flags to 0x%x\n", data)); 1879 error = ipw_cmd(sc, IPW_CMD_SET_WEP_FLAGS, &data, sizeof data); 1880 if (error != 0) 1881 return error; 1882 1883 if (ic->ic_opmode == IEEE80211_M_IBSS || 1884 ic->ic_opmode == IEEE80211_M_HOSTAP) { 1885 data = htole32(ic->ic_lintval); 1886 DPRINTF(("Setting adapter beacon interval to %u\n", data)); 1887 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 1888 sizeof data); 1889 if (error != 0) 1890 return error; 1891 } 1892 1893 options.flags = htole32(0); 1894 options.channels = htole32(0x3fff); /* scan channels 1-14 */ 1895 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &options, sizeof options); 1896 if (error != 0) 1897 return error; 1898 1899 /* finally, enable adapter (start scanning for an access point) */ 1900 DPRINTF(("Enabling adapter\n")); 1901 error = ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1902 if (error != 0) 1903 return error; 1904 1905 return 0; 1906 } 1907 1908 static int 1909 ipw_init(struct ifnet *ifp) 1910 { 1911 struct ipw_softc *sc = ifp->if_softc; 1912 struct ieee80211com *ic = &sc->sc_ic; 1913 1914 /* exit immediately if firmware has not been ioctl'd */ 1915 if (!(sc->flags & IPW_FLAG_FW_INITED)) { 1916 ifp->if_flags &= ~IFF_UP; 1917 return EIO; 1918 } 1919 1920 ipw_stop(ifp, 0); 1921 1922 if (ipw_config(sc) != 0) { 1923 aprint_error("%s: device configuration failed\n", 1924 sc->sc_dev.dv_xname); 1925 goto fail; 1926 } 1927 1928 ifp->if_flags &= ~IFF_OACTIVE; 1929 ifp->if_flags |= IFF_RUNNING; 1930 1931 ic->ic_bss->ni_chan = ic->ic_channels; 1932 1933 return 0; 1934 1935 fail: ipw_stop(ifp, 0); 1936 1937 return EIO; 1938 } 1939 1940 static void 1941 ipw_stop(struct ifnet *ifp, int disable) 1942 { 1943 struct ipw_softc *sc = ifp->if_softc; 1944 struct ieee80211com *ic = &sc->sc_ic; 1945 1946 if (ifp->if_flags & IFF_RUNNING) { 1947 DPRINTF(("Disabling adapter\n")); 1948 ipw_cmd(sc, IPW_CMD_DISABLE, NULL, 0); 1949 } 1950 1951 ifp->if_timer = 0; 1952 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1953 1954 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1955 } 1956 1957 static void 1958 ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, u_int8_t *datap, 1959 bus_size_t count) 1960 { 1961 for (; count > 0; offset++, datap++, count--) { 1962 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 1963 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 1964 } 1965 } 1966 1967 static void 1968 ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, u_int8_t *datap, 1969 bus_size_t count) 1970 { 1971 for (; count > 0; offset++, datap++, count--) { 1972 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 1973 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 1974 } 1975 } 1976 1977 static void 1978 ipw_zero_mem_4(struct ipw_softc *sc, bus_size_t offset, bus_size_t count) 1979 { 1980 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, offset); 1981 while (count-- > 0) 1982 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_DATA, 0); 1983 } 1984 1985
Indexes created Tue Sep 30 20:09:53 GMT 2025