if_ipw.c revision 1.23
1 /* $NetBSD: if_ipw.c,v 1.23 2006/04/29 16:43:40 rpaulo Exp $ */ 2 /* FreeBSD: src/sys/dev/ipw/if_ipw.c,v 1.15 2005/11/13 17:17:40 damien Exp */ 3 4 /*- 5 * Copyright (c) 2004, 2005 6 * Damien Bergamini <damien.bergamini (at) free.fr>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: if_ipw.c,v 1.23 2006/04/29 16:43:40 rpaulo Exp $"); 33 34 /*- 35 * Intel(R) PRO/Wireless 2100 MiniPCI driver 36 * http://www.intel.com/network/connectivity/products/wireless/prowireless_mobile.htm 37 */ 38 39 #include "bpfilter.h" 40 41 #include <sys/param.h> 42 #include <sys/sockio.h> 43 #include <sys/sysctl.h> 44 #include <sys/mbuf.h> 45 #include <sys/kernel.h> 46 #include <sys/socket.h> 47 #include <sys/systm.h> 48 #include <sys/malloc.h> 49 #include <sys/conf.h> 50 51 #include <machine/bus.h> 52 #include <machine/endian.h> 53 #include <machine/intr.h> 54 55 #include <dev/pci/pcireg.h> 56 #include <dev/pci/pcivar.h> 57 #include <dev/pci/pcidevs.h> 58 59 #if NBPFILTER > 0 60 #include <net/bpf.h> 61 #endif 62 #include <net/if.h> 63 #include <net/if_arp.h> 64 #include <net/if_dl.h> 65 #include <net/if_ether.h> 66 #include <net/if_media.h> 67 #include <net/if_types.h> 68 69 #include <net80211/ieee80211_var.h> 70 #include <net80211/ieee80211_radiotap.h> 71 72 #include <netinet/in.h> 73 #include <netinet/in_systm.h> 74 #include <netinet/in_var.h> 75 #include <netinet/ip.h> 76 77 #include <dev/firmload.h> 78 79 #include <dev/pci/if_ipwreg.h> 80 #include <dev/pci/if_ipwvar.h> 81 82 #ifdef IPW_DEBUG 83 #define DPRINTF(x) if (ipw_debug > 0) printf x 84 #define DPRINTFN(n, x) if (ipw_debug >= (n)) printf x 85 int ipw_debug = 0; 86 #else 87 #define DPRINTF(x) 88 #define DPRINTFN(n, x) 89 #endif 90 91 static int ipw_dma_alloc(struct ipw_softc *); 92 static void ipw_release(struct ipw_softc *); 93 static int ipw_match(struct device *, struct cfdata *, void *); 94 static void ipw_attach(struct device *, struct device *, void *); 95 static int ipw_detach(struct device *, int); 96 97 static void ipw_shutdown(void *); 98 static int ipw_suspend(struct ipw_softc *); 99 static int ipw_resume(struct ipw_softc *); 100 static void ipw_powerhook(int, void *); 101 102 static int ipw_media_change(struct ifnet *); 103 static void ipw_media_status(struct ifnet *, struct ifmediareq *); 104 static int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 105 static uint16_t ipw_read_prom_word(struct ipw_softc *, uint8_t); 106 static void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 107 static void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 108 static void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 109 struct ipw_soft_bd *, struct ipw_soft_buf *); 110 static void ipw_rx_intr(struct ipw_softc *); 111 static void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 112 static void ipw_tx_intr(struct ipw_softc *); 113 static int ipw_intr(void *); 114 static int ipw_cmd(struct ipw_softc *, uint32_t, void *, uint32_t); 115 static int ipw_tx_start(struct ifnet *, struct mbuf *, 116 struct ieee80211_node *); 117 static void ipw_start(struct ifnet *); 118 static void ipw_watchdog(struct ifnet *); 119 static int ipw_ioctl(struct ifnet *, u_long, caddr_t); 120 static int ipw_get_table1(struct ipw_softc *, uint32_t *); 121 static int ipw_get_radio(struct ipw_softc *, int *); 122 static void ipw_stop_master(struct ipw_softc *); 123 static int ipw_reset(struct ipw_softc *); 124 static int ipw_load_ucode(struct ipw_softc *, u_char *, int); 125 static int ipw_load_firmware(struct ipw_softc *, u_char *, int); 126 static int ipw_cache_firmware(struct ipw_softc *); 127 static void ipw_free_firmware(struct ipw_softc *); 128 static int ipw_config(struct ipw_softc *); 129 static int ipw_init(struct ifnet *); 130 static void ipw_stop(struct ifnet *, int); 131 static uint32_t ipw_read_table1(struct ipw_softc *, uint32_t); 132 static void ipw_write_table1(struct ipw_softc *, uint32_t, uint32_t); 133 static int ipw_read_table2(struct ipw_softc *, uint32_t, void *, uint32_t *); 134 static void ipw_read_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 135 bus_size_t); 136 static void ipw_write_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 137 bus_size_t); 138 139 /* 140 * Supported rates for 802.11b mode (in 500Kbps unit). 141 */ 142 static const struct ieee80211_rateset ipw_rateset_11b = 143 { 4, { 2, 4, 11, 22 } }; 144 145 static inline uint8_t 146 MEM_READ_1(struct ipw_softc *sc, uint32_t addr) 147 { 148 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 149 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); 150 } 151 152 static inline uint32_t 153 MEM_READ_4(struct ipw_softc *sc, uint32_t addr) 154 { 155 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 156 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); 157 } 158 159 CFATTACH_DECL(ipw, sizeof (struct ipw_softc), ipw_match, ipw_attach, 160 ipw_detach, NULL); 161 162 static int 163 ipw_match(struct device *parent, struct cfdata *match, void *aux) 164 { 165 struct pci_attach_args *pa = aux; 166 167 if (PCI_VENDOR (pa->pa_id) == PCI_VENDOR_INTEL && 168 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_PRO_WL_2100) 169 return 1; 170 171 return 0; 172 } 173 174 /* Base Address Register */ 175 #define IPW_PCI_BAR0 0x10 176 177 static void 178 ipw_attach(struct device *parent, struct device *self, void *aux) 179 { 180 struct ipw_softc *sc = (struct ipw_softc *)self; 181 struct ieee80211com *ic = &sc->sc_ic; 182 struct ifnet *ifp = &sc->sc_if; 183 struct pci_attach_args *pa = aux; 184 const char *intrstr; 185 char devinfo[256]; 186 bus_space_tag_t memt; 187 bus_space_handle_t memh; 188 bus_addr_t base; 189 pci_intr_handle_t ih; 190 uint32_t data; 191 uint16_t val; 192 int i, revision, error; 193 194 sc->sc_pct = pa->pa_pc; 195 sc->sc_pcitag = pa->pa_tag; 196 197 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof devinfo); 198 revision = PCI_REVISION(pa->pa_class); 199 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, revision); 200 201 /* enable bus-mastering */ 202 data = pci_conf_read(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG); 203 data |= PCI_COMMAND_MASTER_ENABLE; 204 pci_conf_write(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG, data); 205 206 /* clear device specific PCI configuration register 0x41 */ 207 data = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 208 data &= ~0x0000ff00; 209 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, data); 210 211 /* map the register window */ 212 error = pci_mapreg_map(pa, IPW_PCI_BAR0, PCI_MAPREG_TYPE_MEM | 213 PCI_MAPREG_MEM_TYPE_32BIT, 0, &memt, &memh, &base, &sc->sc_sz); 214 if (error != 0) { 215 aprint_error("%s: could not map memory space\n", 216 sc->sc_dev.dv_xname); 217 return; 218 } 219 220 sc->sc_st = memt; 221 sc->sc_sh = memh; 222 sc->sc_dmat = pa->pa_dmat; 223 strlcpy(sc->sc_fwname, "ipw2100-1.2.fw", sizeof(sc->sc_fwname)); 224 225 /* disable interrupts */ 226 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 227 228 if (pci_intr_map(pa, &ih) != 0) { 229 aprint_error("%s: could not map interrupt\n", 230 sc->sc_dev.dv_xname); 231 return; 232 } 233 234 intrstr = pci_intr_string(sc->sc_pct, ih); 235 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, ipw_intr, sc); 236 if (sc->sc_ih == NULL) { 237 aprint_error("%s: could not establish interrupt", 238 sc->sc_dev.dv_xname); 239 if (intrstr != NULL) 240 aprint_error(" at %s", intrstr); 241 aprint_error("\n"); 242 return; 243 } 244 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 245 246 if (ipw_reset(sc) != 0) { 247 aprint_error("%s: could not reset adapter\n", 248 sc->sc_dev.dv_xname); 249 goto fail; 250 } 251 252 if (ipw_dma_alloc(sc) != 0) { 253 aprint_error("%s: could not allocate DMA resources\n", 254 sc->sc_dev.dv_xname); 255 goto fail; 256 } 257 258 ifp->if_softc = sc; 259 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 260 ifp->if_init = ipw_init; 261 ifp->if_stop = ipw_stop; 262 ifp->if_ioctl = ipw_ioctl; 263 ifp->if_start = ipw_start; 264 ifp->if_watchdog = ipw_watchdog; 265 IFQ_SET_READY(&ifp->if_snd); 266 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 267 268 ic->ic_ifp = ifp; 269 ic->ic_phytype = IEEE80211_T_DS; 270 ic->ic_opmode = IEEE80211_M_STA; 271 ic->ic_state = IEEE80211_S_INIT; 272 273 /* set device capabilities */ 274 ic->ic_caps = IEEE80211_C_SHPREAMBLE | IEEE80211_C_TXPMGT | 275 IEEE80211_C_IBSS | IEEE80211_C_MONITOR; 276 277 /* read MAC address from EEPROM */ 278 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0); 279 ic->ic_myaddr[0] = val >> 8; 280 ic->ic_myaddr[1] = val & 0xff; 281 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 1); 282 ic->ic_myaddr[2] = val >> 8; 283 ic->ic_myaddr[3] = val & 0xff; 284 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 2); 285 ic->ic_myaddr[4] = val >> 8; 286 ic->ic_myaddr[5] = val & 0xff; 287 288 /* set supported .11b rates */ 289 ic->ic_sup_rates[IEEE80211_MODE_11B] = ipw_rateset_11b; 290 291 /* set supported .11b channels (read from EEPROM) */ 292 if ((val = ipw_read_prom_word(sc, IPW_EEPROM_CHANNEL_LIST)) == 0) 293 val = 0x7ff; /* default to channels 1-11 */ 294 val <<= 1; 295 for (i = 1; i < 16; i++) { 296 if (val & (1 << i)) { 297 ic->ic_channels[i].ic_freq = 298 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 299 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 300 } 301 } 302 303 /* check support for radio transmitter switch in EEPROM */ 304 if (!(ipw_read_prom_word(sc, IPW_EEPROM_RADIO) & 8)) 305 sc->flags |= IPW_FLAG_HAS_RADIO_SWITCH; 306 307 aprint_normal("%s: 802.11 address %s\n", sc->sc_dev.dv_xname, 308 ether_sprintf(ic->ic_myaddr)); 309 310 if_attach(ifp); 311 ieee80211_ifattach(ic); 312 313 /* override state transition machine */ 314 sc->sc_newstate = ic->ic_newstate; 315 ic->ic_newstate = ipw_newstate; 316 317 ieee80211_media_init(ic, ipw_media_change, ipw_media_status); 318 319 #if NBPFILTER > 0 320 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 321 sizeof (struct ieee80211_frame) + 64, &sc->sc_drvbpf); 322 323 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 324 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 325 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 326 327 sc->sc_txtap_len = sizeof sc->sc_txtapu; 328 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 329 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 330 #endif 331 332 /* 333 * Add a few sysctl knobs. 334 * XXX: Not yet 335 */ 336 sc->dwelltime = 100; 337 338 /* 339 * Make sure the interface is shutdown during reboot. 340 */ 341 sc->sc_sdhook = shutdownhook_establish(ipw_shutdown, sc); 342 if (sc->sc_sdhook == NULL) 343 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 344 sc->sc_dev.dv_xname); 345 sc->sc_powerhook = powerhook_establish(ipw_powerhook, sc); 346 if (sc->sc_powerhook == NULL) 347 printf("%s: WARNING: unable to establish power hook\n", 348 sc->sc_dev.dv_xname); 349 350 ieee80211_announce(ic); 351 352 return; 353 354 fail: ipw_detach(self, 0); 355 } 356 357 static int 358 ipw_detach(struct device* self, int flags) 359 { 360 struct ipw_softc *sc = (struct ipw_softc *)self; 361 struct ifnet *ifp = &sc->sc_if; 362 363 if (ifp->if_softc) { 364 ipw_stop(ifp, 1); 365 ipw_free_firmware(sc); 366 367 #if NBPFILTER > 0 368 bpfdetach(ifp); 369 #endif 370 ieee80211_ifdetach(&sc->sc_ic); 371 if_detach(ifp); 372 373 ipw_release(sc); 374 } 375 376 if (sc->sc_ih != NULL) { 377 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 378 sc->sc_ih = NULL; 379 } 380 381 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 382 383 return 0; 384 } 385 386 static int 387 ipw_dma_alloc(struct ipw_softc *sc) 388 { 389 struct ipw_soft_bd *sbd; 390 struct ipw_soft_hdr *shdr; 391 struct ipw_soft_buf *sbuf; 392 int error, i, nsegs; 393 394 /* 395 * Allocate and map tx ring. 396 */ 397 error = bus_dmamap_create(sc->sc_dmat, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, 398 BUS_DMA_NOWAIT, &sc->tbd_map); 399 if (error != 0) { 400 aprint_error("%s: could not create tbd dma map\n", 401 sc->sc_dev.dv_xname); 402 goto fail; 403 } 404 405 error = bus_dmamem_alloc(sc->sc_dmat, IPW_TBD_SZ, PAGE_SIZE, 0, 406 &sc->tbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 407 if (error != 0) { 408 aprint_error("%s: could not allocate tbd dma memory\n", 409 sc->sc_dev.dv_xname); 410 goto fail; 411 } 412 413 error = bus_dmamem_map(sc->sc_dmat, &sc->tbd_seg, nsegs, IPW_TBD_SZ, 414 (caddr_t *)&sc->tbd_list, BUS_DMA_NOWAIT); 415 if (error != 0) { 416 aprint_error("%s: could not map tbd dma memory\n", 417 sc->sc_dev.dv_xname); 418 goto fail; 419 } 420 421 error = bus_dmamap_load(sc->sc_dmat, sc->tbd_map, sc->tbd_list, 422 IPW_TBD_SZ, NULL, BUS_DMA_NOWAIT); 423 if (error != 0) { 424 aprint_error("%s: could not load tbd dma memory\n", 425 sc->sc_dev.dv_xname); 426 goto fail; 427 } 428 429 (void)memset(sc->tbd_list, 0, IPW_TBD_SZ); 430 431 /* 432 * Allocate and map rx ring. 433 */ 434 error = bus_dmamap_create(sc->sc_dmat, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, 435 BUS_DMA_NOWAIT, &sc->rbd_map); 436 if (error != 0) { 437 aprint_error("%s: could not create rbd dma map\n", 438 sc->sc_dev.dv_xname); 439 goto fail; 440 } 441 442 error = bus_dmamem_alloc(sc->sc_dmat, IPW_RBD_SZ, PAGE_SIZE, 0, 443 &sc->rbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 444 if (error != 0) { 445 aprint_error("%s: could not allocate rbd dma memory\n", 446 sc->sc_dev.dv_xname); 447 goto fail; 448 } 449 450 error = bus_dmamem_map(sc->sc_dmat, &sc->rbd_seg, nsegs, IPW_RBD_SZ, 451 (caddr_t *)&sc->rbd_list, BUS_DMA_NOWAIT); 452 if (error != 0) { 453 aprint_error("%s: could not map rbd dma memory\n", 454 sc->sc_dev.dv_xname); 455 goto fail; 456 } 457 458 error = bus_dmamap_load(sc->sc_dmat, sc->rbd_map, sc->rbd_list, 459 IPW_RBD_SZ, NULL, BUS_DMA_NOWAIT); 460 if (error != 0) { 461 aprint_error("%s: could not load rbd dma memory\n", 462 sc->sc_dev.dv_xname); 463 goto fail; 464 } 465 466 (void)memset(sc->rbd_list, 0, IPW_RBD_SZ); 467 468 /* 469 * Allocate and map status ring. 470 */ 471 error = bus_dmamap_create(sc->sc_dmat, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 472 0, BUS_DMA_NOWAIT, &sc->status_map); 473 if (error != 0) { 474 aprint_error("%s: could not create status dma map\n", 475 sc->sc_dev.dv_xname); 476 goto fail; 477 } 478 479 error = bus_dmamem_alloc(sc->sc_dmat, IPW_STATUS_SZ, PAGE_SIZE, 0, 480 &sc->status_seg, 1, &nsegs, BUS_DMA_NOWAIT); 481 if (error != 0) { 482 aprint_error("%s: could not allocate status dma memory\n", 483 sc->sc_dev.dv_xname); 484 goto fail; 485 } 486 487 error = bus_dmamem_map(sc->sc_dmat, &sc->status_seg, nsegs, 488 IPW_STATUS_SZ, (caddr_t *)&sc->status_list, BUS_DMA_NOWAIT); 489 if (error != 0) { 490 aprint_error("%s: could not map status dma memory\n", 491 sc->sc_dev.dv_xname); 492 goto fail; 493 } 494 495 error = bus_dmamap_load(sc->sc_dmat, sc->status_map, sc->status_list, 496 IPW_STATUS_SZ, NULL, BUS_DMA_NOWAIT); 497 if (error != 0) { 498 aprint_error("%s: could not load status dma memory\n", 499 sc->sc_dev.dv_xname); 500 goto fail; 501 } 502 503 (void)memset(sc->status_list, 0, IPW_STATUS_SZ); 504 505 /* 506 * Allocate command DMA map. 507 */ 508 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_cmd), 509 1, sizeof (struct ipw_cmd), 0, BUS_DMA_NOWAIT, &sc->cmd_map); 510 if (error != 0) { 511 aprint_error("%s: could not create cmd dma map\n", 512 sc->sc_dev.dv_xname); 513 goto fail; 514 } 515 516 error = bus_dmamem_alloc(sc->sc_dmat, sizeof (struct ipw_cmd), 517 PAGE_SIZE, 0, &sc->cmd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 518 if (error != 0) { 519 aprint_error("%s: could not allocate cmd dma memory\n", 520 sc->sc_dev.dv_xname); 521 goto fail; 522 } 523 524 error = bus_dmamem_map(sc->sc_dmat, &sc->cmd_seg, nsegs, 525 sizeof (struct ipw_cmd), (caddr_t *)&sc->cmd, BUS_DMA_NOWAIT); 526 if (error != 0) { 527 aprint_error("%s: could not map cmd dma memory\n", 528 sc->sc_dev.dv_xname); 529 goto fail; 530 } 531 532 error = bus_dmamap_load(sc->sc_dmat, sc->cmd_map, &sc->cmd, 533 sizeof (struct ipw_cmd), NULL, BUS_DMA_NOWAIT); 534 if (error != 0) { 535 aprint_error("%s: could not map cmd dma memory\n", 536 sc->sc_dev.dv_xname); 537 return error; 538 } 539 540 /* 541 * Allocate and map hdr list. 542 */ 543 544 error = bus_dmamap_create(sc->sc_dmat, 545 IPW_NDATA * sizeof(struct ipw_hdr), 1, 546 sizeof(struct ipw_hdr), 0, BUS_DMA_NOWAIT, 547 &sc->hdr_map); 548 if (error != 0) { 549 aprint_error("%s: could not create hdr dma map\n", 550 sc->sc_dev.dv_xname); 551 goto fail; 552 } 553 554 error = bus_dmamem_alloc(sc->sc_dmat, 555 IPW_NDATA * sizeof(struct ipw_hdr), PAGE_SIZE, 0, &sc->hdr_seg, 556 1, &nsegs, BUS_DMA_NOWAIT); 557 if (error != 0) { 558 aprint_error("%s: could not allocate hdr memory\n", 559 sc->sc_dev.dv_xname); 560 goto fail; 561 } 562 563 error = bus_dmamem_map(sc->sc_dmat, &sc->hdr_seg, nsegs, 564 IPW_NDATA * sizeof(struct ipw_hdr), (caddr_t *)&sc->hdr_list, 565 BUS_DMA_NOWAIT); 566 if (error != 0) { 567 aprint_error("%s: could not map hdr memory\n", 568 sc->sc_dev.dv_xname); 569 goto fail; 570 } 571 572 error = bus_dmamap_load(sc->sc_dmat, sc->hdr_map, sc->hdr_list, 573 IPW_NDATA * sizeof(struct ipw_hdr), NULL, BUS_DMA_NOWAIT); 574 if (error != 0) { 575 aprint_error("%s: could not load hdr memory\n", 576 sc->sc_dev.dv_xname); 577 goto fail; 578 } 579 580 (void)memset(sc->hdr_list, 0, IPW_HDR_SZ); 581 582 /* 583 * Create DMA hdrs tailq. 584 */ 585 TAILQ_INIT(&sc->sc_free_shdr); 586 for (i = 0; i < IPW_NDATA; i++) { 587 shdr = &sc->shdr_list[i]; 588 shdr->hdr = sc->hdr_list + i; 589 shdr->offset = sizeof(struct ipw_hdr) * i; 590 shdr->addr = sc->hdr_map->dm_segs[0].ds_addr + shdr->offset; 591 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 592 } 593 594 /* 595 * Allocate tx buffers DMA maps. 596 */ 597 TAILQ_INIT(&sc->sc_free_sbuf); 598 for (i = 0; i < IPW_NDATA; i++) { 599 sbuf = &sc->tx_sbuf_list[i]; 600 601 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 602 IPW_MAX_NSEG, MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 603 if (error != 0) { 604 aprint_error("%s: could not create txbuf dma map\n", 605 sc->sc_dev.dv_xname); 606 goto fail; 607 } 608 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 609 } 610 611 /* 612 * Initialize tx ring. 613 */ 614 for (i = 0; i < IPW_NTBD; i++) { 615 sbd = &sc->stbd_list[i]; 616 sbd->bd = &sc->tbd_list[i]; 617 sbd->type = IPW_SBD_TYPE_NOASSOC; 618 } 619 620 /* 621 * Pre-allocate rx buffers and DMA maps 622 */ 623 for (i = 0; i < IPW_NRBD; i++) { 624 sbd = &sc->srbd_list[i]; 625 sbuf = &sc->rx_sbuf_list[i]; 626 sbd->bd = &sc->rbd_list[i]; 627 628 MGETHDR(sbuf->m, M_DONTWAIT, MT_DATA); 629 if (sbuf->m == NULL) { 630 aprint_error("%s: could not allocate rx mbuf\n", 631 sc->sc_dev.dv_xname); 632 error = ENOMEM; 633 goto fail; 634 } 635 636 MCLGET(sbuf->m, M_DONTWAIT); 637 if (!(sbuf->m->m_flags & M_EXT)) { 638 m_freem(sbuf->m); 639 aprint_error("%s: could not allocate rx mbuf cluster\n", 640 sc->sc_dev.dv_xname); 641 error = ENOMEM; 642 goto fail; 643 } 644 645 sbuf->m->m_pkthdr.len = sbuf->m->m_len = sbuf->m->m_ext.ext_size; 646 647 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 648 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sbuf->map); 649 if (error != 0) { 650 aprint_error("%s: could not create rxbuf dma map\n", 651 sc->sc_dev.dv_xname); 652 m_freem(sbuf->m); 653 goto fail; 654 } 655 656 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, 657 sbuf->m, BUS_DMA_READ | BUS_DMA_NOWAIT); 658 if (error != 0) { 659 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 660 m_freem(sbuf->m); 661 aprint_error("%s: could not map rxbuf dma memory\n", 662 sc->sc_dev.dv_xname); 663 goto fail; 664 } 665 666 sbd->type = IPW_SBD_TYPE_DATA; 667 sbd->priv = sbuf; 668 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 669 sbd->bd->len = htole32(MCLBYTES); 670 671 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, 672 sbuf->map->dm_mapsize, BUS_DMASYNC_PREREAD); 673 674 } 675 676 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 0, IPW_RBD_SZ, 677 BUS_DMASYNC_PREREAD); 678 679 return 0; 680 681 fail: ipw_release(sc); 682 return error; 683 } 684 685 static void 686 ipw_release(struct ipw_softc *sc) 687 { 688 struct ipw_soft_buf *sbuf; 689 int i; 690 691 if (sc->tbd_map != NULL) { 692 if (sc->tbd_list != NULL) { 693 bus_dmamap_unload(sc->sc_dmat, sc->tbd_map); 694 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->tbd_list, 695 IPW_TBD_SZ); 696 bus_dmamem_free(sc->sc_dmat, &sc->tbd_seg, 1); 697 } 698 bus_dmamap_destroy(sc->sc_dmat, sc->tbd_map); 699 } 700 701 if (sc->rbd_map != NULL) { 702 if (sc->rbd_list != NULL) { 703 bus_dmamap_unload(sc->sc_dmat, sc->rbd_map); 704 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->rbd_list, 705 IPW_RBD_SZ); 706 bus_dmamem_free(sc->sc_dmat, &sc->rbd_seg, 1); 707 } 708 bus_dmamap_destroy(sc->sc_dmat, sc->rbd_map); 709 } 710 711 if (sc->status_map != NULL) { 712 if (sc->status_list != NULL) { 713 bus_dmamap_unload(sc->sc_dmat, sc->status_map); 714 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->status_list, 715 IPW_RBD_SZ); 716 bus_dmamem_free(sc->sc_dmat, &sc->status_seg, 1); 717 } 718 bus_dmamap_destroy(sc->sc_dmat, sc->status_map); 719 } 720 721 for (i = 0; i < IPW_NTBD; i++) 722 ipw_release_sbd(sc, &sc->stbd_list[i]); 723 724 if (sc->cmd_map != NULL) 725 bus_dmamap_destroy(sc->sc_dmat, sc->cmd_map); 726 727 if (sc->hdr_list != NULL) { 728 bus_dmamap_unload(sc->sc_dmat, sc->hdr_map); 729 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->hdr_list, 730 IPW_NDATA * sizeof(struct ipw_hdr)); 731 } 732 if (sc->hdr_map != NULL) { 733 bus_dmamem_free(sc->sc_dmat, &sc->hdr_seg, 1); 734 bus_dmamap_destroy(sc->sc_dmat, sc->hdr_map); 735 } 736 737 for (i = 0; i < IPW_NDATA; i++) 738 bus_dmamap_destroy(sc->sc_dmat, sc->tx_sbuf_list[i].map); 739 740 for (i = 0; i < IPW_NRBD; i++) { 741 sbuf = &sc->rx_sbuf_list[i]; 742 if (sbuf->map != NULL) { 743 if (sbuf->m != NULL) { 744 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 745 m_freem(sbuf->m); 746 } 747 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 748 } 749 } 750 751 } 752 753 static void 754 ipw_shutdown(void *arg) 755 { 756 struct ipw_softc *sc = (struct ipw_softc *)arg; 757 struct ifnet *ifp = sc->sc_ic.ic_ifp; 758 759 ipw_stop(ifp, 1); 760 } 761 762 763 static int 764 ipw_suspend(struct ipw_softc *sc) 765 { 766 struct ifnet *ifp = sc->sc_ic.ic_ifp; 767 768 ipw_stop(ifp, 1); 769 770 return 0; 771 } 772 773 static int 774 ipw_resume(struct ipw_softc *sc) 775 { 776 struct ifnet *ifp = sc->sc_ic.ic_ifp; 777 pcireg_t data; 778 779 /* clear device specific PCI configuration register 0x41 */ 780 data = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 781 data &= ~0x0000ff00; 782 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, data); 783 784 if (ifp->if_flags & IFF_UP) { 785 ipw_init(ifp); 786 if (ifp->if_flags & IFF_RUNNING) 787 ipw_start(ifp); 788 } 789 790 return 0; 791 } 792 793 static void 794 ipw_powerhook(int why, void *arg) 795 { 796 struct ipw_softc *sc = arg; 797 int s; 798 799 s = splnet(); 800 switch (why) { 801 case PWR_SUSPEND: 802 case PWR_STANDBY: 803 ipw_suspend(sc); 804 break; 805 case PWR_RESUME: 806 ipw_resume(sc); 807 break; 808 case PWR_SOFTSUSPEND: 809 case PWR_SOFTSTANDBY: 810 case PWR_SOFTRESUME: 811 break; 812 } 813 splx(s); 814 } 815 816 static int 817 ipw_media_change(struct ifnet *ifp) 818 { 819 int error; 820 821 error = ieee80211_media_change(ifp); 822 if (error != ENETRESET) 823 return error; 824 825 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 826 ipw_init(ifp); 827 828 return 0; 829 } 830 831 /* 832 * The firmware automatically adapts the transmit speed. We report the current 833 * transmit speed here. 834 */ 835 static void 836 ipw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 837 { 838 #define N(a) (sizeof (a) / sizeof (a[0])) 839 struct ipw_softc *sc = ifp->if_softc; 840 struct ieee80211com *ic = &sc->sc_ic; 841 static const struct { 842 uint32_t val; 843 int rate; 844 } rates[] = { 845 { IPW_RATE_DS1, 2 }, 846 { IPW_RATE_DS2, 4 }, 847 { IPW_RATE_DS5, 11 }, 848 { IPW_RATE_DS11, 22 }, 849 }; 850 uint32_t val; 851 int rate, i; 852 853 imr->ifm_status = IFM_AVALID; 854 imr->ifm_active = IFM_IEEE80211; 855 if (ic->ic_state == IEEE80211_S_RUN) 856 imr->ifm_status |= IFM_ACTIVE; 857 858 /* read current transmission rate from adapter */ 859 val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE) & 0xf; 860 861 /* convert ipw rate to 802.11 rate */ 862 for (i = 0; i < N(rates) && rates[i].val != val; i++); 863 rate = (i < N(rates)) ? rates[i].rate : 0; 864 865 imr->ifm_active |= IFM_IEEE80211_11B; 866 imr->ifm_active |= ieee80211_rate2media(ic, rate, IEEE80211_MODE_11B); 867 switch (ic->ic_opmode) { 868 case IEEE80211_M_STA: 869 break; 870 871 case IEEE80211_M_IBSS: 872 imr->ifm_active |= IFM_IEEE80211_ADHOC; 873 break; 874 875 case IEEE80211_M_MONITOR: 876 imr->ifm_active |= IFM_IEEE80211_MONITOR; 877 break; 878 879 case IEEE80211_M_AHDEMO: 880 case IEEE80211_M_HOSTAP: 881 /* should not get there */ 882 break; 883 } 884 #undef N 885 } 886 887 static int 888 ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 889 { 890 struct ifnet *ifp = ic->ic_ifp; 891 struct ipw_softc *sc = ifp->if_softc; 892 struct ieee80211_node *ni; 893 uint8_t macaddr[IEEE80211_ADDR_LEN]; 894 uint32_t len; 895 896 switch (nstate) { 897 case IEEE80211_S_RUN: 898 DELAY(200); /* firmware needs a short delay here */ 899 900 len = IEEE80211_ADDR_LEN; 901 ipw_read_table2(sc, IPW_INFO_CURRENT_BSSID, macaddr, &len); 902 903 ni = ieee80211_find_node(&ic->ic_scan, macaddr); 904 if (ni == NULL) 905 break; 906 907 ieee80211_ref_node(ni); 908 ieee80211_sta_join(ic, ni); 909 ieee80211_node_authorize(ni); 910 911 if (ic->ic_opmode == IEEE80211_M_STA) 912 ieee80211_notify_node_join(ic, ni, 1); 913 break; 914 915 case IEEE80211_S_INIT: 916 case IEEE80211_S_SCAN: 917 case IEEE80211_S_AUTH: 918 case IEEE80211_S_ASSOC: 919 break; 920 } 921 922 ic->ic_state = nstate; 923 return 0; 924 } 925 926 /* 927 * Read 16 bits at address 'addr' from the serial EEPROM. 928 */ 929 static uint16_t 930 ipw_read_prom_word(struct ipw_softc *sc, uint8_t addr) 931 { 932 uint32_t tmp; 933 uint16_t val; 934 int n; 935 936 /* clock C once before the first command */ 937 IPW_EEPROM_CTL(sc, 0); 938 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 939 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 940 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 941 942 /* write start bit (1) */ 943 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 944 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 945 946 /* write READ opcode (10) */ 947 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 948 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 949 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 950 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 951 952 /* write address A7-A0 */ 953 for (n = 7; n >= 0; n--) { 954 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 955 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D)); 956 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 957 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D) | IPW_EEPROM_C); 958 } 959 960 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 961 962 /* read data Q15-Q0 */ 963 val = 0; 964 for (n = 15; n >= 0; n--) { 965 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 966 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 967 tmp = MEM_READ_4(sc, IPW_MEM_EEPROM_CTL); 968 val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n; 969 } 970 971 IPW_EEPROM_CTL(sc, 0); 972 973 /* clear Chip Select and clock C */ 974 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 975 IPW_EEPROM_CTL(sc, 0); 976 IPW_EEPROM_CTL(sc, IPW_EEPROM_C); 977 978 return le16toh(val); 979 } 980 981 static void 982 ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 983 { 984 struct ipw_cmd *cmd; 985 986 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof (struct ipw_cmd), 987 BUS_DMASYNC_POSTREAD); 988 989 cmd = mtod(sbuf->m, struct ipw_cmd *); 990 991 DPRINTFN(2, ("cmd ack'ed (%u, %u, %u, %u, %u)\n", le32toh(cmd->type), 992 le32toh(cmd->subtype), le32toh(cmd->seq), le32toh(cmd->len), 993 le32toh(cmd->status))); 994 995 wakeup(&sc->cmd); 996 } 997 998 static void 999 ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 1000 { 1001 struct ieee80211com *ic = &sc->sc_ic; 1002 struct ifnet *ifp = sc->sc_ic.ic_ifp; 1003 uint32_t state; 1004 1005 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof state, 1006 BUS_DMASYNC_POSTREAD); 1007 1008 state = le32toh(*mtod(sbuf->m, uint32_t *)); 1009 1010 DPRINTFN(2, ("entering state %u\n", state)); 1011 1012 switch (state) { 1013 case IPW_STATE_ASSOCIATED: 1014 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1015 break; 1016 1017 case IPW_STATE_SCANNING: 1018 /* don't leave run state on background scan */ 1019 if (ic->ic_state != IEEE80211_S_RUN) 1020 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1021 1022 ic->ic_flags |= IEEE80211_F_SCAN; 1023 break; 1024 1025 case IPW_STATE_SCAN_COMPLETE: 1026 ieee80211_notify_scan_done(ic); 1027 ic->ic_flags &= ~IEEE80211_F_SCAN; 1028 break; 1029 1030 case IPW_STATE_ASSOCIATION_LOST: 1031 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1032 break; 1033 1034 case IPW_STATE_RADIO_DISABLED: 1035 ic->ic_ifp->if_flags &= ~IFF_UP; 1036 ipw_stop(ifp, 1); 1037 break; 1038 } 1039 } 1040 1041 /* 1042 * XXX: Hack to set the current channel to the value advertised in beacons or 1043 * probe responses. Only used during AP detection. 1044 */ 1045 static void 1046 ipw_fix_channel(struct ieee80211com *ic, struct mbuf *m) 1047 { 1048 struct ieee80211_frame *wh; 1049 uint8_t subtype; 1050 uint8_t *frm, *efrm; 1051 1052 wh = mtod(m, struct ieee80211_frame *); 1053 1054 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_MGT) 1055 return; 1056 1057 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 1058 1059 if (subtype != IEEE80211_FC0_SUBTYPE_BEACON && 1060 subtype != IEEE80211_FC0_SUBTYPE_PROBE_RESP) 1061 return; 1062 1063 frm = (uint8_t *)(wh + 1); 1064 efrm = mtod(m, uint8_t *) + m->m_len; 1065 1066 frm += 12; /* skip tstamp, bintval and capinfo fields */ 1067 while (frm < efrm) { 1068 if (*frm == IEEE80211_ELEMID_DSPARMS) 1069 #if IEEE80211_CHAN_MAX < 255 1070 if (frm[2] <= IEEE80211_CHAN_MAX) 1071 #endif 1072 ic->ic_curchan = &ic->ic_channels[frm[2]]; 1073 1074 frm += frm[1] + 2; 1075 } 1076 } 1077 1078 static void 1079 ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 1080 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 1081 { 1082 struct ieee80211com *ic = &sc->sc_ic; 1083 struct ifnet *ifp = &sc->sc_if; 1084 struct mbuf *mnew, *m; 1085 struct ieee80211_frame *wh; 1086 struct ieee80211_node *ni; 1087 int error; 1088 1089 DPRINTFN(5, ("received frame len=%u, rssi=%u\n", le32toh(status->len), 1090 status->rssi)); 1091 1092 if (le32toh(status->len) < sizeof (struct ieee80211_frame_min) || 1093 le32toh(status->len) > MCLBYTES) 1094 return; 1095 1096 /* 1097 * Try to allocate a new mbuf for this ring element and load it before 1098 * processing the current mbuf. If the ring element cannot be loaded, 1099 * drop the received packet and reuse the old mbuf. In the unlikely 1100 * case that the old mbuf can't be reloaded either, explicitly panic. 1101 */ 1102 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1103 if (mnew == NULL) { 1104 aprint_error("%s: could not allocate rx mbuf\n", 1105 sc->sc_dev.dv_xname); 1106 ifp->if_ierrors++; 1107 return; 1108 } 1109 1110 MCLGET(mnew, M_DONTWAIT); 1111 if (!(mnew->m_flags & M_EXT)) { 1112 aprint_error("%s: could not allocate rx mbuf cluster\n", 1113 sc->sc_dev.dv_xname); 1114 m_freem(mnew); 1115 ifp->if_ierrors++; 1116 return; 1117 } 1118 1119 mnew->m_pkthdr.len = mnew->m_len = mnew->m_ext.ext_size; 1120 1121 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, le32toh(status->len), 1122 BUS_DMASYNC_POSTREAD); 1123 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1124 1125 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, mnew, 1126 BUS_DMA_READ | BUS_DMA_NOWAIT); 1127 if (error != 0) { 1128 aprint_error("%s: could not load rx buf DMA map\n", 1129 sc->sc_dev.dv_xname); 1130 m_freem(mnew); 1131 1132 /* try to reload the old mbuf */ 1133 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, 1134 sbuf->m, BUS_DMA_READ | BUS_DMA_NOWAIT); 1135 if (error != 0) { 1136 /* very unlikely that it will fail... */ 1137 panic("%s: unable to remap rx buf", 1138 sc->sc_dev.dv_xname); 1139 } 1140 ifp->if_ierrors++; 1141 return; 1142 } 1143 1144 /* 1145 * New mbuf successfully loaded, update Rx ring and continue 1146 * processing. 1147 */ 1148 m = sbuf->m; 1149 sbuf->m = mnew; 1150 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 1151 1152 /* finalize mbuf */ 1153 m->m_pkthdr.rcvif = ifp; 1154 m->m_pkthdr.len = m->m_len = le32toh(status->len); 1155 1156 #if NBPFILTER > 0 1157 if (sc->sc_drvbpf != NULL) { 1158 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 1159 1160 tap->wr_flags = 0; 1161 tap->wr_antsignal = status->rssi; 1162 tap->wr_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 1163 tap->wr_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 1164 1165 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 1166 } 1167 #endif 1168 1169 if (ic->ic_state == IEEE80211_S_SCAN) 1170 ipw_fix_channel(ic, m); 1171 1172 wh = mtod(m, struct ieee80211_frame *); 1173 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 1174 1175 /* send the frame to the 802.11 layer */ 1176 ieee80211_input(ic, m, ni, status->rssi, 0); 1177 1178 /* node is no longer needed */ 1179 ieee80211_free_node(ni); 1180 1181 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, 1182 sbuf->map->dm_mapsize, BUS_DMASYNC_PREREAD); 1183 } 1184 1185 static void 1186 ipw_rx_intr(struct ipw_softc *sc) 1187 { 1188 struct ipw_status *status; 1189 struct ipw_soft_bd *sbd; 1190 struct ipw_soft_buf *sbuf; 1191 uint32_t r, i; 1192 1193 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1194 return; 1195 1196 r = CSR_READ_4(sc, IPW_CSR_RX_READ); 1197 1198 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 1199 1200 /* firmware was killed, stop processing received frames */ 1201 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1202 return; 1203 1204 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 1205 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1206 BUS_DMASYNC_POSTREAD); 1207 1208 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 1209 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 1210 BUS_DMASYNC_POSTREAD); 1211 1212 status = &sc->status_list[i]; 1213 sbd = &sc->srbd_list[i]; 1214 sbuf = sbd->priv; 1215 1216 switch (le16toh(status->code) & 0xf) { 1217 case IPW_STATUS_CODE_COMMAND: 1218 ipw_command_intr(sc, sbuf); 1219 break; 1220 1221 case IPW_STATUS_CODE_NEWSTATE: 1222 ipw_newstate_intr(sc, sbuf); 1223 break; 1224 1225 case IPW_STATUS_CODE_DATA_802_3: 1226 case IPW_STATUS_CODE_DATA_802_11: 1227 ipw_data_intr(sc, status, sbd, sbuf); 1228 break; 1229 1230 case IPW_STATUS_CODE_NOTIFICATION: 1231 DPRINTFN(2, ("received notification\n")); 1232 break; 1233 1234 default: 1235 aprint_debug("%s: unknown status code %u\n", 1236 sc->sc_dev.dv_xname, le16toh(status->code)); 1237 } 1238 1239 sbd->bd->flags = 0; 1240 1241 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 1242 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1243 BUS_DMASYNC_PREREAD); 1244 1245 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 1246 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 1247 BUS_DMASYNC_PREREAD); 1248 } 1249 1250 /* Tell the firmware what we have processed */ 1251 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 1252 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 1253 } 1254 1255 static void 1256 ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 1257 { 1258 struct ieee80211com *ic; 1259 struct ipw_soft_hdr *shdr; 1260 struct ipw_soft_buf *sbuf; 1261 1262 switch (sbd->type) { 1263 case IPW_SBD_TYPE_COMMAND: 1264 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 1265 0, sizeof(struct ipw_cmd), BUS_DMASYNC_POSTWRITE); 1266 /* bus_dmamap_unload(sc->sc_dmat, sc->cmd_map); */ 1267 break; 1268 1269 case IPW_SBD_TYPE_HEADER: 1270 shdr = sbd->priv; 1271 bus_dmamap_sync(sc->sc_dmat, sc->hdr_map, 1272 shdr->offset, sizeof(struct ipw_hdr), BUS_DMASYNC_POSTWRITE); 1273 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 1274 break; 1275 1276 case IPW_SBD_TYPE_DATA: 1277 ic = &sc->sc_ic; 1278 sbuf = sbd->priv; 1279 1280 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 1281 0, MCLBYTES, BUS_DMASYNC_POSTWRITE); 1282 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1283 m_freem(sbuf->m); 1284 if (sbuf->ni != NULL) 1285 ieee80211_free_node(sbuf->ni); 1286 /* kill watchdog timer */ 1287 sc->sc_tx_timer = 0; 1288 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 1289 break; 1290 } 1291 sbd->type = IPW_SBD_TYPE_NOASSOC; 1292 } 1293 1294 static void 1295 ipw_tx_intr(struct ipw_softc *sc) 1296 { 1297 struct ifnet *ifp = &sc->sc_if; 1298 struct ipw_soft_bd *sbd; 1299 uint32_t r, i; 1300 1301 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1302 return; 1303 1304 r = CSR_READ_4(sc, IPW_CSR_TX_READ); 1305 1306 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) { 1307 sbd = &sc->stbd_list[i]; 1308 1309 if (sbd->type == IPW_SBD_TYPE_DATA) 1310 ifp->if_opackets++; 1311 1312 ipw_release_sbd(sc, sbd); 1313 sc->txfree++; 1314 } 1315 1316 /* remember what the firmware has processed */ 1317 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 1318 1319 /* Call start() since some buffer descriptors have been released */ 1320 ifp->if_flags &= ~IFF_OACTIVE; 1321 (*ifp->if_start)(ifp); 1322 } 1323 1324 static int 1325 ipw_intr(void *arg) 1326 { 1327 struct ipw_softc *sc = arg; 1328 uint32_t r; 1329 1330 r = CSR_READ_4(sc, IPW_CSR_INTR); 1331 if (r == 0 || r == 0xffffffff) 1332 return 0; 1333 1334 /* Disable interrupts */ 1335 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1336 1337 if (r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR)) { 1338 aprint_error("%s: fatal error\n", 1339 sc->sc_dev.dv_xname); 1340 sc->sc_ic.ic_ifp->if_flags &= ~IFF_UP; 1341 ipw_stop(&sc->sc_if, 1); 1342 } 1343 1344 if (r & IPW_INTR_FW_INIT_DONE) { 1345 if (!(r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR))) 1346 wakeup(sc); 1347 } 1348 1349 if (r & IPW_INTR_RX_TRANSFER) 1350 ipw_rx_intr(sc); 1351 1352 if (r & IPW_INTR_TX_TRANSFER) 1353 ipw_tx_intr(sc); 1354 1355 /* Acknowledge all interrupts */ 1356 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 1357 1358 /* Re-enable interrupts */ 1359 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1360 1361 return 0; 1362 } 1363 1364 /* 1365 * Send a command to the firmware and wait for the acknowledgement. 1366 */ 1367 static int 1368 ipw_cmd(struct ipw_softc *sc, uint32_t type, void *data, uint32_t len) 1369 { 1370 struct ipw_soft_bd *sbd; 1371 1372 sbd = &sc->stbd_list[sc->txcur]; 1373 1374 sc->cmd.type = htole32(type); 1375 sc->cmd.subtype = 0; 1376 sc->cmd.len = htole32(len); 1377 sc->cmd.seq = 0; 1378 1379 (void)memcpy(sc->cmd.data, data, len); 1380 1381 sbd->type = IPW_SBD_TYPE_COMMAND; 1382 sbd->bd->physaddr = htole32(sc->cmd_map->dm_segs[0].ds_addr); 1383 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 1384 sbd->bd->nfrag = 1; 1385 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 1386 IPW_BD_FLAG_TX_LAST_FRAGMENT; 1387 1388 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 0, sizeof (struct ipw_cmd), 1389 BUS_DMASYNC_PREWRITE); 1390 1391 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1392 sc->txcur * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1393 BUS_DMASYNC_PREWRITE); 1394 1395 DPRINTFN(2, ("sending command (%u, %u, %u, %u)\n", type, 0, 0, len)); 1396 1397 /* kick firmware */ 1398 sc->txfree--; 1399 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1400 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1401 1402 /* Wait at most one second for command to complete */ 1403 return tsleep(&sc->cmd, 0, "ipwcmd", hz); 1404 } 1405 1406 static int 1407 ipw_tx_start(struct ifnet *ifp, struct mbuf *m0, struct ieee80211_node *ni) 1408 { 1409 struct ipw_softc *sc = ifp->if_softc; 1410 struct ieee80211com *ic = &sc->sc_ic; 1411 struct ieee80211_frame *wh; 1412 struct ipw_soft_bd *sbd; 1413 struct ipw_soft_hdr *shdr; 1414 struct ipw_soft_buf *sbuf; 1415 struct ieee80211_key *k; 1416 struct mbuf *mnew; 1417 int error, i; 1418 1419 wh = mtod(m0, struct ieee80211_frame *); 1420 1421 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1422 k = ieee80211_crypto_encap(ic, ni, m0); 1423 if (k == NULL) { 1424 m_freem(m0); 1425 return ENOBUFS; 1426 } 1427 1428 /* packet header may have moved, reset our local pointer */ 1429 wh = mtod(m0, struct ieee80211_frame *); 1430 } 1431 1432 #if NBPFILTER > 0 1433 if (sc->sc_drvbpf != NULL) { 1434 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 1435 1436 tap->wt_flags = 0; 1437 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 1438 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 1439 1440 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 1441 } 1442 #endif 1443 1444 shdr = TAILQ_FIRST(&sc->sc_free_shdr); 1445 sbuf = TAILQ_FIRST(&sc->sc_free_sbuf); 1446 KASSERT(shdr != NULL && sbuf != NULL); 1447 1448 shdr->hdr->type = htole32(IPW_HDR_TYPE_SEND); 1449 shdr->hdr->subtype = 0; 1450 shdr->hdr->encrypted = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0; 1451 shdr->hdr->encrypt = 0; 1452 shdr->hdr->keyidx = 0; 1453 shdr->hdr->keysz = 0; 1454 shdr->hdr->fragmentsz = 0; 1455 IEEE80211_ADDR_COPY(shdr->hdr->src_addr, wh->i_addr2); 1456 if (ic->ic_opmode == IEEE80211_M_STA) 1457 IEEE80211_ADDR_COPY(shdr->hdr->dst_addr, wh->i_addr3); 1458 else 1459 IEEE80211_ADDR_COPY(shdr->hdr->dst_addr, wh->i_addr1); 1460 1461 /* trim IEEE802.11 header */ 1462 m_adj(m0, sizeof (struct ieee80211_frame)); 1463 1464 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m0, BUS_DMA_NOWAIT); 1465 if (error != 0 && error != EFBIG) { 1466 aprint_error("%s: could not map mbuf (error %d)\n", 1467 sc->sc_dev.dv_xname, error); 1468 m_freem(m0); 1469 return error; 1470 } 1471 1472 if (error != 0) { 1473 /* too many fragments, linearize */ 1474 1475 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1476 if (mnew == NULL) { 1477 m_freem(m0); 1478 return ENOMEM; 1479 } 1480 1481 M_COPY_PKTHDR(mnew, m0); 1482 1483 /* If the data won't fit in the header, get a cluster */ 1484 if (m0->m_pkthdr.len > MHLEN) { 1485 MCLGET(mnew, M_DONTWAIT); 1486 if (!(mnew->m_flags & M_EXT)) { 1487 m_freem(m0); 1488 m_freem(mnew); 1489 return ENOMEM; 1490 } 1491 } 1492 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(mnew, caddr_t)); 1493 m_freem(m0); 1494 mnew->m_len = mnew->m_pkthdr.len; 1495 m0 = mnew; 1496 1497 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m0, 1498 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1499 if (error != 0) { 1500 aprint_error("%s: could not map mbuf (error %d)\n", 1501 sc->sc_dev.dv_xname, error); 1502 m_freem(m0); 1503 return error; 1504 } 1505 } 1506 1507 TAILQ_REMOVE(&sc->sc_free_sbuf, sbuf, next); 1508 TAILQ_REMOVE(&sc->sc_free_shdr, shdr, next); 1509 1510 sbd = &sc->stbd_list[sc->txcur]; 1511 sbd->type = IPW_SBD_TYPE_HEADER; 1512 sbd->priv = shdr; 1513 sbd->bd->physaddr = htole32(shdr->addr); 1514 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 1515 sbd->bd->nfrag = 1 + sbuf->map->dm_nsegs; 1516 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 1517 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1518 1519 DPRINTFN(5, ("sending tx hdr (%u, %u, %u, %u, )\n", 1520 shdr->hdr->type, shdr->hdr->subtype, shdr->hdr->encrypted, 1521 shdr->hdr->encrypt)); 1522 DPRINTFN(5, ("%s->", ether_sprintf(shdr->hdr->src_addr))); 1523 DPRINTFN(5, ("%s\n", ether_sprintf(shdr->hdr->dst_addr))); 1524 1525 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1526 sc->txcur * sizeof (struct ipw_bd), 1527 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1528 1529 sc->txfree--; 1530 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1531 1532 sbuf->m = m0; 1533 sbuf->ni = ni; 1534 1535 for (i = 0; i < sbuf->map->dm_nsegs; i++) { 1536 sbd = &sc->stbd_list[sc->txcur]; 1537 1538 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[i].ds_addr); 1539 sbd->bd->len = htole32(sbuf->map->dm_segs[i].ds_len); 1540 sbd->bd->nfrag = 0; 1541 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 1542 if (i == sbuf->map->dm_nsegs - 1) { 1543 sbd->type = IPW_SBD_TYPE_DATA; 1544 sbd->priv = sbuf; 1545 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 1546 } else { 1547 sbd->type = IPW_SBD_TYPE_NOASSOC; 1548 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1549 } 1550 1551 DPRINTFN(5, ("sending fragment (%d, %d)\n", i, 1552 (int)sbuf->map->dm_segs[i].ds_len)); 1553 1554 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1555 sc->txcur * sizeof (struct ipw_bd), 1556 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1557 1558 sc->txfree--; 1559 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1560 } 1561 1562 bus_dmamap_sync(sc->sc_dmat, sc->hdr_map, shdr->offset, 1563 sizeof (struct ipw_hdr), BUS_DMASYNC_PREWRITE); 1564 1565 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, MCLBYTES, 1566 BUS_DMASYNC_PREWRITE); 1567 1568 /* Inform firmware about this new packet */ 1569 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1570 1571 return 0; 1572 } 1573 1574 static void 1575 ipw_start(struct ifnet *ifp) 1576 { 1577 struct ipw_softc *sc = ifp->if_softc; 1578 struct ieee80211com *ic = &sc->sc_ic; 1579 struct mbuf *m0; 1580 struct ether_header *eh; 1581 struct ieee80211_node *ni; 1582 1583 1584 if (ic->ic_state != IEEE80211_S_RUN) 1585 return; 1586 1587 for (;;) { 1588 IF_DEQUEUE(&ifp->if_snd, m0); 1589 if (m0 == NULL) 1590 break; 1591 1592 if (sc->txfree < 1 + IPW_MAX_NSEG) { 1593 IF_PREPEND(&ifp->if_snd, m0); 1594 ifp->if_flags |= IFF_OACTIVE; 1595 break; 1596 } 1597 1598 if (m0->m_len < sizeof (struct ether_header) && 1599 (m0 = m_pullup(m0, sizeof (struct ether_header))) == NULL) 1600 continue; 1601 1602 eh = mtod(m0, struct ether_header *); 1603 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1604 if (ni == NULL) { 1605 m_freem(m0); 1606 continue; 1607 } 1608 1609 #if NBPFILTER > 0 1610 if (ifp->if_bpf != NULL) 1611 bpf_mtap(ifp->if_bpf, m0); 1612 #endif 1613 1614 m0 = ieee80211_encap(ic, m0, ni); 1615 if (m0 == NULL) { 1616 ieee80211_free_node(ni); 1617 continue; 1618 } 1619 1620 #if NBPFILTER > 0 1621 if (ic->ic_rawbpf != NULL) 1622 bpf_mtap(ic->ic_rawbpf, m0); 1623 #endif 1624 1625 if (ipw_tx_start(ifp, m0, ni) != 0) { 1626 ieee80211_free_node(ni); 1627 ifp->if_oerrors++; 1628 break; 1629 } 1630 1631 /* start watchdog timer */ 1632 sc->sc_tx_timer = 5; 1633 ifp->if_timer = 1; 1634 } 1635 } 1636 1637 static void 1638 ipw_watchdog(struct ifnet *ifp) 1639 { 1640 struct ipw_softc *sc = ifp->if_softc; 1641 1642 ifp->if_timer = 0; 1643 1644 if (sc->sc_tx_timer > 0) { 1645 if (--sc->sc_tx_timer == 0) { 1646 aprint_error("%s: device timeout\n", 1647 sc->sc_dev.dv_xname); 1648 ifp->if_oerrors++; 1649 ifp->if_flags &= ~IFF_UP; 1650 ipw_stop(ifp, 1); 1651 return; 1652 } 1653 ifp->if_timer = 1; 1654 } 1655 1656 ieee80211_watchdog(&sc->sc_ic); 1657 } 1658 1659 static int 1660 ipw_get_table1(struct ipw_softc *sc, uint32_t *tbl) 1661 { 1662 uint32_t addr, size, i; 1663 1664 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1665 return ENOTTY; 1666 1667 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, sc->table1_base); 1668 1669 size = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 1670 if (suword(tbl, size) != 0) 1671 return EFAULT; 1672 1673 for (i = 1, ++tbl; i < size; i++, tbl++) { 1674 addr = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 1675 if (suword(tbl, MEM_READ_4(sc, addr)) != 0) 1676 return EFAULT; 1677 } 1678 return 0; 1679 } 1680 1681 static int 1682 ipw_get_radio(struct ipw_softc *sc, int *ret) 1683 { 1684 uint32_t addr; 1685 1686 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1687 return ENOTTY; 1688 1689 addr = ipw_read_table1(sc, IPW_INFO_EEPROM_ADDRESS); 1690 if ((MEM_READ_4(sc, addr + 32) >> 24) & 1) { 1691 suword(ret, -1); 1692 return 0; 1693 } 1694 1695 if (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED) 1696 suword(ret, 0); 1697 else 1698 suword(ret, 1); 1699 1700 return 0; 1701 } 1702 1703 static int 1704 ipw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1705 { 1706 #define IS_RUNNING(ifp) \ 1707 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 1708 1709 struct ipw_softc *sc = ifp->if_softc; 1710 struct ieee80211com *ic = &sc->sc_ic; 1711 struct ifreq *ifr = (struct ifreq *)data; 1712 int s, error = 0; 1713 1714 s = splnet(); 1715 1716 switch (cmd) { 1717 case SIOCSIFFLAGS: 1718 if (ifp->if_flags & IFF_UP) { 1719 if (!(ifp->if_flags & IFF_RUNNING)) 1720 ipw_init(ifp); 1721 } else { 1722 if (ifp->if_flags & IFF_RUNNING) 1723 ipw_stop(ifp, 1); 1724 } 1725 break; 1726 1727 case SIOCADDMULTI: 1728 case SIOCDELMULTI: 1729 error = (cmd == SIOCADDMULTI) ? 1730 ether_addmulti(ifr, &sc->sc_ec) : 1731 ether_delmulti(ifr, &sc->sc_ec); 1732 if (error == ENETRESET) { 1733 /* setup multicast filter, etc */ 1734 error = 0; 1735 } 1736 break; 1737 1738 case SIOCGTABLE1: 1739 error = ipw_get_table1(sc, (uint32_t *)ifr->ifr_data); 1740 break; 1741 1742 case SIOCGRADIO: 1743 error = ipw_get_radio(sc, (int *)ifr->ifr_data); 1744 break; 1745 1746 case SIOCSIFMEDIA: 1747 if (ifr->ifr_media & IFM_IEEE80211_ADHOC) 1748 strlcpy(sc->sc_fwname, "ipw2100-1.2-i.fw", 1749 sizeof(sc->sc_fwname)); 1750 else if (ifr->ifr_media & IFM_IEEE80211_MONITOR) 1751 strlcpy(sc->sc_fwname, "ipw2100-1.2-p.fw", 1752 sizeof(sc->sc_fwname)); 1753 else 1754 strlcpy(sc->sc_fwname, "ipw2100-1.2.fw", 1755 sizeof(sc->sc_fwname)); 1756 1757 ipw_free_firmware(sc); 1758 /* FALLTRHOUGH */ 1759 default: 1760 error = ieee80211_ioctl(&sc->sc_ic, cmd, data); 1761 if (error != ENETRESET) 1762 break; 1763 1764 if (error == ENETRESET) { 1765 if (IS_RUNNING(ifp) && 1766 (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)) 1767 ipw_init(ifp); 1768 error = 0; 1769 } 1770 1771 } 1772 1773 splx(s); 1774 return error; 1775 #undef IS_RUNNING 1776 } 1777 1778 static uint32_t 1779 ipw_read_table1(struct ipw_softc *sc, uint32_t off) 1780 { 1781 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 1782 } 1783 1784 static void 1785 ipw_write_table1(struct ipw_softc *sc, uint32_t off, uint32_t info) 1786 { 1787 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 1788 } 1789 1790 static int 1791 ipw_read_table2(struct ipw_softc *sc, uint32_t off, void *buf, uint32_t *len) 1792 { 1793 uint32_t addr, info; 1794 uint16_t count, size; 1795 uint32_t total; 1796 1797 /* addr[4] + count[2] + size[2] */ 1798 addr = MEM_READ_4(sc, sc->table2_base + off); 1799 info = MEM_READ_4(sc, sc->table2_base + off + 4); 1800 1801 count = info >> 16; 1802 size = info & 0xffff; 1803 total = count * size; 1804 1805 if (total > *len) { 1806 *len = total; 1807 return EINVAL; 1808 } 1809 1810 *len = total; 1811 ipw_read_mem_1(sc, addr, buf, total); 1812 1813 return 0; 1814 } 1815 1816 static void 1817 ipw_stop_master(struct ipw_softc *sc) 1818 { 1819 int ntries; 1820 1821 /* disable interrupts */ 1822 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1823 1824 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1825 for (ntries = 0; ntries < 50; ntries++) { 1826 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1827 break; 1828 DELAY(10); 1829 } 1830 if (ntries == 50) 1831 aprint_error("%s: timeout waiting for master\n", 1832 sc->sc_dev.dv_xname); 1833 1834 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1835 IPW_RST_PRINCETON_RESET); 1836 1837 sc->flags &= ~IPW_FLAG_FW_INITED; 1838 } 1839 1840 static int 1841 ipw_reset(struct ipw_softc *sc) 1842 { 1843 int ntries; 1844 1845 ipw_stop_master(sc); 1846 1847 /* move adapter to D0 state */ 1848 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1849 IPW_CTL_INIT); 1850 1851 /* wait for clock stabilization */ 1852 for (ntries = 0; ntries < 1000; ntries++) { 1853 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY) 1854 break; 1855 DELAY(200); 1856 } 1857 if (ntries == 1000) 1858 return EIO; 1859 1860 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1861 IPW_RST_SW_RESET); 1862 1863 DELAY(10); 1864 1865 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1866 IPW_CTL_INIT); 1867 1868 return 0; 1869 } 1870 1871 /* 1872 * Upload the microcode to the device. 1873 */ 1874 static int 1875 ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size) 1876 { 1877 int ntries; 1878 1879 MEM_WRITE_4(sc, 0x3000e0, 0x80000000); 1880 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1881 1882 MEM_WRITE_2(sc, 0x220000, 0x0703); 1883 MEM_WRITE_2(sc, 0x220000, 0x0707); 1884 1885 MEM_WRITE_1(sc, 0x210014, 0x72); 1886 MEM_WRITE_1(sc, 0x210014, 0x72); 1887 1888 MEM_WRITE_1(sc, 0x210000, 0x40); 1889 MEM_WRITE_1(sc, 0x210000, 0x00); 1890 MEM_WRITE_1(sc, 0x210000, 0x40); 1891 1892 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1893 1894 MEM_WRITE_1(sc, 0x210000, 0x00); 1895 MEM_WRITE_1(sc, 0x210000, 0x00); 1896 MEM_WRITE_1(sc, 0x210000, 0x80); 1897 1898 MEM_WRITE_2(sc, 0x220000, 0x0703); 1899 MEM_WRITE_2(sc, 0x220000, 0x0707); 1900 1901 MEM_WRITE_1(sc, 0x210014, 0x72); 1902 MEM_WRITE_1(sc, 0x210014, 0x72); 1903 1904 MEM_WRITE_1(sc, 0x210000, 0x00); 1905 MEM_WRITE_1(sc, 0x210000, 0x80); 1906 1907 for (ntries = 0; ntries < 10; ntries++) { 1908 if (MEM_READ_1(sc, 0x210000) & 1) 1909 break; 1910 DELAY(10); 1911 } 1912 if (ntries == 10) { 1913 aprint_error("%s: timeout waiting for ucode to initialize\n", 1914 sc->sc_dev.dv_xname); 1915 return EIO; 1916 } 1917 1918 MEM_WRITE_4(sc, 0x3000e0, 0); 1919 1920 return 0; 1921 } 1922 1923 /* set of macros to handle unaligned little endian data in firmware image */ 1924 #define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1925 #define GETLE16(p) ((p)[0] | (p)[1] << 8) 1926 static int 1927 ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size) 1928 { 1929 u_char *p, *end; 1930 uint32_t dst; 1931 uint16_t len; 1932 int error; 1933 1934 p = fw; 1935 end = fw + size; 1936 while (p < end) { 1937 dst = GETLE32(p); p += 4; 1938 len = GETLE16(p); p += 2; 1939 1940 ipw_write_mem_1(sc, dst, p, len); 1941 p += len; 1942 } 1943 1944 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1945 IPW_IO_LED_OFF); 1946 1947 /* enable interrupts */ 1948 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1949 1950 /* kick the firmware */ 1951 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1952 1953 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1954 IPW_CTL_ALLOW_STANDBY); 1955 1956 /* wait at most one second for firmware initialization to complete */ 1957 if ((error = tsleep(sc, 0, "ipwinit", hz)) != 0) { 1958 aprint_error("%s: timeout waiting for firmware initialization " 1959 "to complete\n", sc->sc_dev.dv_xname); 1960 return error; 1961 } 1962 1963 CSR_WRITE_4(sc, IPW_CSR_IO, CSR_READ_4(sc, IPW_CSR_IO) | 1964 IPW_IO_GPIO1_MASK | IPW_IO_GPIO3_MASK); 1965 1966 return 0; 1967 } 1968 1969 /* 1970 * Store firmware into kernel memory so we can download it when we need to, 1971 * e.g when the adapter wakes up from suspend mode. 1972 */ 1973 static int 1974 ipw_cache_firmware(struct ipw_softc *sc) 1975 { 1976 struct ipw_firmware *fw = &sc->fw; 1977 struct ipw_firmware_hdr hdr; 1978 firmware_handle_t fwh; 1979 off_t fwsz, p; 1980 int error; 1981 1982 ipw_free_firmware(sc); 1983 1984 if ((error = firmware_open("if_ipw", sc->sc_fwname, &fwh)) != 0) 1985 goto fail0; 1986 1987 fwsz = firmware_get_size(fwh); 1988 1989 if (fwsz < sizeof(hdr)) 1990 goto fail2; 1991 1992 if ((error = firmware_read(fwh, 0, &hdr, sizeof(hdr))) != 0) 1993 goto fail2; 1994 1995 fw->main_size = le32toh(hdr.main_size); 1996 fw->ucode_size = le32toh(hdr.ucode_size); 1997 1998 fw->main = firmware_malloc(fw->main_size); 1999 if (fw->main == NULL) { 2000 error = ENOMEM; 2001 goto fail1; 2002 } 2003 2004 fw->ucode = firmware_malloc(fw->ucode_size); 2005 if (fw->ucode == NULL) { 2006 error = ENOMEM; 2007 goto fail2; 2008 } 2009 2010 p = sizeof(hdr); 2011 if ((error = firmware_read(fwh, p, fw->main, fw->main_size)) != 0) 2012 goto fail3; 2013 2014 if ((error = firmware_read(fwh, p, fw->main, fw->main_size)) != 0) 2015 goto fail3; 2016 2017 p += fw->main_size; 2018 if ((error = firmware_read(fwh, p, fw->ucode, fw->ucode_size)) != 0) 2019 goto fail3; 2020 2021 DPRINTF(("Firmware cached: main %u, ucode %u\n", fw->main_size, 2022 fw->ucode_size)); 2023 2024 sc->flags |= IPW_FLAG_FW_CACHED; 2025 2026 return 0; 2027 2028 fail3: firmware_free(fw->ucode, 0); 2029 fail2: firmware_free(fw->main, 0); 2030 fail1: firmware_close(fwh); 2031 fail0: 2032 return error; 2033 } 2034 2035 static void 2036 ipw_free_firmware(struct ipw_softc *sc) 2037 { 2038 if (!(sc->flags & IPW_FLAG_FW_CACHED)) 2039 return; 2040 2041 firmware_free(sc->fw.main, 0); 2042 firmware_free(sc->fw.ucode, 0); 2043 2044 sc->flags &= ~IPW_FLAG_FW_CACHED; 2045 } 2046 2047 static int 2048 ipw_config(struct ipw_softc *sc) 2049 { 2050 struct ieee80211com *ic = &sc->sc_ic; 2051 struct ifnet *ifp = &sc->sc_if; 2052 struct ipw_security security; 2053 struct ieee80211_key *k; 2054 struct ipw_wep_key wepkey; 2055 struct ipw_scan_options options; 2056 struct ipw_configuration config; 2057 uint32_t data; 2058 int error, i; 2059 2060 switch (ic->ic_opmode) { 2061 case IEEE80211_M_STA: 2062 case IEEE80211_M_HOSTAP: 2063 data = htole32(IPW_MODE_BSS); 2064 break; 2065 2066 case IEEE80211_M_IBSS: 2067 case IEEE80211_M_AHDEMO: 2068 data = htole32(IPW_MODE_IBSS); 2069 break; 2070 2071 case IEEE80211_M_MONITOR: 2072 data = htole32(IPW_MODE_MONITOR); 2073 break; 2074 } 2075 DPRINTF(("Setting mode to %u\n", le32toh(data))); 2076 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 2077 if (error != 0) 2078 return error; 2079 2080 if (ic->ic_opmode == IEEE80211_M_IBSS || 2081 ic->ic_opmode == IEEE80211_M_MONITOR) { 2082 data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); 2083 DPRINTF(("Setting channel to %u\n", le32toh(data))); 2084 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 2085 if (error != 0) 2086 return error; 2087 } 2088 2089 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2090 DPRINTF(("Enabling adapter\n")); 2091 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 2092 } 2093 2094 DPRINTF(("Setting MAC to %s\n", ether_sprintf(ic->ic_myaddr))); 2095 IEEE80211_ADDR_COPY(LLADDR(ifp->if_sadl), ic->ic_myaddr); 2096 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 2097 IEEE80211_ADDR_LEN); 2098 if (error != 0) 2099 return error; 2100 2101 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 2102 IPW_CFG_PREAMBLE_AUTO | IPW_CFG_802_1x_ENABLE); 2103 2104 if (ic->ic_opmode == IEEE80211_M_IBSS) 2105 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 2106 if (ifp->if_flags & IFF_PROMISC) 2107 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 2108 config.bss_chan = htole32(0x3fff); /* channels 1-14 */ 2109 config.ibss_chan = htole32(0x7ff); /* channels 1-11 */ 2110 DPRINTF(("Setting adapter configuration 0x%08x\n", config.flags)); 2111 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 2112 if (error != 0) 2113 return error; 2114 2115 data = htole32(0x3); /* 1, 2 */ 2116 DPRINTF(("Setting basic tx rates to 0x%x\n", le32toh(data))); 2117 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 2118 if (error != 0) 2119 return error; 2120 2121 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 2122 DPRINTF(("Setting tx rates to 0x%x\n", le32toh(data))); 2123 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 2124 if (error != 0) 2125 return error; 2126 2127 data = htole32(IPW_POWER_MODE_CAM); 2128 DPRINTF(("Setting power mode to %u\n", le32toh(data))); 2129 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 2130 if (error != 0) 2131 return error; 2132 2133 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2134 data = htole32(32); /* default value */ 2135 DPRINTF(("Setting tx power index to %u\n", le32toh(data))); 2136 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 2137 sizeof data); 2138 if (error != 0) 2139 return error; 2140 } 2141 2142 data = htole32(ic->ic_rtsthreshold); 2143 DPRINTF(("Setting RTS threshold to %u\n", le32toh(data))); 2144 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 2145 if (error != 0) 2146 return error; 2147 2148 data = htole32(ic->ic_fragthreshold); 2149 DPRINTF(("Setting frag threshold to %u\n", le32toh(data))); 2150 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 2151 if (error != 0) 2152 return error; 2153 2154 #ifdef IPW_DEBUG 2155 if (ipw_debug > 0) { 2156 printf("Setting ESSID to "); 2157 ieee80211_print_essid(ic->ic_des_essid, ic->ic_des_esslen); 2158 printf("\n"); 2159 } 2160 #endif 2161 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ic->ic_des_essid, 2162 ic->ic_des_esslen); 2163 if (error != 0) 2164 return error; 2165 2166 /* no mandatory BSSID */ 2167 DPRINTF(("Setting mandatory BSSID to null\n")); 2168 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 2169 if (error != 0) 2170 return error; 2171 2172 if (ic->ic_flags & IEEE80211_F_DESBSSID) { 2173 DPRINTF(("Setting desired BSSID to %s\n", 2174 ether_sprintf(ic->ic_des_bssid))); 2175 error = ipw_cmd(sc, IPW_CMD_SET_DESIRED_BSSID, 2176 ic->ic_des_bssid, IEEE80211_ADDR_LEN); 2177 if (error != 0) 2178 return error; 2179 } 2180 2181 (void)memset(&security, 0, sizeof(security)); 2182 security.authmode = (ic->ic_bss->ni_authmode == IEEE80211_AUTH_SHARED) ? 2183 IPW_AUTH_SHARED : IPW_AUTH_OPEN; 2184 security.ciphers = htole32(IPW_CIPHER_NONE); 2185 DPRINTF(("Setting authmode to %u\n", security.authmode)); 2186 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 2187 sizeof security); 2188 if (error != 0) 2189 return error; 2190 2191 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 2192 k = ic->ic_crypto.cs_nw_keys; 2193 for (i = 0; i < IEEE80211_WEP_NKID; i++, k++) { 2194 if (k->wk_keylen == 0) 2195 continue; 2196 2197 wepkey.idx = i; 2198 wepkey.len = k->wk_keylen; 2199 memset(wepkey.key, 0, sizeof(wepkey.key)); 2200 memcpy(wepkey.key, k->wk_key, k->wk_keylen); 2201 DPRINTF(("Setting wep key index %u len %u\n", 2202 wepkey.idx, wepkey.len)); 2203 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY, &wepkey, 2204 sizeof wepkey); 2205 if (error != 0) 2206 return error; 2207 } 2208 2209 data = htole32(ic->ic_crypto.cs_def_txkey); 2210 DPRINTF(("Setting tx key index to %u\n", le32toh(data))); 2211 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY_INDEX, &data, 2212 sizeof data); 2213 if (error != 0) 2214 return error; 2215 } 2216 2217 data = htole32((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) ? IPW_WEPON : 0); 2218 DPRINTF(("Setting wep flags to 0x%x\n", le32toh(data))); 2219 error = ipw_cmd(sc, IPW_CMD_SET_WEP_FLAGS, &data, sizeof data); 2220 if (error != 0) 2221 return error; 2222 2223 #if 0 2224 struct ipw_wpa_ie ie; 2225 2226 memset(&ie, 0 sizeof(ie)); 2227 ie.len = htole32(sizeof (struct ieee80211_ie_wpa)); 2228 DPRINTF(("Setting wpa ie\n")); 2229 error = ipw_cmd(sc, IPW_CMD_SET_WPA_IE, &ie, sizeof ie); 2230 if (error != 0) 2231 return error; 2232 #endif 2233 2234 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2235 data = htole32(ic->ic_bintval); 2236 DPRINTF(("Setting beacon interval to %u\n", le32toh(data))); 2237 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 2238 sizeof data); 2239 if (error != 0) 2240 return error; 2241 } 2242 2243 options.flags = 0; 2244 options.channels = htole32(0x3fff); /* scan channels 1-14 */ 2245 DPRINTF(("Setting scan options to 0x%x\n", le32toh(options.flags))); 2246 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &options, sizeof options); 2247 if (error != 0) 2248 return error; 2249 2250 /* finally, enable adapter (start scanning for an access point) */ 2251 DPRINTF(("Enabling adapter\n")); 2252 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 2253 } 2254 2255 static int 2256 ipw_init(struct ifnet *ifp) 2257 { 2258 struct ipw_softc *sc = ifp->if_softc; 2259 struct ipw_firmware *fw = &sc->fw; 2260 2261 if (!(sc->flags & IPW_FLAG_FW_CACHED)) { 2262 if (ipw_cache_firmware(sc) != 0) { 2263 aprint_error("%s: could not cache the firmware (%s)\n", 2264 sc->sc_dev.dv_xname, sc->sc_fwname); 2265 goto fail; 2266 } 2267 } 2268 2269 ipw_stop(ifp, 0); 2270 2271 if (ipw_reset(sc) != 0) { 2272 aprint_error("%s: could not reset adapter\n", 2273 sc->sc_dev.dv_xname); 2274 goto fail; 2275 } 2276 2277 if (ipw_load_ucode(sc, fw->ucode, fw->ucode_size) != 0) { 2278 aprint_error("%s: could not load microcode\n", 2279 sc->sc_dev.dv_xname); 2280 goto fail; 2281 } 2282 2283 ipw_stop_master(sc); 2284 2285 /* 2286 * Setup tx, rx and status rings. 2287 */ 2288 sc->txold = IPW_NTBD - 1; 2289 sc->txcur = 0; 2290 sc->txfree = IPW_NTBD - 2; 2291 sc->rxcur = IPW_NRBD - 1; 2292 2293 CSR_WRITE_4(sc, IPW_CSR_TX_BASE, sc->tbd_map->dm_segs[0].ds_addr); 2294 CSR_WRITE_4(sc, IPW_CSR_TX_SIZE, IPW_NTBD); 2295 CSR_WRITE_4(sc, IPW_CSR_TX_READ, 0); 2296 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 2297 2298 CSR_WRITE_4(sc, IPW_CSR_RX_BASE, sc->rbd_map->dm_segs[0].ds_addr); 2299 CSR_WRITE_4(sc, IPW_CSR_RX_SIZE, IPW_NRBD); 2300 CSR_WRITE_4(sc, IPW_CSR_RX_READ, 0); 2301 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 2302 2303 CSR_WRITE_4(sc, IPW_CSR_STATUS_BASE, sc->status_map->dm_segs[0].ds_addr); 2304 2305 if (ipw_load_firmware(sc, fw->main, fw->main_size) != 0) { 2306 aprint_error("%s: could not load firmware\n", 2307 sc->sc_dev.dv_xname); 2308 goto fail; 2309 } 2310 2311 sc->flags |= IPW_FLAG_FW_INITED; 2312 2313 /* retrieve information tables base addresses */ 2314 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 2315 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 2316 2317 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 2318 2319 if (ipw_config(sc) != 0) { 2320 aprint_error("%s: device configuration failed\n", 2321 sc->sc_dev.dv_xname); 2322 goto fail; 2323 } 2324 2325 ifp->if_flags &= ~IFF_OACTIVE; 2326 ifp->if_flags |= IFF_RUNNING; 2327 2328 return 0; 2329 2330 fail: ifp->if_flags &= ~IFF_UP; 2331 ipw_stop(ifp, 0); 2332 2333 return EIO; 2334 } 2335 2336 static void 2337 ipw_stop(struct ifnet *ifp, int disable) 2338 { 2339 struct ipw_softc *sc = ifp->if_softc; 2340 struct ieee80211com *ic = &sc->sc_ic; 2341 int i; 2342 2343 ipw_stop_master(sc); 2344 2345 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 2346 2347 /* 2348 * Release tx buffers. 2349 */ 2350 for (i = 0; i < IPW_NTBD; i++) 2351 ipw_release_sbd(sc, &sc->stbd_list[i]); 2352 2353 sc->sc_tx_timer = 0; 2354 ifp->if_timer = 0; 2355 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2356 2357 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2358 } 2359 2360 static void 2361 ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2362 bus_size_t count) 2363 { 2364 for (; count > 0; offset++, datap++, count--) { 2365 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2366 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 2367 } 2368 } 2369 2370 static void 2371 ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2372 bus_size_t count) 2373 { 2374 for (; count > 0; offset++, datap++, count--) { 2375 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2376 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 2377 } 2378 } 2379
Indexes created Tue Sep 30 20:09:53 GMT 2025