if_ipw.c revision 1.28
1 /* $NetBSD: if_ipw.c,v 1.28 2006/09/24 03:53:09 jmcneill Exp $ */ 2 /* FreeBSD: src/sys/dev/ipw/if_ipw.c,v 1.15 2005/11/13 17:17:40 damien Exp */ 3 4 /*- 5 * Copyright (c) 2004, 2005 6 * Damien Bergamini <damien.bergamini (at) free.fr>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: if_ipw.c,v 1.28 2006/09/24 03:53:09 jmcneill Exp $"); 33 34 /*- 35 * Intel(R) PRO/Wireless 2100 MiniPCI driver 36 * http://www.intel.com/network/connectivity/products/wireless/prowireless_mobile.htm 37 */ 38 39 #include "bpfilter.h" 40 41 #include <sys/param.h> 42 #include <sys/sockio.h> 43 #include <sys/sysctl.h> 44 #include <sys/mbuf.h> 45 #include <sys/kernel.h> 46 #include <sys/socket.h> 47 #include <sys/systm.h> 48 #include <sys/malloc.h> 49 #include <sys/conf.h> 50 51 #include <machine/bus.h> 52 #include <machine/endian.h> 53 #include <machine/intr.h> 54 55 #include <dev/pci/pcireg.h> 56 #include <dev/pci/pcivar.h> 57 #include <dev/pci/pcidevs.h> 58 59 #if NBPFILTER > 0 60 #include <net/bpf.h> 61 #endif 62 #include <net/if.h> 63 #include <net/if_arp.h> 64 #include <net/if_dl.h> 65 #include <net/if_ether.h> 66 #include <net/if_media.h> 67 #include <net/if_types.h> 68 69 #include <net80211/ieee80211_var.h> 70 #include <net80211/ieee80211_radiotap.h> 71 72 #include <netinet/in.h> 73 #include <netinet/in_systm.h> 74 #include <netinet/in_var.h> 75 #include <netinet/ip.h> 76 77 #include <dev/firmload.h> 78 79 #include <dev/pci/if_ipwreg.h> 80 #include <dev/pci/if_ipwvar.h> 81 82 #ifdef IPW_DEBUG 83 #define DPRINTF(x) if (ipw_debug > 0) printf x 84 #define DPRINTFN(n, x) if (ipw_debug >= (n)) printf x 85 int ipw_debug = 0; 86 #else 87 #define DPRINTF(x) 88 #define DPRINTFN(n, x) 89 #endif 90 91 static int ipw_dma_alloc(struct ipw_softc *); 92 static void ipw_release(struct ipw_softc *); 93 static int ipw_match(struct device *, struct cfdata *, void *); 94 static void ipw_attach(struct device *, struct device *, void *); 95 static int ipw_detach(struct device *, int); 96 97 static void ipw_shutdown(void *); 98 static int ipw_suspend(struct ipw_softc *); 99 static int ipw_resume(struct ipw_softc *); 100 static void ipw_powerhook(int, void *); 101 102 static int ipw_media_change(struct ifnet *); 103 static void ipw_media_status(struct ifnet *, struct ifmediareq *); 104 static int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 105 static uint16_t ipw_read_prom_word(struct ipw_softc *, uint8_t); 106 static void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 107 static void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 108 static void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 109 struct ipw_soft_bd *, struct ipw_soft_buf *); 110 static void ipw_rx_intr(struct ipw_softc *); 111 static void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 112 static void ipw_tx_intr(struct ipw_softc *); 113 static int ipw_intr(void *); 114 static int ipw_cmd(struct ipw_softc *, uint32_t, void *, uint32_t); 115 static int ipw_tx_start(struct ifnet *, struct mbuf *, 116 struct ieee80211_node *); 117 static void ipw_start(struct ifnet *); 118 static void ipw_watchdog(struct ifnet *); 119 static int ipw_ioctl(struct ifnet *, u_long, caddr_t); 120 static int ipw_get_table1(struct ipw_softc *, uint32_t *); 121 static int ipw_get_radio(struct ipw_softc *, int *); 122 static void ipw_stop_master(struct ipw_softc *); 123 static int ipw_reset(struct ipw_softc *); 124 static int ipw_load_ucode(struct ipw_softc *, u_char *, int); 125 static int ipw_load_firmware(struct ipw_softc *, u_char *, int); 126 static int ipw_cache_firmware(struct ipw_softc *); 127 static void ipw_free_firmware(struct ipw_softc *); 128 static int ipw_config(struct ipw_softc *); 129 static int ipw_init(struct ifnet *); 130 static void ipw_stop(struct ifnet *, int); 131 static uint32_t ipw_read_table1(struct ipw_softc *, uint32_t); 132 static void ipw_write_table1(struct ipw_softc *, uint32_t, uint32_t); 133 static int ipw_read_table2(struct ipw_softc *, uint32_t, void *, uint32_t *); 134 static void ipw_read_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 135 bus_size_t); 136 static void ipw_write_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 137 bus_size_t); 138 139 /* 140 * Supported rates for 802.11b mode (in 500Kbps unit). 141 */ 142 static const struct ieee80211_rateset ipw_rateset_11b = 143 { 4, { 2, 4, 11, 22 } }; 144 145 static inline uint8_t 146 MEM_READ_1(struct ipw_softc *sc, uint32_t addr) 147 { 148 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 149 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); 150 } 151 152 static inline uint32_t 153 MEM_READ_4(struct ipw_softc *sc, uint32_t addr) 154 { 155 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 156 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); 157 } 158 159 CFATTACH_DECL(ipw, sizeof (struct ipw_softc), ipw_match, ipw_attach, 160 ipw_detach, NULL); 161 162 static int 163 ipw_match(struct device *parent, struct cfdata *match, void *aux) 164 { 165 struct pci_attach_args *pa = aux; 166 167 if (PCI_VENDOR (pa->pa_id) == PCI_VENDOR_INTEL && 168 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_PRO_WL_2100) 169 return 1; 170 171 return 0; 172 } 173 174 /* Base Address Register */ 175 #define IPW_PCI_BAR0 0x10 176 177 static void 178 ipw_attach(struct device *parent, struct device *self, void *aux) 179 { 180 struct ipw_softc *sc = (struct ipw_softc *)self; 181 struct ieee80211com *ic = &sc->sc_ic; 182 struct ifnet *ifp = &sc->sc_if; 183 struct pci_attach_args *pa = aux; 184 const char *intrstr; 185 char devinfo[256]; 186 bus_space_tag_t memt; 187 bus_space_handle_t memh; 188 bus_addr_t base; 189 pci_intr_handle_t ih; 190 uint32_t data; 191 uint16_t val; 192 int i, revision, error; 193 194 sc->sc_pct = pa->pa_pc; 195 sc->sc_pcitag = pa->pa_tag; 196 197 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof devinfo); 198 revision = PCI_REVISION(pa->pa_class); 199 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, revision); 200 201 /* enable bus-mastering */ 202 data = pci_conf_read(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG); 203 data |= PCI_COMMAND_MASTER_ENABLE; 204 pci_conf_write(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG, data); 205 206 /* clear device specific PCI configuration register 0x41 */ 207 data = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 208 data &= ~0x0000ff00; 209 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, data); 210 211 /* map the register window */ 212 error = pci_mapreg_map(pa, IPW_PCI_BAR0, PCI_MAPREG_TYPE_MEM | 213 PCI_MAPREG_MEM_TYPE_32BIT, 0, &memt, &memh, &base, &sc->sc_sz); 214 if (error != 0) { 215 aprint_error("%s: could not map memory space\n", 216 sc->sc_dev.dv_xname); 217 return; 218 } 219 220 sc->sc_st = memt; 221 sc->sc_sh = memh; 222 sc->sc_dmat = pa->pa_dmat; 223 strlcpy(sc->sc_fwname, "ipw2100-1.2.fw", sizeof(sc->sc_fwname)); 224 225 /* disable interrupts */ 226 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 227 228 if (pci_intr_map(pa, &ih) != 0) { 229 aprint_error("%s: could not map interrupt\n", 230 sc->sc_dev.dv_xname); 231 return; 232 } 233 234 intrstr = pci_intr_string(sc->sc_pct, ih); 235 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, ipw_intr, sc); 236 if (sc->sc_ih == NULL) { 237 aprint_error("%s: could not establish interrupt", 238 sc->sc_dev.dv_xname); 239 if (intrstr != NULL) 240 aprint_error(" at %s", intrstr); 241 aprint_error("\n"); 242 return; 243 } 244 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 245 246 if (ipw_reset(sc) != 0) { 247 aprint_error("%s: could not reset adapter\n", 248 sc->sc_dev.dv_xname); 249 goto fail; 250 } 251 252 if (ipw_dma_alloc(sc) != 0) { 253 aprint_error("%s: could not allocate DMA resources\n", 254 sc->sc_dev.dv_xname); 255 goto fail; 256 } 257 258 ifp->if_softc = sc; 259 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 260 ifp->if_init = ipw_init; 261 ifp->if_stop = ipw_stop; 262 ifp->if_ioctl = ipw_ioctl; 263 ifp->if_start = ipw_start; 264 ifp->if_watchdog = ipw_watchdog; 265 IFQ_SET_READY(&ifp->if_snd); 266 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 267 268 ic->ic_ifp = ifp; 269 ic->ic_phytype = IEEE80211_T_DS; 270 ic->ic_opmode = IEEE80211_M_STA; 271 ic->ic_state = IEEE80211_S_INIT; 272 273 /* set device capabilities */ 274 ic->ic_caps = 275 IEEE80211_C_SHPREAMBLE /* short preamble supported */ 276 | IEEE80211_C_TXPMGT /* tx power management */ 277 | IEEE80211_C_IBSS /* ibss mode */ 278 | IEEE80211_C_MONITOR /* monitor mode */ 279 ; 280 281 /* read MAC address from EEPROM */ 282 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0); 283 ic->ic_myaddr[0] = val >> 8; 284 ic->ic_myaddr[1] = val & 0xff; 285 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 1); 286 ic->ic_myaddr[2] = val >> 8; 287 ic->ic_myaddr[3] = val & 0xff; 288 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 2); 289 ic->ic_myaddr[4] = val >> 8; 290 ic->ic_myaddr[5] = val & 0xff; 291 292 /* set supported .11b rates */ 293 ic->ic_sup_rates[IEEE80211_MODE_11B] = ipw_rateset_11b; 294 295 /* set supported .11b channels (read from EEPROM) */ 296 if ((val = ipw_read_prom_word(sc, IPW_EEPROM_CHANNEL_LIST)) == 0) 297 val = 0x7ff; /* default to channels 1-11 */ 298 val <<= 1; 299 for (i = 1; i < 16; i++) { 300 if (val & (1 << i)) { 301 ic->ic_channels[i].ic_freq = 302 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 303 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 304 } 305 } 306 307 /* check support for radio transmitter switch in EEPROM */ 308 if (!(ipw_read_prom_word(sc, IPW_EEPROM_RADIO) & 8)) 309 sc->flags |= IPW_FLAG_HAS_RADIO_SWITCH; 310 311 aprint_normal("%s: 802.11 address %s\n", sc->sc_dev.dv_xname, 312 ether_sprintf(ic->ic_myaddr)); 313 314 if_attach(ifp); 315 ieee80211_ifattach(ic); 316 317 /* override state transition machine */ 318 sc->sc_newstate = ic->ic_newstate; 319 ic->ic_newstate = ipw_newstate; 320 321 ieee80211_media_init(ic, ipw_media_change, ipw_media_status); 322 323 #if NBPFILTER > 0 324 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 325 sizeof (struct ieee80211_frame) + 64, &sc->sc_drvbpf); 326 327 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 328 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 329 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 330 331 sc->sc_txtap_len = sizeof sc->sc_txtapu; 332 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 333 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 334 #endif 335 336 /* 337 * Add a few sysctl knobs. 338 * XXX: Not yet 339 */ 340 sc->dwelltime = 100; 341 342 /* 343 * Make sure the interface is shutdown during reboot. 344 */ 345 sc->sc_sdhook = shutdownhook_establish(ipw_shutdown, sc); 346 if (sc->sc_sdhook == NULL) 347 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 348 sc->sc_dev.dv_xname); 349 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 350 ipw_powerhook, sc); 351 if (sc->sc_powerhook == NULL) 352 printf("%s: WARNING: unable to establish power hook\n", 353 sc->sc_dev.dv_xname); 354 355 ieee80211_announce(ic); 356 357 return; 358 359 fail: ipw_detach(self, 0); 360 } 361 362 static int 363 ipw_detach(struct device* self, int flags) 364 { 365 struct ipw_softc *sc = (struct ipw_softc *)self; 366 struct ifnet *ifp = &sc->sc_if; 367 368 if (ifp->if_softc) { 369 ipw_stop(ifp, 1); 370 ipw_free_firmware(sc); 371 372 #if NBPFILTER > 0 373 bpfdetach(ifp); 374 #endif 375 ieee80211_ifdetach(&sc->sc_ic); 376 if_detach(ifp); 377 378 ipw_release(sc); 379 } 380 381 if (sc->sc_ih != NULL) { 382 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 383 sc->sc_ih = NULL; 384 } 385 386 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 387 388 return 0; 389 } 390 391 static int 392 ipw_dma_alloc(struct ipw_softc *sc) 393 { 394 struct ipw_soft_bd *sbd; 395 struct ipw_soft_hdr *shdr; 396 struct ipw_soft_buf *sbuf; 397 int error, i, nsegs; 398 399 /* 400 * Allocate and map tx ring. 401 */ 402 error = bus_dmamap_create(sc->sc_dmat, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, 403 BUS_DMA_NOWAIT, &sc->tbd_map); 404 if (error != 0) { 405 aprint_error("%s: could not create tbd dma map\n", 406 sc->sc_dev.dv_xname); 407 goto fail; 408 } 409 410 error = bus_dmamem_alloc(sc->sc_dmat, IPW_TBD_SZ, PAGE_SIZE, 0, 411 &sc->tbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 412 if (error != 0) { 413 aprint_error("%s: could not allocate tbd dma memory\n", 414 sc->sc_dev.dv_xname); 415 goto fail; 416 } 417 418 error = bus_dmamem_map(sc->sc_dmat, &sc->tbd_seg, nsegs, IPW_TBD_SZ, 419 (caddr_t *)&sc->tbd_list, BUS_DMA_NOWAIT); 420 if (error != 0) { 421 aprint_error("%s: could not map tbd dma memory\n", 422 sc->sc_dev.dv_xname); 423 goto fail; 424 } 425 426 error = bus_dmamap_load(sc->sc_dmat, sc->tbd_map, sc->tbd_list, 427 IPW_TBD_SZ, NULL, BUS_DMA_NOWAIT); 428 if (error != 0) { 429 aprint_error("%s: could not load tbd dma memory\n", 430 sc->sc_dev.dv_xname); 431 goto fail; 432 } 433 434 (void)memset(sc->tbd_list, 0, IPW_TBD_SZ); 435 436 /* 437 * Allocate and map rx ring. 438 */ 439 error = bus_dmamap_create(sc->sc_dmat, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, 440 BUS_DMA_NOWAIT, &sc->rbd_map); 441 if (error != 0) { 442 aprint_error("%s: could not create rbd dma map\n", 443 sc->sc_dev.dv_xname); 444 goto fail; 445 } 446 447 error = bus_dmamem_alloc(sc->sc_dmat, IPW_RBD_SZ, PAGE_SIZE, 0, 448 &sc->rbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 449 if (error != 0) { 450 aprint_error("%s: could not allocate rbd dma memory\n", 451 sc->sc_dev.dv_xname); 452 goto fail; 453 } 454 455 error = bus_dmamem_map(sc->sc_dmat, &sc->rbd_seg, nsegs, IPW_RBD_SZ, 456 (caddr_t *)&sc->rbd_list, BUS_DMA_NOWAIT); 457 if (error != 0) { 458 aprint_error("%s: could not map rbd dma memory\n", 459 sc->sc_dev.dv_xname); 460 goto fail; 461 } 462 463 error = bus_dmamap_load(sc->sc_dmat, sc->rbd_map, sc->rbd_list, 464 IPW_RBD_SZ, NULL, BUS_DMA_NOWAIT); 465 if (error != 0) { 466 aprint_error("%s: could not load rbd dma memory\n", 467 sc->sc_dev.dv_xname); 468 goto fail; 469 } 470 471 (void)memset(sc->rbd_list, 0, IPW_RBD_SZ); 472 473 /* 474 * Allocate and map status ring. 475 */ 476 error = bus_dmamap_create(sc->sc_dmat, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 477 0, BUS_DMA_NOWAIT, &sc->status_map); 478 if (error != 0) { 479 aprint_error("%s: could not create status dma map\n", 480 sc->sc_dev.dv_xname); 481 goto fail; 482 } 483 484 error = bus_dmamem_alloc(sc->sc_dmat, IPW_STATUS_SZ, PAGE_SIZE, 0, 485 &sc->status_seg, 1, &nsegs, BUS_DMA_NOWAIT); 486 if (error != 0) { 487 aprint_error("%s: could not allocate status dma memory\n", 488 sc->sc_dev.dv_xname); 489 goto fail; 490 } 491 492 error = bus_dmamem_map(sc->sc_dmat, &sc->status_seg, nsegs, 493 IPW_STATUS_SZ, (caddr_t *)&sc->status_list, BUS_DMA_NOWAIT); 494 if (error != 0) { 495 aprint_error("%s: could not map status dma memory\n", 496 sc->sc_dev.dv_xname); 497 goto fail; 498 } 499 500 error = bus_dmamap_load(sc->sc_dmat, sc->status_map, sc->status_list, 501 IPW_STATUS_SZ, NULL, BUS_DMA_NOWAIT); 502 if (error != 0) { 503 aprint_error("%s: could not load status dma memory\n", 504 sc->sc_dev.dv_xname); 505 goto fail; 506 } 507 508 (void)memset(sc->status_list, 0, IPW_STATUS_SZ); 509 510 /* 511 * Allocate command DMA map. 512 */ 513 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_cmd), 514 1, sizeof (struct ipw_cmd), 0, BUS_DMA_NOWAIT, &sc->cmd_map); 515 if (error != 0) { 516 aprint_error("%s: could not create cmd dma map\n", 517 sc->sc_dev.dv_xname); 518 goto fail; 519 } 520 521 error = bus_dmamem_alloc(sc->sc_dmat, sizeof (struct ipw_cmd), 522 PAGE_SIZE, 0, &sc->cmd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 523 if (error != 0) { 524 aprint_error("%s: could not allocate cmd dma memory\n", 525 sc->sc_dev.dv_xname); 526 goto fail; 527 } 528 529 error = bus_dmamem_map(sc->sc_dmat, &sc->cmd_seg, nsegs, 530 sizeof (struct ipw_cmd), (caddr_t *)&sc->cmd, BUS_DMA_NOWAIT); 531 if (error != 0) { 532 aprint_error("%s: could not map cmd dma memory\n", 533 sc->sc_dev.dv_xname); 534 goto fail; 535 } 536 537 error = bus_dmamap_load(sc->sc_dmat, sc->cmd_map, &sc->cmd, 538 sizeof (struct ipw_cmd), NULL, BUS_DMA_NOWAIT); 539 if (error != 0) { 540 aprint_error("%s: could not map cmd dma memory\n", 541 sc->sc_dev.dv_xname); 542 return error; 543 } 544 545 /* 546 * Allocate and map hdr list. 547 */ 548 549 error = bus_dmamap_create(sc->sc_dmat, 550 IPW_NDATA * sizeof(struct ipw_hdr), 1, 551 sizeof(struct ipw_hdr), 0, BUS_DMA_NOWAIT, 552 &sc->hdr_map); 553 if (error != 0) { 554 aprint_error("%s: could not create hdr dma map\n", 555 sc->sc_dev.dv_xname); 556 goto fail; 557 } 558 559 error = bus_dmamem_alloc(sc->sc_dmat, 560 IPW_NDATA * sizeof(struct ipw_hdr), PAGE_SIZE, 0, &sc->hdr_seg, 561 1, &nsegs, BUS_DMA_NOWAIT); 562 if (error != 0) { 563 aprint_error("%s: could not allocate hdr memory\n", 564 sc->sc_dev.dv_xname); 565 goto fail; 566 } 567 568 error = bus_dmamem_map(sc->sc_dmat, &sc->hdr_seg, nsegs, 569 IPW_NDATA * sizeof(struct ipw_hdr), (caddr_t *)&sc->hdr_list, 570 BUS_DMA_NOWAIT); 571 if (error != 0) { 572 aprint_error("%s: could not map hdr memory\n", 573 sc->sc_dev.dv_xname); 574 goto fail; 575 } 576 577 error = bus_dmamap_load(sc->sc_dmat, sc->hdr_map, sc->hdr_list, 578 IPW_NDATA * sizeof(struct ipw_hdr), NULL, BUS_DMA_NOWAIT); 579 if (error != 0) { 580 aprint_error("%s: could not load hdr memory\n", 581 sc->sc_dev.dv_xname); 582 goto fail; 583 } 584 585 (void)memset(sc->hdr_list, 0, IPW_HDR_SZ); 586 587 /* 588 * Create DMA hdrs tailq. 589 */ 590 TAILQ_INIT(&sc->sc_free_shdr); 591 for (i = 0; i < IPW_NDATA; i++) { 592 shdr = &sc->shdr_list[i]; 593 shdr->hdr = sc->hdr_list + i; 594 shdr->offset = sizeof(struct ipw_hdr) * i; 595 shdr->addr = sc->hdr_map->dm_segs[0].ds_addr + shdr->offset; 596 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 597 } 598 599 /* 600 * Allocate tx buffers DMA maps. 601 */ 602 TAILQ_INIT(&sc->sc_free_sbuf); 603 for (i = 0; i < IPW_NDATA; i++) { 604 sbuf = &sc->tx_sbuf_list[i]; 605 606 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 607 IPW_MAX_NSEG, MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 608 if (error != 0) { 609 aprint_error("%s: could not create txbuf dma map\n", 610 sc->sc_dev.dv_xname); 611 goto fail; 612 } 613 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 614 } 615 616 /* 617 * Initialize tx ring. 618 */ 619 for (i = 0; i < IPW_NTBD; i++) { 620 sbd = &sc->stbd_list[i]; 621 sbd->bd = &sc->tbd_list[i]; 622 sbd->type = IPW_SBD_TYPE_NOASSOC; 623 } 624 625 /* 626 * Pre-allocate rx buffers and DMA maps 627 */ 628 for (i = 0; i < IPW_NRBD; i++) { 629 sbd = &sc->srbd_list[i]; 630 sbuf = &sc->rx_sbuf_list[i]; 631 sbd->bd = &sc->rbd_list[i]; 632 633 MGETHDR(sbuf->m, M_DONTWAIT, MT_DATA); 634 if (sbuf->m == NULL) { 635 aprint_error("%s: could not allocate rx mbuf\n", 636 sc->sc_dev.dv_xname); 637 error = ENOMEM; 638 goto fail; 639 } 640 641 MCLGET(sbuf->m, M_DONTWAIT); 642 if (!(sbuf->m->m_flags & M_EXT)) { 643 m_freem(sbuf->m); 644 aprint_error("%s: could not allocate rx mbuf cluster\n", 645 sc->sc_dev.dv_xname); 646 error = ENOMEM; 647 goto fail; 648 } 649 650 sbuf->m->m_pkthdr.len = sbuf->m->m_len = sbuf->m->m_ext.ext_size; 651 652 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 653 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sbuf->map); 654 if (error != 0) { 655 aprint_error("%s: could not create rxbuf dma map\n", 656 sc->sc_dev.dv_xname); 657 m_freem(sbuf->m); 658 goto fail; 659 } 660 661 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, 662 sbuf->m, BUS_DMA_READ | BUS_DMA_NOWAIT); 663 if (error != 0) { 664 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 665 m_freem(sbuf->m); 666 aprint_error("%s: could not map rxbuf dma memory\n", 667 sc->sc_dev.dv_xname); 668 goto fail; 669 } 670 671 sbd->type = IPW_SBD_TYPE_DATA; 672 sbd->priv = sbuf; 673 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 674 sbd->bd->len = htole32(MCLBYTES); 675 676 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, 677 sbuf->map->dm_mapsize, BUS_DMASYNC_PREREAD); 678 679 } 680 681 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 0, IPW_RBD_SZ, 682 BUS_DMASYNC_PREREAD); 683 684 return 0; 685 686 fail: ipw_release(sc); 687 return error; 688 } 689 690 static void 691 ipw_release(struct ipw_softc *sc) 692 { 693 struct ipw_soft_buf *sbuf; 694 int i; 695 696 if (sc->tbd_map != NULL) { 697 if (sc->tbd_list != NULL) { 698 bus_dmamap_unload(sc->sc_dmat, sc->tbd_map); 699 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->tbd_list, 700 IPW_TBD_SZ); 701 bus_dmamem_free(sc->sc_dmat, &sc->tbd_seg, 1); 702 } 703 bus_dmamap_destroy(sc->sc_dmat, sc->tbd_map); 704 } 705 706 if (sc->rbd_map != NULL) { 707 if (sc->rbd_list != NULL) { 708 bus_dmamap_unload(sc->sc_dmat, sc->rbd_map); 709 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->rbd_list, 710 IPW_RBD_SZ); 711 bus_dmamem_free(sc->sc_dmat, &sc->rbd_seg, 1); 712 } 713 bus_dmamap_destroy(sc->sc_dmat, sc->rbd_map); 714 } 715 716 if (sc->status_map != NULL) { 717 if (sc->status_list != NULL) { 718 bus_dmamap_unload(sc->sc_dmat, sc->status_map); 719 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->status_list, 720 IPW_RBD_SZ); 721 bus_dmamem_free(sc->sc_dmat, &sc->status_seg, 1); 722 } 723 bus_dmamap_destroy(sc->sc_dmat, sc->status_map); 724 } 725 726 for (i = 0; i < IPW_NTBD; i++) 727 ipw_release_sbd(sc, &sc->stbd_list[i]); 728 729 if (sc->cmd_map != NULL) 730 bus_dmamap_destroy(sc->sc_dmat, sc->cmd_map); 731 732 if (sc->hdr_list != NULL) { 733 bus_dmamap_unload(sc->sc_dmat, sc->hdr_map); 734 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->hdr_list, 735 IPW_NDATA * sizeof(struct ipw_hdr)); 736 } 737 if (sc->hdr_map != NULL) { 738 bus_dmamem_free(sc->sc_dmat, &sc->hdr_seg, 1); 739 bus_dmamap_destroy(sc->sc_dmat, sc->hdr_map); 740 } 741 742 for (i = 0; i < IPW_NDATA; i++) 743 bus_dmamap_destroy(sc->sc_dmat, sc->tx_sbuf_list[i].map); 744 745 for (i = 0; i < IPW_NRBD; i++) { 746 sbuf = &sc->rx_sbuf_list[i]; 747 if (sbuf->map != NULL) { 748 if (sbuf->m != NULL) { 749 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 750 m_freem(sbuf->m); 751 } 752 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 753 } 754 } 755 756 } 757 758 static void 759 ipw_shutdown(void *arg) 760 { 761 struct ipw_softc *sc = (struct ipw_softc *)arg; 762 struct ifnet *ifp = sc->sc_ic.ic_ifp; 763 764 ipw_stop(ifp, 1); 765 } 766 767 768 static int 769 ipw_suspend(struct ipw_softc *sc) 770 { 771 struct ifnet *ifp = sc->sc_ic.ic_ifp; 772 773 ipw_stop(ifp, 1); 774 775 return 0; 776 } 777 778 static int 779 ipw_resume(struct ipw_softc *sc) 780 { 781 struct ifnet *ifp = sc->sc_ic.ic_ifp; 782 pcireg_t data; 783 784 /* clear device specific PCI configuration register 0x41 */ 785 data = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 786 data &= ~0x0000ff00; 787 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, data); 788 789 if (ifp->if_flags & IFF_UP) { 790 ipw_init(ifp); 791 if (ifp->if_flags & IFF_RUNNING) 792 ipw_start(ifp); 793 } 794 795 return 0; 796 } 797 798 static void 799 ipw_powerhook(int why, void *arg) 800 { 801 struct ipw_softc *sc = arg; 802 int s; 803 804 s = splnet(); 805 switch (why) { 806 case PWR_SUSPEND: 807 case PWR_STANDBY: 808 ipw_suspend(sc); 809 break; 810 case PWR_RESUME: 811 ipw_resume(sc); 812 break; 813 case PWR_SOFTSUSPEND: 814 case PWR_SOFTSTANDBY: 815 case PWR_SOFTRESUME: 816 break; 817 } 818 splx(s); 819 } 820 821 static int 822 ipw_media_change(struct ifnet *ifp) 823 { 824 int error; 825 826 error = ieee80211_media_change(ifp); 827 if (error != ENETRESET) 828 return error; 829 830 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 831 ipw_init(ifp); 832 833 return 0; 834 } 835 836 /* 837 * The firmware automatically adapts the transmit speed. We report the current 838 * transmit speed here. 839 */ 840 static void 841 ipw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 842 { 843 #define N(a) (sizeof (a) / sizeof (a[0])) 844 struct ipw_softc *sc = ifp->if_softc; 845 struct ieee80211com *ic = &sc->sc_ic; 846 static const struct { 847 uint32_t val; 848 int rate; 849 } rates[] = { 850 { IPW_RATE_DS1, 2 }, 851 { IPW_RATE_DS2, 4 }, 852 { IPW_RATE_DS5, 11 }, 853 { IPW_RATE_DS11, 22 }, 854 }; 855 uint32_t val; 856 int rate, i; 857 858 imr->ifm_status = IFM_AVALID; 859 imr->ifm_active = IFM_IEEE80211; 860 if (ic->ic_state == IEEE80211_S_RUN) 861 imr->ifm_status |= IFM_ACTIVE; 862 863 /* read current transmission rate from adapter */ 864 val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE) & 0xf; 865 866 /* convert ipw rate to 802.11 rate */ 867 for (i = 0; i < N(rates) && rates[i].val != val; i++); 868 rate = (i < N(rates)) ? rates[i].rate : 0; 869 870 imr->ifm_active |= IFM_IEEE80211_11B; 871 imr->ifm_active |= ieee80211_rate2media(ic, rate, IEEE80211_MODE_11B); 872 switch (ic->ic_opmode) { 873 case IEEE80211_M_STA: 874 break; 875 876 case IEEE80211_M_IBSS: 877 imr->ifm_active |= IFM_IEEE80211_ADHOC; 878 break; 879 880 case IEEE80211_M_MONITOR: 881 imr->ifm_active |= IFM_IEEE80211_MONITOR; 882 break; 883 884 case IEEE80211_M_AHDEMO: 885 case IEEE80211_M_HOSTAP: 886 /* should not get there */ 887 break; 888 } 889 #undef N 890 } 891 892 static int 893 ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 894 { 895 struct ifnet *ifp = ic->ic_ifp; 896 struct ipw_softc *sc = ifp->if_softc; 897 struct ieee80211_node *ni; 898 uint8_t macaddr[IEEE80211_ADDR_LEN]; 899 uint32_t len; 900 901 switch (nstate) { 902 case IEEE80211_S_RUN: 903 DELAY(200); /* firmware needs a short delay here */ 904 905 len = IEEE80211_ADDR_LEN; 906 ipw_read_table2(sc, IPW_INFO_CURRENT_BSSID, macaddr, &len); 907 908 ni = ieee80211_find_node(&ic->ic_scan, macaddr); 909 if (ni == NULL) 910 break; 911 912 ieee80211_ref_node(ni); 913 ieee80211_sta_join(ic, ni); 914 ieee80211_node_authorize(ni); 915 916 if (ic->ic_opmode == IEEE80211_M_STA) 917 ieee80211_notify_node_join(ic, ni, 1); 918 break; 919 920 case IEEE80211_S_INIT: 921 case IEEE80211_S_SCAN: 922 case IEEE80211_S_AUTH: 923 case IEEE80211_S_ASSOC: 924 break; 925 } 926 927 ic->ic_state = nstate; 928 return 0; 929 } 930 931 /* 932 * Read 16 bits at address 'addr' from the serial EEPROM. 933 */ 934 static uint16_t 935 ipw_read_prom_word(struct ipw_softc *sc, uint8_t addr) 936 { 937 uint32_t tmp; 938 uint16_t val; 939 int n; 940 941 /* clock C once before the first command */ 942 IPW_EEPROM_CTL(sc, 0); 943 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 944 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 945 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 946 947 /* write start bit (1) */ 948 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 949 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 950 951 /* write READ opcode (10) */ 952 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 953 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 954 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 955 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 956 957 /* write address A7-A0 */ 958 for (n = 7; n >= 0; n--) { 959 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 960 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D)); 961 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 962 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D) | IPW_EEPROM_C); 963 } 964 965 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 966 967 /* read data Q15-Q0 */ 968 val = 0; 969 for (n = 15; n >= 0; n--) { 970 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 971 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 972 tmp = MEM_READ_4(sc, IPW_MEM_EEPROM_CTL); 973 val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n; 974 } 975 976 IPW_EEPROM_CTL(sc, 0); 977 978 /* clear Chip Select and clock C */ 979 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 980 IPW_EEPROM_CTL(sc, 0); 981 IPW_EEPROM_CTL(sc, IPW_EEPROM_C); 982 983 return le16toh(val); 984 } 985 986 static void 987 ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 988 { 989 struct ipw_cmd *cmd; 990 991 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof (struct ipw_cmd), 992 BUS_DMASYNC_POSTREAD); 993 994 cmd = mtod(sbuf->m, struct ipw_cmd *); 995 996 DPRINTFN(2, ("cmd ack'ed (%u, %u, %u, %u, %u)\n", le32toh(cmd->type), 997 le32toh(cmd->subtype), le32toh(cmd->seq), le32toh(cmd->len), 998 le32toh(cmd->status))); 999 1000 wakeup(&sc->cmd); 1001 } 1002 1003 static void 1004 ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 1005 { 1006 struct ieee80211com *ic = &sc->sc_ic; 1007 struct ifnet *ifp = sc->sc_ic.ic_ifp; 1008 uint32_t state; 1009 1010 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof state, 1011 BUS_DMASYNC_POSTREAD); 1012 1013 state = le32toh(*mtod(sbuf->m, uint32_t *)); 1014 1015 DPRINTFN(2, ("entering state %u\n", state)); 1016 1017 switch (state) { 1018 case IPW_STATE_ASSOCIATED: 1019 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1020 break; 1021 1022 case IPW_STATE_SCANNING: 1023 /* don't leave run state on background scan */ 1024 if (ic->ic_state != IEEE80211_S_RUN) 1025 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1026 1027 ic->ic_flags |= IEEE80211_F_SCAN; 1028 break; 1029 1030 case IPW_STATE_SCAN_COMPLETE: 1031 ieee80211_notify_scan_done(ic); 1032 ic->ic_flags &= ~IEEE80211_F_SCAN; 1033 break; 1034 1035 case IPW_STATE_ASSOCIATION_LOST: 1036 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1037 break; 1038 1039 case IPW_STATE_RADIO_DISABLED: 1040 ic->ic_ifp->if_flags &= ~IFF_UP; 1041 ipw_stop(ifp, 1); 1042 break; 1043 } 1044 } 1045 1046 /* 1047 * XXX: Hack to set the current channel to the value advertised in beacons or 1048 * probe responses. Only used during AP detection. 1049 */ 1050 static void 1051 ipw_fix_channel(struct ieee80211com *ic, struct mbuf *m) 1052 { 1053 struct ieee80211_frame *wh; 1054 uint8_t subtype; 1055 uint8_t *frm, *efrm; 1056 1057 wh = mtod(m, struct ieee80211_frame *); 1058 1059 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_MGT) 1060 return; 1061 1062 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 1063 1064 if (subtype != IEEE80211_FC0_SUBTYPE_BEACON && 1065 subtype != IEEE80211_FC0_SUBTYPE_PROBE_RESP) 1066 return; 1067 1068 frm = (uint8_t *)(wh + 1); 1069 efrm = mtod(m, uint8_t *) + m->m_len; 1070 1071 frm += 12; /* skip tstamp, bintval and capinfo fields */ 1072 while (frm < efrm) { 1073 if (*frm == IEEE80211_ELEMID_DSPARMS) 1074 #if IEEE80211_CHAN_MAX < 255 1075 if (frm[2] <= IEEE80211_CHAN_MAX) 1076 #endif 1077 ic->ic_curchan = &ic->ic_channels[frm[2]]; 1078 1079 frm += frm[1] + 2; 1080 } 1081 } 1082 1083 static void 1084 ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 1085 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 1086 { 1087 struct ieee80211com *ic = &sc->sc_ic; 1088 struct ifnet *ifp = &sc->sc_if; 1089 struct mbuf *mnew, *m; 1090 struct ieee80211_frame *wh; 1091 struct ieee80211_node *ni; 1092 int error; 1093 1094 DPRINTFN(5, ("received frame len=%u, rssi=%u\n", le32toh(status->len), 1095 status->rssi)); 1096 1097 if (le32toh(status->len) < sizeof (struct ieee80211_frame_min) || 1098 le32toh(status->len) > MCLBYTES) 1099 return; 1100 1101 /* 1102 * Try to allocate a new mbuf for this ring element and load it before 1103 * processing the current mbuf. If the ring element cannot be loaded, 1104 * drop the received packet and reuse the old mbuf. In the unlikely 1105 * case that the old mbuf can't be reloaded either, explicitly panic. 1106 */ 1107 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1108 if (mnew == NULL) { 1109 aprint_error("%s: could not allocate rx mbuf\n", 1110 sc->sc_dev.dv_xname); 1111 ifp->if_ierrors++; 1112 return; 1113 } 1114 1115 MCLGET(mnew, M_DONTWAIT); 1116 if (!(mnew->m_flags & M_EXT)) { 1117 aprint_error("%s: could not allocate rx mbuf cluster\n", 1118 sc->sc_dev.dv_xname); 1119 m_freem(mnew); 1120 ifp->if_ierrors++; 1121 return; 1122 } 1123 1124 mnew->m_pkthdr.len = mnew->m_len = mnew->m_ext.ext_size; 1125 1126 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, le32toh(status->len), 1127 BUS_DMASYNC_POSTREAD); 1128 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1129 1130 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, mnew, 1131 BUS_DMA_READ | BUS_DMA_NOWAIT); 1132 if (error != 0) { 1133 aprint_error("%s: could not load rx buf DMA map\n", 1134 sc->sc_dev.dv_xname); 1135 m_freem(mnew); 1136 1137 /* try to reload the old mbuf */ 1138 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, 1139 sbuf->m, BUS_DMA_READ | BUS_DMA_NOWAIT); 1140 if (error != 0) { 1141 /* very unlikely that it will fail... */ 1142 panic("%s: unable to remap rx buf", 1143 sc->sc_dev.dv_xname); 1144 } 1145 ifp->if_ierrors++; 1146 return; 1147 } 1148 1149 /* 1150 * New mbuf successfully loaded, update Rx ring and continue 1151 * processing. 1152 */ 1153 m = sbuf->m; 1154 sbuf->m = mnew; 1155 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 1156 1157 /* finalize mbuf */ 1158 m->m_pkthdr.rcvif = ifp; 1159 m->m_pkthdr.len = m->m_len = le32toh(status->len); 1160 1161 #if NBPFILTER > 0 1162 if (sc->sc_drvbpf != NULL) { 1163 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 1164 1165 tap->wr_flags = 0; 1166 tap->wr_antsignal = status->rssi; 1167 tap->wr_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 1168 tap->wr_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 1169 1170 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 1171 } 1172 #endif 1173 1174 if (ic->ic_state == IEEE80211_S_SCAN) 1175 ipw_fix_channel(ic, m); 1176 1177 wh = mtod(m, struct ieee80211_frame *); 1178 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 1179 1180 /* send the frame to the 802.11 layer */ 1181 ieee80211_input(ic, m, ni, status->rssi, 0); 1182 1183 /* node is no longer needed */ 1184 ieee80211_free_node(ni); 1185 1186 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, 1187 sbuf->map->dm_mapsize, BUS_DMASYNC_PREREAD); 1188 } 1189 1190 static void 1191 ipw_rx_intr(struct ipw_softc *sc) 1192 { 1193 struct ipw_status *status; 1194 struct ipw_soft_bd *sbd; 1195 struct ipw_soft_buf *sbuf; 1196 uint32_t r, i; 1197 1198 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1199 return; 1200 1201 r = CSR_READ_4(sc, IPW_CSR_RX_READ); 1202 1203 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 1204 1205 /* firmware was killed, stop processing received frames */ 1206 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1207 return; 1208 1209 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 1210 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1211 BUS_DMASYNC_POSTREAD); 1212 1213 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 1214 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 1215 BUS_DMASYNC_POSTREAD); 1216 1217 status = &sc->status_list[i]; 1218 sbd = &sc->srbd_list[i]; 1219 sbuf = sbd->priv; 1220 1221 switch (le16toh(status->code) & 0xf) { 1222 case IPW_STATUS_CODE_COMMAND: 1223 ipw_command_intr(sc, sbuf); 1224 break; 1225 1226 case IPW_STATUS_CODE_NEWSTATE: 1227 ipw_newstate_intr(sc, sbuf); 1228 break; 1229 1230 case IPW_STATUS_CODE_DATA_802_3: 1231 case IPW_STATUS_CODE_DATA_802_11: 1232 ipw_data_intr(sc, status, sbd, sbuf); 1233 break; 1234 1235 case IPW_STATUS_CODE_NOTIFICATION: 1236 DPRINTFN(2, ("received notification\n")); 1237 break; 1238 1239 default: 1240 aprint_error("%s: unknown status code %u\n", 1241 sc->sc_dev.dv_xname, le16toh(status->code)); 1242 } 1243 1244 sbd->bd->flags = 0; 1245 1246 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 1247 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1248 BUS_DMASYNC_PREREAD); 1249 1250 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 1251 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 1252 BUS_DMASYNC_PREREAD); 1253 } 1254 1255 /* Tell the firmware what we have processed */ 1256 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 1257 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 1258 } 1259 1260 static void 1261 ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 1262 { 1263 struct ieee80211com *ic; 1264 struct ipw_soft_hdr *shdr; 1265 struct ipw_soft_buf *sbuf; 1266 1267 switch (sbd->type) { 1268 case IPW_SBD_TYPE_COMMAND: 1269 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 1270 0, sizeof(struct ipw_cmd), BUS_DMASYNC_POSTWRITE); 1271 /* bus_dmamap_unload(sc->sc_dmat, sc->cmd_map); */ 1272 break; 1273 1274 case IPW_SBD_TYPE_HEADER: 1275 shdr = sbd->priv; 1276 bus_dmamap_sync(sc->sc_dmat, sc->hdr_map, 1277 shdr->offset, sizeof(struct ipw_hdr), BUS_DMASYNC_POSTWRITE); 1278 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 1279 break; 1280 1281 case IPW_SBD_TYPE_DATA: 1282 ic = &sc->sc_ic; 1283 sbuf = sbd->priv; 1284 1285 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 1286 0, MCLBYTES, BUS_DMASYNC_POSTWRITE); 1287 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1288 m_freem(sbuf->m); 1289 if (sbuf->ni != NULL) 1290 ieee80211_free_node(sbuf->ni); 1291 /* kill watchdog timer */ 1292 sc->sc_tx_timer = 0; 1293 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 1294 break; 1295 } 1296 sbd->type = IPW_SBD_TYPE_NOASSOC; 1297 } 1298 1299 static void 1300 ipw_tx_intr(struct ipw_softc *sc) 1301 { 1302 struct ifnet *ifp = &sc->sc_if; 1303 struct ipw_soft_bd *sbd; 1304 uint32_t r, i; 1305 1306 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1307 return; 1308 1309 r = CSR_READ_4(sc, IPW_CSR_TX_READ); 1310 1311 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) { 1312 sbd = &sc->stbd_list[i]; 1313 1314 if (sbd->type == IPW_SBD_TYPE_DATA) 1315 ifp->if_opackets++; 1316 1317 ipw_release_sbd(sc, sbd); 1318 sc->txfree++; 1319 } 1320 1321 /* remember what the firmware has processed */ 1322 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 1323 1324 /* Call start() since some buffer descriptors have been released */ 1325 ifp->if_flags &= ~IFF_OACTIVE; 1326 (*ifp->if_start)(ifp); 1327 } 1328 1329 static int 1330 ipw_intr(void *arg) 1331 { 1332 struct ipw_softc *sc = arg; 1333 uint32_t r; 1334 1335 r = CSR_READ_4(sc, IPW_CSR_INTR); 1336 if (r == 0 || r == 0xffffffff) 1337 return 0; 1338 1339 /* Disable interrupts */ 1340 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1341 1342 if (r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR)) { 1343 aprint_error("%s: fatal error\n", 1344 sc->sc_dev.dv_xname); 1345 sc->sc_ic.ic_ifp->if_flags &= ~IFF_UP; 1346 ipw_stop(&sc->sc_if, 1); 1347 } 1348 1349 if (r & IPW_INTR_FW_INIT_DONE) { 1350 if (!(r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR))) 1351 wakeup(sc); 1352 } 1353 1354 if (r & IPW_INTR_RX_TRANSFER) 1355 ipw_rx_intr(sc); 1356 1357 if (r & IPW_INTR_TX_TRANSFER) 1358 ipw_tx_intr(sc); 1359 1360 /* Acknowledge all interrupts */ 1361 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 1362 1363 /* Re-enable interrupts */ 1364 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1365 1366 return 0; 1367 } 1368 1369 /* 1370 * Send a command to the firmware and wait for the acknowledgement. 1371 */ 1372 static int 1373 ipw_cmd(struct ipw_softc *sc, uint32_t type, void *data, uint32_t len) 1374 { 1375 struct ipw_soft_bd *sbd; 1376 1377 sbd = &sc->stbd_list[sc->txcur]; 1378 1379 sc->cmd.type = htole32(type); 1380 sc->cmd.subtype = 0; 1381 sc->cmd.len = htole32(len); 1382 sc->cmd.seq = 0; 1383 1384 (void)memcpy(sc->cmd.data, data, len); 1385 1386 sbd->type = IPW_SBD_TYPE_COMMAND; 1387 sbd->bd->physaddr = htole32(sc->cmd_map->dm_segs[0].ds_addr); 1388 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 1389 sbd->bd->nfrag = 1; 1390 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 1391 IPW_BD_FLAG_TX_LAST_FRAGMENT; 1392 1393 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 0, sizeof (struct ipw_cmd), 1394 BUS_DMASYNC_PREWRITE); 1395 1396 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1397 sc->txcur * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1398 BUS_DMASYNC_PREWRITE); 1399 1400 DPRINTFN(2, ("sending command (%u, %u, %u, %u)\n", type, 0, 0, len)); 1401 1402 /* kick firmware */ 1403 sc->txfree--; 1404 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1405 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1406 1407 /* Wait at most one second for command to complete */ 1408 return tsleep(&sc->cmd, 0, "ipwcmd", hz); 1409 } 1410 1411 static int 1412 ipw_tx_start(struct ifnet *ifp, struct mbuf *m0, struct ieee80211_node *ni) 1413 { 1414 struct ipw_softc *sc = ifp->if_softc; 1415 struct ieee80211com *ic = &sc->sc_ic; 1416 struct ieee80211_frame *wh; 1417 struct ipw_soft_bd *sbd; 1418 struct ipw_soft_hdr *shdr; 1419 struct ipw_soft_buf *sbuf; 1420 struct ieee80211_key *k; 1421 struct mbuf *mnew; 1422 int error, i; 1423 1424 wh = mtod(m0, struct ieee80211_frame *); 1425 1426 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1427 k = ieee80211_crypto_encap(ic, ni, m0); 1428 if (k == NULL) { 1429 m_freem(m0); 1430 return ENOBUFS; 1431 } 1432 1433 /* packet header may have moved, reset our local pointer */ 1434 wh = mtod(m0, struct ieee80211_frame *); 1435 } 1436 1437 #if NBPFILTER > 0 1438 if (sc->sc_drvbpf != NULL) { 1439 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 1440 1441 tap->wt_flags = 0; 1442 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 1443 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 1444 1445 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 1446 } 1447 #endif 1448 1449 shdr = TAILQ_FIRST(&sc->sc_free_shdr); 1450 sbuf = TAILQ_FIRST(&sc->sc_free_sbuf); 1451 KASSERT(shdr != NULL && sbuf != NULL); 1452 1453 shdr->hdr->type = htole32(IPW_HDR_TYPE_SEND); 1454 shdr->hdr->subtype = 0; 1455 shdr->hdr->encrypted = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0; 1456 shdr->hdr->encrypt = 0; 1457 shdr->hdr->keyidx = 0; 1458 shdr->hdr->keysz = 0; 1459 shdr->hdr->fragmentsz = 0; 1460 IEEE80211_ADDR_COPY(shdr->hdr->src_addr, wh->i_addr2); 1461 if (ic->ic_opmode == IEEE80211_M_STA) 1462 IEEE80211_ADDR_COPY(shdr->hdr->dst_addr, wh->i_addr3); 1463 else 1464 IEEE80211_ADDR_COPY(shdr->hdr->dst_addr, wh->i_addr1); 1465 1466 /* trim IEEE802.11 header */ 1467 m_adj(m0, sizeof (struct ieee80211_frame)); 1468 1469 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m0, BUS_DMA_NOWAIT); 1470 if (error != 0 && error != EFBIG) { 1471 aprint_error("%s: could not map mbuf (error %d)\n", 1472 sc->sc_dev.dv_xname, error); 1473 m_freem(m0); 1474 return error; 1475 } 1476 1477 if (error != 0) { 1478 /* too many fragments, linearize */ 1479 1480 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1481 if (mnew == NULL) { 1482 m_freem(m0); 1483 return ENOMEM; 1484 } 1485 1486 M_COPY_PKTHDR(mnew, m0); 1487 1488 /* If the data won't fit in the header, get a cluster */ 1489 if (m0->m_pkthdr.len > MHLEN) { 1490 MCLGET(mnew, M_DONTWAIT); 1491 if (!(mnew->m_flags & M_EXT)) { 1492 m_freem(m0); 1493 m_freem(mnew); 1494 return ENOMEM; 1495 } 1496 } 1497 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(mnew, caddr_t)); 1498 m_freem(m0); 1499 mnew->m_len = mnew->m_pkthdr.len; 1500 m0 = mnew; 1501 1502 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m0, 1503 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1504 if (error != 0) { 1505 aprint_error("%s: could not map mbuf (error %d)\n", 1506 sc->sc_dev.dv_xname, error); 1507 m_freem(m0); 1508 return error; 1509 } 1510 } 1511 1512 TAILQ_REMOVE(&sc->sc_free_sbuf, sbuf, next); 1513 TAILQ_REMOVE(&sc->sc_free_shdr, shdr, next); 1514 1515 sbd = &sc->stbd_list[sc->txcur]; 1516 sbd->type = IPW_SBD_TYPE_HEADER; 1517 sbd->priv = shdr; 1518 sbd->bd->physaddr = htole32(shdr->addr); 1519 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 1520 sbd->bd->nfrag = 1 + sbuf->map->dm_nsegs; 1521 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 1522 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1523 1524 DPRINTFN(5, ("sending tx hdr (%u, %u, %u, %u, )\n", 1525 shdr->hdr->type, shdr->hdr->subtype, shdr->hdr->encrypted, 1526 shdr->hdr->encrypt)); 1527 DPRINTFN(5, ("%s->", ether_sprintf(shdr->hdr->src_addr))); 1528 DPRINTFN(5, ("%s\n", ether_sprintf(shdr->hdr->dst_addr))); 1529 1530 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1531 sc->txcur * sizeof (struct ipw_bd), 1532 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1533 1534 sc->txfree--; 1535 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1536 1537 sbuf->m = m0; 1538 sbuf->ni = ni; 1539 1540 for (i = 0; i < sbuf->map->dm_nsegs; i++) { 1541 sbd = &sc->stbd_list[sc->txcur]; 1542 1543 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[i].ds_addr); 1544 sbd->bd->len = htole32(sbuf->map->dm_segs[i].ds_len); 1545 sbd->bd->nfrag = 0; 1546 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 1547 if (i == sbuf->map->dm_nsegs - 1) { 1548 sbd->type = IPW_SBD_TYPE_DATA; 1549 sbd->priv = sbuf; 1550 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 1551 } else { 1552 sbd->type = IPW_SBD_TYPE_NOASSOC; 1553 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1554 } 1555 1556 DPRINTFN(5, ("sending fragment (%d, %d)\n", i, 1557 (int)sbuf->map->dm_segs[i].ds_len)); 1558 1559 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1560 sc->txcur * sizeof (struct ipw_bd), 1561 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1562 1563 sc->txfree--; 1564 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1565 } 1566 1567 bus_dmamap_sync(sc->sc_dmat, sc->hdr_map, shdr->offset, 1568 sizeof (struct ipw_hdr), BUS_DMASYNC_PREWRITE); 1569 1570 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, MCLBYTES, 1571 BUS_DMASYNC_PREWRITE); 1572 1573 /* Inform firmware about this new packet */ 1574 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1575 1576 return 0; 1577 } 1578 1579 static void 1580 ipw_start(struct ifnet *ifp) 1581 { 1582 struct ipw_softc *sc = ifp->if_softc; 1583 struct ieee80211com *ic = &sc->sc_ic; 1584 struct mbuf *m0; 1585 struct ether_header *eh; 1586 struct ieee80211_node *ni; 1587 1588 1589 if (ic->ic_state != IEEE80211_S_RUN) 1590 return; 1591 1592 for (;;) { 1593 IF_DEQUEUE(&ifp->if_snd, m0); 1594 if (m0 == NULL) 1595 break; 1596 1597 if (sc->txfree < 1 + IPW_MAX_NSEG) { 1598 IF_PREPEND(&ifp->if_snd, m0); 1599 ifp->if_flags |= IFF_OACTIVE; 1600 break; 1601 } 1602 1603 if (m0->m_len < sizeof (struct ether_header) && 1604 (m0 = m_pullup(m0, sizeof (struct ether_header))) == NULL) 1605 continue; 1606 1607 eh = mtod(m0, struct ether_header *); 1608 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1609 if (ni == NULL) { 1610 m_freem(m0); 1611 continue; 1612 } 1613 1614 #if NBPFILTER > 0 1615 if (ifp->if_bpf != NULL) 1616 bpf_mtap(ifp->if_bpf, m0); 1617 #endif 1618 1619 m0 = ieee80211_encap(ic, m0, ni); 1620 if (m0 == NULL) { 1621 ieee80211_free_node(ni); 1622 continue; 1623 } 1624 1625 #if NBPFILTER > 0 1626 if (ic->ic_rawbpf != NULL) 1627 bpf_mtap(ic->ic_rawbpf, m0); 1628 #endif 1629 1630 if (ipw_tx_start(ifp, m0, ni) != 0) { 1631 ieee80211_free_node(ni); 1632 ifp->if_oerrors++; 1633 break; 1634 } 1635 1636 /* start watchdog timer */ 1637 sc->sc_tx_timer = 5; 1638 ifp->if_timer = 1; 1639 } 1640 } 1641 1642 static void 1643 ipw_watchdog(struct ifnet *ifp) 1644 { 1645 struct ipw_softc *sc = ifp->if_softc; 1646 1647 ifp->if_timer = 0; 1648 1649 if (sc->sc_tx_timer > 0) { 1650 if (--sc->sc_tx_timer == 0) { 1651 aprint_error("%s: device timeout\n", 1652 sc->sc_dev.dv_xname); 1653 ifp->if_oerrors++; 1654 ifp->if_flags &= ~IFF_UP; 1655 ipw_stop(ifp, 1); 1656 return; 1657 } 1658 ifp->if_timer = 1; 1659 } 1660 1661 ieee80211_watchdog(&sc->sc_ic); 1662 } 1663 1664 static int 1665 ipw_get_table1(struct ipw_softc *sc, uint32_t *tbl) 1666 { 1667 uint32_t addr, size, i; 1668 1669 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1670 return ENOTTY; 1671 1672 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, sc->table1_base); 1673 1674 size = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 1675 if (suword(tbl, size) != 0) 1676 return EFAULT; 1677 1678 for (i = 1, ++tbl; i < size; i++, tbl++) { 1679 addr = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 1680 if (suword(tbl, MEM_READ_4(sc, addr)) != 0) 1681 return EFAULT; 1682 } 1683 return 0; 1684 } 1685 1686 static int 1687 ipw_get_radio(struct ipw_softc *sc, int *ret) 1688 { 1689 uint32_t addr; 1690 1691 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1692 return ENOTTY; 1693 1694 addr = ipw_read_table1(sc, IPW_INFO_EEPROM_ADDRESS); 1695 if ((MEM_READ_4(sc, addr + 32) >> 24) & 1) { 1696 suword(ret, -1); 1697 return 0; 1698 } 1699 1700 if (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED) 1701 suword(ret, 0); 1702 else 1703 suword(ret, 1); 1704 1705 return 0; 1706 } 1707 1708 static int 1709 ipw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1710 { 1711 #define IS_RUNNING(ifp) \ 1712 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 1713 1714 struct ipw_softc *sc = ifp->if_softc; 1715 struct ieee80211com *ic = &sc->sc_ic; 1716 struct ifreq *ifr = (struct ifreq *)data; 1717 int s, error = 0; 1718 1719 s = splnet(); 1720 1721 switch (cmd) { 1722 case SIOCSIFFLAGS: 1723 if (ifp->if_flags & IFF_UP) { 1724 if (!(ifp->if_flags & IFF_RUNNING)) 1725 ipw_init(ifp); 1726 } else { 1727 if (ifp->if_flags & IFF_RUNNING) 1728 ipw_stop(ifp, 1); 1729 } 1730 break; 1731 1732 case SIOCADDMULTI: 1733 case SIOCDELMULTI: 1734 error = (cmd == SIOCADDMULTI) ? 1735 ether_addmulti(ifr, &sc->sc_ec) : 1736 ether_delmulti(ifr, &sc->sc_ec); 1737 if (error == ENETRESET) { 1738 /* setup multicast filter, etc */ 1739 error = 0; 1740 } 1741 break; 1742 1743 case SIOCGTABLE1: 1744 error = ipw_get_table1(sc, (uint32_t *)ifr->ifr_data); 1745 break; 1746 1747 case SIOCGRADIO: 1748 error = ipw_get_radio(sc, (int *)ifr->ifr_data); 1749 break; 1750 1751 case SIOCSIFMEDIA: 1752 if (ifr->ifr_media & IFM_IEEE80211_ADHOC) 1753 strlcpy(sc->sc_fwname, "ipw2100-1.2-i.fw", 1754 sizeof(sc->sc_fwname)); 1755 else if (ifr->ifr_media & IFM_IEEE80211_MONITOR) 1756 strlcpy(sc->sc_fwname, "ipw2100-1.2-p.fw", 1757 sizeof(sc->sc_fwname)); 1758 else 1759 strlcpy(sc->sc_fwname, "ipw2100-1.2.fw", 1760 sizeof(sc->sc_fwname)); 1761 1762 ipw_free_firmware(sc); 1763 /* FALLTRHOUGH */ 1764 default: 1765 error = ieee80211_ioctl(&sc->sc_ic, cmd, data); 1766 if (error != ENETRESET) 1767 break; 1768 1769 if (error == ENETRESET) { 1770 if (IS_RUNNING(ifp) && 1771 (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)) 1772 ipw_init(ifp); 1773 error = 0; 1774 } 1775 1776 } 1777 1778 splx(s); 1779 return error; 1780 #undef IS_RUNNING 1781 } 1782 1783 static uint32_t 1784 ipw_read_table1(struct ipw_softc *sc, uint32_t off) 1785 { 1786 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 1787 } 1788 1789 static void 1790 ipw_write_table1(struct ipw_softc *sc, uint32_t off, uint32_t info) 1791 { 1792 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 1793 } 1794 1795 static int 1796 ipw_read_table2(struct ipw_softc *sc, uint32_t off, void *buf, uint32_t *len) 1797 { 1798 uint32_t addr, info; 1799 uint16_t count, size; 1800 uint32_t total; 1801 1802 /* addr[4] + count[2] + size[2] */ 1803 addr = MEM_READ_4(sc, sc->table2_base + off); 1804 info = MEM_READ_4(sc, sc->table2_base + off + 4); 1805 1806 count = info >> 16; 1807 size = info & 0xffff; 1808 total = count * size; 1809 1810 if (total > *len) { 1811 *len = total; 1812 return EINVAL; 1813 } 1814 1815 *len = total; 1816 ipw_read_mem_1(sc, addr, buf, total); 1817 1818 return 0; 1819 } 1820 1821 static void 1822 ipw_stop_master(struct ipw_softc *sc) 1823 { 1824 int ntries; 1825 1826 /* disable interrupts */ 1827 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1828 1829 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1830 for (ntries = 0; ntries < 50; ntries++) { 1831 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1832 break; 1833 DELAY(10); 1834 } 1835 if (ntries == 50) 1836 aprint_error("%s: timeout waiting for master\n", 1837 sc->sc_dev.dv_xname); 1838 1839 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1840 IPW_RST_PRINCETON_RESET); 1841 1842 sc->flags &= ~IPW_FLAG_FW_INITED; 1843 } 1844 1845 static int 1846 ipw_reset(struct ipw_softc *sc) 1847 { 1848 int ntries; 1849 1850 ipw_stop_master(sc); 1851 1852 /* move adapter to D0 state */ 1853 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1854 IPW_CTL_INIT); 1855 1856 /* wait for clock stabilization */ 1857 for (ntries = 0; ntries < 1000; ntries++) { 1858 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY) 1859 break; 1860 DELAY(200); 1861 } 1862 if (ntries == 1000) 1863 return EIO; 1864 1865 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1866 IPW_RST_SW_RESET); 1867 1868 DELAY(10); 1869 1870 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1871 IPW_CTL_INIT); 1872 1873 return 0; 1874 } 1875 1876 /* 1877 * Upload the microcode to the device. 1878 */ 1879 static int 1880 ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size) 1881 { 1882 int ntries; 1883 1884 MEM_WRITE_4(sc, 0x3000e0, 0x80000000); 1885 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1886 1887 MEM_WRITE_2(sc, 0x220000, 0x0703); 1888 MEM_WRITE_2(sc, 0x220000, 0x0707); 1889 1890 MEM_WRITE_1(sc, 0x210014, 0x72); 1891 MEM_WRITE_1(sc, 0x210014, 0x72); 1892 1893 MEM_WRITE_1(sc, 0x210000, 0x40); 1894 MEM_WRITE_1(sc, 0x210000, 0x00); 1895 MEM_WRITE_1(sc, 0x210000, 0x40); 1896 1897 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1898 1899 MEM_WRITE_1(sc, 0x210000, 0x00); 1900 MEM_WRITE_1(sc, 0x210000, 0x00); 1901 MEM_WRITE_1(sc, 0x210000, 0x80); 1902 1903 MEM_WRITE_2(sc, 0x220000, 0x0703); 1904 MEM_WRITE_2(sc, 0x220000, 0x0707); 1905 1906 MEM_WRITE_1(sc, 0x210014, 0x72); 1907 MEM_WRITE_1(sc, 0x210014, 0x72); 1908 1909 MEM_WRITE_1(sc, 0x210000, 0x00); 1910 MEM_WRITE_1(sc, 0x210000, 0x80); 1911 1912 for (ntries = 0; ntries < 10; ntries++) { 1913 if (MEM_READ_1(sc, 0x210000) & 1) 1914 break; 1915 DELAY(10); 1916 } 1917 if (ntries == 10) { 1918 aprint_error("%s: timeout waiting for ucode to initialize\n", 1919 sc->sc_dev.dv_xname); 1920 return EIO; 1921 } 1922 1923 MEM_WRITE_4(sc, 0x3000e0, 0); 1924 1925 return 0; 1926 } 1927 1928 /* set of macros to handle unaligned little endian data in firmware image */ 1929 #define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1930 #define GETLE16(p) ((p)[0] | (p)[1] << 8) 1931 static int 1932 ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size) 1933 { 1934 u_char *p, *end; 1935 uint32_t dst; 1936 uint16_t len; 1937 int error; 1938 1939 p = fw; 1940 end = fw + size; 1941 while (p < end) { 1942 dst = GETLE32(p); p += 4; 1943 len = GETLE16(p); p += 2; 1944 1945 ipw_write_mem_1(sc, dst, p, len); 1946 p += len; 1947 } 1948 1949 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1950 IPW_IO_LED_OFF); 1951 1952 /* enable interrupts */ 1953 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1954 1955 /* kick the firmware */ 1956 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1957 1958 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1959 IPW_CTL_ALLOW_STANDBY); 1960 1961 /* wait at most one second for firmware initialization to complete */ 1962 if ((error = tsleep(sc, 0, "ipwinit", hz)) != 0) { 1963 aprint_error("%s: timeout waiting for firmware initialization " 1964 "to complete\n", sc->sc_dev.dv_xname); 1965 return error; 1966 } 1967 1968 CSR_WRITE_4(sc, IPW_CSR_IO, CSR_READ_4(sc, IPW_CSR_IO) | 1969 IPW_IO_GPIO1_MASK | IPW_IO_GPIO3_MASK); 1970 1971 return 0; 1972 } 1973 1974 /* 1975 * Store firmware into kernel memory so we can download it when we need to, 1976 * e.g when the adapter wakes up from suspend mode. 1977 */ 1978 static int 1979 ipw_cache_firmware(struct ipw_softc *sc) 1980 { 1981 struct ipw_firmware *fw = &sc->fw; 1982 struct ipw_firmware_hdr hdr; 1983 firmware_handle_t fwh; 1984 off_t fwsz, p; 1985 int error; 1986 1987 ipw_free_firmware(sc); 1988 1989 if ((error = firmware_open("if_ipw", sc->sc_fwname, &fwh)) != 0) 1990 goto fail0; 1991 1992 fwsz = firmware_get_size(fwh); 1993 1994 if (fwsz < sizeof(hdr)) 1995 goto fail2; 1996 1997 if ((error = firmware_read(fwh, 0, &hdr, sizeof(hdr))) != 0) 1998 goto fail2; 1999 2000 fw->main_size = le32toh(hdr.main_size); 2001 fw->ucode_size = le32toh(hdr.ucode_size); 2002 2003 fw->main = firmware_malloc(fw->main_size); 2004 if (fw->main == NULL) { 2005 error = ENOMEM; 2006 goto fail1; 2007 } 2008 2009 fw->ucode = firmware_malloc(fw->ucode_size); 2010 if (fw->ucode == NULL) { 2011 error = ENOMEM; 2012 goto fail2; 2013 } 2014 2015 p = sizeof(hdr); 2016 if ((error = firmware_read(fwh, p, fw->main, fw->main_size)) != 0) 2017 goto fail3; 2018 2019 p += fw->main_size; 2020 if ((error = firmware_read(fwh, p, fw->ucode, fw->ucode_size)) != 0) 2021 goto fail3; 2022 2023 DPRINTF(("Firmware cached: main %u, ucode %u\n", fw->main_size, 2024 fw->ucode_size)); 2025 2026 sc->flags |= IPW_FLAG_FW_CACHED; 2027 2028 return 0; 2029 2030 fail3: firmware_free(fw->ucode, 0); 2031 fail2: firmware_free(fw->main, 0); 2032 fail1: firmware_close(fwh); 2033 fail0: 2034 return error; 2035 } 2036 2037 static void 2038 ipw_free_firmware(struct ipw_softc *sc) 2039 { 2040 if (!(sc->flags & IPW_FLAG_FW_CACHED)) 2041 return; 2042 2043 firmware_free(sc->fw.main, 0); 2044 firmware_free(sc->fw.ucode, 0); 2045 2046 sc->flags &= ~IPW_FLAG_FW_CACHED; 2047 } 2048 2049 static int 2050 ipw_config(struct ipw_softc *sc) 2051 { 2052 struct ieee80211com *ic = &sc->sc_ic; 2053 struct ifnet *ifp = &sc->sc_if; 2054 struct ipw_security security; 2055 struct ieee80211_key *k; 2056 struct ipw_wep_key wepkey; 2057 struct ipw_scan_options options; 2058 struct ipw_configuration config; 2059 uint32_t data; 2060 int error, i; 2061 2062 switch (ic->ic_opmode) { 2063 case IEEE80211_M_STA: 2064 case IEEE80211_M_HOSTAP: 2065 data = htole32(IPW_MODE_BSS); 2066 break; 2067 2068 case IEEE80211_M_IBSS: 2069 case IEEE80211_M_AHDEMO: 2070 data = htole32(IPW_MODE_IBSS); 2071 break; 2072 2073 case IEEE80211_M_MONITOR: 2074 data = htole32(IPW_MODE_MONITOR); 2075 break; 2076 } 2077 DPRINTF(("Setting mode to %u\n", le32toh(data))); 2078 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 2079 if (error != 0) 2080 return error; 2081 2082 if (ic->ic_opmode == IEEE80211_M_IBSS || 2083 ic->ic_opmode == IEEE80211_M_MONITOR) { 2084 data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); 2085 DPRINTF(("Setting channel to %u\n", le32toh(data))); 2086 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 2087 if (error != 0) 2088 return error; 2089 } 2090 2091 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2092 DPRINTF(("Enabling adapter\n")); 2093 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 2094 } 2095 2096 DPRINTF(("Setting MAC to %s\n", ether_sprintf(ic->ic_myaddr))); 2097 IEEE80211_ADDR_COPY(LLADDR(ifp->if_sadl), ic->ic_myaddr); 2098 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 2099 IEEE80211_ADDR_LEN); 2100 if (error != 0) 2101 return error; 2102 2103 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 2104 IPW_CFG_PREAMBLE_AUTO | IPW_CFG_802_1x_ENABLE); 2105 2106 if (ic->ic_opmode == IEEE80211_M_IBSS) 2107 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 2108 if (ifp->if_flags & IFF_PROMISC) 2109 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 2110 config.bss_chan = htole32(0x3fff); /* channels 1-14 */ 2111 config.ibss_chan = htole32(0x7ff); /* channels 1-11 */ 2112 DPRINTF(("Setting adapter configuration 0x%08x\n", config.flags)); 2113 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 2114 if (error != 0) 2115 return error; 2116 2117 data = htole32(0x3); /* 1, 2 */ 2118 DPRINTF(("Setting basic tx rates to 0x%x\n", le32toh(data))); 2119 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 2120 if (error != 0) 2121 return error; 2122 2123 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 2124 DPRINTF(("Setting tx rates to 0x%x\n", le32toh(data))); 2125 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 2126 if (error != 0) 2127 return error; 2128 2129 data = htole32(IPW_POWER_MODE_CAM); 2130 DPRINTF(("Setting power mode to %u\n", le32toh(data))); 2131 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 2132 if (error != 0) 2133 return error; 2134 2135 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2136 data = htole32(32); /* default value */ 2137 DPRINTF(("Setting tx power index to %u\n", le32toh(data))); 2138 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 2139 sizeof data); 2140 if (error != 0) 2141 return error; 2142 } 2143 2144 data = htole32(ic->ic_rtsthreshold); 2145 DPRINTF(("Setting RTS threshold to %u\n", le32toh(data))); 2146 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 2147 if (error != 0) 2148 return error; 2149 2150 data = htole32(ic->ic_fragthreshold); 2151 DPRINTF(("Setting frag threshold to %u\n", le32toh(data))); 2152 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 2153 if (error != 0) 2154 return error; 2155 2156 #ifdef IPW_DEBUG 2157 if (ipw_debug > 0) { 2158 printf("Setting ESSID to "); 2159 ieee80211_print_essid(ic->ic_des_essid, ic->ic_des_esslen); 2160 printf("\n"); 2161 } 2162 #endif 2163 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ic->ic_des_essid, 2164 ic->ic_des_esslen); 2165 if (error != 0) 2166 return error; 2167 2168 /* no mandatory BSSID */ 2169 DPRINTF(("Setting mandatory BSSID to null\n")); 2170 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 2171 if (error != 0) 2172 return error; 2173 2174 if (ic->ic_flags & IEEE80211_F_DESBSSID) { 2175 DPRINTF(("Setting desired BSSID to %s\n", 2176 ether_sprintf(ic->ic_des_bssid))); 2177 error = ipw_cmd(sc, IPW_CMD_SET_DESIRED_BSSID, 2178 ic->ic_des_bssid, IEEE80211_ADDR_LEN); 2179 if (error != 0) 2180 return error; 2181 } 2182 2183 (void)memset(&security, 0, sizeof(security)); 2184 security.authmode = (ic->ic_bss->ni_authmode == IEEE80211_AUTH_SHARED) ? 2185 IPW_AUTH_SHARED : IPW_AUTH_OPEN; 2186 security.ciphers = htole32(IPW_CIPHER_NONE); 2187 DPRINTF(("Setting authmode to %u\n", security.authmode)); 2188 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 2189 sizeof security); 2190 if (error != 0) 2191 return error; 2192 2193 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 2194 k = ic->ic_crypto.cs_nw_keys; 2195 for (i = 0; i < IEEE80211_WEP_NKID; i++, k++) { 2196 if (k->wk_keylen == 0) 2197 continue; 2198 2199 wepkey.idx = i; 2200 wepkey.len = k->wk_keylen; 2201 memset(wepkey.key, 0, sizeof(wepkey.key)); 2202 memcpy(wepkey.key, k->wk_key, k->wk_keylen); 2203 DPRINTF(("Setting wep key index %u len %u\n", 2204 wepkey.idx, wepkey.len)); 2205 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY, &wepkey, 2206 sizeof wepkey); 2207 if (error != 0) 2208 return error; 2209 } 2210 2211 data = htole32(ic->ic_crypto.cs_def_txkey); 2212 DPRINTF(("Setting tx key index to %u\n", le32toh(data))); 2213 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY_INDEX, &data, 2214 sizeof data); 2215 if (error != 0) 2216 return error; 2217 } 2218 2219 data = htole32((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) ? IPW_WEPON : 0); 2220 DPRINTF(("Setting wep flags to 0x%x\n", le32toh(data))); 2221 error = ipw_cmd(sc, IPW_CMD_SET_WEP_FLAGS, &data, sizeof data); 2222 if (error != 0) 2223 return error; 2224 2225 #if 0 2226 struct ipw_wpa_ie ie; 2227 2228 memset(&ie, 0 sizeof(ie)); 2229 ie.len = htole32(sizeof (struct ieee80211_ie_wpa)); 2230 DPRINTF(("Setting wpa ie\n")); 2231 error = ipw_cmd(sc, IPW_CMD_SET_WPA_IE, &ie, sizeof ie); 2232 if (error != 0) 2233 return error; 2234 #endif 2235 2236 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2237 data = htole32(ic->ic_bintval); 2238 DPRINTF(("Setting beacon interval to %u\n", le32toh(data))); 2239 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 2240 sizeof data); 2241 if (error != 0) 2242 return error; 2243 } 2244 2245 options.flags = 0; 2246 options.channels = htole32(0x3fff); /* scan channels 1-14 */ 2247 DPRINTF(("Setting scan options to 0x%x\n", le32toh(options.flags))); 2248 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &options, sizeof options); 2249 if (error != 0) 2250 return error; 2251 2252 /* finally, enable adapter (start scanning for an access point) */ 2253 DPRINTF(("Enabling adapter\n")); 2254 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 2255 } 2256 2257 static int 2258 ipw_init(struct ifnet *ifp) 2259 { 2260 struct ipw_softc *sc = ifp->if_softc; 2261 struct ipw_firmware *fw = &sc->fw; 2262 2263 if (!(sc->flags & IPW_FLAG_FW_CACHED)) { 2264 if (ipw_cache_firmware(sc) != 0) { 2265 aprint_error("%s: could not cache the firmware (%s)\n", 2266 sc->sc_dev.dv_xname, sc->sc_fwname); 2267 goto fail; 2268 } 2269 } 2270 2271 ipw_stop(ifp, 0); 2272 2273 if (ipw_reset(sc) != 0) { 2274 aprint_error("%s: could not reset adapter\n", 2275 sc->sc_dev.dv_xname); 2276 goto fail; 2277 } 2278 2279 if (ipw_load_ucode(sc, fw->ucode, fw->ucode_size) != 0) { 2280 aprint_error("%s: could not load microcode\n", 2281 sc->sc_dev.dv_xname); 2282 goto fail; 2283 } 2284 2285 ipw_stop_master(sc); 2286 2287 /* 2288 * Setup tx, rx and status rings. 2289 */ 2290 sc->txold = IPW_NTBD - 1; 2291 sc->txcur = 0; 2292 sc->txfree = IPW_NTBD - 2; 2293 sc->rxcur = IPW_NRBD - 1; 2294 2295 CSR_WRITE_4(sc, IPW_CSR_TX_BASE, sc->tbd_map->dm_segs[0].ds_addr); 2296 CSR_WRITE_4(sc, IPW_CSR_TX_SIZE, IPW_NTBD); 2297 CSR_WRITE_4(sc, IPW_CSR_TX_READ, 0); 2298 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 2299 2300 CSR_WRITE_4(sc, IPW_CSR_RX_BASE, sc->rbd_map->dm_segs[0].ds_addr); 2301 CSR_WRITE_4(sc, IPW_CSR_RX_SIZE, IPW_NRBD); 2302 CSR_WRITE_4(sc, IPW_CSR_RX_READ, 0); 2303 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 2304 2305 CSR_WRITE_4(sc, IPW_CSR_STATUS_BASE, sc->status_map->dm_segs[0].ds_addr); 2306 2307 if (ipw_load_firmware(sc, fw->main, fw->main_size) != 0) { 2308 aprint_error("%s: could not load firmware\n", 2309 sc->sc_dev.dv_xname); 2310 goto fail; 2311 } 2312 2313 sc->flags |= IPW_FLAG_FW_INITED; 2314 2315 /* retrieve information tables base addresses */ 2316 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 2317 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 2318 2319 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 2320 2321 if (ipw_config(sc) != 0) { 2322 aprint_error("%s: device configuration failed\n", 2323 sc->sc_dev.dv_xname); 2324 goto fail; 2325 } 2326 2327 ifp->if_flags &= ~IFF_OACTIVE; 2328 ifp->if_flags |= IFF_RUNNING; 2329 2330 return 0; 2331 2332 fail: ifp->if_flags &= ~IFF_UP; 2333 ipw_stop(ifp, 0); 2334 2335 return EIO; 2336 } 2337 2338 static void 2339 ipw_stop(struct ifnet *ifp, int disable) 2340 { 2341 struct ipw_softc *sc = ifp->if_softc; 2342 struct ieee80211com *ic = &sc->sc_ic; 2343 int i; 2344 2345 ipw_stop_master(sc); 2346 2347 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 2348 2349 /* 2350 * Release tx buffers. 2351 */ 2352 for (i = 0; i < IPW_NTBD; i++) 2353 ipw_release_sbd(sc, &sc->stbd_list[i]); 2354 2355 sc->sc_tx_timer = 0; 2356 ifp->if_timer = 0; 2357 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2358 2359 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2360 } 2361 2362 static void 2363 ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2364 bus_size_t count) 2365 { 2366 for (; count > 0; offset++, datap++, count--) { 2367 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2368 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 2369 } 2370 } 2371 2372 static void 2373 ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2374 bus_size_t count) 2375 { 2376 for (; count > 0; offset++, datap++, count--) { 2377 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2378 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 2379 } 2380 } 2381
Indexes created Tue Sep 30 11:09:46 GMT 2025