if_ipw.c revision 1.31
1 /* $NetBSD: if_ipw.c,v 1.31 2006/11/16 01:33:08 christos Exp $ */ 2 /* FreeBSD: src/sys/dev/ipw/if_ipw.c,v 1.15 2005/11/13 17:17:40 damien Exp */ 3 4 /*- 5 * Copyright (c) 2004, 2005 6 * Damien Bergamini <damien.bergamini (at) free.fr>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: if_ipw.c,v 1.31 2006/11/16 01:33:08 christos Exp $"); 33 34 /*- 35 * Intel(R) PRO/Wireless 2100 MiniPCI driver 36 * http://www.intel.com/network/connectivity/products/wireless/prowireless_mobile.htm 37 */ 38 39 #include "bpfilter.h" 40 41 #include <sys/param.h> 42 #include <sys/sockio.h> 43 #include <sys/sysctl.h> 44 #include <sys/mbuf.h> 45 #include <sys/kernel.h> 46 #include <sys/socket.h> 47 #include <sys/systm.h> 48 #include <sys/malloc.h> 49 #include <sys/conf.h> 50 51 #include <machine/bus.h> 52 #include <machine/endian.h> 53 #include <machine/intr.h> 54 55 #include <dev/pci/pcireg.h> 56 #include <dev/pci/pcivar.h> 57 #include <dev/pci/pcidevs.h> 58 59 #if NBPFILTER > 0 60 #include <net/bpf.h> 61 #endif 62 #include <net/if.h> 63 #include <net/if_arp.h> 64 #include <net/if_dl.h> 65 #include <net/if_ether.h> 66 #include <net/if_media.h> 67 #include <net/if_types.h> 68 69 #include <net80211/ieee80211_var.h> 70 #include <net80211/ieee80211_radiotap.h> 71 72 #include <netinet/in.h> 73 #include <netinet/in_systm.h> 74 #include <netinet/in_var.h> 75 #include <netinet/ip.h> 76 77 #include <dev/firmload.h> 78 79 #include <dev/pci/if_ipwreg.h> 80 #include <dev/pci/if_ipwvar.h> 81 82 #ifdef IPW_DEBUG 83 #define DPRINTF(x) if (ipw_debug > 0) printf x 84 #define DPRINTFN(n, x) if (ipw_debug >= (n)) printf x 85 int ipw_debug = 0; 86 #else 87 #define DPRINTF(x) 88 #define DPRINTFN(n, x) 89 #endif 90 91 static int ipw_dma_alloc(struct ipw_softc *); 92 static void ipw_release(struct ipw_softc *); 93 static int ipw_match(struct device *, struct cfdata *, void *); 94 static void ipw_attach(struct device *, struct device *, void *); 95 static int ipw_detach(struct device *, int); 96 97 static void ipw_shutdown(void *); 98 static int ipw_suspend(struct ipw_softc *); 99 static int ipw_resume(struct ipw_softc *); 100 static void ipw_powerhook(int, void *); 101 102 static int ipw_media_change(struct ifnet *); 103 static void ipw_media_status(struct ifnet *, struct ifmediareq *); 104 static int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 105 static uint16_t ipw_read_prom_word(struct ipw_softc *, uint8_t); 106 static void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 107 static void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 108 static void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 109 struct ipw_soft_bd *, struct ipw_soft_buf *); 110 static void ipw_rx_intr(struct ipw_softc *); 111 static void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 112 static void ipw_tx_intr(struct ipw_softc *); 113 static int ipw_intr(void *); 114 static int ipw_cmd(struct ipw_softc *, uint32_t, void *, uint32_t); 115 static int ipw_tx_start(struct ifnet *, struct mbuf *, 116 struct ieee80211_node *); 117 static void ipw_start(struct ifnet *); 118 static void ipw_watchdog(struct ifnet *); 119 static int ipw_ioctl(struct ifnet *, u_long, caddr_t); 120 static int ipw_get_table1(struct ipw_softc *, uint32_t *); 121 static int ipw_get_radio(struct ipw_softc *, int *); 122 static void ipw_stop_master(struct ipw_softc *); 123 static int ipw_reset(struct ipw_softc *); 124 static int ipw_load_ucode(struct ipw_softc *, u_char *, int); 125 static int ipw_load_firmware(struct ipw_softc *, u_char *, int); 126 static int ipw_cache_firmware(struct ipw_softc *); 127 static void ipw_free_firmware(struct ipw_softc *); 128 static int ipw_config(struct ipw_softc *); 129 static int ipw_init(struct ifnet *); 130 static void ipw_stop(struct ifnet *, int); 131 static uint32_t ipw_read_table1(struct ipw_softc *, uint32_t); 132 static void ipw_write_table1(struct ipw_softc *, uint32_t, uint32_t); 133 static int ipw_read_table2(struct ipw_softc *, uint32_t, void *, uint32_t *); 134 static void ipw_read_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 135 bus_size_t); 136 static void ipw_write_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 137 bus_size_t); 138 139 /* 140 * Supported rates for 802.11b mode (in 500Kbps unit). 141 */ 142 static const struct ieee80211_rateset ipw_rateset_11b = 143 { 4, { 2, 4, 11, 22 } }; 144 145 static inline uint8_t 146 MEM_READ_1(struct ipw_softc *sc, uint32_t addr) 147 { 148 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 149 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); 150 } 151 152 static inline uint32_t 153 MEM_READ_4(struct ipw_softc *sc, uint32_t addr) 154 { 155 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 156 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); 157 } 158 159 CFATTACH_DECL(ipw, sizeof (struct ipw_softc), ipw_match, ipw_attach, 160 ipw_detach, NULL); 161 162 static int 163 ipw_match(struct device *parent, struct cfdata *match, 164 void *aux) 165 { 166 struct pci_attach_args *pa = aux; 167 168 if (PCI_VENDOR (pa->pa_id) == PCI_VENDOR_INTEL && 169 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_PRO_WL_2100) 170 return 1; 171 172 return 0; 173 } 174 175 /* Base Address Register */ 176 #define IPW_PCI_BAR0 0x10 177 178 static void 179 ipw_attach(struct device *parent, struct device *self, void *aux) 180 { 181 struct ipw_softc *sc = (struct ipw_softc *)self; 182 struct ieee80211com *ic = &sc->sc_ic; 183 struct ifnet *ifp = &sc->sc_if; 184 struct pci_attach_args *pa = aux; 185 const char *intrstr; 186 char devinfo[256]; 187 bus_space_tag_t memt; 188 bus_space_handle_t memh; 189 bus_addr_t base; 190 pci_intr_handle_t ih; 191 uint32_t data; 192 uint16_t val; 193 int i, revision, error; 194 195 sc->sc_pct = pa->pa_pc; 196 sc->sc_pcitag = pa->pa_tag; 197 198 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof devinfo); 199 revision = PCI_REVISION(pa->pa_class); 200 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, revision); 201 202 /* enable bus-mastering */ 203 data = pci_conf_read(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG); 204 data |= PCI_COMMAND_MASTER_ENABLE; 205 pci_conf_write(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG, data); 206 207 /* clear device specific PCI configuration register 0x41 */ 208 data = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 209 data &= ~0x0000ff00; 210 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, data); 211 212 /* map the register window */ 213 error = pci_mapreg_map(pa, IPW_PCI_BAR0, PCI_MAPREG_TYPE_MEM | 214 PCI_MAPREG_MEM_TYPE_32BIT, 0, &memt, &memh, &base, &sc->sc_sz); 215 if (error != 0) { 216 aprint_error("%s: could not map memory space\n", 217 sc->sc_dev.dv_xname); 218 return; 219 } 220 221 sc->sc_st = memt; 222 sc->sc_sh = memh; 223 sc->sc_dmat = pa->pa_dmat; 224 strlcpy(sc->sc_fwname, "ipw2100-1.2.fw", sizeof(sc->sc_fwname)); 225 226 /* disable interrupts */ 227 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 228 229 if (pci_intr_map(pa, &ih) != 0) { 230 aprint_error("%s: could not map interrupt\n", 231 sc->sc_dev.dv_xname); 232 return; 233 } 234 235 intrstr = pci_intr_string(sc->sc_pct, ih); 236 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, ipw_intr, sc); 237 if (sc->sc_ih == NULL) { 238 aprint_error("%s: could not establish interrupt", 239 sc->sc_dev.dv_xname); 240 if (intrstr != NULL) 241 aprint_error(" at %s", intrstr); 242 aprint_error("\n"); 243 return; 244 } 245 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 246 247 if (ipw_reset(sc) != 0) { 248 aprint_error("%s: could not reset adapter\n", 249 sc->sc_dev.dv_xname); 250 goto fail; 251 } 252 253 if (ipw_dma_alloc(sc) != 0) { 254 aprint_error("%s: could not allocate DMA resources\n", 255 sc->sc_dev.dv_xname); 256 goto fail; 257 } 258 259 ifp->if_softc = sc; 260 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 261 ifp->if_init = ipw_init; 262 ifp->if_stop = ipw_stop; 263 ifp->if_ioctl = ipw_ioctl; 264 ifp->if_start = ipw_start; 265 ifp->if_watchdog = ipw_watchdog; 266 IFQ_SET_READY(&ifp->if_snd); 267 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 268 269 ic->ic_ifp = ifp; 270 ic->ic_phytype = IEEE80211_T_DS; 271 ic->ic_opmode = IEEE80211_M_STA; 272 ic->ic_state = IEEE80211_S_INIT; 273 274 /* set device capabilities */ 275 ic->ic_caps = 276 IEEE80211_C_SHPREAMBLE /* short preamble supported */ 277 | IEEE80211_C_TXPMGT /* tx power management */ 278 | IEEE80211_C_IBSS /* ibss mode */ 279 | IEEE80211_C_MONITOR /* monitor mode */ 280 ; 281 282 /* read MAC address from EEPROM */ 283 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0); 284 ic->ic_myaddr[0] = val >> 8; 285 ic->ic_myaddr[1] = val & 0xff; 286 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 1); 287 ic->ic_myaddr[2] = val >> 8; 288 ic->ic_myaddr[3] = val & 0xff; 289 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 2); 290 ic->ic_myaddr[4] = val >> 8; 291 ic->ic_myaddr[5] = val & 0xff; 292 293 /* set supported .11b rates */ 294 ic->ic_sup_rates[IEEE80211_MODE_11B] = ipw_rateset_11b; 295 296 /* set supported .11b channels (read from EEPROM) */ 297 if ((val = ipw_read_prom_word(sc, IPW_EEPROM_CHANNEL_LIST)) == 0) 298 val = 0x7ff; /* default to channels 1-11 */ 299 val <<= 1; 300 for (i = 1; i < 16; i++) { 301 if (val & (1 << i)) { 302 ic->ic_channels[i].ic_freq = 303 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 304 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 305 } 306 } 307 308 /* check support for radio transmitter switch in EEPROM */ 309 if (!(ipw_read_prom_word(sc, IPW_EEPROM_RADIO) & 8)) 310 sc->flags |= IPW_FLAG_HAS_RADIO_SWITCH; 311 312 aprint_normal("%s: 802.11 address %s\n", sc->sc_dev.dv_xname, 313 ether_sprintf(ic->ic_myaddr)); 314 315 if_attach(ifp); 316 ieee80211_ifattach(ic); 317 318 /* override state transition machine */ 319 sc->sc_newstate = ic->ic_newstate; 320 ic->ic_newstate = ipw_newstate; 321 322 ieee80211_media_init(ic, ipw_media_change, ipw_media_status); 323 324 #if NBPFILTER > 0 325 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 326 sizeof (struct ieee80211_frame) + 64, &sc->sc_drvbpf); 327 328 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 329 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 330 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 331 332 sc->sc_txtap_len = sizeof sc->sc_txtapu; 333 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 334 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 335 #endif 336 337 /* 338 * Add a few sysctl knobs. 339 * XXX: Not yet 340 */ 341 sc->dwelltime = 100; 342 343 /* 344 * Make sure the interface is shutdown during reboot. 345 */ 346 sc->sc_sdhook = shutdownhook_establish(ipw_shutdown, sc); 347 if (sc->sc_sdhook == NULL) 348 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 349 sc->sc_dev.dv_xname); 350 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 351 ipw_powerhook, sc); 352 if (sc->sc_powerhook == NULL) 353 printf("%s: WARNING: unable to establish power hook\n", 354 sc->sc_dev.dv_xname); 355 356 ieee80211_announce(ic); 357 358 return; 359 360 fail: ipw_detach(self, 0); 361 } 362 363 static int 364 ipw_detach(struct device* self, int flags) 365 { 366 struct ipw_softc *sc = (struct ipw_softc *)self; 367 struct ifnet *ifp = &sc->sc_if; 368 369 if (ifp->if_softc) { 370 ipw_stop(ifp, 1); 371 ipw_free_firmware(sc); 372 373 #if NBPFILTER > 0 374 bpfdetach(ifp); 375 #endif 376 ieee80211_ifdetach(&sc->sc_ic); 377 if_detach(ifp); 378 379 ipw_release(sc); 380 } 381 382 if (sc->sc_ih != NULL) { 383 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 384 sc->sc_ih = NULL; 385 } 386 387 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 388 389 return 0; 390 } 391 392 static int 393 ipw_dma_alloc(struct ipw_softc *sc) 394 { 395 struct ipw_soft_bd *sbd; 396 struct ipw_soft_hdr *shdr; 397 struct ipw_soft_buf *sbuf; 398 int error, i, nsegs; 399 400 /* 401 * Allocate and map tx ring. 402 */ 403 error = bus_dmamap_create(sc->sc_dmat, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, 404 BUS_DMA_NOWAIT, &sc->tbd_map); 405 if (error != 0) { 406 aprint_error("%s: could not create tbd dma map\n", 407 sc->sc_dev.dv_xname); 408 goto fail; 409 } 410 411 error = bus_dmamem_alloc(sc->sc_dmat, IPW_TBD_SZ, PAGE_SIZE, 0, 412 &sc->tbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 413 if (error != 0) { 414 aprint_error("%s: could not allocate tbd dma memory\n", 415 sc->sc_dev.dv_xname); 416 goto fail; 417 } 418 419 error = bus_dmamem_map(sc->sc_dmat, &sc->tbd_seg, nsegs, IPW_TBD_SZ, 420 (caddr_t *)&sc->tbd_list, BUS_DMA_NOWAIT); 421 if (error != 0) { 422 aprint_error("%s: could not map tbd dma memory\n", 423 sc->sc_dev.dv_xname); 424 goto fail; 425 } 426 427 error = bus_dmamap_load(sc->sc_dmat, sc->tbd_map, sc->tbd_list, 428 IPW_TBD_SZ, NULL, BUS_DMA_NOWAIT); 429 if (error != 0) { 430 aprint_error("%s: could not load tbd dma memory\n", 431 sc->sc_dev.dv_xname); 432 goto fail; 433 } 434 435 (void)memset(sc->tbd_list, 0, IPW_TBD_SZ); 436 437 /* 438 * Allocate and map rx ring. 439 */ 440 error = bus_dmamap_create(sc->sc_dmat, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, 441 BUS_DMA_NOWAIT, &sc->rbd_map); 442 if (error != 0) { 443 aprint_error("%s: could not create rbd dma map\n", 444 sc->sc_dev.dv_xname); 445 goto fail; 446 } 447 448 error = bus_dmamem_alloc(sc->sc_dmat, IPW_RBD_SZ, PAGE_SIZE, 0, 449 &sc->rbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 450 if (error != 0) { 451 aprint_error("%s: could not allocate rbd dma memory\n", 452 sc->sc_dev.dv_xname); 453 goto fail; 454 } 455 456 error = bus_dmamem_map(sc->sc_dmat, &sc->rbd_seg, nsegs, IPW_RBD_SZ, 457 (caddr_t *)&sc->rbd_list, BUS_DMA_NOWAIT); 458 if (error != 0) { 459 aprint_error("%s: could not map rbd dma memory\n", 460 sc->sc_dev.dv_xname); 461 goto fail; 462 } 463 464 error = bus_dmamap_load(sc->sc_dmat, sc->rbd_map, sc->rbd_list, 465 IPW_RBD_SZ, NULL, BUS_DMA_NOWAIT); 466 if (error != 0) { 467 aprint_error("%s: could not load rbd dma memory\n", 468 sc->sc_dev.dv_xname); 469 goto fail; 470 } 471 472 (void)memset(sc->rbd_list, 0, IPW_RBD_SZ); 473 474 /* 475 * Allocate and map status ring. 476 */ 477 error = bus_dmamap_create(sc->sc_dmat, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 478 0, BUS_DMA_NOWAIT, &sc->status_map); 479 if (error != 0) { 480 aprint_error("%s: could not create status dma map\n", 481 sc->sc_dev.dv_xname); 482 goto fail; 483 } 484 485 error = bus_dmamem_alloc(sc->sc_dmat, IPW_STATUS_SZ, PAGE_SIZE, 0, 486 &sc->status_seg, 1, &nsegs, BUS_DMA_NOWAIT); 487 if (error != 0) { 488 aprint_error("%s: could not allocate status dma memory\n", 489 sc->sc_dev.dv_xname); 490 goto fail; 491 } 492 493 error = bus_dmamem_map(sc->sc_dmat, &sc->status_seg, nsegs, 494 IPW_STATUS_SZ, (caddr_t *)&sc->status_list, BUS_DMA_NOWAIT); 495 if (error != 0) { 496 aprint_error("%s: could not map status dma memory\n", 497 sc->sc_dev.dv_xname); 498 goto fail; 499 } 500 501 error = bus_dmamap_load(sc->sc_dmat, sc->status_map, sc->status_list, 502 IPW_STATUS_SZ, NULL, BUS_DMA_NOWAIT); 503 if (error != 0) { 504 aprint_error("%s: could not load status dma memory\n", 505 sc->sc_dev.dv_xname); 506 goto fail; 507 } 508 509 (void)memset(sc->status_list, 0, IPW_STATUS_SZ); 510 511 /* 512 * Allocate command DMA map. 513 */ 514 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_cmd), 515 1, sizeof (struct ipw_cmd), 0, BUS_DMA_NOWAIT, &sc->cmd_map); 516 if (error != 0) { 517 aprint_error("%s: could not create cmd dma map\n", 518 sc->sc_dev.dv_xname); 519 goto fail; 520 } 521 522 error = bus_dmamem_alloc(sc->sc_dmat, sizeof (struct ipw_cmd), 523 PAGE_SIZE, 0, &sc->cmd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 524 if (error != 0) { 525 aprint_error("%s: could not allocate cmd dma memory\n", 526 sc->sc_dev.dv_xname); 527 goto fail; 528 } 529 530 error = bus_dmamem_map(sc->sc_dmat, &sc->cmd_seg, nsegs, 531 sizeof (struct ipw_cmd), (caddr_t *)&sc->cmd, BUS_DMA_NOWAIT); 532 if (error != 0) { 533 aprint_error("%s: could not map cmd dma memory\n", 534 sc->sc_dev.dv_xname); 535 goto fail; 536 } 537 538 error = bus_dmamap_load(sc->sc_dmat, sc->cmd_map, &sc->cmd, 539 sizeof (struct ipw_cmd), NULL, BUS_DMA_NOWAIT); 540 if (error != 0) { 541 aprint_error("%s: could not map cmd dma memory\n", 542 sc->sc_dev.dv_xname); 543 return error; 544 } 545 546 /* 547 * Allocate and map hdr list. 548 */ 549 550 error = bus_dmamap_create(sc->sc_dmat, 551 IPW_NDATA * sizeof(struct ipw_hdr), 1, 552 sizeof(struct ipw_hdr), 0, BUS_DMA_NOWAIT, 553 &sc->hdr_map); 554 if (error != 0) { 555 aprint_error("%s: could not create hdr dma map\n", 556 sc->sc_dev.dv_xname); 557 goto fail; 558 } 559 560 error = bus_dmamem_alloc(sc->sc_dmat, 561 IPW_NDATA * sizeof(struct ipw_hdr), PAGE_SIZE, 0, &sc->hdr_seg, 562 1, &nsegs, BUS_DMA_NOWAIT); 563 if (error != 0) { 564 aprint_error("%s: could not allocate hdr memory\n", 565 sc->sc_dev.dv_xname); 566 goto fail; 567 } 568 569 error = bus_dmamem_map(sc->sc_dmat, &sc->hdr_seg, nsegs, 570 IPW_NDATA * sizeof(struct ipw_hdr), (caddr_t *)&sc->hdr_list, 571 BUS_DMA_NOWAIT); 572 if (error != 0) { 573 aprint_error("%s: could not map hdr memory\n", 574 sc->sc_dev.dv_xname); 575 goto fail; 576 } 577 578 error = bus_dmamap_load(sc->sc_dmat, sc->hdr_map, sc->hdr_list, 579 IPW_NDATA * sizeof(struct ipw_hdr), NULL, BUS_DMA_NOWAIT); 580 if (error != 0) { 581 aprint_error("%s: could not load hdr memory\n", 582 sc->sc_dev.dv_xname); 583 goto fail; 584 } 585 586 (void)memset(sc->hdr_list, 0, IPW_HDR_SZ); 587 588 /* 589 * Create DMA hdrs tailq. 590 */ 591 TAILQ_INIT(&sc->sc_free_shdr); 592 for (i = 0; i < IPW_NDATA; i++) { 593 shdr = &sc->shdr_list[i]; 594 shdr->hdr = sc->hdr_list + i; 595 shdr->offset = sizeof(struct ipw_hdr) * i; 596 shdr->addr = sc->hdr_map->dm_segs[0].ds_addr + shdr->offset; 597 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 598 } 599 600 /* 601 * Allocate tx buffers DMA maps. 602 */ 603 TAILQ_INIT(&sc->sc_free_sbuf); 604 for (i = 0; i < IPW_NDATA; i++) { 605 sbuf = &sc->tx_sbuf_list[i]; 606 607 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 608 IPW_MAX_NSEG, MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 609 if (error != 0) { 610 aprint_error("%s: could not create txbuf dma map\n", 611 sc->sc_dev.dv_xname); 612 goto fail; 613 } 614 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 615 } 616 617 /* 618 * Initialize tx ring. 619 */ 620 for (i = 0; i < IPW_NTBD; i++) { 621 sbd = &sc->stbd_list[i]; 622 sbd->bd = &sc->tbd_list[i]; 623 sbd->type = IPW_SBD_TYPE_NOASSOC; 624 } 625 626 /* 627 * Pre-allocate rx buffers and DMA maps 628 */ 629 for (i = 0; i < IPW_NRBD; i++) { 630 sbd = &sc->srbd_list[i]; 631 sbuf = &sc->rx_sbuf_list[i]; 632 sbd->bd = &sc->rbd_list[i]; 633 634 MGETHDR(sbuf->m, M_DONTWAIT, MT_DATA); 635 if (sbuf->m == NULL) { 636 aprint_error("%s: could not allocate rx mbuf\n", 637 sc->sc_dev.dv_xname); 638 error = ENOMEM; 639 goto fail; 640 } 641 642 MCLGET(sbuf->m, M_DONTWAIT); 643 if (!(sbuf->m->m_flags & M_EXT)) { 644 m_freem(sbuf->m); 645 aprint_error("%s: could not allocate rx mbuf cluster\n", 646 sc->sc_dev.dv_xname); 647 error = ENOMEM; 648 goto fail; 649 } 650 651 sbuf->m->m_pkthdr.len = sbuf->m->m_len = sbuf->m->m_ext.ext_size; 652 653 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 654 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sbuf->map); 655 if (error != 0) { 656 aprint_error("%s: could not create rxbuf dma map\n", 657 sc->sc_dev.dv_xname); 658 m_freem(sbuf->m); 659 goto fail; 660 } 661 662 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, 663 sbuf->m, BUS_DMA_READ | BUS_DMA_NOWAIT); 664 if (error != 0) { 665 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 666 m_freem(sbuf->m); 667 aprint_error("%s: could not map rxbuf dma memory\n", 668 sc->sc_dev.dv_xname); 669 goto fail; 670 } 671 672 sbd->type = IPW_SBD_TYPE_DATA; 673 sbd->priv = sbuf; 674 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 675 sbd->bd->len = htole32(MCLBYTES); 676 677 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, 678 sbuf->map->dm_mapsize, BUS_DMASYNC_PREREAD); 679 680 } 681 682 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 0, IPW_RBD_SZ, 683 BUS_DMASYNC_PREREAD); 684 685 return 0; 686 687 fail: ipw_release(sc); 688 return error; 689 } 690 691 static void 692 ipw_release(struct ipw_softc *sc) 693 { 694 struct ipw_soft_buf *sbuf; 695 int i; 696 697 if (sc->tbd_map != NULL) { 698 if (sc->tbd_list != NULL) { 699 bus_dmamap_unload(sc->sc_dmat, sc->tbd_map); 700 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->tbd_list, 701 IPW_TBD_SZ); 702 bus_dmamem_free(sc->sc_dmat, &sc->tbd_seg, 1); 703 } 704 bus_dmamap_destroy(sc->sc_dmat, sc->tbd_map); 705 } 706 707 if (sc->rbd_map != NULL) { 708 if (sc->rbd_list != NULL) { 709 bus_dmamap_unload(sc->sc_dmat, sc->rbd_map); 710 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->rbd_list, 711 IPW_RBD_SZ); 712 bus_dmamem_free(sc->sc_dmat, &sc->rbd_seg, 1); 713 } 714 bus_dmamap_destroy(sc->sc_dmat, sc->rbd_map); 715 } 716 717 if (sc->status_map != NULL) { 718 if (sc->status_list != NULL) { 719 bus_dmamap_unload(sc->sc_dmat, sc->status_map); 720 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->status_list, 721 IPW_RBD_SZ); 722 bus_dmamem_free(sc->sc_dmat, &sc->status_seg, 1); 723 } 724 bus_dmamap_destroy(sc->sc_dmat, sc->status_map); 725 } 726 727 for (i = 0; i < IPW_NTBD; i++) 728 ipw_release_sbd(sc, &sc->stbd_list[i]); 729 730 if (sc->cmd_map != NULL) 731 bus_dmamap_destroy(sc->sc_dmat, sc->cmd_map); 732 733 if (sc->hdr_list != NULL) { 734 bus_dmamap_unload(sc->sc_dmat, sc->hdr_map); 735 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->hdr_list, 736 IPW_NDATA * sizeof(struct ipw_hdr)); 737 } 738 if (sc->hdr_map != NULL) { 739 bus_dmamem_free(sc->sc_dmat, &sc->hdr_seg, 1); 740 bus_dmamap_destroy(sc->sc_dmat, sc->hdr_map); 741 } 742 743 for (i = 0; i < IPW_NDATA; i++) 744 bus_dmamap_destroy(sc->sc_dmat, sc->tx_sbuf_list[i].map); 745 746 for (i = 0; i < IPW_NRBD; i++) { 747 sbuf = &sc->rx_sbuf_list[i]; 748 if (sbuf->map != NULL) { 749 if (sbuf->m != NULL) { 750 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 751 m_freem(sbuf->m); 752 } 753 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 754 } 755 } 756 757 } 758 759 static void 760 ipw_shutdown(void *arg) 761 { 762 struct ipw_softc *sc = (struct ipw_softc *)arg; 763 struct ifnet *ifp = sc->sc_ic.ic_ifp; 764 765 ipw_stop(ifp, 1); 766 } 767 768 769 static int 770 ipw_suspend(struct ipw_softc *sc) 771 { 772 struct ifnet *ifp = sc->sc_ic.ic_ifp; 773 774 ipw_stop(ifp, 1); 775 776 return 0; 777 } 778 779 static int 780 ipw_resume(struct ipw_softc *sc) 781 { 782 struct ifnet *ifp = sc->sc_ic.ic_ifp; 783 pcireg_t data; 784 785 /* clear device specific PCI configuration register 0x41 */ 786 data = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 787 data &= ~0x0000ff00; 788 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, data); 789 790 if (ifp->if_flags & IFF_UP) { 791 ipw_init(ifp); 792 if (ifp->if_flags & IFF_RUNNING) 793 ipw_start(ifp); 794 } 795 796 return 0; 797 } 798 799 static void 800 ipw_powerhook(int why, void *arg) 801 { 802 struct ipw_softc *sc = arg; 803 int s; 804 805 s = splnet(); 806 switch (why) { 807 case PWR_SUSPEND: 808 case PWR_STANDBY: 809 ipw_suspend(sc); 810 break; 811 case PWR_RESUME: 812 ipw_resume(sc); 813 break; 814 case PWR_SOFTSUSPEND: 815 case PWR_SOFTSTANDBY: 816 case PWR_SOFTRESUME: 817 break; 818 } 819 splx(s); 820 } 821 822 static int 823 ipw_media_change(struct ifnet *ifp) 824 { 825 int error; 826 827 error = ieee80211_media_change(ifp); 828 if (error != ENETRESET) 829 return error; 830 831 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 832 ipw_init(ifp); 833 834 return 0; 835 } 836 837 /* 838 * The firmware automatically adapts the transmit speed. We report the current 839 * transmit speed here. 840 */ 841 static void 842 ipw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 843 { 844 #define N(a) (sizeof (a) / sizeof (a[0])) 845 struct ipw_softc *sc = ifp->if_softc; 846 struct ieee80211com *ic = &sc->sc_ic; 847 static const struct { 848 uint32_t val; 849 int rate; 850 } rates[] = { 851 { IPW_RATE_DS1, 2 }, 852 { IPW_RATE_DS2, 4 }, 853 { IPW_RATE_DS5, 11 }, 854 { IPW_RATE_DS11, 22 }, 855 }; 856 uint32_t val; 857 int rate, i; 858 859 imr->ifm_status = IFM_AVALID; 860 imr->ifm_active = IFM_IEEE80211; 861 if (ic->ic_state == IEEE80211_S_RUN) 862 imr->ifm_status |= IFM_ACTIVE; 863 864 /* read current transmission rate from adapter */ 865 val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE) & 0xf; 866 867 /* convert ipw rate to 802.11 rate */ 868 for (i = 0; i < N(rates) && rates[i].val != val; i++); 869 rate = (i < N(rates)) ? rates[i].rate : 0; 870 871 imr->ifm_active |= IFM_IEEE80211_11B; 872 imr->ifm_active |= ieee80211_rate2media(ic, rate, IEEE80211_MODE_11B); 873 switch (ic->ic_opmode) { 874 case IEEE80211_M_STA: 875 break; 876 877 case IEEE80211_M_IBSS: 878 imr->ifm_active |= IFM_IEEE80211_ADHOC; 879 break; 880 881 case IEEE80211_M_MONITOR: 882 imr->ifm_active |= IFM_IEEE80211_MONITOR; 883 break; 884 885 case IEEE80211_M_AHDEMO: 886 case IEEE80211_M_HOSTAP: 887 /* should not get there */ 888 break; 889 } 890 #undef N 891 } 892 893 static int 894 ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, 895 int arg) 896 { 897 struct ifnet *ifp = ic->ic_ifp; 898 struct ipw_softc *sc = ifp->if_softc; 899 struct ieee80211_node *ni; 900 uint8_t macaddr[IEEE80211_ADDR_LEN]; 901 uint32_t len; 902 903 switch (nstate) { 904 case IEEE80211_S_RUN: 905 DELAY(200); /* firmware needs a short delay here */ 906 907 len = IEEE80211_ADDR_LEN; 908 ipw_read_table2(sc, IPW_INFO_CURRENT_BSSID, macaddr, &len); 909 910 ni = ieee80211_find_node(&ic->ic_scan, macaddr); 911 if (ni == NULL) 912 break; 913 914 ieee80211_ref_node(ni); 915 ieee80211_sta_join(ic, ni); 916 ieee80211_node_authorize(ni); 917 918 if (ic->ic_opmode == IEEE80211_M_STA) 919 ieee80211_notify_node_join(ic, ni, 1); 920 break; 921 922 case IEEE80211_S_INIT: 923 case IEEE80211_S_SCAN: 924 case IEEE80211_S_AUTH: 925 case IEEE80211_S_ASSOC: 926 break; 927 } 928 929 ic->ic_state = nstate; 930 return 0; 931 } 932 933 /* 934 * Read 16 bits at address 'addr' from the serial EEPROM. 935 */ 936 static uint16_t 937 ipw_read_prom_word(struct ipw_softc *sc, uint8_t addr) 938 { 939 uint32_t tmp; 940 uint16_t val; 941 int n; 942 943 /* clock C once before the first command */ 944 IPW_EEPROM_CTL(sc, 0); 945 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 946 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 947 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 948 949 /* write start bit (1) */ 950 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 951 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 952 953 /* write READ opcode (10) */ 954 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 955 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 956 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 957 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 958 959 /* write address A7-A0 */ 960 for (n = 7; n >= 0; n--) { 961 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 962 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D)); 963 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 964 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D) | IPW_EEPROM_C); 965 } 966 967 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 968 969 /* read data Q15-Q0 */ 970 val = 0; 971 for (n = 15; n >= 0; n--) { 972 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 973 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 974 tmp = MEM_READ_4(sc, IPW_MEM_EEPROM_CTL); 975 val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n; 976 } 977 978 IPW_EEPROM_CTL(sc, 0); 979 980 /* clear Chip Select and clock C */ 981 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 982 IPW_EEPROM_CTL(sc, 0); 983 IPW_EEPROM_CTL(sc, IPW_EEPROM_C); 984 985 return le16toh(val); 986 } 987 988 static void 989 ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 990 { 991 struct ipw_cmd *cmd; 992 993 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof (struct ipw_cmd), 994 BUS_DMASYNC_POSTREAD); 995 996 cmd = mtod(sbuf->m, struct ipw_cmd *); 997 998 DPRINTFN(2, ("cmd ack'ed (%u, %u, %u, %u, %u)\n", le32toh(cmd->type), 999 le32toh(cmd->subtype), le32toh(cmd->seq), le32toh(cmd->len), 1000 le32toh(cmd->status))); 1001 1002 wakeup(&sc->cmd); 1003 } 1004 1005 static void 1006 ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 1007 { 1008 struct ieee80211com *ic = &sc->sc_ic; 1009 struct ifnet *ifp = sc->sc_ic.ic_ifp; 1010 uint32_t state; 1011 1012 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof state, 1013 BUS_DMASYNC_POSTREAD); 1014 1015 state = le32toh(*mtod(sbuf->m, uint32_t *)); 1016 1017 DPRINTFN(2, ("entering state %u\n", state)); 1018 1019 switch (state) { 1020 case IPW_STATE_ASSOCIATED: 1021 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1022 break; 1023 1024 case IPW_STATE_SCANNING: 1025 /* don't leave run state on background scan */ 1026 if (ic->ic_state != IEEE80211_S_RUN) 1027 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1028 1029 ic->ic_flags |= IEEE80211_F_SCAN; 1030 break; 1031 1032 case IPW_STATE_SCAN_COMPLETE: 1033 ieee80211_notify_scan_done(ic); 1034 ic->ic_flags &= ~IEEE80211_F_SCAN; 1035 break; 1036 1037 case IPW_STATE_ASSOCIATION_LOST: 1038 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1039 break; 1040 1041 case IPW_STATE_RADIO_DISABLED: 1042 ic->ic_ifp->if_flags &= ~IFF_UP; 1043 ipw_stop(ifp, 1); 1044 break; 1045 } 1046 } 1047 1048 /* 1049 * XXX: Hack to set the current channel to the value advertised in beacons or 1050 * probe responses. Only used during AP detection. 1051 */ 1052 static void 1053 ipw_fix_channel(struct ieee80211com *ic, struct mbuf *m) 1054 { 1055 struct ieee80211_frame *wh; 1056 uint8_t subtype; 1057 uint8_t *frm, *efrm; 1058 1059 wh = mtod(m, struct ieee80211_frame *); 1060 1061 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_MGT) 1062 return; 1063 1064 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 1065 1066 if (subtype != IEEE80211_FC0_SUBTYPE_BEACON && 1067 subtype != IEEE80211_FC0_SUBTYPE_PROBE_RESP) 1068 return; 1069 1070 frm = (uint8_t *)(wh + 1); 1071 efrm = mtod(m, uint8_t *) + m->m_len; 1072 1073 frm += 12; /* skip tstamp, bintval and capinfo fields */ 1074 while (frm < efrm) { 1075 if (*frm == IEEE80211_ELEMID_DSPARMS) 1076 #if IEEE80211_CHAN_MAX < 255 1077 if (frm[2] <= IEEE80211_CHAN_MAX) 1078 #endif 1079 ic->ic_curchan = &ic->ic_channels[frm[2]]; 1080 1081 frm += frm[1] + 2; 1082 } 1083 } 1084 1085 static void 1086 ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 1087 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 1088 { 1089 struct ieee80211com *ic = &sc->sc_ic; 1090 struct ifnet *ifp = &sc->sc_if; 1091 struct mbuf *mnew, *m; 1092 struct ieee80211_frame *wh; 1093 struct ieee80211_node *ni; 1094 int error; 1095 1096 DPRINTFN(5, ("received frame len=%u, rssi=%u\n", le32toh(status->len), 1097 status->rssi)); 1098 1099 if (le32toh(status->len) < sizeof (struct ieee80211_frame_min) || 1100 le32toh(status->len) > MCLBYTES) 1101 return; 1102 1103 /* 1104 * Try to allocate a new mbuf for this ring element and load it before 1105 * processing the current mbuf. If the ring element cannot be loaded, 1106 * drop the received packet and reuse the old mbuf. In the unlikely 1107 * case that the old mbuf can't be reloaded either, explicitly panic. 1108 */ 1109 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1110 if (mnew == NULL) { 1111 aprint_error("%s: could not allocate rx mbuf\n", 1112 sc->sc_dev.dv_xname); 1113 ifp->if_ierrors++; 1114 return; 1115 } 1116 1117 MCLGET(mnew, M_DONTWAIT); 1118 if (!(mnew->m_flags & M_EXT)) { 1119 aprint_error("%s: could not allocate rx mbuf cluster\n", 1120 sc->sc_dev.dv_xname); 1121 m_freem(mnew); 1122 ifp->if_ierrors++; 1123 return; 1124 } 1125 1126 mnew->m_pkthdr.len = mnew->m_len = mnew->m_ext.ext_size; 1127 1128 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, le32toh(status->len), 1129 BUS_DMASYNC_POSTREAD); 1130 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1131 1132 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, mnew, 1133 BUS_DMA_READ | BUS_DMA_NOWAIT); 1134 if (error != 0) { 1135 aprint_error("%s: could not load rx buf DMA map\n", 1136 sc->sc_dev.dv_xname); 1137 m_freem(mnew); 1138 1139 /* try to reload the old mbuf */ 1140 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, 1141 sbuf->m, BUS_DMA_READ | BUS_DMA_NOWAIT); 1142 if (error != 0) { 1143 /* very unlikely that it will fail... */ 1144 panic("%s: unable to remap rx buf", 1145 sc->sc_dev.dv_xname); 1146 } 1147 ifp->if_ierrors++; 1148 return; 1149 } 1150 1151 /* 1152 * New mbuf successfully loaded, update Rx ring and continue 1153 * processing. 1154 */ 1155 m = sbuf->m; 1156 sbuf->m = mnew; 1157 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 1158 1159 /* finalize mbuf */ 1160 m->m_pkthdr.rcvif = ifp; 1161 m->m_pkthdr.len = m->m_len = le32toh(status->len); 1162 1163 #if NBPFILTER > 0 1164 if (sc->sc_drvbpf != NULL) { 1165 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 1166 1167 tap->wr_flags = 0; 1168 tap->wr_antsignal = status->rssi; 1169 tap->wr_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 1170 tap->wr_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 1171 1172 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 1173 } 1174 #endif 1175 1176 if (ic->ic_state == IEEE80211_S_SCAN) 1177 ipw_fix_channel(ic, m); 1178 1179 wh = mtod(m, struct ieee80211_frame *); 1180 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 1181 1182 /* send the frame to the 802.11 layer */ 1183 ieee80211_input(ic, m, ni, status->rssi, 0); 1184 1185 /* node is no longer needed */ 1186 ieee80211_free_node(ni); 1187 1188 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, 1189 sbuf->map->dm_mapsize, BUS_DMASYNC_PREREAD); 1190 } 1191 1192 static void 1193 ipw_rx_intr(struct ipw_softc *sc) 1194 { 1195 struct ipw_status *status; 1196 struct ipw_soft_bd *sbd; 1197 struct ipw_soft_buf *sbuf; 1198 uint32_t r, i; 1199 1200 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1201 return; 1202 1203 r = CSR_READ_4(sc, IPW_CSR_RX_READ); 1204 1205 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 1206 1207 /* firmware was killed, stop processing received frames */ 1208 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1209 return; 1210 1211 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 1212 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1213 BUS_DMASYNC_POSTREAD); 1214 1215 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 1216 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 1217 BUS_DMASYNC_POSTREAD); 1218 1219 status = &sc->status_list[i]; 1220 sbd = &sc->srbd_list[i]; 1221 sbuf = sbd->priv; 1222 1223 switch (le16toh(status->code) & 0xf) { 1224 case IPW_STATUS_CODE_COMMAND: 1225 ipw_command_intr(sc, sbuf); 1226 break; 1227 1228 case IPW_STATUS_CODE_NEWSTATE: 1229 ipw_newstate_intr(sc, sbuf); 1230 break; 1231 1232 case IPW_STATUS_CODE_DATA_802_3: 1233 case IPW_STATUS_CODE_DATA_802_11: 1234 ipw_data_intr(sc, status, sbd, sbuf); 1235 break; 1236 1237 case IPW_STATUS_CODE_NOTIFICATION: 1238 DPRINTFN(2, ("received notification\n")); 1239 break; 1240 1241 default: 1242 aprint_error("%s: unknown status code %u\n", 1243 sc->sc_dev.dv_xname, le16toh(status->code)); 1244 } 1245 1246 sbd->bd->flags = 0; 1247 1248 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 1249 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1250 BUS_DMASYNC_PREREAD); 1251 1252 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 1253 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 1254 BUS_DMASYNC_PREREAD); 1255 } 1256 1257 /* Tell the firmware what we have processed */ 1258 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 1259 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 1260 } 1261 1262 static void 1263 ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 1264 { 1265 struct ieee80211com *ic; 1266 struct ipw_soft_hdr *shdr; 1267 struct ipw_soft_buf *sbuf; 1268 1269 switch (sbd->type) { 1270 case IPW_SBD_TYPE_COMMAND: 1271 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 1272 0, sizeof(struct ipw_cmd), BUS_DMASYNC_POSTWRITE); 1273 /* bus_dmamap_unload(sc->sc_dmat, sc->cmd_map); */ 1274 break; 1275 1276 case IPW_SBD_TYPE_HEADER: 1277 shdr = sbd->priv; 1278 bus_dmamap_sync(sc->sc_dmat, sc->hdr_map, 1279 shdr->offset, sizeof(struct ipw_hdr), BUS_DMASYNC_POSTWRITE); 1280 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 1281 break; 1282 1283 case IPW_SBD_TYPE_DATA: 1284 ic = &sc->sc_ic; 1285 sbuf = sbd->priv; 1286 1287 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 1288 0, MCLBYTES, BUS_DMASYNC_POSTWRITE); 1289 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1290 m_freem(sbuf->m); 1291 if (sbuf->ni != NULL) 1292 ieee80211_free_node(sbuf->ni); 1293 /* kill watchdog timer */ 1294 sc->sc_tx_timer = 0; 1295 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 1296 break; 1297 } 1298 sbd->type = IPW_SBD_TYPE_NOASSOC; 1299 } 1300 1301 static void 1302 ipw_tx_intr(struct ipw_softc *sc) 1303 { 1304 struct ifnet *ifp = &sc->sc_if; 1305 struct ipw_soft_bd *sbd; 1306 uint32_t r, i; 1307 1308 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1309 return; 1310 1311 r = CSR_READ_4(sc, IPW_CSR_TX_READ); 1312 1313 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) { 1314 sbd = &sc->stbd_list[i]; 1315 1316 if (sbd->type == IPW_SBD_TYPE_DATA) 1317 ifp->if_opackets++; 1318 1319 ipw_release_sbd(sc, sbd); 1320 sc->txfree++; 1321 } 1322 1323 /* remember what the firmware has processed */ 1324 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 1325 1326 /* Call start() since some buffer descriptors have been released */ 1327 ifp->if_flags &= ~IFF_OACTIVE; 1328 (*ifp->if_start)(ifp); 1329 } 1330 1331 static int 1332 ipw_intr(void *arg) 1333 { 1334 struct ipw_softc *sc = arg; 1335 uint32_t r; 1336 1337 r = CSR_READ_4(sc, IPW_CSR_INTR); 1338 if (r == 0 || r == 0xffffffff) 1339 return 0; 1340 1341 /* Disable interrupts */ 1342 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1343 1344 if (r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR)) { 1345 aprint_error("%s: fatal error\n", 1346 sc->sc_dev.dv_xname); 1347 sc->sc_ic.ic_ifp->if_flags &= ~IFF_UP; 1348 ipw_stop(&sc->sc_if, 1); 1349 } 1350 1351 if (r & IPW_INTR_FW_INIT_DONE) { 1352 if (!(r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR))) 1353 wakeup(sc); 1354 } 1355 1356 if (r & IPW_INTR_RX_TRANSFER) 1357 ipw_rx_intr(sc); 1358 1359 if (r & IPW_INTR_TX_TRANSFER) 1360 ipw_tx_intr(sc); 1361 1362 /* Acknowledge all interrupts */ 1363 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 1364 1365 /* Re-enable interrupts */ 1366 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1367 1368 return 0; 1369 } 1370 1371 /* 1372 * Send a command to the firmware and wait for the acknowledgement. 1373 */ 1374 static int 1375 ipw_cmd(struct ipw_softc *sc, uint32_t type, void *data, uint32_t len) 1376 { 1377 struct ipw_soft_bd *sbd; 1378 1379 sbd = &sc->stbd_list[sc->txcur]; 1380 1381 sc->cmd.type = htole32(type); 1382 sc->cmd.subtype = 0; 1383 sc->cmd.len = htole32(len); 1384 sc->cmd.seq = 0; 1385 1386 (void)memcpy(sc->cmd.data, data, len); 1387 1388 sbd->type = IPW_SBD_TYPE_COMMAND; 1389 sbd->bd->physaddr = htole32(sc->cmd_map->dm_segs[0].ds_addr); 1390 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 1391 sbd->bd->nfrag = 1; 1392 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 1393 IPW_BD_FLAG_TX_LAST_FRAGMENT; 1394 1395 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 0, sizeof (struct ipw_cmd), 1396 BUS_DMASYNC_PREWRITE); 1397 1398 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1399 sc->txcur * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1400 BUS_DMASYNC_PREWRITE); 1401 1402 DPRINTFN(2, ("sending command (%u, %u, %u, %u)\n", type, 0, 0, len)); 1403 1404 /* kick firmware */ 1405 sc->txfree--; 1406 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1407 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1408 1409 /* Wait at most one second for command to complete */ 1410 return tsleep(&sc->cmd, 0, "ipwcmd", hz); 1411 } 1412 1413 static int 1414 ipw_tx_start(struct ifnet *ifp, struct mbuf *m0, struct ieee80211_node *ni) 1415 { 1416 struct ipw_softc *sc = ifp->if_softc; 1417 struct ieee80211com *ic = &sc->sc_ic; 1418 struct ieee80211_frame *wh; 1419 struct ipw_soft_bd *sbd; 1420 struct ipw_soft_hdr *shdr; 1421 struct ipw_soft_buf *sbuf; 1422 struct ieee80211_key *k; 1423 struct mbuf *mnew; 1424 int error, i; 1425 1426 wh = mtod(m0, struct ieee80211_frame *); 1427 1428 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1429 k = ieee80211_crypto_encap(ic, ni, m0); 1430 if (k == NULL) { 1431 m_freem(m0); 1432 return ENOBUFS; 1433 } 1434 1435 /* packet header may have moved, reset our local pointer */ 1436 wh = mtod(m0, struct ieee80211_frame *); 1437 } 1438 1439 #if NBPFILTER > 0 1440 if (sc->sc_drvbpf != NULL) { 1441 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 1442 1443 tap->wt_flags = 0; 1444 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 1445 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 1446 1447 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 1448 } 1449 #endif 1450 1451 shdr = TAILQ_FIRST(&sc->sc_free_shdr); 1452 sbuf = TAILQ_FIRST(&sc->sc_free_sbuf); 1453 KASSERT(shdr != NULL && sbuf != NULL); 1454 1455 shdr->hdr->type = htole32(IPW_HDR_TYPE_SEND); 1456 shdr->hdr->subtype = 0; 1457 shdr->hdr->encrypted = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0; 1458 shdr->hdr->encrypt = 0; 1459 shdr->hdr->keyidx = 0; 1460 shdr->hdr->keysz = 0; 1461 shdr->hdr->fragmentsz = 0; 1462 IEEE80211_ADDR_COPY(shdr->hdr->src_addr, wh->i_addr2); 1463 if (ic->ic_opmode == IEEE80211_M_STA) 1464 IEEE80211_ADDR_COPY(shdr->hdr->dst_addr, wh->i_addr3); 1465 else 1466 IEEE80211_ADDR_COPY(shdr->hdr->dst_addr, wh->i_addr1); 1467 1468 /* trim IEEE802.11 header */ 1469 m_adj(m0, sizeof (struct ieee80211_frame)); 1470 1471 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m0, BUS_DMA_NOWAIT); 1472 if (error != 0 && error != EFBIG) { 1473 aprint_error("%s: could not map mbuf (error %d)\n", 1474 sc->sc_dev.dv_xname, error); 1475 m_freem(m0); 1476 return error; 1477 } 1478 1479 if (error != 0) { 1480 /* too many fragments, linearize */ 1481 1482 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1483 if (mnew == NULL) { 1484 m_freem(m0); 1485 return ENOMEM; 1486 } 1487 1488 M_COPY_PKTHDR(mnew, m0); 1489 1490 /* If the data won't fit in the header, get a cluster */ 1491 if (m0->m_pkthdr.len > MHLEN) { 1492 MCLGET(mnew, M_DONTWAIT); 1493 if (!(mnew->m_flags & M_EXT)) { 1494 m_freem(m0); 1495 m_freem(mnew); 1496 return ENOMEM; 1497 } 1498 } 1499 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(mnew, caddr_t)); 1500 m_freem(m0); 1501 mnew->m_len = mnew->m_pkthdr.len; 1502 m0 = mnew; 1503 1504 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m0, 1505 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1506 if (error != 0) { 1507 aprint_error("%s: could not map mbuf (error %d)\n", 1508 sc->sc_dev.dv_xname, error); 1509 m_freem(m0); 1510 return error; 1511 } 1512 } 1513 1514 TAILQ_REMOVE(&sc->sc_free_sbuf, sbuf, next); 1515 TAILQ_REMOVE(&sc->sc_free_shdr, shdr, next); 1516 1517 sbd = &sc->stbd_list[sc->txcur]; 1518 sbd->type = IPW_SBD_TYPE_HEADER; 1519 sbd->priv = shdr; 1520 sbd->bd->physaddr = htole32(shdr->addr); 1521 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 1522 sbd->bd->nfrag = 1 + sbuf->map->dm_nsegs; 1523 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 1524 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1525 1526 DPRINTFN(5, ("sending tx hdr (%u, %u, %u, %u, )\n", 1527 shdr->hdr->type, shdr->hdr->subtype, shdr->hdr->encrypted, 1528 shdr->hdr->encrypt)); 1529 DPRINTFN(5, ("%s->", ether_sprintf(shdr->hdr->src_addr))); 1530 DPRINTFN(5, ("%s\n", ether_sprintf(shdr->hdr->dst_addr))); 1531 1532 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1533 sc->txcur * sizeof (struct ipw_bd), 1534 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1535 1536 sc->txfree--; 1537 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1538 1539 sbuf->m = m0; 1540 sbuf->ni = ni; 1541 1542 for (i = 0; i < sbuf->map->dm_nsegs; i++) { 1543 sbd = &sc->stbd_list[sc->txcur]; 1544 1545 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[i].ds_addr); 1546 sbd->bd->len = htole32(sbuf->map->dm_segs[i].ds_len); 1547 sbd->bd->nfrag = 0; 1548 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 1549 if (i == sbuf->map->dm_nsegs - 1) { 1550 sbd->type = IPW_SBD_TYPE_DATA; 1551 sbd->priv = sbuf; 1552 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 1553 } else { 1554 sbd->type = IPW_SBD_TYPE_NOASSOC; 1555 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1556 } 1557 1558 DPRINTFN(5, ("sending fragment (%d, %d)\n", i, 1559 (int)sbuf->map->dm_segs[i].ds_len)); 1560 1561 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1562 sc->txcur * sizeof (struct ipw_bd), 1563 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1564 1565 sc->txfree--; 1566 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1567 } 1568 1569 bus_dmamap_sync(sc->sc_dmat, sc->hdr_map, shdr->offset, 1570 sizeof (struct ipw_hdr), BUS_DMASYNC_PREWRITE); 1571 1572 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, MCLBYTES, 1573 BUS_DMASYNC_PREWRITE); 1574 1575 /* Inform firmware about this new packet */ 1576 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1577 1578 return 0; 1579 } 1580 1581 static void 1582 ipw_start(struct ifnet *ifp) 1583 { 1584 struct ipw_softc *sc = ifp->if_softc; 1585 struct ieee80211com *ic = &sc->sc_ic; 1586 struct mbuf *m0; 1587 struct ether_header *eh; 1588 struct ieee80211_node *ni; 1589 1590 1591 if (ic->ic_state != IEEE80211_S_RUN) 1592 return; 1593 1594 for (;;) { 1595 IF_DEQUEUE(&ifp->if_snd, m0); 1596 if (m0 == NULL) 1597 break; 1598 1599 if (sc->txfree < 1 + IPW_MAX_NSEG) { 1600 IF_PREPEND(&ifp->if_snd, m0); 1601 ifp->if_flags |= IFF_OACTIVE; 1602 break; 1603 } 1604 1605 if (m0->m_len < sizeof (struct ether_header) && 1606 (m0 = m_pullup(m0, sizeof (struct ether_header))) == NULL) 1607 continue; 1608 1609 eh = mtod(m0, struct ether_header *); 1610 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1611 if (ni == NULL) { 1612 m_freem(m0); 1613 continue; 1614 } 1615 1616 #if NBPFILTER > 0 1617 if (ifp->if_bpf != NULL) 1618 bpf_mtap(ifp->if_bpf, m0); 1619 #endif 1620 1621 m0 = ieee80211_encap(ic, m0, ni); 1622 if (m0 == NULL) { 1623 ieee80211_free_node(ni); 1624 continue; 1625 } 1626 1627 #if NBPFILTER > 0 1628 if (ic->ic_rawbpf != NULL) 1629 bpf_mtap(ic->ic_rawbpf, m0); 1630 #endif 1631 1632 if (ipw_tx_start(ifp, m0, ni) != 0) { 1633 ieee80211_free_node(ni); 1634 ifp->if_oerrors++; 1635 break; 1636 } 1637 1638 /* start watchdog timer */ 1639 sc->sc_tx_timer = 5; 1640 ifp->if_timer = 1; 1641 } 1642 } 1643 1644 static void 1645 ipw_watchdog(struct ifnet *ifp) 1646 { 1647 struct ipw_softc *sc = ifp->if_softc; 1648 1649 ifp->if_timer = 0; 1650 1651 if (sc->sc_tx_timer > 0) { 1652 if (--sc->sc_tx_timer == 0) { 1653 aprint_error("%s: device timeout\n", 1654 sc->sc_dev.dv_xname); 1655 ifp->if_oerrors++; 1656 ifp->if_flags &= ~IFF_UP; 1657 ipw_stop(ifp, 1); 1658 return; 1659 } 1660 ifp->if_timer = 1; 1661 } 1662 1663 ieee80211_watchdog(&sc->sc_ic); 1664 } 1665 1666 static int 1667 ipw_get_table1(struct ipw_softc *sc, uint32_t *tbl) 1668 { 1669 uint32_t addr, size, i; 1670 1671 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1672 return ENOTTY; 1673 1674 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, sc->table1_base); 1675 1676 size = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 1677 if (suword(tbl, size) != 0) 1678 return EFAULT; 1679 1680 for (i = 1, ++tbl; i < size; i++, tbl++) { 1681 addr = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 1682 if (suword(tbl, MEM_READ_4(sc, addr)) != 0) 1683 return EFAULT; 1684 } 1685 return 0; 1686 } 1687 1688 static int 1689 ipw_get_radio(struct ipw_softc *sc, int *ret) 1690 { 1691 uint32_t addr; 1692 1693 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1694 return ENOTTY; 1695 1696 addr = ipw_read_table1(sc, IPW_INFO_EEPROM_ADDRESS); 1697 if ((MEM_READ_4(sc, addr + 32) >> 24) & 1) { 1698 suword(ret, -1); 1699 return 0; 1700 } 1701 1702 if (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED) 1703 suword(ret, 0); 1704 else 1705 suword(ret, 1); 1706 1707 return 0; 1708 } 1709 1710 static int 1711 ipw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1712 { 1713 #define IS_RUNNING(ifp) \ 1714 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 1715 1716 struct ipw_softc *sc = ifp->if_softc; 1717 struct ieee80211com *ic = &sc->sc_ic; 1718 struct ifreq *ifr = (struct ifreq *)data; 1719 int s, error = 0; 1720 1721 s = splnet(); 1722 1723 switch (cmd) { 1724 case SIOCSIFFLAGS: 1725 if (ifp->if_flags & IFF_UP) { 1726 if (!(ifp->if_flags & IFF_RUNNING)) 1727 ipw_init(ifp); 1728 } else { 1729 if (ifp->if_flags & IFF_RUNNING) 1730 ipw_stop(ifp, 1); 1731 } 1732 break; 1733 1734 case SIOCADDMULTI: 1735 case SIOCDELMULTI: 1736 error = (cmd == SIOCADDMULTI) ? 1737 ether_addmulti(ifr, &sc->sc_ec) : 1738 ether_delmulti(ifr, &sc->sc_ec); 1739 if (error == ENETRESET) { 1740 /* setup multicast filter, etc */ 1741 error = 0; 1742 } 1743 break; 1744 1745 case SIOCGTABLE1: 1746 error = ipw_get_table1(sc, (uint32_t *)ifr->ifr_data); 1747 break; 1748 1749 case SIOCGRADIO: 1750 error = ipw_get_radio(sc, (int *)ifr->ifr_data); 1751 break; 1752 1753 case SIOCSIFMEDIA: 1754 if (ifr->ifr_media & IFM_IEEE80211_ADHOC) 1755 strlcpy(sc->sc_fwname, "ipw2100-1.2-i.fw", 1756 sizeof(sc->sc_fwname)); 1757 else if (ifr->ifr_media & IFM_IEEE80211_MONITOR) 1758 strlcpy(sc->sc_fwname, "ipw2100-1.2-p.fw", 1759 sizeof(sc->sc_fwname)); 1760 else 1761 strlcpy(sc->sc_fwname, "ipw2100-1.2.fw", 1762 sizeof(sc->sc_fwname)); 1763 1764 ipw_free_firmware(sc); 1765 /* FALLTRHOUGH */ 1766 default: 1767 error = ieee80211_ioctl(&sc->sc_ic, cmd, data); 1768 if (error != ENETRESET) 1769 break; 1770 1771 if (error == ENETRESET) { 1772 if (IS_RUNNING(ifp) && 1773 (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)) 1774 ipw_init(ifp); 1775 error = 0; 1776 } 1777 1778 } 1779 1780 splx(s); 1781 return error; 1782 #undef IS_RUNNING 1783 } 1784 1785 static uint32_t 1786 ipw_read_table1(struct ipw_softc *sc, uint32_t off) 1787 { 1788 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 1789 } 1790 1791 static void 1792 ipw_write_table1(struct ipw_softc *sc, uint32_t off, uint32_t info) 1793 { 1794 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 1795 } 1796 1797 static int 1798 ipw_read_table2(struct ipw_softc *sc, uint32_t off, void *buf, uint32_t *len) 1799 { 1800 uint32_t addr, info; 1801 uint16_t count, size; 1802 uint32_t total; 1803 1804 /* addr[4] + count[2] + size[2] */ 1805 addr = MEM_READ_4(sc, sc->table2_base + off); 1806 info = MEM_READ_4(sc, sc->table2_base + off + 4); 1807 1808 count = info >> 16; 1809 size = info & 0xffff; 1810 total = count * size; 1811 1812 if (total > *len) { 1813 *len = total; 1814 return EINVAL; 1815 } 1816 1817 *len = total; 1818 ipw_read_mem_1(sc, addr, buf, total); 1819 1820 return 0; 1821 } 1822 1823 static void 1824 ipw_stop_master(struct ipw_softc *sc) 1825 { 1826 int ntries; 1827 1828 /* disable interrupts */ 1829 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1830 1831 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1832 for (ntries = 0; ntries < 50; ntries++) { 1833 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1834 break; 1835 DELAY(10); 1836 } 1837 if (ntries == 50) 1838 aprint_error("%s: timeout waiting for master\n", 1839 sc->sc_dev.dv_xname); 1840 1841 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1842 IPW_RST_PRINCETON_RESET); 1843 1844 sc->flags &= ~IPW_FLAG_FW_INITED; 1845 } 1846 1847 static int 1848 ipw_reset(struct ipw_softc *sc) 1849 { 1850 int ntries; 1851 1852 ipw_stop_master(sc); 1853 1854 /* move adapter to D0 state */ 1855 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1856 IPW_CTL_INIT); 1857 1858 /* wait for clock stabilization */ 1859 for (ntries = 0; ntries < 1000; ntries++) { 1860 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY) 1861 break; 1862 DELAY(200); 1863 } 1864 if (ntries == 1000) 1865 return EIO; 1866 1867 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1868 IPW_RST_SW_RESET); 1869 1870 DELAY(10); 1871 1872 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1873 IPW_CTL_INIT); 1874 1875 return 0; 1876 } 1877 1878 /* 1879 * Upload the microcode to the device. 1880 */ 1881 static int 1882 ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size) 1883 { 1884 int ntries; 1885 1886 MEM_WRITE_4(sc, 0x3000e0, 0x80000000); 1887 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1888 1889 MEM_WRITE_2(sc, 0x220000, 0x0703); 1890 MEM_WRITE_2(sc, 0x220000, 0x0707); 1891 1892 MEM_WRITE_1(sc, 0x210014, 0x72); 1893 MEM_WRITE_1(sc, 0x210014, 0x72); 1894 1895 MEM_WRITE_1(sc, 0x210000, 0x40); 1896 MEM_WRITE_1(sc, 0x210000, 0x00); 1897 MEM_WRITE_1(sc, 0x210000, 0x40); 1898 1899 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1900 1901 MEM_WRITE_1(sc, 0x210000, 0x00); 1902 MEM_WRITE_1(sc, 0x210000, 0x00); 1903 MEM_WRITE_1(sc, 0x210000, 0x80); 1904 1905 MEM_WRITE_2(sc, 0x220000, 0x0703); 1906 MEM_WRITE_2(sc, 0x220000, 0x0707); 1907 1908 MEM_WRITE_1(sc, 0x210014, 0x72); 1909 MEM_WRITE_1(sc, 0x210014, 0x72); 1910 1911 MEM_WRITE_1(sc, 0x210000, 0x00); 1912 MEM_WRITE_1(sc, 0x210000, 0x80); 1913 1914 for (ntries = 0; ntries < 10; ntries++) { 1915 if (MEM_READ_1(sc, 0x210000) & 1) 1916 break; 1917 DELAY(10); 1918 } 1919 if (ntries == 10) { 1920 aprint_error("%s: timeout waiting for ucode to initialize\n", 1921 sc->sc_dev.dv_xname); 1922 return EIO; 1923 } 1924 1925 MEM_WRITE_4(sc, 0x3000e0, 0); 1926 1927 return 0; 1928 } 1929 1930 /* set of macros to handle unaligned little endian data in firmware image */ 1931 #define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1932 #define GETLE16(p) ((p)[0] | (p)[1] << 8) 1933 static int 1934 ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size) 1935 { 1936 u_char *p, *end; 1937 uint32_t dst; 1938 uint16_t len; 1939 int error; 1940 1941 p = fw; 1942 end = fw + size; 1943 while (p < end) { 1944 dst = GETLE32(p); p += 4; 1945 len = GETLE16(p); p += 2; 1946 1947 ipw_write_mem_1(sc, dst, p, len); 1948 p += len; 1949 } 1950 1951 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1952 IPW_IO_LED_OFF); 1953 1954 /* enable interrupts */ 1955 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1956 1957 /* kick the firmware */ 1958 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1959 1960 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1961 IPW_CTL_ALLOW_STANDBY); 1962 1963 /* wait at most one second for firmware initialization to complete */ 1964 if ((error = tsleep(sc, 0, "ipwinit", hz)) != 0) { 1965 aprint_error("%s: timeout waiting for firmware initialization " 1966 "to complete\n", sc->sc_dev.dv_xname); 1967 return error; 1968 } 1969 1970 CSR_WRITE_4(sc, IPW_CSR_IO, CSR_READ_4(sc, IPW_CSR_IO) | 1971 IPW_IO_GPIO1_MASK | IPW_IO_GPIO3_MASK); 1972 1973 return 0; 1974 } 1975 1976 /* 1977 * Store firmware into kernel memory so we can download it when we need to, 1978 * e.g when the adapter wakes up from suspend mode. 1979 */ 1980 static int 1981 ipw_cache_firmware(struct ipw_softc *sc) 1982 { 1983 struct ipw_firmware *fw = &sc->fw; 1984 struct ipw_firmware_hdr hdr; 1985 firmware_handle_t fwh; 1986 off_t fwsz, p; 1987 int error; 1988 1989 ipw_free_firmware(sc); 1990 1991 if ((error = firmware_open("if_ipw", sc->sc_fwname, &fwh)) != 0) 1992 goto fail0; 1993 1994 fwsz = firmware_get_size(fwh); 1995 1996 if (fwsz < sizeof(hdr)) 1997 goto fail2; 1998 1999 if ((error = firmware_read(fwh, 0, &hdr, sizeof(hdr))) != 0) 2000 goto fail2; 2001 2002 fw->main_size = le32toh(hdr.main_size); 2003 fw->ucode_size = le32toh(hdr.ucode_size); 2004 2005 fw->main = firmware_malloc(fw->main_size); 2006 if (fw->main == NULL) { 2007 error = ENOMEM; 2008 goto fail1; 2009 } 2010 2011 fw->ucode = firmware_malloc(fw->ucode_size); 2012 if (fw->ucode == NULL) { 2013 error = ENOMEM; 2014 goto fail2; 2015 } 2016 2017 p = sizeof(hdr); 2018 if ((error = firmware_read(fwh, p, fw->main, fw->main_size)) != 0) 2019 goto fail3; 2020 2021 p += fw->main_size; 2022 if ((error = firmware_read(fwh, p, fw->ucode, fw->ucode_size)) != 0) 2023 goto fail3; 2024 2025 DPRINTF(("Firmware cached: main %u, ucode %u\n", fw->main_size, 2026 fw->ucode_size)); 2027 2028 sc->flags |= IPW_FLAG_FW_CACHED; 2029 2030 firmware_close(fwh); 2031 2032 return 0; 2033 2034 fail3: firmware_free(fw->ucode, 0); 2035 fail2: firmware_free(fw->main, 0); 2036 fail1: firmware_close(fwh); 2037 fail0: 2038 return error; 2039 } 2040 2041 static void 2042 ipw_free_firmware(struct ipw_softc *sc) 2043 { 2044 if (!(sc->flags & IPW_FLAG_FW_CACHED)) 2045 return; 2046 2047 firmware_free(sc->fw.main, 0); 2048 firmware_free(sc->fw.ucode, 0); 2049 2050 sc->flags &= ~IPW_FLAG_FW_CACHED; 2051 } 2052 2053 static int 2054 ipw_config(struct ipw_softc *sc) 2055 { 2056 struct ieee80211com *ic = &sc->sc_ic; 2057 struct ifnet *ifp = &sc->sc_if; 2058 struct ipw_security security; 2059 struct ieee80211_key *k; 2060 struct ipw_wep_key wepkey; 2061 struct ipw_scan_options options; 2062 struct ipw_configuration config; 2063 uint32_t data; 2064 int error, i; 2065 2066 switch (ic->ic_opmode) { 2067 case IEEE80211_M_STA: 2068 case IEEE80211_M_HOSTAP: 2069 data = htole32(IPW_MODE_BSS); 2070 break; 2071 2072 case IEEE80211_M_IBSS: 2073 case IEEE80211_M_AHDEMO: 2074 data = htole32(IPW_MODE_IBSS); 2075 break; 2076 2077 case IEEE80211_M_MONITOR: 2078 data = htole32(IPW_MODE_MONITOR); 2079 break; 2080 } 2081 DPRINTF(("Setting mode to %u\n", le32toh(data))); 2082 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 2083 if (error != 0) 2084 return error; 2085 2086 if (ic->ic_opmode == IEEE80211_M_IBSS || 2087 ic->ic_opmode == IEEE80211_M_MONITOR) { 2088 data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); 2089 DPRINTF(("Setting channel to %u\n", le32toh(data))); 2090 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 2091 if (error != 0) 2092 return error; 2093 } 2094 2095 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2096 DPRINTF(("Enabling adapter\n")); 2097 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 2098 } 2099 2100 DPRINTF(("Setting MAC to %s\n", ether_sprintf(ic->ic_myaddr))); 2101 IEEE80211_ADDR_COPY(LLADDR(ifp->if_sadl), ic->ic_myaddr); 2102 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 2103 IEEE80211_ADDR_LEN); 2104 if (error != 0) 2105 return error; 2106 2107 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 2108 IPW_CFG_PREAMBLE_AUTO | IPW_CFG_802_1x_ENABLE); 2109 2110 if (ic->ic_opmode == IEEE80211_M_IBSS) 2111 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 2112 if (ifp->if_flags & IFF_PROMISC) 2113 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 2114 config.bss_chan = htole32(0x3fff); /* channels 1-14 */ 2115 config.ibss_chan = htole32(0x7ff); /* channels 1-11 */ 2116 DPRINTF(("Setting adapter configuration 0x%08x\n", config.flags)); 2117 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 2118 if (error != 0) 2119 return error; 2120 2121 data = htole32(0x3); /* 1, 2 */ 2122 DPRINTF(("Setting basic tx rates to 0x%x\n", le32toh(data))); 2123 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 2124 if (error != 0) 2125 return error; 2126 2127 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 2128 DPRINTF(("Setting tx rates to 0x%x\n", le32toh(data))); 2129 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 2130 if (error != 0) 2131 return error; 2132 2133 data = htole32(IPW_POWER_MODE_CAM); 2134 DPRINTF(("Setting power mode to %u\n", le32toh(data))); 2135 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 2136 if (error != 0) 2137 return error; 2138 2139 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2140 data = htole32(32); /* default value */ 2141 DPRINTF(("Setting tx power index to %u\n", le32toh(data))); 2142 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 2143 sizeof data); 2144 if (error != 0) 2145 return error; 2146 } 2147 2148 data = htole32(ic->ic_rtsthreshold); 2149 DPRINTF(("Setting RTS threshold to %u\n", le32toh(data))); 2150 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 2151 if (error != 0) 2152 return error; 2153 2154 data = htole32(ic->ic_fragthreshold); 2155 DPRINTF(("Setting frag threshold to %u\n", le32toh(data))); 2156 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 2157 if (error != 0) 2158 return error; 2159 2160 #ifdef IPW_DEBUG 2161 if (ipw_debug > 0) { 2162 printf("Setting ESSID to "); 2163 ieee80211_print_essid(ic->ic_des_essid, ic->ic_des_esslen); 2164 printf("\n"); 2165 } 2166 #endif 2167 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ic->ic_des_essid, 2168 ic->ic_des_esslen); 2169 if (error != 0) 2170 return error; 2171 2172 /* no mandatory BSSID */ 2173 DPRINTF(("Setting mandatory BSSID to null\n")); 2174 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 2175 if (error != 0) 2176 return error; 2177 2178 if (ic->ic_flags & IEEE80211_F_DESBSSID) { 2179 DPRINTF(("Setting desired BSSID to %s\n", 2180 ether_sprintf(ic->ic_des_bssid))); 2181 error = ipw_cmd(sc, IPW_CMD_SET_DESIRED_BSSID, 2182 ic->ic_des_bssid, IEEE80211_ADDR_LEN); 2183 if (error != 0) 2184 return error; 2185 } 2186 2187 (void)memset(&security, 0, sizeof(security)); 2188 security.authmode = (ic->ic_bss->ni_authmode == IEEE80211_AUTH_SHARED) ? 2189 IPW_AUTH_SHARED : IPW_AUTH_OPEN; 2190 security.ciphers = htole32(IPW_CIPHER_NONE); 2191 DPRINTF(("Setting authmode to %u\n", security.authmode)); 2192 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 2193 sizeof security); 2194 if (error != 0) 2195 return error; 2196 2197 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 2198 k = ic->ic_crypto.cs_nw_keys; 2199 for (i = 0; i < IEEE80211_WEP_NKID; i++, k++) { 2200 if (k->wk_keylen == 0) 2201 continue; 2202 2203 wepkey.idx = i; 2204 wepkey.len = k->wk_keylen; 2205 memset(wepkey.key, 0, sizeof(wepkey.key)); 2206 memcpy(wepkey.key, k->wk_key, k->wk_keylen); 2207 DPRINTF(("Setting wep key index %u len %u\n", 2208 wepkey.idx, wepkey.len)); 2209 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY, &wepkey, 2210 sizeof wepkey); 2211 if (error != 0) 2212 return error; 2213 } 2214 2215 data = htole32(ic->ic_crypto.cs_def_txkey); 2216 DPRINTF(("Setting tx key index to %u\n", le32toh(data))); 2217 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY_INDEX, &data, 2218 sizeof data); 2219 if (error != 0) 2220 return error; 2221 } 2222 2223 data = htole32((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) ? IPW_WEPON : 0); 2224 DPRINTF(("Setting wep flags to 0x%x\n", le32toh(data))); 2225 error = ipw_cmd(sc, IPW_CMD_SET_WEP_FLAGS, &data, sizeof data); 2226 if (error != 0) 2227 return error; 2228 2229 #if 0 2230 struct ipw_wpa_ie ie; 2231 2232 memset(&ie, 0 sizeof(ie)); 2233 ie.len = htole32(sizeof (struct ieee80211_ie_wpa)); 2234 DPRINTF(("Setting wpa ie\n")); 2235 error = ipw_cmd(sc, IPW_CMD_SET_WPA_IE, &ie, sizeof ie); 2236 if (error != 0) 2237 return error; 2238 #endif 2239 2240 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2241 data = htole32(ic->ic_bintval); 2242 DPRINTF(("Setting beacon interval to %u\n", le32toh(data))); 2243 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 2244 sizeof data); 2245 if (error != 0) 2246 return error; 2247 } 2248 2249 options.flags = 0; 2250 options.channels = htole32(0x3fff); /* scan channels 1-14 */ 2251 DPRINTF(("Setting scan options to 0x%x\n", le32toh(options.flags))); 2252 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &options, sizeof options); 2253 if (error != 0) 2254 return error; 2255 2256 /* finally, enable adapter (start scanning for an access point) */ 2257 DPRINTF(("Enabling adapter\n")); 2258 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 2259 } 2260 2261 static int 2262 ipw_init(struct ifnet *ifp) 2263 { 2264 struct ipw_softc *sc = ifp->if_softc; 2265 struct ipw_firmware *fw = &sc->fw; 2266 2267 if (!(sc->flags & IPW_FLAG_FW_CACHED)) { 2268 if (ipw_cache_firmware(sc) != 0) { 2269 aprint_error("%s: could not cache the firmware (%s)\n", 2270 sc->sc_dev.dv_xname, sc->sc_fwname); 2271 goto fail; 2272 } 2273 } 2274 2275 ipw_stop(ifp, 0); 2276 2277 if (ipw_reset(sc) != 0) { 2278 aprint_error("%s: could not reset adapter\n", 2279 sc->sc_dev.dv_xname); 2280 goto fail; 2281 } 2282 2283 if (ipw_load_ucode(sc, fw->ucode, fw->ucode_size) != 0) { 2284 aprint_error("%s: could not load microcode\n", 2285 sc->sc_dev.dv_xname); 2286 goto fail; 2287 } 2288 2289 ipw_stop_master(sc); 2290 2291 /* 2292 * Setup tx, rx and status rings. 2293 */ 2294 sc->txold = IPW_NTBD - 1; 2295 sc->txcur = 0; 2296 sc->txfree = IPW_NTBD - 2; 2297 sc->rxcur = IPW_NRBD - 1; 2298 2299 CSR_WRITE_4(sc, IPW_CSR_TX_BASE, sc->tbd_map->dm_segs[0].ds_addr); 2300 CSR_WRITE_4(sc, IPW_CSR_TX_SIZE, IPW_NTBD); 2301 CSR_WRITE_4(sc, IPW_CSR_TX_READ, 0); 2302 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 2303 2304 CSR_WRITE_4(sc, IPW_CSR_RX_BASE, sc->rbd_map->dm_segs[0].ds_addr); 2305 CSR_WRITE_4(sc, IPW_CSR_RX_SIZE, IPW_NRBD); 2306 CSR_WRITE_4(sc, IPW_CSR_RX_READ, 0); 2307 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 2308 2309 CSR_WRITE_4(sc, IPW_CSR_STATUS_BASE, sc->status_map->dm_segs[0].ds_addr); 2310 2311 if (ipw_load_firmware(sc, fw->main, fw->main_size) != 0) { 2312 aprint_error("%s: could not load firmware\n", 2313 sc->sc_dev.dv_xname); 2314 goto fail; 2315 } 2316 2317 sc->flags |= IPW_FLAG_FW_INITED; 2318 2319 /* retrieve information tables base addresses */ 2320 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 2321 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 2322 2323 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 2324 2325 if (ipw_config(sc) != 0) { 2326 aprint_error("%s: device configuration failed\n", 2327 sc->sc_dev.dv_xname); 2328 goto fail; 2329 } 2330 2331 ifp->if_flags &= ~IFF_OACTIVE; 2332 ifp->if_flags |= IFF_RUNNING; 2333 2334 return 0; 2335 2336 fail: ifp->if_flags &= ~IFF_UP; 2337 ipw_stop(ifp, 0); 2338 2339 return EIO; 2340 } 2341 2342 static void 2343 ipw_stop(struct ifnet *ifp, int disable) 2344 { 2345 struct ipw_softc *sc = ifp->if_softc; 2346 struct ieee80211com *ic = &sc->sc_ic; 2347 int i; 2348 2349 ipw_stop_master(sc); 2350 2351 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 2352 2353 /* 2354 * Release tx buffers. 2355 */ 2356 for (i = 0; i < IPW_NTBD; i++) 2357 ipw_release_sbd(sc, &sc->stbd_list[i]); 2358 2359 sc->sc_tx_timer = 0; 2360 ifp->if_timer = 0; 2361 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2362 2363 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2364 } 2365 2366 static void 2367 ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2368 bus_size_t count) 2369 { 2370 for (; count > 0; offset++, datap++, count--) { 2371 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2372 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 2373 } 2374 } 2375 2376 static void 2377 ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2378 bus_size_t count) 2379 { 2380 for (; count > 0; offset++, datap++, count--) { 2381 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2382 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 2383 } 2384 } 2385
Indexes created Mon Sep 29 21:09:56 GMT 2025