if_ipw.c revision 1.31.8.1
1 /* $NetBSD: if_ipw.c,v 1.31.8.1 2008/09/04 08:46:45 skrll Exp $ */ 2 /* FreeBSD: src/sys/dev/ipw/if_ipw.c,v 1.15 2005/11/13 17:17:40 damien Exp */ 3 4 /*- 5 * Copyright (c) 2004, 2005 6 * Damien Bergamini <damien.bergamini (at) free.fr>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: if_ipw.c,v 1.31.8.1 2008/09/04 08:46:45 skrll Exp $"); 33 34 /*- 35 * Intel(R) PRO/Wireless 2100 MiniPCI driver 36 * http://www.intel.com/network/connectivity/products/wireless/prowireless_mobile.htm 37 */ 38 39 #include "bpfilter.h" 40 41 #include <sys/param.h> 42 #include <sys/sockio.h> 43 #include <sys/sysctl.h> 44 #include <sys/mbuf.h> 45 #include <sys/kernel.h> 46 #include <sys/socket.h> 47 #include <sys/systm.h> 48 #include <sys/malloc.h> 49 #include <sys/conf.h> 50 51 #include <machine/bus.h> 52 #include <machine/endian.h> 53 #include <machine/intr.h> 54 55 #include <dev/pci/pcireg.h> 56 #include <dev/pci/pcivar.h> 57 #include <dev/pci/pcidevs.h> 58 59 #if NBPFILTER > 0 60 #include <net/bpf.h> 61 #endif 62 #include <net/if.h> 63 #include <net/if_arp.h> 64 #include <net/if_dl.h> 65 #include <net/if_ether.h> 66 #include <net/if_media.h> 67 #include <net/if_types.h> 68 69 #include <net80211/ieee80211_var.h> 70 #include <net80211/ieee80211_radiotap.h> 71 72 #include <netinet/in.h> 73 #include <netinet/in_systm.h> 74 #include <netinet/in_var.h> 75 #include <netinet/ip.h> 76 77 #include <dev/firmload.h> 78 79 #include <dev/pci/if_ipwreg.h> 80 #include <dev/pci/if_ipwvar.h> 81 82 #ifdef IPW_DEBUG 83 #define DPRINTF(x) if (ipw_debug > 0) printf x 84 #define DPRINTFN(n, x) if (ipw_debug >= (n)) printf x 85 int ipw_debug = 0; 86 #else 87 #define DPRINTF(x) 88 #define DPRINTFN(n, x) 89 #endif 90 91 static int ipw_dma_alloc(struct ipw_softc *); 92 static void ipw_release(struct ipw_softc *); 93 static int ipw_match(struct device *, struct cfdata *, void *); 94 static void ipw_attach(struct device *, struct device *, void *); 95 static int ipw_detach(struct device *, int); 96 97 static void ipw_shutdown(void *); 98 static int ipw_suspend(struct ipw_softc *); 99 static int ipw_resume(struct ipw_softc *); 100 static void ipw_powerhook(int, void *); 101 102 static int ipw_media_change(struct ifnet *); 103 static void ipw_media_status(struct ifnet *, struct ifmediareq *); 104 static int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 105 static uint16_t ipw_read_prom_word(struct ipw_softc *, uint8_t); 106 static void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 107 static void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 108 static void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 109 struct ipw_soft_bd *, struct ipw_soft_buf *); 110 static void ipw_rx_intr(struct ipw_softc *); 111 static void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 112 static void ipw_tx_intr(struct ipw_softc *); 113 static int ipw_intr(void *); 114 static int ipw_cmd(struct ipw_softc *, uint32_t, void *, uint32_t); 115 static int ipw_tx_start(struct ifnet *, struct mbuf *, 116 struct ieee80211_node *); 117 static void ipw_start(struct ifnet *); 118 static void ipw_watchdog(struct ifnet *); 119 static int ipw_ioctl(struct ifnet *, u_long, caddr_t); 120 static int ipw_get_table1(struct ipw_softc *, uint32_t *); 121 static int ipw_get_radio(struct ipw_softc *, int *); 122 static void ipw_stop_master(struct ipw_softc *); 123 static int ipw_reset(struct ipw_softc *); 124 static int ipw_load_ucode(struct ipw_softc *, u_char *, int); 125 static int ipw_load_firmware(struct ipw_softc *, u_char *, int); 126 static int ipw_cache_firmware(struct ipw_softc *); 127 static void ipw_free_firmware(struct ipw_softc *); 128 static int ipw_config(struct ipw_softc *); 129 static int ipw_init(struct ifnet *); 130 static void ipw_stop(struct ifnet *, int); 131 static uint32_t ipw_read_table1(struct ipw_softc *, uint32_t); 132 static void ipw_write_table1(struct ipw_softc *, uint32_t, uint32_t); 133 static int ipw_read_table2(struct ipw_softc *, uint32_t, void *, uint32_t *); 134 static void ipw_read_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 135 bus_size_t); 136 static void ipw_write_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 137 bus_size_t); 138 139 /* 140 * Supported rates for 802.11b mode (in 500Kbps unit). 141 */ 142 static const struct ieee80211_rateset ipw_rateset_11b = 143 { 4, { 2, 4, 11, 22 } }; 144 145 static inline uint8_t 146 MEM_READ_1(struct ipw_softc *sc, uint32_t addr) 147 { 148 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 149 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); 150 } 151 152 static inline uint32_t 153 MEM_READ_4(struct ipw_softc *sc, uint32_t addr) 154 { 155 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 156 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); 157 } 158 159 CFATTACH_DECL(ipw, sizeof (struct ipw_softc), ipw_match, ipw_attach, 160 ipw_detach, NULL); 161 162 static int 163 ipw_match(struct device *parent, struct cfdata *match, 164 void *aux) 165 { 166 struct pci_attach_args *pa = aux; 167 168 if (PCI_VENDOR (pa->pa_id) == PCI_VENDOR_INTEL && 169 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_PRO_WL_2100) 170 return 1; 171 172 return 0; 173 } 174 175 /* Base Address Register */ 176 #define IPW_PCI_BAR0 0x10 177 178 static void 179 ipw_attach(struct device *parent, struct device *self, void *aux) 180 { 181 struct ipw_softc *sc = (struct ipw_softc *)self; 182 struct ieee80211com *ic = &sc->sc_ic; 183 struct ifnet *ifp = &sc->sc_if; 184 struct pci_attach_args *pa = aux; 185 const char *intrstr; 186 char devinfo[256]; 187 bus_space_tag_t memt; 188 bus_space_handle_t memh; 189 bus_addr_t base; 190 pci_intr_handle_t ih; 191 uint32_t data; 192 uint16_t val; 193 int i, revision, error; 194 195 sc->sc_pct = pa->pa_pc; 196 sc->sc_pcitag = pa->pa_tag; 197 198 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof devinfo); 199 revision = PCI_REVISION(pa->pa_class); 200 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, revision); 201 202 /* enable bus-mastering */ 203 data = pci_conf_read(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG); 204 data |= PCI_COMMAND_MASTER_ENABLE; 205 pci_conf_write(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG, data); 206 207 /* clear device specific PCI configuration register 0x41 */ 208 data = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 209 data &= ~0x0000ff00; 210 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, data); 211 212 /* map the register window */ 213 error = pci_mapreg_map(pa, IPW_PCI_BAR0, PCI_MAPREG_TYPE_MEM | 214 PCI_MAPREG_MEM_TYPE_32BIT, 0, &memt, &memh, &base, &sc->sc_sz); 215 if (error != 0) { 216 aprint_error("%s: could not map memory space\n", 217 sc->sc_dev.dv_xname); 218 return; 219 } 220 221 sc->sc_st = memt; 222 sc->sc_sh = memh; 223 sc->sc_dmat = pa->pa_dmat; 224 strlcpy(sc->sc_fwname, "ipw2100-1.2.fw", sizeof(sc->sc_fwname)); 225 226 /* disable interrupts */ 227 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 228 229 if (pci_intr_map(pa, &ih) != 0) { 230 aprint_error("%s: could not map interrupt\n", 231 sc->sc_dev.dv_xname); 232 return; 233 } 234 235 intrstr = pci_intr_string(sc->sc_pct, ih); 236 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, ipw_intr, sc); 237 if (sc->sc_ih == NULL) { 238 aprint_error("%s: could not establish interrupt", 239 sc->sc_dev.dv_xname); 240 if (intrstr != NULL) 241 aprint_error(" at %s", intrstr); 242 aprint_error("\n"); 243 return; 244 } 245 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 246 247 if (ipw_reset(sc) != 0) { 248 aprint_error("%s: could not reset adapter\n", 249 sc->sc_dev.dv_xname); 250 goto fail; 251 } 252 253 if (ipw_dma_alloc(sc) != 0) { 254 aprint_error("%s: could not allocate DMA resources\n", 255 sc->sc_dev.dv_xname); 256 goto fail; 257 } 258 259 ifp->if_softc = sc; 260 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 261 ifp->if_init = ipw_init; 262 ifp->if_stop = ipw_stop; 263 ifp->if_ioctl = ipw_ioctl; 264 ifp->if_start = ipw_start; 265 ifp->if_watchdog = ipw_watchdog; 266 IFQ_SET_READY(&ifp->if_snd); 267 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 268 269 ic->ic_ifp = ifp; 270 ic->ic_phytype = IEEE80211_T_DS; 271 ic->ic_opmode = IEEE80211_M_STA; 272 ic->ic_state = IEEE80211_S_INIT; 273 274 /* set device capabilities */ 275 ic->ic_caps = 276 IEEE80211_C_SHPREAMBLE /* short preamble supported */ 277 | IEEE80211_C_TXPMGT /* tx power management */ 278 | IEEE80211_C_IBSS /* ibss mode */ 279 | IEEE80211_C_MONITOR /* monitor mode */ 280 ; 281 282 /* read MAC address from EEPROM */ 283 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0); 284 ic->ic_myaddr[0] = val >> 8; 285 ic->ic_myaddr[1] = val & 0xff; 286 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 1); 287 ic->ic_myaddr[2] = val >> 8; 288 ic->ic_myaddr[3] = val & 0xff; 289 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 2); 290 ic->ic_myaddr[4] = val >> 8; 291 ic->ic_myaddr[5] = val & 0xff; 292 293 /* set supported .11b rates */ 294 ic->ic_sup_rates[IEEE80211_MODE_11B] = ipw_rateset_11b; 295 296 /* set supported .11b channels (read from EEPROM) */ 297 if ((val = ipw_read_prom_word(sc, IPW_EEPROM_CHANNEL_LIST)) == 0) 298 val = 0x7ff; /* default to channels 1-11 */ 299 val <<= 1; 300 for (i = 1; i < 16; i++) { 301 if (val & (1 << i)) { 302 ic->ic_channels[i].ic_freq = 303 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 304 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 305 } 306 } 307 308 /* check support for radio transmitter switch in EEPROM */ 309 if (!(ipw_read_prom_word(sc, IPW_EEPROM_RADIO) & 8)) 310 sc->flags |= IPW_FLAG_HAS_RADIO_SWITCH; 311 312 aprint_normal("%s: 802.11 address %s\n", sc->sc_dev.dv_xname, 313 ether_sprintf(ic->ic_myaddr)); 314 315 if_attach(ifp); 316 ieee80211_ifattach(ic); 317 318 /* override state transition machine */ 319 sc->sc_newstate = ic->ic_newstate; 320 ic->ic_newstate = ipw_newstate; 321 322 ieee80211_media_init(ic, ipw_media_change, ipw_media_status); 323 324 #if NBPFILTER > 0 325 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 326 sizeof (struct ieee80211_frame) + 64, &sc->sc_drvbpf); 327 328 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 329 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 330 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 331 332 sc->sc_txtap_len = sizeof sc->sc_txtapu; 333 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 334 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 335 #endif 336 337 /* 338 * Add a few sysctl knobs. 339 * XXX: Not yet 340 */ 341 sc->dwelltime = 100; 342 343 /* 344 * Make sure the interface is shutdown during reboot. 345 */ 346 sc->sc_sdhook = shutdownhook_establish(ipw_shutdown, sc); 347 if (sc->sc_sdhook == NULL) 348 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 349 sc->sc_dev.dv_xname); 350 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 351 ipw_powerhook, sc); 352 if (sc->sc_powerhook == NULL) 353 printf("%s: WARNING: unable to establish power hook\n", 354 sc->sc_dev.dv_xname); 355 356 ieee80211_announce(ic); 357 358 return; 359 360 fail: ipw_detach(self, 0); 361 } 362 363 static int 364 ipw_detach(struct device* self, int flags) 365 { 366 struct ipw_softc *sc = (struct ipw_softc *)self; 367 struct ifnet *ifp = &sc->sc_if; 368 369 if (ifp->if_softc) { 370 ipw_stop(ifp, 1); 371 ipw_free_firmware(sc); 372 373 #if NBPFILTER > 0 374 bpfdetach(ifp); 375 #endif 376 ieee80211_ifdetach(&sc->sc_ic); 377 if_detach(ifp); 378 379 ipw_release(sc); 380 } 381 382 if (sc->sc_ih != NULL) { 383 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 384 sc->sc_ih = NULL; 385 } 386 387 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 388 389 return 0; 390 } 391 392 static int 393 ipw_dma_alloc(struct ipw_softc *sc) 394 { 395 struct ipw_soft_bd *sbd; 396 struct ipw_soft_hdr *shdr; 397 struct ipw_soft_buf *sbuf; 398 int error, i, nsegs; 399 400 /* 401 * Allocate and map tx ring. 402 */ 403 error = bus_dmamap_create(sc->sc_dmat, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, 404 BUS_DMA_NOWAIT, &sc->tbd_map); 405 if (error != 0) { 406 aprint_error("%s: could not create tbd dma map\n", 407 sc->sc_dev.dv_xname); 408 goto fail; 409 } 410 411 error = bus_dmamem_alloc(sc->sc_dmat, IPW_TBD_SZ, PAGE_SIZE, 0, 412 &sc->tbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 413 if (error != 0) { 414 aprint_error("%s: could not allocate tbd dma memory\n", 415 sc->sc_dev.dv_xname); 416 goto fail; 417 } 418 419 error = bus_dmamem_map(sc->sc_dmat, &sc->tbd_seg, nsegs, IPW_TBD_SZ, 420 (caddr_t *)&sc->tbd_list, BUS_DMA_NOWAIT); 421 if (error != 0) { 422 aprint_error("%s: could not map tbd dma memory\n", 423 sc->sc_dev.dv_xname); 424 goto fail; 425 } 426 427 error = bus_dmamap_load(sc->sc_dmat, sc->tbd_map, sc->tbd_list, 428 IPW_TBD_SZ, NULL, BUS_DMA_NOWAIT); 429 if (error != 0) { 430 aprint_error("%s: could not load tbd dma memory\n", 431 sc->sc_dev.dv_xname); 432 goto fail; 433 } 434 435 (void)memset(sc->tbd_list, 0, IPW_TBD_SZ); 436 437 /* 438 * Allocate and map rx ring. 439 */ 440 error = bus_dmamap_create(sc->sc_dmat, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, 441 BUS_DMA_NOWAIT, &sc->rbd_map); 442 if (error != 0) { 443 aprint_error("%s: could not create rbd dma map\n", 444 sc->sc_dev.dv_xname); 445 goto fail; 446 } 447 448 error = bus_dmamem_alloc(sc->sc_dmat, IPW_RBD_SZ, PAGE_SIZE, 0, 449 &sc->rbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 450 if (error != 0) { 451 aprint_error("%s: could not allocate rbd dma memory\n", 452 sc->sc_dev.dv_xname); 453 goto fail; 454 } 455 456 error = bus_dmamem_map(sc->sc_dmat, &sc->rbd_seg, nsegs, IPW_RBD_SZ, 457 (caddr_t *)&sc->rbd_list, BUS_DMA_NOWAIT); 458 if (error != 0) { 459 aprint_error("%s: could not map rbd dma memory\n", 460 sc->sc_dev.dv_xname); 461 goto fail; 462 } 463 464 error = bus_dmamap_load(sc->sc_dmat, sc->rbd_map, sc->rbd_list, 465 IPW_RBD_SZ, NULL, BUS_DMA_NOWAIT); 466 if (error != 0) { 467 aprint_error("%s: could not load rbd dma memory\n", 468 sc->sc_dev.dv_xname); 469 goto fail; 470 } 471 472 (void)memset(sc->rbd_list, 0, IPW_RBD_SZ); 473 474 /* 475 * Allocate and map status ring. 476 */ 477 error = bus_dmamap_create(sc->sc_dmat, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 478 0, BUS_DMA_NOWAIT, &sc->status_map); 479 if (error != 0) { 480 aprint_error("%s: could not create status dma map\n", 481 sc->sc_dev.dv_xname); 482 goto fail; 483 } 484 485 error = bus_dmamem_alloc(sc->sc_dmat, IPW_STATUS_SZ, PAGE_SIZE, 0, 486 &sc->status_seg, 1, &nsegs, BUS_DMA_NOWAIT); 487 if (error != 0) { 488 aprint_error("%s: could not allocate status dma memory\n", 489 sc->sc_dev.dv_xname); 490 goto fail; 491 } 492 493 error = bus_dmamem_map(sc->sc_dmat, &sc->status_seg, nsegs, 494 IPW_STATUS_SZ, (caddr_t *)&sc->status_list, BUS_DMA_NOWAIT); 495 if (error != 0) { 496 aprint_error("%s: could not map status dma memory\n", 497 sc->sc_dev.dv_xname); 498 goto fail; 499 } 500 501 error = bus_dmamap_load(sc->sc_dmat, sc->status_map, sc->status_list, 502 IPW_STATUS_SZ, NULL, BUS_DMA_NOWAIT); 503 if (error != 0) { 504 aprint_error("%s: could not load status dma memory\n", 505 sc->sc_dev.dv_xname); 506 goto fail; 507 } 508 509 (void)memset(sc->status_list, 0, IPW_STATUS_SZ); 510 511 /* 512 * Allocate command DMA map. 513 */ 514 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_cmd), 515 1, sizeof (struct ipw_cmd), 0, BUS_DMA_NOWAIT, &sc->cmd_map); 516 if (error != 0) { 517 aprint_error("%s: could not create cmd dma map\n", 518 sc->sc_dev.dv_xname); 519 goto fail; 520 } 521 522 error = bus_dmamem_alloc(sc->sc_dmat, sizeof (struct ipw_cmd), 523 PAGE_SIZE, 0, &sc->cmd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 524 if (error != 0) { 525 aprint_error("%s: could not allocate cmd dma memory\n", 526 sc->sc_dev.dv_xname); 527 goto fail; 528 } 529 530 error = bus_dmamem_map(sc->sc_dmat, &sc->cmd_seg, nsegs, 531 sizeof (struct ipw_cmd), (caddr_t *)&sc->cmd, BUS_DMA_NOWAIT); 532 if (error != 0) { 533 aprint_error("%s: could not map cmd dma memory\n", 534 sc->sc_dev.dv_xname); 535 goto fail; 536 } 537 538 error = bus_dmamap_load(sc->sc_dmat, sc->cmd_map, &sc->cmd, 539 sizeof (struct ipw_cmd), NULL, BUS_DMA_NOWAIT); 540 if (error != 0) { 541 aprint_error("%s: could not map cmd dma memory\n", 542 sc->sc_dev.dv_xname); 543 return error; 544 } 545 546 /* 547 * Allocate and map hdr list. 548 */ 549 550 error = bus_dmamap_create(sc->sc_dmat, 551 IPW_NDATA * sizeof(struct ipw_hdr), 1, 552 sizeof(struct ipw_hdr), 0, BUS_DMA_NOWAIT, 553 &sc->hdr_map); 554 if (error != 0) { 555 aprint_error("%s: could not create hdr dma map\n", 556 sc->sc_dev.dv_xname); 557 goto fail; 558 } 559 560 error = bus_dmamem_alloc(sc->sc_dmat, 561 IPW_NDATA * sizeof(struct ipw_hdr), PAGE_SIZE, 0, &sc->hdr_seg, 562 1, &nsegs, BUS_DMA_NOWAIT); 563 if (error != 0) { 564 aprint_error("%s: could not allocate hdr memory\n", 565 sc->sc_dev.dv_xname); 566 goto fail; 567 } 568 569 error = bus_dmamem_map(sc->sc_dmat, &sc->hdr_seg, nsegs, 570 IPW_NDATA * sizeof(struct ipw_hdr), (caddr_t *)&sc->hdr_list, 571 BUS_DMA_NOWAIT); 572 if (error != 0) { 573 aprint_error("%s: could not map hdr memory\n", 574 sc->sc_dev.dv_xname); 575 goto fail; 576 } 577 578 error = bus_dmamap_load(sc->sc_dmat, sc->hdr_map, sc->hdr_list, 579 IPW_NDATA * sizeof(struct ipw_hdr), NULL, BUS_DMA_NOWAIT); 580 if (error != 0) { 581 aprint_error("%s: could not load hdr memory\n", 582 sc->sc_dev.dv_xname); 583 goto fail; 584 } 585 586 (void)memset(sc->hdr_list, 0, IPW_HDR_SZ); 587 588 /* 589 * Create DMA hdrs tailq. 590 */ 591 TAILQ_INIT(&sc->sc_free_shdr); 592 for (i = 0; i < IPW_NDATA; i++) { 593 shdr = &sc->shdr_list[i]; 594 shdr->hdr = sc->hdr_list + i; 595 shdr->offset = sizeof(struct ipw_hdr) * i; 596 shdr->addr = sc->hdr_map->dm_segs[0].ds_addr + shdr->offset; 597 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 598 } 599 600 /* 601 * Allocate tx buffers DMA maps. 602 */ 603 TAILQ_INIT(&sc->sc_free_sbuf); 604 for (i = 0; i < IPW_NDATA; i++) { 605 sbuf = &sc->tx_sbuf_list[i]; 606 607 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 608 IPW_MAX_NSEG, MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 609 if (error != 0) { 610 aprint_error("%s: could not create txbuf dma map\n", 611 sc->sc_dev.dv_xname); 612 goto fail; 613 } 614 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 615 } 616 617 /* 618 * Initialize tx ring. 619 */ 620 for (i = 0; i < IPW_NTBD; i++) { 621 sbd = &sc->stbd_list[i]; 622 sbd->bd = &sc->tbd_list[i]; 623 sbd->type = IPW_SBD_TYPE_NOASSOC; 624 } 625 626 /* 627 * Pre-allocate rx buffers and DMA maps 628 */ 629 for (i = 0; i < IPW_NRBD; i++) { 630 sbd = &sc->srbd_list[i]; 631 sbuf = &sc->rx_sbuf_list[i]; 632 sbd->bd = &sc->rbd_list[i]; 633 634 MGETHDR(sbuf->m, M_DONTWAIT, MT_DATA); 635 if (sbuf->m == NULL) { 636 aprint_error("%s: could not allocate rx mbuf\n", 637 sc->sc_dev.dv_xname); 638 error = ENOMEM; 639 goto fail; 640 } 641 642 MCLGET(sbuf->m, M_DONTWAIT); 643 if (!(sbuf->m->m_flags & M_EXT)) { 644 m_freem(sbuf->m); 645 aprint_error("%s: could not allocate rx mbuf cluster\n", 646 sc->sc_dev.dv_xname); 647 error = ENOMEM; 648 goto fail; 649 } 650 651 sbuf->m->m_pkthdr.len = sbuf->m->m_len = sbuf->m->m_ext.ext_size; 652 653 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 654 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sbuf->map); 655 if (error != 0) { 656 aprint_error("%s: could not create rxbuf dma map\n", 657 sc->sc_dev.dv_xname); 658 m_freem(sbuf->m); 659 goto fail; 660 } 661 662 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, 663 sbuf->m, BUS_DMA_READ | BUS_DMA_NOWAIT); 664 if (error != 0) { 665 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 666 m_freem(sbuf->m); 667 aprint_error("%s: could not map rxbuf dma memory\n", 668 sc->sc_dev.dv_xname); 669 goto fail; 670 } 671 672 sbd->type = IPW_SBD_TYPE_DATA; 673 sbd->priv = sbuf; 674 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 675 sbd->bd->len = htole32(MCLBYTES); 676 677 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, 678 sbuf->map->dm_mapsize, BUS_DMASYNC_PREREAD); 679 680 } 681 682 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 0, IPW_RBD_SZ, 683 BUS_DMASYNC_PREREAD); 684 685 return 0; 686 687 fail: ipw_release(sc); 688 return error; 689 } 690 691 static void 692 ipw_release(struct ipw_softc *sc) 693 { 694 struct ipw_soft_buf *sbuf; 695 int i; 696 697 if (sc->tbd_map != NULL) { 698 if (sc->tbd_list != NULL) { 699 bus_dmamap_unload(sc->sc_dmat, sc->tbd_map); 700 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->tbd_list, 701 IPW_TBD_SZ); 702 bus_dmamem_free(sc->sc_dmat, &sc->tbd_seg, 1); 703 } 704 bus_dmamap_destroy(sc->sc_dmat, sc->tbd_map); 705 } 706 707 if (sc->rbd_map != NULL) { 708 if (sc->rbd_list != NULL) { 709 bus_dmamap_unload(sc->sc_dmat, sc->rbd_map); 710 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->rbd_list, 711 IPW_RBD_SZ); 712 bus_dmamem_free(sc->sc_dmat, &sc->rbd_seg, 1); 713 } 714 bus_dmamap_destroy(sc->sc_dmat, sc->rbd_map); 715 } 716 717 if (sc->status_map != NULL) { 718 if (sc->status_list != NULL) { 719 bus_dmamap_unload(sc->sc_dmat, sc->status_map); 720 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->status_list, 721 IPW_RBD_SZ); 722 bus_dmamem_free(sc->sc_dmat, &sc->status_seg, 1); 723 } 724 bus_dmamap_destroy(sc->sc_dmat, sc->status_map); 725 } 726 727 for (i = 0; i < IPW_NTBD; i++) 728 ipw_release_sbd(sc, &sc->stbd_list[i]); 729 730 if (sc->cmd_map != NULL) 731 bus_dmamap_destroy(sc->sc_dmat, sc->cmd_map); 732 733 if (sc->hdr_list != NULL) { 734 bus_dmamap_unload(sc->sc_dmat, sc->hdr_map); 735 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->hdr_list, 736 IPW_NDATA * sizeof(struct ipw_hdr)); 737 } 738 if (sc->hdr_map != NULL) { 739 bus_dmamem_free(sc->sc_dmat, &sc->hdr_seg, 1); 740 bus_dmamap_destroy(sc->sc_dmat, sc->hdr_map); 741 } 742 743 for (i = 0; i < IPW_NDATA; i++) 744 bus_dmamap_destroy(sc->sc_dmat, sc->tx_sbuf_list[i].map); 745 746 for (i = 0; i < IPW_NRBD; i++) { 747 sbuf = &sc->rx_sbuf_list[i]; 748 if (sbuf->map != NULL) { 749 if (sbuf->m != NULL) { 750 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 751 m_freem(sbuf->m); 752 } 753 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 754 } 755 } 756 757 } 758 759 static void 760 ipw_shutdown(void *arg) 761 { 762 struct ipw_softc *sc = (struct ipw_softc *)arg; 763 struct ifnet *ifp = sc->sc_ic.ic_ifp; 764 765 ipw_stop(ifp, 1); 766 } 767 768 769 static int 770 ipw_suspend(struct ipw_softc *sc) 771 { 772 struct ifnet *ifp = sc->sc_ic.ic_ifp; 773 774 ipw_stop(ifp, 1); 775 776 return 0; 777 } 778 779 static int 780 ipw_resume(struct ipw_softc *sc) 781 { 782 struct ifnet *ifp = sc->sc_ic.ic_ifp; 783 pcireg_t data; 784 785 /* clear device specific PCI configuration register 0x41 */ 786 data = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 787 data &= ~0x0000ff00; 788 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, data); 789 790 if (ifp->if_flags & IFF_UP) { 791 ipw_init(ifp); 792 if (ifp->if_flags & IFF_RUNNING) 793 ipw_start(ifp); 794 } 795 796 return 0; 797 } 798 799 static void 800 ipw_powerhook(int why, void *arg) 801 { 802 struct ipw_softc *sc = arg; 803 int s; 804 805 s = splnet(); 806 switch (why) { 807 case PWR_SUSPEND: 808 case PWR_STANDBY: 809 ipw_suspend(sc); 810 break; 811 case PWR_RESUME: 812 ipw_resume(sc); 813 break; 814 case PWR_SOFTSUSPEND: 815 case PWR_SOFTSTANDBY: 816 case PWR_SOFTRESUME: 817 break; 818 } 819 splx(s); 820 } 821 822 static int 823 ipw_media_change(struct ifnet *ifp) 824 { 825 int error; 826 827 error = ieee80211_media_change(ifp); 828 if (error != ENETRESET) 829 return error; 830 831 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 832 ipw_init(ifp); 833 834 return 0; 835 } 836 837 /* 838 * The firmware automatically adapts the transmit speed. We report the current 839 * transmit speed here. 840 */ 841 static void 842 ipw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 843 { 844 #define N(a) (sizeof (a) / sizeof (a[0])) 845 struct ipw_softc *sc = ifp->if_softc; 846 struct ieee80211com *ic = &sc->sc_ic; 847 static const struct { 848 uint32_t val; 849 int rate; 850 } rates[] = { 851 { IPW_RATE_DS1, 2 }, 852 { IPW_RATE_DS2, 4 }, 853 { IPW_RATE_DS5, 11 }, 854 { IPW_RATE_DS11, 22 }, 855 }; 856 uint32_t val; 857 int rate, i; 858 859 imr->ifm_status = IFM_AVALID; 860 imr->ifm_active = IFM_IEEE80211; 861 if (ic->ic_state == IEEE80211_S_RUN) 862 imr->ifm_status |= IFM_ACTIVE; 863 864 /* read current transmission rate from adapter */ 865 val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE) & 0xf; 866 867 /* convert ipw rate to 802.11 rate */ 868 for (i = 0; i < N(rates) && rates[i].val != val; i++); 869 rate = (i < N(rates)) ? rates[i].rate : 0; 870 871 imr->ifm_active |= IFM_IEEE80211_11B; 872 imr->ifm_active |= ieee80211_rate2media(ic, rate, IEEE80211_MODE_11B); 873 switch (ic->ic_opmode) { 874 case IEEE80211_M_STA: 875 break; 876 877 case IEEE80211_M_IBSS: 878 imr->ifm_active |= IFM_IEEE80211_ADHOC; 879 break; 880 881 case IEEE80211_M_MONITOR: 882 imr->ifm_active |= IFM_IEEE80211_MONITOR; 883 break; 884 885 case IEEE80211_M_AHDEMO: 886 case IEEE80211_M_HOSTAP: 887 /* should not get there */ 888 break; 889 } 890 #undef N 891 } 892 893 static int 894 ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, 895 int arg) 896 { 897 struct ifnet *ifp = ic->ic_ifp; 898 struct ipw_softc *sc = ifp->if_softc; 899 struct ieee80211_node *ni; 900 uint8_t macaddr[IEEE80211_ADDR_LEN]; 901 uint32_t len; 902 903 switch (nstate) { 904 case IEEE80211_S_RUN: 905 DELAY(200); /* firmware needs a short delay here */ 906 907 len = IEEE80211_ADDR_LEN; 908 ipw_read_table2(sc, IPW_INFO_CURRENT_BSSID, macaddr, &len); 909 910 ni = ieee80211_find_node(&ic->ic_scan, macaddr); 911 if (ni == NULL) 912 break; 913 914 ieee80211_ref_node(ni); 915 ieee80211_sta_join(ic, ni); 916 ieee80211_node_authorize(ni); 917 918 if (ic->ic_opmode == IEEE80211_M_STA) 919 ieee80211_notify_node_join(ic, ni, 1); 920 break; 921 922 case IEEE80211_S_INIT: 923 case IEEE80211_S_SCAN: 924 case IEEE80211_S_AUTH: 925 case IEEE80211_S_ASSOC: 926 break; 927 } 928 929 ic->ic_state = nstate; 930 return 0; 931 } 932 933 /* 934 * Read 16 bits at address 'addr' from the serial EEPROM. 935 */ 936 static uint16_t 937 ipw_read_prom_word(struct ipw_softc *sc, uint8_t addr) 938 { 939 uint32_t tmp; 940 uint16_t val; 941 int n; 942 943 /* clock C once before the first command */ 944 IPW_EEPROM_CTL(sc, 0); 945 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 946 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 947 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 948 949 /* write start bit (1) */ 950 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 951 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 952 953 /* write READ opcode (10) */ 954 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 955 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 956 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 957 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 958 959 /* write address A7-A0 */ 960 for (n = 7; n >= 0; n--) { 961 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 962 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D)); 963 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 964 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D) | IPW_EEPROM_C); 965 } 966 967 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 968 969 /* read data Q15-Q0 */ 970 val = 0; 971 for (n = 15; n >= 0; n--) { 972 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 973 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 974 tmp = MEM_READ_4(sc, IPW_MEM_EEPROM_CTL); 975 val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n; 976 } 977 978 IPW_EEPROM_CTL(sc, 0); 979 980 /* clear Chip Select and clock C */ 981 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 982 IPW_EEPROM_CTL(sc, 0); 983 IPW_EEPROM_CTL(sc, IPW_EEPROM_C); 984 985 return le16toh(val); 986 } 987 988 static void 989 ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 990 { 991 struct ipw_cmd *cmd; 992 993 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof (struct ipw_cmd), 994 BUS_DMASYNC_POSTREAD); 995 996 cmd = mtod(sbuf->m, struct ipw_cmd *); 997 998 DPRINTFN(2, ("cmd ack'ed (%u, %u, %u, %u, %u)\n", le32toh(cmd->type), 999 le32toh(cmd->subtype), le32toh(cmd->seq), le32toh(cmd->len), 1000 le32toh(cmd->status))); 1001 1002 wakeup(&sc->cmd); 1003 } 1004 1005 static void 1006 ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 1007 { 1008 struct ieee80211com *ic = &sc->sc_ic; 1009 struct ifnet *ifp = sc->sc_ic.ic_ifp; 1010 uint32_t state; 1011 1012 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof state, 1013 BUS_DMASYNC_POSTREAD); 1014 1015 state = le32toh(*mtod(sbuf->m, uint32_t *)); 1016 1017 DPRINTFN(2, ("entering state %u\n", state)); 1018 1019 switch (state) { 1020 case IPW_STATE_ASSOCIATED: 1021 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1022 break; 1023 1024 case IPW_STATE_SCANNING: 1025 /* don't leave run state on background scan */ 1026 if (ic->ic_state != IEEE80211_S_RUN) 1027 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1028 1029 ic->ic_flags |= IEEE80211_F_SCAN; 1030 break; 1031 1032 case IPW_STATE_SCAN_COMPLETE: 1033 ieee80211_notify_scan_done(ic); 1034 ic->ic_flags &= ~IEEE80211_F_SCAN; 1035 break; 1036 1037 case IPW_STATE_ASSOCIATION_LOST: 1038 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1039 break; 1040 1041 case IPW_STATE_RADIO_DISABLED: 1042 ic->ic_ifp->if_flags &= ~IFF_UP; 1043 ipw_stop(ifp, 1); 1044 break; 1045 } 1046 } 1047 1048 /* 1049 * XXX: Hack to set the current channel to the value advertised in beacons or 1050 * probe responses. Only used during AP detection. 1051 */ 1052 static void 1053 ipw_fix_channel(struct ieee80211com *ic, struct mbuf *m) 1054 { 1055 struct ieee80211_frame *wh; 1056 uint8_t subtype; 1057 uint8_t *frm, *efrm; 1058 1059 wh = mtod(m, struct ieee80211_frame *); 1060 1061 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_MGT) 1062 return; 1063 1064 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 1065 1066 if (subtype != IEEE80211_FC0_SUBTYPE_BEACON && 1067 subtype != IEEE80211_FC0_SUBTYPE_PROBE_RESP) 1068 return; 1069 1070 frm = (uint8_t *)(wh + 1); 1071 efrm = mtod(m, uint8_t *) + m->m_len; 1072 1073 frm += 12; /* skip tstamp, bintval and capinfo fields */ 1074 while (frm < efrm) { 1075 if (*frm == IEEE80211_ELEMID_DSPARMS) 1076 #if IEEE80211_CHAN_MAX < 255 1077 if (frm[2] <= IEEE80211_CHAN_MAX) 1078 #endif 1079 ic->ic_curchan = &ic->ic_channels[frm[2]]; 1080 1081 frm += frm[1] + 2; 1082 } 1083 } 1084 1085 static void 1086 ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 1087 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 1088 { 1089 struct ieee80211com *ic = &sc->sc_ic; 1090 struct ifnet *ifp = &sc->sc_if; 1091 struct mbuf *mnew, *m; 1092 struct ieee80211_frame *wh; 1093 struct ieee80211_node *ni; 1094 int error; 1095 1096 DPRINTFN(5, ("received frame len=%u, rssi=%u\n", le32toh(status->len), 1097 status->rssi)); 1098 1099 if (le32toh(status->len) < sizeof (struct ieee80211_frame_min) || 1100 le32toh(status->len) > MCLBYTES) 1101 return; 1102 1103 /* 1104 * Try to allocate a new mbuf for this ring element and load it before 1105 * processing the current mbuf. If the ring element cannot be loaded, 1106 * drop the received packet and reuse the old mbuf. In the unlikely 1107 * case that the old mbuf can't be reloaded either, explicitly panic. 1108 */ 1109 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1110 if (mnew == NULL) { 1111 aprint_error("%s: could not allocate rx mbuf\n", 1112 sc->sc_dev.dv_xname); 1113 ifp->if_ierrors++; 1114 return; 1115 } 1116 1117 MCLGET(mnew, M_DONTWAIT); 1118 if (!(mnew->m_flags & M_EXT)) { 1119 aprint_error("%s: could not allocate rx mbuf cluster\n", 1120 sc->sc_dev.dv_xname); 1121 m_freem(mnew); 1122 ifp->if_ierrors++; 1123 return; 1124 } 1125 1126 mnew->m_pkthdr.len = mnew->m_len = mnew->m_ext.ext_size; 1127 1128 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, le32toh(status->len), 1129 BUS_DMASYNC_POSTREAD); 1130 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1131 1132 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, mnew, 1133 BUS_DMA_READ | BUS_DMA_NOWAIT); 1134 if (error != 0) { 1135 aprint_error("%s: could not load rx buf DMA map\n", 1136 sc->sc_dev.dv_xname); 1137 m_freem(mnew); 1138 1139 /* try to reload the old mbuf */ 1140 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, 1141 sbuf->m, BUS_DMA_READ | BUS_DMA_NOWAIT); 1142 if (error != 0) { 1143 /* very unlikely that it will fail... */ 1144 panic("%s: unable to remap rx buf", 1145 sc->sc_dev.dv_xname); 1146 } 1147 ifp->if_ierrors++; 1148 return; 1149 } 1150 1151 /* 1152 * New mbuf successfully loaded, update Rx ring and continue 1153 * processing. 1154 */ 1155 m = sbuf->m; 1156 sbuf->m = mnew; 1157 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 1158 1159 /* finalize mbuf */ 1160 m->m_pkthdr.rcvif = ifp; 1161 m->m_pkthdr.len = m->m_len = le32toh(status->len); 1162 1163 #if NBPFILTER > 0 1164 if (sc->sc_drvbpf != NULL) { 1165 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 1166 1167 tap->wr_flags = 0; 1168 tap->wr_antsignal = status->rssi; 1169 if (ic->ic_bss->ni_chan != IEEE80211_CHAN_ANYC) { 1170 tap->wr_chan_freq = 1171 htole16(ic->ic_bss->ni_chan->ic_freq); 1172 tap->wr_chan_flags = 1173 htole16(ic->ic_bss->ni_chan->ic_flags); 1174 } else 1175 tap->wr_chan_freq = tap->wr_chan_flags = 0; 1176 1177 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 1178 } 1179 #endif 1180 1181 if (ic->ic_state == IEEE80211_S_SCAN) 1182 ipw_fix_channel(ic, m); 1183 1184 wh = mtod(m, struct ieee80211_frame *); 1185 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 1186 1187 /* send the frame to the 802.11 layer */ 1188 ieee80211_input(ic, m, ni, status->rssi, 0); 1189 1190 /* node is no longer needed */ 1191 ieee80211_free_node(ni); 1192 1193 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, 1194 sbuf->map->dm_mapsize, BUS_DMASYNC_PREREAD); 1195 } 1196 1197 static void 1198 ipw_rx_intr(struct ipw_softc *sc) 1199 { 1200 struct ipw_status *status; 1201 struct ipw_soft_bd *sbd; 1202 struct ipw_soft_buf *sbuf; 1203 uint32_t r, i; 1204 1205 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1206 return; 1207 1208 r = CSR_READ_4(sc, IPW_CSR_RX_READ); 1209 1210 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 1211 1212 /* firmware was killed, stop processing received frames */ 1213 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1214 return; 1215 1216 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 1217 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1218 BUS_DMASYNC_POSTREAD); 1219 1220 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 1221 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 1222 BUS_DMASYNC_POSTREAD); 1223 1224 status = &sc->status_list[i]; 1225 sbd = &sc->srbd_list[i]; 1226 sbuf = sbd->priv; 1227 1228 switch (le16toh(status->code) & 0xf) { 1229 case IPW_STATUS_CODE_COMMAND: 1230 ipw_command_intr(sc, sbuf); 1231 break; 1232 1233 case IPW_STATUS_CODE_NEWSTATE: 1234 ipw_newstate_intr(sc, sbuf); 1235 break; 1236 1237 case IPW_STATUS_CODE_DATA_802_3: 1238 case IPW_STATUS_CODE_DATA_802_11: 1239 ipw_data_intr(sc, status, sbd, sbuf); 1240 break; 1241 1242 case IPW_STATUS_CODE_NOTIFICATION: 1243 DPRINTFN(2, ("received notification\n")); 1244 break; 1245 1246 default: 1247 aprint_error("%s: unknown status code %u\n", 1248 sc->sc_dev.dv_xname, le16toh(status->code)); 1249 } 1250 1251 sbd->bd->flags = 0; 1252 1253 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 1254 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1255 BUS_DMASYNC_PREREAD); 1256 1257 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 1258 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 1259 BUS_DMASYNC_PREREAD); 1260 } 1261 1262 /* Tell the firmware what we have processed */ 1263 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 1264 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 1265 } 1266 1267 static void 1268 ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 1269 { 1270 struct ieee80211com *ic; 1271 struct ipw_soft_hdr *shdr; 1272 struct ipw_soft_buf *sbuf; 1273 1274 switch (sbd->type) { 1275 case IPW_SBD_TYPE_COMMAND: 1276 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 1277 0, sizeof(struct ipw_cmd), BUS_DMASYNC_POSTWRITE); 1278 /* bus_dmamap_unload(sc->sc_dmat, sc->cmd_map); */ 1279 break; 1280 1281 case IPW_SBD_TYPE_HEADER: 1282 shdr = sbd->priv; 1283 bus_dmamap_sync(sc->sc_dmat, sc->hdr_map, 1284 shdr->offset, sizeof(struct ipw_hdr), BUS_DMASYNC_POSTWRITE); 1285 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 1286 break; 1287 1288 case IPW_SBD_TYPE_DATA: 1289 ic = &sc->sc_ic; 1290 sbuf = sbd->priv; 1291 1292 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 1293 0, MCLBYTES, BUS_DMASYNC_POSTWRITE); 1294 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1295 m_freem(sbuf->m); 1296 if (sbuf->ni != NULL) 1297 ieee80211_free_node(sbuf->ni); 1298 /* kill watchdog timer */ 1299 sc->sc_tx_timer = 0; 1300 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 1301 break; 1302 } 1303 sbd->type = IPW_SBD_TYPE_NOASSOC; 1304 } 1305 1306 static void 1307 ipw_tx_intr(struct ipw_softc *sc) 1308 { 1309 struct ifnet *ifp = &sc->sc_if; 1310 struct ipw_soft_bd *sbd; 1311 uint32_t r, i; 1312 1313 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1314 return; 1315 1316 r = CSR_READ_4(sc, IPW_CSR_TX_READ); 1317 1318 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) { 1319 sbd = &sc->stbd_list[i]; 1320 1321 if (sbd->type == IPW_SBD_TYPE_DATA) 1322 ifp->if_opackets++; 1323 1324 ipw_release_sbd(sc, sbd); 1325 sc->txfree++; 1326 } 1327 1328 /* remember what the firmware has processed */ 1329 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 1330 1331 /* Call start() since some buffer descriptors have been released */ 1332 ifp->if_flags &= ~IFF_OACTIVE; 1333 (*ifp->if_start)(ifp); 1334 } 1335 1336 static int 1337 ipw_intr(void *arg) 1338 { 1339 struct ipw_softc *sc = arg; 1340 uint32_t r; 1341 1342 r = CSR_READ_4(sc, IPW_CSR_INTR); 1343 if (r == 0 || r == 0xffffffff) 1344 return 0; 1345 1346 /* Disable interrupts */ 1347 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1348 1349 if (r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR)) { 1350 aprint_error("%s: fatal error\n", 1351 sc->sc_dev.dv_xname); 1352 sc->sc_ic.ic_ifp->if_flags &= ~IFF_UP; 1353 ipw_stop(&sc->sc_if, 1); 1354 } 1355 1356 if (r & IPW_INTR_FW_INIT_DONE) { 1357 if (!(r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR))) 1358 wakeup(sc); 1359 } 1360 1361 if (r & IPW_INTR_RX_TRANSFER) 1362 ipw_rx_intr(sc); 1363 1364 if (r & IPW_INTR_TX_TRANSFER) 1365 ipw_tx_intr(sc); 1366 1367 /* Acknowledge all interrupts */ 1368 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 1369 1370 /* Re-enable interrupts */ 1371 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1372 1373 return 0; 1374 } 1375 1376 /* 1377 * Send a command to the firmware and wait for the acknowledgement. 1378 */ 1379 static int 1380 ipw_cmd(struct ipw_softc *sc, uint32_t type, void *data, uint32_t len) 1381 { 1382 struct ipw_soft_bd *sbd; 1383 1384 sbd = &sc->stbd_list[sc->txcur]; 1385 1386 sc->cmd.type = htole32(type); 1387 sc->cmd.subtype = 0; 1388 sc->cmd.len = htole32(len); 1389 sc->cmd.seq = 0; 1390 1391 (void)memcpy(sc->cmd.data, data, len); 1392 1393 sbd->type = IPW_SBD_TYPE_COMMAND; 1394 sbd->bd->physaddr = htole32(sc->cmd_map->dm_segs[0].ds_addr); 1395 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 1396 sbd->bd->nfrag = 1; 1397 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 1398 IPW_BD_FLAG_TX_LAST_FRAGMENT; 1399 1400 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 0, sizeof (struct ipw_cmd), 1401 BUS_DMASYNC_PREWRITE); 1402 1403 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1404 sc->txcur * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1405 BUS_DMASYNC_PREWRITE); 1406 1407 DPRINTFN(2, ("sending command (%u, %u, %u, %u)\n", type, 0, 0, len)); 1408 1409 /* kick firmware */ 1410 sc->txfree--; 1411 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1412 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1413 1414 /* Wait at most one second for command to complete */ 1415 return tsleep(&sc->cmd, 0, "ipwcmd", hz); 1416 } 1417 1418 static int 1419 ipw_tx_start(struct ifnet *ifp, struct mbuf *m0, struct ieee80211_node *ni) 1420 { 1421 struct ipw_softc *sc = ifp->if_softc; 1422 struct ieee80211com *ic = &sc->sc_ic; 1423 struct ieee80211_frame *wh; 1424 struct ipw_soft_bd *sbd; 1425 struct ipw_soft_hdr *shdr; 1426 struct ipw_soft_buf *sbuf; 1427 struct ieee80211_key *k; 1428 struct mbuf *mnew; 1429 int error, i; 1430 1431 wh = mtod(m0, struct ieee80211_frame *); 1432 1433 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1434 k = ieee80211_crypto_encap(ic, ni, m0); 1435 if (k == NULL) { 1436 m_freem(m0); 1437 return ENOBUFS; 1438 } 1439 1440 /* packet header may have moved, reset our local pointer */ 1441 wh = mtod(m0, struct ieee80211_frame *); 1442 } 1443 1444 #if NBPFILTER > 0 1445 if (sc->sc_drvbpf != NULL) { 1446 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 1447 1448 tap->wt_flags = 0; 1449 if (ic->ic_bss->ni_chan != IEEE80211_CHAN_ANYC) { 1450 tap->wt_chan_freq = 1451 htole16(ic->ic_bss->ni_chan->ic_freq); 1452 tap->wt_chan_flags = 1453 htole16(ic->ic_bss->ni_chan->ic_flags); 1454 } else 1455 tap->wt_chan_freq = tap->wt_chan_flags = 0; 1456 1457 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 1458 } 1459 #endif 1460 1461 shdr = TAILQ_FIRST(&sc->sc_free_shdr); 1462 sbuf = TAILQ_FIRST(&sc->sc_free_sbuf); 1463 KASSERT(shdr != NULL && sbuf != NULL); 1464 1465 shdr->hdr->type = htole32(IPW_HDR_TYPE_SEND); 1466 shdr->hdr->subtype = 0; 1467 shdr->hdr->encrypted = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0; 1468 shdr->hdr->encrypt = 0; 1469 shdr->hdr->keyidx = 0; 1470 shdr->hdr->keysz = 0; 1471 shdr->hdr->fragmentsz = 0; 1472 IEEE80211_ADDR_COPY(shdr->hdr->src_addr, wh->i_addr2); 1473 if (ic->ic_opmode == IEEE80211_M_STA) 1474 IEEE80211_ADDR_COPY(shdr->hdr->dst_addr, wh->i_addr3); 1475 else 1476 IEEE80211_ADDR_COPY(shdr->hdr->dst_addr, wh->i_addr1); 1477 1478 /* trim IEEE802.11 header */ 1479 m_adj(m0, sizeof (struct ieee80211_frame)); 1480 1481 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m0, BUS_DMA_NOWAIT); 1482 if (error != 0 && error != EFBIG) { 1483 aprint_error("%s: could not map mbuf (error %d)\n", 1484 sc->sc_dev.dv_xname, error); 1485 m_freem(m0); 1486 return error; 1487 } 1488 1489 if (error != 0) { 1490 /* too many fragments, linearize */ 1491 1492 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1493 if (mnew == NULL) { 1494 m_freem(m0); 1495 return ENOMEM; 1496 } 1497 1498 M_COPY_PKTHDR(mnew, m0); 1499 1500 /* If the data won't fit in the header, get a cluster */ 1501 if (m0->m_pkthdr.len > MHLEN) { 1502 MCLGET(mnew, M_DONTWAIT); 1503 if (!(mnew->m_flags & M_EXT)) { 1504 m_freem(m0); 1505 m_freem(mnew); 1506 return ENOMEM; 1507 } 1508 } 1509 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(mnew, caddr_t)); 1510 m_freem(m0); 1511 mnew->m_len = mnew->m_pkthdr.len; 1512 m0 = mnew; 1513 1514 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m0, 1515 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1516 if (error != 0) { 1517 aprint_error("%s: could not map mbuf (error %d)\n", 1518 sc->sc_dev.dv_xname, error); 1519 m_freem(m0); 1520 return error; 1521 } 1522 } 1523 1524 TAILQ_REMOVE(&sc->sc_free_sbuf, sbuf, next); 1525 TAILQ_REMOVE(&sc->sc_free_shdr, shdr, next); 1526 1527 sbd = &sc->stbd_list[sc->txcur]; 1528 sbd->type = IPW_SBD_TYPE_HEADER; 1529 sbd->priv = shdr; 1530 sbd->bd->physaddr = htole32(shdr->addr); 1531 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 1532 sbd->bd->nfrag = 1 + sbuf->map->dm_nsegs; 1533 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 1534 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1535 1536 DPRINTFN(5, ("sending tx hdr (%u, %u, %u, %u, )\n", 1537 shdr->hdr->type, shdr->hdr->subtype, shdr->hdr->encrypted, 1538 shdr->hdr->encrypt)); 1539 DPRINTFN(5, ("%s->", ether_sprintf(shdr->hdr->src_addr))); 1540 DPRINTFN(5, ("%s\n", ether_sprintf(shdr->hdr->dst_addr))); 1541 1542 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1543 sc->txcur * sizeof (struct ipw_bd), 1544 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1545 1546 sc->txfree--; 1547 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1548 1549 sbuf->m = m0; 1550 sbuf->ni = ni; 1551 1552 for (i = 0; i < sbuf->map->dm_nsegs; i++) { 1553 sbd = &sc->stbd_list[sc->txcur]; 1554 1555 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[i].ds_addr); 1556 sbd->bd->len = htole32(sbuf->map->dm_segs[i].ds_len); 1557 sbd->bd->nfrag = 0; 1558 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 1559 if (i == sbuf->map->dm_nsegs - 1) { 1560 sbd->type = IPW_SBD_TYPE_DATA; 1561 sbd->priv = sbuf; 1562 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 1563 } else { 1564 sbd->type = IPW_SBD_TYPE_NOASSOC; 1565 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1566 } 1567 1568 DPRINTFN(5, ("sending fragment (%d, %d)\n", i, 1569 (int)sbuf->map->dm_segs[i].ds_len)); 1570 1571 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1572 sc->txcur * sizeof (struct ipw_bd), 1573 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1574 1575 sc->txfree--; 1576 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1577 } 1578 1579 bus_dmamap_sync(sc->sc_dmat, sc->hdr_map, shdr->offset, 1580 sizeof (struct ipw_hdr), BUS_DMASYNC_PREWRITE); 1581 1582 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, MCLBYTES, 1583 BUS_DMASYNC_PREWRITE); 1584 1585 /* Inform firmware about this new packet */ 1586 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1587 1588 return 0; 1589 } 1590 1591 static void 1592 ipw_start(struct ifnet *ifp) 1593 { 1594 struct ipw_softc *sc = ifp->if_softc; 1595 struct ieee80211com *ic = &sc->sc_ic; 1596 struct mbuf *m0; 1597 struct ether_header *eh; 1598 struct ieee80211_node *ni; 1599 1600 1601 if (ic->ic_state != IEEE80211_S_RUN) 1602 return; 1603 1604 for (;;) { 1605 IF_DEQUEUE(&ifp->if_snd, m0); 1606 if (m0 == NULL) 1607 break; 1608 1609 if (sc->txfree < 1 + IPW_MAX_NSEG) { 1610 IF_PREPEND(&ifp->if_snd, m0); 1611 ifp->if_flags |= IFF_OACTIVE; 1612 break; 1613 } 1614 1615 if (m0->m_len < sizeof (struct ether_header) && 1616 (m0 = m_pullup(m0, sizeof (struct ether_header))) == NULL) 1617 continue; 1618 1619 eh = mtod(m0, struct ether_header *); 1620 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1621 if (ni == NULL) { 1622 m_freem(m0); 1623 continue; 1624 } 1625 1626 #if NBPFILTER > 0 1627 if (ifp->if_bpf != NULL) 1628 bpf_mtap(ifp->if_bpf, m0); 1629 #endif 1630 1631 m0 = ieee80211_encap(ic, m0, ni); 1632 if (m0 == NULL) { 1633 ieee80211_free_node(ni); 1634 continue; 1635 } 1636 1637 #if NBPFILTER > 0 1638 if (ic->ic_rawbpf != NULL) 1639 bpf_mtap(ic->ic_rawbpf, m0); 1640 #endif 1641 1642 if (ipw_tx_start(ifp, m0, ni) != 0) { 1643 ieee80211_free_node(ni); 1644 ifp->if_oerrors++; 1645 break; 1646 } 1647 1648 /* start watchdog timer */ 1649 sc->sc_tx_timer = 5; 1650 ifp->if_timer = 1; 1651 } 1652 } 1653 1654 static void 1655 ipw_watchdog(struct ifnet *ifp) 1656 { 1657 struct ipw_softc *sc = ifp->if_softc; 1658 1659 ifp->if_timer = 0; 1660 1661 if (sc->sc_tx_timer > 0) { 1662 if (--sc->sc_tx_timer == 0) { 1663 aprint_error("%s: device timeout\n", 1664 sc->sc_dev.dv_xname); 1665 ifp->if_oerrors++; 1666 ifp->if_flags &= ~IFF_UP; 1667 ipw_stop(ifp, 1); 1668 return; 1669 } 1670 ifp->if_timer = 1; 1671 } 1672 1673 ieee80211_watchdog(&sc->sc_ic); 1674 } 1675 1676 static int 1677 ipw_get_table1(struct ipw_softc *sc, uint32_t *tbl) 1678 { 1679 uint32_t addr, size, i; 1680 1681 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1682 return ENOTTY; 1683 1684 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, sc->table1_base); 1685 1686 size = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 1687 if (suword(tbl, size) != 0) 1688 return EFAULT; 1689 1690 for (i = 1, ++tbl; i < size; i++, tbl++) { 1691 addr = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 1692 if (suword(tbl, MEM_READ_4(sc, addr)) != 0) 1693 return EFAULT; 1694 } 1695 return 0; 1696 } 1697 1698 static int 1699 ipw_get_radio(struct ipw_softc *sc, int *ret) 1700 { 1701 uint32_t addr; 1702 1703 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1704 return ENOTTY; 1705 1706 addr = ipw_read_table1(sc, IPW_INFO_EEPROM_ADDRESS); 1707 if ((MEM_READ_4(sc, addr + 32) >> 24) & 1) { 1708 suword(ret, -1); 1709 return 0; 1710 } 1711 1712 if (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED) 1713 suword(ret, 0); 1714 else 1715 suword(ret, 1); 1716 1717 return 0; 1718 } 1719 1720 static int 1721 ipw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1722 { 1723 #define IS_RUNNING(ifp) \ 1724 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 1725 1726 struct ipw_softc *sc = ifp->if_softc; 1727 struct ieee80211com *ic = &sc->sc_ic; 1728 struct ifreq *ifr = (struct ifreq *)data; 1729 int s, error = 0; 1730 1731 s = splnet(); 1732 1733 switch (cmd) { 1734 case SIOCSIFFLAGS: 1735 if (ifp->if_flags & IFF_UP) { 1736 if (!(ifp->if_flags & IFF_RUNNING)) 1737 ipw_init(ifp); 1738 } else { 1739 if (ifp->if_flags & IFF_RUNNING) 1740 ipw_stop(ifp, 1); 1741 } 1742 break; 1743 1744 case SIOCADDMULTI: 1745 case SIOCDELMULTI: 1746 error = (cmd == SIOCADDMULTI) ? 1747 ether_addmulti(ifr, &sc->sc_ec) : 1748 ether_delmulti(ifr, &sc->sc_ec); 1749 if (error == ENETRESET) { 1750 /* setup multicast filter, etc */ 1751 error = 0; 1752 } 1753 break; 1754 1755 case SIOCGTABLE1: 1756 error = ipw_get_table1(sc, (uint32_t *)ifr->ifr_data); 1757 break; 1758 1759 case SIOCGRADIO: 1760 error = ipw_get_radio(sc, (int *)ifr->ifr_data); 1761 break; 1762 1763 case SIOCSIFMEDIA: 1764 if (ifr->ifr_media & IFM_IEEE80211_ADHOC) 1765 strlcpy(sc->sc_fwname, "ipw2100-1.2-i.fw", 1766 sizeof(sc->sc_fwname)); 1767 else if (ifr->ifr_media & IFM_IEEE80211_MONITOR) 1768 strlcpy(sc->sc_fwname, "ipw2100-1.2-p.fw", 1769 sizeof(sc->sc_fwname)); 1770 else 1771 strlcpy(sc->sc_fwname, "ipw2100-1.2.fw", 1772 sizeof(sc->sc_fwname)); 1773 1774 ipw_free_firmware(sc); 1775 /* FALLTRHOUGH */ 1776 default: 1777 error = ieee80211_ioctl(&sc->sc_ic, cmd, data); 1778 if (error != ENETRESET) 1779 break; 1780 1781 if (error == ENETRESET) { 1782 if (IS_RUNNING(ifp) && 1783 (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)) 1784 ipw_init(ifp); 1785 error = 0; 1786 } 1787 1788 } 1789 1790 splx(s); 1791 return error; 1792 #undef IS_RUNNING 1793 } 1794 1795 static uint32_t 1796 ipw_read_table1(struct ipw_softc *sc, uint32_t off) 1797 { 1798 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 1799 } 1800 1801 static void 1802 ipw_write_table1(struct ipw_softc *sc, uint32_t off, uint32_t info) 1803 { 1804 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 1805 } 1806 1807 static int 1808 ipw_read_table2(struct ipw_softc *sc, uint32_t off, void *buf, uint32_t *len) 1809 { 1810 uint32_t addr, info; 1811 uint16_t count, size; 1812 uint32_t total; 1813 1814 /* addr[4] + count[2] + size[2] */ 1815 addr = MEM_READ_4(sc, sc->table2_base + off); 1816 info = MEM_READ_4(sc, sc->table2_base + off + 4); 1817 1818 count = info >> 16; 1819 size = info & 0xffff; 1820 total = count * size; 1821 1822 if (total > *len) { 1823 *len = total; 1824 return EINVAL; 1825 } 1826 1827 *len = total; 1828 ipw_read_mem_1(sc, addr, buf, total); 1829 1830 return 0; 1831 } 1832 1833 static void 1834 ipw_stop_master(struct ipw_softc *sc) 1835 { 1836 int ntries; 1837 1838 /* disable interrupts */ 1839 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1840 1841 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1842 for (ntries = 0; ntries < 50; ntries++) { 1843 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1844 break; 1845 DELAY(10); 1846 } 1847 if (ntries == 50) 1848 aprint_error("%s: timeout waiting for master\n", 1849 sc->sc_dev.dv_xname); 1850 1851 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1852 IPW_RST_PRINCETON_RESET); 1853 1854 sc->flags &= ~IPW_FLAG_FW_INITED; 1855 } 1856 1857 static int 1858 ipw_reset(struct ipw_softc *sc) 1859 { 1860 int ntries; 1861 1862 ipw_stop_master(sc); 1863 1864 /* move adapter to D0 state */ 1865 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1866 IPW_CTL_INIT); 1867 1868 /* wait for clock stabilization */ 1869 for (ntries = 0; ntries < 1000; ntries++) { 1870 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY) 1871 break; 1872 DELAY(200); 1873 } 1874 if (ntries == 1000) 1875 return EIO; 1876 1877 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1878 IPW_RST_SW_RESET); 1879 1880 DELAY(10); 1881 1882 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1883 IPW_CTL_INIT); 1884 1885 return 0; 1886 } 1887 1888 /* 1889 * Upload the microcode to the device. 1890 */ 1891 static int 1892 ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size) 1893 { 1894 int ntries; 1895 1896 MEM_WRITE_4(sc, 0x3000e0, 0x80000000); 1897 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1898 1899 MEM_WRITE_2(sc, 0x220000, 0x0703); 1900 MEM_WRITE_2(sc, 0x220000, 0x0707); 1901 1902 MEM_WRITE_1(sc, 0x210014, 0x72); 1903 MEM_WRITE_1(sc, 0x210014, 0x72); 1904 1905 MEM_WRITE_1(sc, 0x210000, 0x40); 1906 MEM_WRITE_1(sc, 0x210000, 0x00); 1907 MEM_WRITE_1(sc, 0x210000, 0x40); 1908 1909 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1910 1911 MEM_WRITE_1(sc, 0x210000, 0x00); 1912 MEM_WRITE_1(sc, 0x210000, 0x00); 1913 MEM_WRITE_1(sc, 0x210000, 0x80); 1914 1915 MEM_WRITE_2(sc, 0x220000, 0x0703); 1916 MEM_WRITE_2(sc, 0x220000, 0x0707); 1917 1918 MEM_WRITE_1(sc, 0x210014, 0x72); 1919 MEM_WRITE_1(sc, 0x210014, 0x72); 1920 1921 MEM_WRITE_1(sc, 0x210000, 0x00); 1922 MEM_WRITE_1(sc, 0x210000, 0x80); 1923 1924 for (ntries = 0; ntries < 10; ntries++) { 1925 if (MEM_READ_1(sc, 0x210000) & 1) 1926 break; 1927 DELAY(10); 1928 } 1929 if (ntries == 10) { 1930 aprint_error("%s: timeout waiting for ucode to initialize\n", 1931 sc->sc_dev.dv_xname); 1932 return EIO; 1933 } 1934 1935 MEM_WRITE_4(sc, 0x3000e0, 0); 1936 1937 return 0; 1938 } 1939 1940 /* set of macros to handle unaligned little endian data in firmware image */ 1941 #define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1942 #define GETLE16(p) ((p)[0] | (p)[1] << 8) 1943 static int 1944 ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size) 1945 { 1946 u_char *p, *end; 1947 uint32_t dst; 1948 uint16_t len; 1949 int error; 1950 1951 p = fw; 1952 end = fw + size; 1953 while (p < end) { 1954 dst = GETLE32(p); p += 4; 1955 len = GETLE16(p); p += 2; 1956 1957 ipw_write_mem_1(sc, dst, p, len); 1958 p += len; 1959 } 1960 1961 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1962 IPW_IO_LED_OFF); 1963 1964 /* enable interrupts */ 1965 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1966 1967 /* kick the firmware */ 1968 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1969 1970 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1971 IPW_CTL_ALLOW_STANDBY); 1972 1973 /* wait at most one second for firmware initialization to complete */ 1974 if ((error = tsleep(sc, 0, "ipwinit", hz)) != 0) { 1975 aprint_error("%s: timeout waiting for firmware initialization " 1976 "to complete\n", sc->sc_dev.dv_xname); 1977 return error; 1978 } 1979 1980 CSR_WRITE_4(sc, IPW_CSR_IO, CSR_READ_4(sc, IPW_CSR_IO) | 1981 IPW_IO_GPIO1_MASK | IPW_IO_GPIO3_MASK); 1982 1983 return 0; 1984 } 1985 1986 /* 1987 * Store firmware into kernel memory so we can download it when we need to, 1988 * e.g when the adapter wakes up from suspend mode. 1989 */ 1990 static int 1991 ipw_cache_firmware(struct ipw_softc *sc) 1992 { 1993 struct ipw_firmware *fw = &sc->fw; 1994 struct ipw_firmware_hdr hdr; 1995 firmware_handle_t fwh; 1996 off_t fwsz, p; 1997 int error; 1998 1999 ipw_free_firmware(sc); 2000 2001 if ((error = firmware_open("if_ipw", sc->sc_fwname, &fwh)) != 0) 2002 goto fail0; 2003 2004 fwsz = firmware_get_size(fwh); 2005 2006 if (fwsz < sizeof(hdr)) 2007 goto fail2; 2008 2009 if ((error = firmware_read(fwh, 0, &hdr, sizeof(hdr))) != 0) 2010 goto fail2; 2011 2012 fw->main_size = le32toh(hdr.main_size); 2013 fw->ucode_size = le32toh(hdr.ucode_size); 2014 2015 fw->main = firmware_malloc(fw->main_size); 2016 if (fw->main == NULL) { 2017 error = ENOMEM; 2018 goto fail1; 2019 } 2020 2021 fw->ucode = firmware_malloc(fw->ucode_size); 2022 if (fw->ucode == NULL) { 2023 error = ENOMEM; 2024 goto fail2; 2025 } 2026 2027 p = sizeof(hdr); 2028 if ((error = firmware_read(fwh, p, fw->main, fw->main_size)) != 0) 2029 goto fail3; 2030 2031 p += fw->main_size; 2032 if ((error = firmware_read(fwh, p, fw->ucode, fw->ucode_size)) != 0) 2033 goto fail3; 2034 2035 DPRINTF(("Firmware cached: main %u, ucode %u\n", fw->main_size, 2036 fw->ucode_size)); 2037 2038 sc->flags |= IPW_FLAG_FW_CACHED; 2039 2040 firmware_close(fwh); 2041 2042 return 0; 2043 2044 fail3: firmware_free(fw->ucode, 0); 2045 fail2: firmware_free(fw->main, 0); 2046 fail1: firmware_close(fwh); 2047 fail0: 2048 return error; 2049 } 2050 2051 static void 2052 ipw_free_firmware(struct ipw_softc *sc) 2053 { 2054 if (!(sc->flags & IPW_FLAG_FW_CACHED)) 2055 return; 2056 2057 firmware_free(sc->fw.main, 0); 2058 firmware_free(sc->fw.ucode, 0); 2059 2060 sc->flags &= ~IPW_FLAG_FW_CACHED; 2061 } 2062 2063 static int 2064 ipw_config(struct ipw_softc *sc) 2065 { 2066 struct ieee80211com *ic = &sc->sc_ic; 2067 struct ifnet *ifp = &sc->sc_if; 2068 struct ipw_security security; 2069 struct ieee80211_key *k; 2070 struct ipw_wep_key wepkey; 2071 struct ipw_scan_options options; 2072 struct ipw_configuration config; 2073 uint32_t data; 2074 int error, i; 2075 2076 switch (ic->ic_opmode) { 2077 case IEEE80211_M_STA: 2078 case IEEE80211_M_HOSTAP: 2079 data = htole32(IPW_MODE_BSS); 2080 break; 2081 2082 case IEEE80211_M_IBSS: 2083 case IEEE80211_M_AHDEMO: 2084 data = htole32(IPW_MODE_IBSS); 2085 break; 2086 2087 case IEEE80211_M_MONITOR: 2088 data = htole32(IPW_MODE_MONITOR); 2089 break; 2090 } 2091 DPRINTF(("Setting mode to %u\n", le32toh(data))); 2092 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 2093 if (error != 0) 2094 return error; 2095 2096 if (ic->ic_opmode == IEEE80211_M_IBSS || 2097 ic->ic_opmode == IEEE80211_M_MONITOR) { 2098 data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); 2099 DPRINTF(("Setting channel to %u\n", le32toh(data))); 2100 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 2101 if (error != 0) 2102 return error; 2103 } 2104 2105 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2106 DPRINTF(("Enabling adapter\n")); 2107 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 2108 } 2109 2110 DPRINTF(("Setting MAC to %s\n", ether_sprintf(ic->ic_myaddr))); 2111 IEEE80211_ADDR_COPY(LLADDR(ifp->if_sadl), ic->ic_myaddr); 2112 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 2113 IEEE80211_ADDR_LEN); 2114 if (error != 0) 2115 return error; 2116 2117 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 2118 IPW_CFG_PREAMBLE_AUTO | IPW_CFG_802_1x_ENABLE); 2119 2120 if (ic->ic_opmode == IEEE80211_M_IBSS) 2121 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 2122 if (ifp->if_flags & IFF_PROMISC) 2123 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 2124 config.bss_chan = htole32(0x3fff); /* channels 1-14 */ 2125 config.ibss_chan = htole32(0x7ff); /* channels 1-11 */ 2126 DPRINTF(("Setting adapter configuration 0x%08x\n", config.flags)); 2127 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 2128 if (error != 0) 2129 return error; 2130 2131 data = htole32(0x3); /* 1, 2 */ 2132 DPRINTF(("Setting basic tx rates to 0x%x\n", le32toh(data))); 2133 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 2134 if (error != 0) 2135 return error; 2136 2137 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 2138 DPRINTF(("Setting tx rates to 0x%x\n", le32toh(data))); 2139 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 2140 if (error != 0) 2141 return error; 2142 2143 data = htole32(IPW_POWER_MODE_CAM); 2144 DPRINTF(("Setting power mode to %u\n", le32toh(data))); 2145 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 2146 if (error != 0) 2147 return error; 2148 2149 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2150 data = htole32(32); /* default value */ 2151 DPRINTF(("Setting tx power index to %u\n", le32toh(data))); 2152 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 2153 sizeof data); 2154 if (error != 0) 2155 return error; 2156 } 2157 2158 data = htole32(ic->ic_rtsthreshold); 2159 DPRINTF(("Setting RTS threshold to %u\n", le32toh(data))); 2160 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 2161 if (error != 0) 2162 return error; 2163 2164 data = htole32(ic->ic_fragthreshold); 2165 DPRINTF(("Setting frag threshold to %u\n", le32toh(data))); 2166 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 2167 if (error != 0) 2168 return error; 2169 2170 #ifdef IPW_DEBUG 2171 if (ipw_debug > 0) { 2172 printf("Setting ESSID to "); 2173 ieee80211_print_essid(ic->ic_des_essid, ic->ic_des_esslen); 2174 printf("\n"); 2175 } 2176 #endif 2177 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ic->ic_des_essid, 2178 ic->ic_des_esslen); 2179 if (error != 0) 2180 return error; 2181 2182 /* no mandatory BSSID */ 2183 DPRINTF(("Setting mandatory BSSID to null\n")); 2184 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 2185 if (error != 0) 2186 return error; 2187 2188 if (ic->ic_flags & IEEE80211_F_DESBSSID) { 2189 DPRINTF(("Setting desired BSSID to %s\n", 2190 ether_sprintf(ic->ic_des_bssid))); 2191 error = ipw_cmd(sc, IPW_CMD_SET_DESIRED_BSSID, 2192 ic->ic_des_bssid, IEEE80211_ADDR_LEN); 2193 if (error != 0) 2194 return error; 2195 } 2196 2197 (void)memset(&security, 0, sizeof(security)); 2198 security.authmode = (ic->ic_bss->ni_authmode == IEEE80211_AUTH_SHARED) ? 2199 IPW_AUTH_SHARED : IPW_AUTH_OPEN; 2200 security.ciphers = htole32(IPW_CIPHER_NONE); 2201 DPRINTF(("Setting authmode to %u\n", security.authmode)); 2202 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 2203 sizeof security); 2204 if (error != 0) 2205 return error; 2206 2207 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 2208 k = ic->ic_crypto.cs_nw_keys; 2209 for (i = 0; i < IEEE80211_WEP_NKID; i++, k++) { 2210 if (k->wk_keylen == 0) 2211 continue; 2212 2213 wepkey.idx = i; 2214 wepkey.len = k->wk_keylen; 2215 memset(wepkey.key, 0, sizeof(wepkey.key)); 2216 memcpy(wepkey.key, k->wk_key, k->wk_keylen); 2217 DPRINTF(("Setting wep key index %u len %u\n", 2218 wepkey.idx, wepkey.len)); 2219 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY, &wepkey, 2220 sizeof wepkey); 2221 if (error != 0) 2222 return error; 2223 } 2224 2225 data = htole32(ic->ic_crypto.cs_def_txkey); 2226 DPRINTF(("Setting tx key index to %u\n", le32toh(data))); 2227 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY_INDEX, &data, 2228 sizeof data); 2229 if (error != 0) 2230 return error; 2231 } 2232 2233 data = htole32((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) ? IPW_WEPON : 0); 2234 DPRINTF(("Setting wep flags to 0x%x\n", le32toh(data))); 2235 error = ipw_cmd(sc, IPW_CMD_SET_WEP_FLAGS, &data, sizeof data); 2236 if (error != 0) 2237 return error; 2238 2239 #if 0 2240 struct ipw_wpa_ie ie; 2241 2242 memset(&ie, 0 sizeof(ie)); 2243 ie.len = htole32(sizeof (struct ieee80211_ie_wpa)); 2244 DPRINTF(("Setting wpa ie\n")); 2245 error = ipw_cmd(sc, IPW_CMD_SET_WPA_IE, &ie, sizeof ie); 2246 if (error != 0) 2247 return error; 2248 #endif 2249 2250 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2251 data = htole32(ic->ic_bintval); 2252 DPRINTF(("Setting beacon interval to %u\n", le32toh(data))); 2253 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 2254 sizeof data); 2255 if (error != 0) 2256 return error; 2257 } 2258 2259 options.flags = 0; 2260 options.channels = htole32(0x3fff); /* scan channels 1-14 */ 2261 DPRINTF(("Setting scan options to 0x%x\n", le32toh(options.flags))); 2262 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &options, sizeof options); 2263 if (error != 0) 2264 return error; 2265 2266 /* finally, enable adapter (start scanning for an access point) */ 2267 DPRINTF(("Enabling adapter\n")); 2268 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 2269 } 2270 2271 static int 2272 ipw_init(struct ifnet *ifp) 2273 { 2274 struct ipw_softc *sc = ifp->if_softc; 2275 struct ipw_firmware *fw = &sc->fw; 2276 2277 if (!(sc->flags & IPW_FLAG_FW_CACHED)) { 2278 if (ipw_cache_firmware(sc) != 0) { 2279 aprint_error("%s: could not cache the firmware (%s)\n", 2280 sc->sc_dev.dv_xname, sc->sc_fwname); 2281 goto fail; 2282 } 2283 } 2284 2285 ipw_stop(ifp, 0); 2286 2287 if (ipw_reset(sc) != 0) { 2288 aprint_error("%s: could not reset adapter\n", 2289 sc->sc_dev.dv_xname); 2290 goto fail; 2291 } 2292 2293 if (ipw_load_ucode(sc, fw->ucode, fw->ucode_size) != 0) { 2294 aprint_error("%s: could not load microcode\n", 2295 sc->sc_dev.dv_xname); 2296 goto fail; 2297 } 2298 2299 ipw_stop_master(sc); 2300 2301 /* 2302 * Setup tx, rx and status rings. 2303 */ 2304 sc->txold = IPW_NTBD - 1; 2305 sc->txcur = 0; 2306 sc->txfree = IPW_NTBD - 2; 2307 sc->rxcur = IPW_NRBD - 1; 2308 2309 CSR_WRITE_4(sc, IPW_CSR_TX_BASE, sc->tbd_map->dm_segs[0].ds_addr); 2310 CSR_WRITE_4(sc, IPW_CSR_TX_SIZE, IPW_NTBD); 2311 CSR_WRITE_4(sc, IPW_CSR_TX_READ, 0); 2312 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 2313 2314 CSR_WRITE_4(sc, IPW_CSR_RX_BASE, sc->rbd_map->dm_segs[0].ds_addr); 2315 CSR_WRITE_4(sc, IPW_CSR_RX_SIZE, IPW_NRBD); 2316 CSR_WRITE_4(sc, IPW_CSR_RX_READ, 0); 2317 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 2318 2319 CSR_WRITE_4(sc, IPW_CSR_STATUS_BASE, sc->status_map->dm_segs[0].ds_addr); 2320 2321 if (ipw_load_firmware(sc, fw->main, fw->main_size) != 0) { 2322 aprint_error("%s: could not load firmware\n", 2323 sc->sc_dev.dv_xname); 2324 goto fail; 2325 } 2326 2327 sc->flags |= IPW_FLAG_FW_INITED; 2328 2329 /* retrieve information tables base addresses */ 2330 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 2331 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 2332 2333 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 2334 2335 if (ipw_config(sc) != 0) { 2336 aprint_error("%s: device configuration failed\n", 2337 sc->sc_dev.dv_xname); 2338 goto fail; 2339 } 2340 2341 ifp->if_flags &= ~IFF_OACTIVE; 2342 ifp->if_flags |= IFF_RUNNING; 2343 2344 return 0; 2345 2346 fail: ifp->if_flags &= ~IFF_UP; 2347 ipw_stop(ifp, 0); 2348 2349 return EIO; 2350 } 2351 2352 static void 2353 ipw_stop(struct ifnet *ifp, int disable) 2354 { 2355 struct ipw_softc *sc = ifp->if_softc; 2356 struct ieee80211com *ic = &sc->sc_ic; 2357 int i; 2358 2359 ipw_stop_master(sc); 2360 2361 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 2362 2363 /* 2364 * Release tx buffers. 2365 */ 2366 for (i = 0; i < IPW_NTBD; i++) 2367 ipw_release_sbd(sc, &sc->stbd_list[i]); 2368 2369 sc->sc_tx_timer = 0; 2370 ifp->if_timer = 0; 2371 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2372 2373 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2374 } 2375 2376 static void 2377 ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2378 bus_size_t count) 2379 { 2380 for (; count > 0; offset++, datap++, count--) { 2381 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2382 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 2383 } 2384 } 2385 2386 static void 2387 ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2388 bus_size_t count) 2389 { 2390 for (; count > 0; offset++, datap++, count--) { 2391 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2392 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 2393 } 2394 } 2395
Indexes created Tue Sep 30 17:09:57 GMT 2025