if_ipw.c revision 1.32.16.3
1 /* if_ipw.c,v 1.32.16.2 2008/01/09 01:53:45 matt Exp */ 2 /* FreeBSD: src/sys/dev/ipw/if_ipw.c,v 1.15 2005/11/13 17:17:40 damien Exp */ 3 4 /*- 5 * Copyright (c) 2004, 2005 6 * Damien Bergamini <damien.bergamini (at) free.fr>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "if_ipw.c,v 1.32.16.2 2008/01/09 01:53:45 matt Exp"); 33 34 /*- 35 * Intel(R) PRO/Wireless 2100 MiniPCI driver 36 * http://www.intel.com/network/connectivity/products/wireless/prowireless_mobile.htm 37 */ 38 39 #include "bpfilter.h" 40 41 #include <sys/param.h> 42 #include <sys/sockio.h> 43 #include <sys/sysctl.h> 44 #include <sys/mbuf.h> 45 #include <sys/kernel.h> 46 #include <sys/socket.h> 47 #include <sys/systm.h> 48 #include <sys/malloc.h> 49 #include <sys/conf.h> 50 51 #include <sys/bus.h> 52 #include <machine/endian.h> 53 #include <sys/intr.h> 54 55 #include <dev/pci/pcireg.h> 56 #include <dev/pci/pcivar.h> 57 #include <dev/pci/pcidevs.h> 58 59 #if NBPFILTER > 0 60 #include <net/bpf.h> 61 #endif 62 #include <net/if.h> 63 #include <net/if_arp.h> 64 #include <net/if_dl.h> 65 #include <net/if_ether.h> 66 #include <net/if_media.h> 67 #include <net/if_types.h> 68 69 #include <net80211/ieee80211_var.h> 70 #include <net80211/ieee80211_radiotap.h> 71 72 #include <netinet/in.h> 73 #include <netinet/in_systm.h> 74 #include <netinet/in_var.h> 75 #include <netinet/ip.h> 76 77 #include <dev/firmload.h> 78 79 #include <dev/pci/if_ipwreg.h> 80 #include <dev/pci/if_ipwvar.h> 81 82 #ifdef IPW_DEBUG 83 #define DPRINTF(x) if (ipw_debug > 0) printf x 84 #define DPRINTFN(n, x) if (ipw_debug >= (n)) printf x 85 int ipw_debug = 0; 86 #else 87 #define DPRINTF(x) 88 #define DPRINTFN(n, x) 89 #endif 90 91 static int ipw_dma_alloc(struct ipw_softc *); 92 static void ipw_release(struct ipw_softc *); 93 static int ipw_match(struct device *, struct cfdata *, void *); 94 static void ipw_attach(struct device *, struct device *, void *); 95 static int ipw_detach(struct device *, int); 96 97 static int ipw_media_change(struct ifnet *); 98 static void ipw_media_status(struct ifnet *, struct ifmediareq *); 99 static int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 100 static uint16_t ipw_read_prom_word(struct ipw_softc *, uint8_t); 101 static void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 102 static void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 103 static void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 104 struct ipw_soft_bd *, struct ipw_soft_buf *); 105 static void ipw_rx_intr(struct ipw_softc *); 106 static void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 107 static void ipw_tx_intr(struct ipw_softc *); 108 static int ipw_intr(void *); 109 static int ipw_cmd(struct ipw_softc *, uint32_t, void *, uint32_t); 110 static int ipw_tx_start(struct ifnet *, struct mbuf *, 111 struct ieee80211_node *); 112 static void ipw_start(struct ifnet *); 113 static void ipw_watchdog(struct ifnet *); 114 static int ipw_ioctl(struct ifnet *, u_long, void *); 115 static int ipw_get_table1(struct ipw_softc *, uint32_t *); 116 static int ipw_get_radio(struct ipw_softc *, int *); 117 static void ipw_stop_master(struct ipw_softc *); 118 static int ipw_reset(struct ipw_softc *); 119 static int ipw_load_ucode(struct ipw_softc *, u_char *, int); 120 static int ipw_load_firmware(struct ipw_softc *, u_char *, int); 121 static int ipw_cache_firmware(struct ipw_softc *); 122 static void ipw_free_firmware(struct ipw_softc *); 123 static int ipw_config(struct ipw_softc *); 124 static int ipw_init(struct ifnet *); 125 static void ipw_stop(struct ifnet *, int); 126 static uint32_t ipw_read_table1(struct ipw_softc *, uint32_t); 127 static void ipw_write_table1(struct ipw_softc *, uint32_t, uint32_t); 128 static int ipw_read_table2(struct ipw_softc *, uint32_t, void *, uint32_t *); 129 static void ipw_read_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 130 bus_size_t); 131 static void ipw_write_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 132 bus_size_t); 133 134 /* 135 * Supported rates for 802.11b mode (in 500Kbps unit). 136 */ 137 static const struct ieee80211_rateset ipw_rateset_11b = 138 { 4, { 2, 4, 11, 22 } }; 139 140 static inline uint8_t 141 MEM_READ_1(struct ipw_softc *sc, uint32_t addr) 142 { 143 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 144 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); 145 } 146 147 static inline uint32_t 148 MEM_READ_4(struct ipw_softc *sc, uint32_t addr) 149 { 150 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 151 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); 152 } 153 154 CFATTACH_DECL(ipw, sizeof (struct ipw_softc), ipw_match, ipw_attach, 155 ipw_detach, NULL); 156 157 static int 158 ipw_match(struct device *parent, struct cfdata *match, 159 void *aux) 160 { 161 struct pci_attach_args *pa = aux; 162 163 if (PCI_VENDOR (pa->pa_id) == PCI_VENDOR_INTEL && 164 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_PRO_WL_2100) 165 return 1; 166 167 return 0; 168 } 169 170 /* Base Address Register */ 171 #define IPW_PCI_BAR0 0x10 172 173 static void 174 ipw_attach(struct device *parent, struct device *self, void *aux) 175 { 176 struct ipw_softc *sc = (struct ipw_softc *)self; 177 struct ieee80211com *ic = &sc->sc_ic; 178 struct ifnet *ifp = &sc->sc_if; 179 struct pci_attach_args *pa = aux; 180 const char *intrstr; 181 char devinfo[256]; 182 bus_space_tag_t memt; 183 bus_space_handle_t memh; 184 bus_addr_t base; 185 pci_intr_handle_t ih; 186 uint32_t data; 187 uint16_t val; 188 int i, revision, error; 189 190 sc->sc_pct = pa->pa_pc; 191 sc->sc_pcitag = pa->pa_tag; 192 193 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof devinfo); 194 revision = PCI_REVISION(pa->pa_class); 195 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, revision); 196 197 /* enable bus-mastering */ 198 data = pci_conf_read(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG); 199 data |= PCI_COMMAND_MASTER_ENABLE; 200 pci_conf_write(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG, data); 201 202 /* map the register window */ 203 error = pci_mapreg_map(pa, IPW_PCI_BAR0, PCI_MAPREG_TYPE_MEM | 204 PCI_MAPREG_MEM_TYPE_32BIT, 0, &memt, &memh, &base, &sc->sc_sz); 205 if (error != 0) { 206 aprint_error("%s: could not map memory space\n", 207 sc->sc_dev.dv_xname); 208 return; 209 } 210 211 sc->sc_st = memt; 212 sc->sc_sh = memh; 213 sc->sc_dmat = pa->pa_dmat; 214 strlcpy(sc->sc_fwname, "ipw2100-1.2.fw", sizeof(sc->sc_fwname)); 215 216 /* disable interrupts */ 217 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 218 219 if (pci_intr_map(pa, &ih) != 0) { 220 aprint_error("%s: could not map interrupt\n", 221 sc->sc_dev.dv_xname); 222 return; 223 } 224 225 intrstr = pci_intr_string(sc->sc_pct, ih); 226 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, ipw_intr, sc); 227 if (sc->sc_ih == NULL) { 228 aprint_error("%s: could not establish interrupt", 229 sc->sc_dev.dv_xname); 230 if (intrstr != NULL) 231 aprint_error(" at %s", intrstr); 232 aprint_error("\n"); 233 return; 234 } 235 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 236 237 if (ipw_reset(sc) != 0) { 238 aprint_error("%s: could not reset adapter\n", 239 sc->sc_dev.dv_xname); 240 goto fail; 241 } 242 243 if (ipw_dma_alloc(sc) != 0) { 244 aprint_error("%s: could not allocate DMA resources\n", 245 sc->sc_dev.dv_xname); 246 goto fail; 247 } 248 249 ifp->if_softc = sc; 250 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 251 ifp->if_init = ipw_init; 252 ifp->if_stop = ipw_stop; 253 ifp->if_ioctl = ipw_ioctl; 254 ifp->if_start = ipw_start; 255 ifp->if_watchdog = ipw_watchdog; 256 IFQ_SET_READY(&ifp->if_snd); 257 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 258 259 ic->ic_ifp = ifp; 260 ic->ic_phytype = IEEE80211_T_DS; 261 ic->ic_opmode = IEEE80211_M_STA; 262 ic->ic_state = IEEE80211_S_INIT; 263 264 /* set device capabilities */ 265 ic->ic_caps = 266 IEEE80211_C_SHPREAMBLE /* short preamble supported */ 267 | IEEE80211_C_TXPMGT /* tx power management */ 268 | IEEE80211_C_IBSS /* ibss mode */ 269 | IEEE80211_C_MONITOR /* monitor mode */ 270 ; 271 272 /* read MAC address from EEPROM */ 273 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0); 274 ic->ic_myaddr[0] = val >> 8; 275 ic->ic_myaddr[1] = val & 0xff; 276 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 1); 277 ic->ic_myaddr[2] = val >> 8; 278 ic->ic_myaddr[3] = val & 0xff; 279 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 2); 280 ic->ic_myaddr[4] = val >> 8; 281 ic->ic_myaddr[5] = val & 0xff; 282 283 /* set supported .11b rates */ 284 ic->ic_sup_rates[IEEE80211_MODE_11B] = ipw_rateset_11b; 285 286 /* set supported .11b channels (read from EEPROM) */ 287 if ((val = ipw_read_prom_word(sc, IPW_EEPROM_CHANNEL_LIST)) == 0) 288 val = 0x7ff; /* default to channels 1-11 */ 289 val <<= 1; 290 for (i = 1; i < 16; i++) { 291 if (val & (1 << i)) { 292 ic->ic_channels[i].ic_freq = 293 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 294 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 295 } 296 } 297 298 /* check support for radio transmitter switch in EEPROM */ 299 if (!(ipw_read_prom_word(sc, IPW_EEPROM_RADIO) & 8)) 300 sc->flags |= IPW_FLAG_HAS_RADIO_SWITCH; 301 302 aprint_normal("%s: 802.11 address %s\n", sc->sc_dev.dv_xname, 303 ether_sprintf(ic->ic_myaddr)); 304 305 if_attach(ifp); 306 ieee80211_ifattach(ic); 307 308 /* override state transition machine */ 309 sc->sc_newstate = ic->ic_newstate; 310 ic->ic_newstate = ipw_newstate; 311 312 ieee80211_media_init(ic, ipw_media_change, ipw_media_status); 313 314 #if NBPFILTER > 0 315 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 316 sizeof (struct ieee80211_frame) + 64, &sc->sc_drvbpf); 317 318 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 319 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 320 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 321 322 sc->sc_txtap_len = sizeof sc->sc_txtapu; 323 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 324 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 325 #endif 326 327 /* 328 * Add a few sysctl knobs. 329 * XXX: Not yet 330 */ 331 sc->dwelltime = 100; 332 333 if (!pmf_device_register(self, NULL, NULL)) 334 aprint_error_dev(self, "couldn't establish power handler\n"); 335 else 336 pmf_class_network_register(self, ifp); 337 338 ieee80211_announce(ic); 339 340 return; 341 342 fail: ipw_detach(self, 0); 343 } 344 345 static int 346 ipw_detach(struct device* self, int flags) 347 { 348 struct ipw_softc *sc = (struct ipw_softc *)self; 349 struct ifnet *ifp = &sc->sc_if; 350 351 if (ifp->if_softc) { 352 ipw_stop(ifp, 1); 353 ipw_free_firmware(sc); 354 355 #if NBPFILTER > 0 356 bpfdetach(ifp); 357 #endif 358 ieee80211_ifdetach(&sc->sc_ic); 359 if_detach(ifp); 360 361 ipw_release(sc); 362 } 363 364 if (sc->sc_ih != NULL) { 365 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 366 sc->sc_ih = NULL; 367 } 368 369 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 370 371 return 0; 372 } 373 374 static int 375 ipw_dma_alloc(struct ipw_softc *sc) 376 { 377 struct ipw_soft_bd *sbd; 378 struct ipw_soft_hdr *shdr; 379 struct ipw_soft_buf *sbuf; 380 int error, i, nsegs; 381 382 /* 383 * Allocate and map tx ring. 384 */ 385 error = bus_dmamap_create(sc->sc_dmat, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, 386 BUS_DMA_NOWAIT, &sc->tbd_map); 387 if (error != 0) { 388 aprint_error("%s: could not create tbd dma map\n", 389 sc->sc_dev.dv_xname); 390 goto fail; 391 } 392 393 error = bus_dmamem_alloc(sc->sc_dmat, IPW_TBD_SZ, PAGE_SIZE, 0, 394 &sc->tbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 395 if (error != 0) { 396 aprint_error("%s: could not allocate tbd dma memory\n", 397 sc->sc_dev.dv_xname); 398 goto fail; 399 } 400 401 error = bus_dmamem_map(sc->sc_dmat, &sc->tbd_seg, nsegs, IPW_TBD_SZ, 402 (void **)&sc->tbd_list, BUS_DMA_NOWAIT); 403 if (error != 0) { 404 aprint_error("%s: could not map tbd dma memory\n", 405 sc->sc_dev.dv_xname); 406 goto fail; 407 } 408 409 error = bus_dmamap_load(sc->sc_dmat, sc->tbd_map, sc->tbd_list, 410 IPW_TBD_SZ, NULL, BUS_DMA_NOWAIT); 411 if (error != 0) { 412 aprint_error("%s: could not load tbd dma memory\n", 413 sc->sc_dev.dv_xname); 414 goto fail; 415 } 416 417 (void)memset(sc->tbd_list, 0, IPW_TBD_SZ); 418 419 /* 420 * Allocate and map rx ring. 421 */ 422 error = bus_dmamap_create(sc->sc_dmat, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, 423 BUS_DMA_NOWAIT, &sc->rbd_map); 424 if (error != 0) { 425 aprint_error("%s: could not create rbd dma map\n", 426 sc->sc_dev.dv_xname); 427 goto fail; 428 } 429 430 error = bus_dmamem_alloc(sc->sc_dmat, IPW_RBD_SZ, PAGE_SIZE, 0, 431 &sc->rbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 432 if (error != 0) { 433 aprint_error("%s: could not allocate rbd dma memory\n", 434 sc->sc_dev.dv_xname); 435 goto fail; 436 } 437 438 error = bus_dmamem_map(sc->sc_dmat, &sc->rbd_seg, nsegs, IPW_RBD_SZ, 439 (void **)&sc->rbd_list, BUS_DMA_NOWAIT); 440 if (error != 0) { 441 aprint_error("%s: could not map rbd dma memory\n", 442 sc->sc_dev.dv_xname); 443 goto fail; 444 } 445 446 error = bus_dmamap_load(sc->sc_dmat, sc->rbd_map, sc->rbd_list, 447 IPW_RBD_SZ, NULL, BUS_DMA_NOWAIT); 448 if (error != 0) { 449 aprint_error("%s: could not load rbd dma memory\n", 450 sc->sc_dev.dv_xname); 451 goto fail; 452 } 453 454 (void)memset(sc->rbd_list, 0, IPW_RBD_SZ); 455 456 /* 457 * Allocate and map status ring. 458 */ 459 error = bus_dmamap_create(sc->sc_dmat, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 460 0, BUS_DMA_NOWAIT, &sc->status_map); 461 if (error != 0) { 462 aprint_error("%s: could not create status dma map\n", 463 sc->sc_dev.dv_xname); 464 goto fail; 465 } 466 467 error = bus_dmamem_alloc(sc->sc_dmat, IPW_STATUS_SZ, PAGE_SIZE, 0, 468 &sc->status_seg, 1, &nsegs, BUS_DMA_NOWAIT); 469 if (error != 0) { 470 aprint_error("%s: could not allocate status dma memory\n", 471 sc->sc_dev.dv_xname); 472 goto fail; 473 } 474 475 error = bus_dmamem_map(sc->sc_dmat, &sc->status_seg, nsegs, 476 IPW_STATUS_SZ, (void **)&sc->status_list, BUS_DMA_NOWAIT); 477 if (error != 0) { 478 aprint_error("%s: could not map status dma memory\n", 479 sc->sc_dev.dv_xname); 480 goto fail; 481 } 482 483 error = bus_dmamap_load(sc->sc_dmat, sc->status_map, sc->status_list, 484 IPW_STATUS_SZ, NULL, BUS_DMA_NOWAIT); 485 if (error != 0) { 486 aprint_error("%s: could not load status dma memory\n", 487 sc->sc_dev.dv_xname); 488 goto fail; 489 } 490 491 (void)memset(sc->status_list, 0, IPW_STATUS_SZ); 492 493 /* 494 * Allocate command DMA map. 495 */ 496 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_cmd), 497 1, sizeof (struct ipw_cmd), 0, BUS_DMA_NOWAIT, &sc->cmd_map); 498 if (error != 0) { 499 aprint_error("%s: could not create cmd dma map\n", 500 sc->sc_dev.dv_xname); 501 goto fail; 502 } 503 504 error = bus_dmamem_alloc(sc->sc_dmat, sizeof (struct ipw_cmd), 505 PAGE_SIZE, 0, &sc->cmd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 506 if (error != 0) { 507 aprint_error("%s: could not allocate cmd dma memory\n", 508 sc->sc_dev.dv_xname); 509 goto fail; 510 } 511 512 error = bus_dmamem_map(sc->sc_dmat, &sc->cmd_seg, nsegs, 513 sizeof (struct ipw_cmd), (void **)&sc->cmd, BUS_DMA_NOWAIT); 514 if (error != 0) { 515 aprint_error("%s: could not map cmd dma memory\n", 516 sc->sc_dev.dv_xname); 517 goto fail; 518 } 519 520 error = bus_dmamap_load(sc->sc_dmat, sc->cmd_map, &sc->cmd, 521 sizeof (struct ipw_cmd), NULL, BUS_DMA_NOWAIT); 522 if (error != 0) { 523 aprint_error("%s: could not map cmd dma memory\n", 524 sc->sc_dev.dv_xname); 525 return error; 526 } 527 528 /* 529 * Allocate and map hdr list. 530 */ 531 532 error = bus_dmamap_create(sc->sc_dmat, 533 IPW_NDATA * sizeof(struct ipw_hdr), 1, 534 sizeof(struct ipw_hdr), 0, BUS_DMA_NOWAIT, 535 &sc->hdr_map); 536 if (error != 0) { 537 aprint_error("%s: could not create hdr dma map\n", 538 sc->sc_dev.dv_xname); 539 goto fail; 540 } 541 542 error = bus_dmamem_alloc(sc->sc_dmat, 543 IPW_NDATA * sizeof(struct ipw_hdr), PAGE_SIZE, 0, &sc->hdr_seg, 544 1, &nsegs, BUS_DMA_NOWAIT); 545 if (error != 0) { 546 aprint_error("%s: could not allocate hdr memory\n", 547 sc->sc_dev.dv_xname); 548 goto fail; 549 } 550 551 error = bus_dmamem_map(sc->sc_dmat, &sc->hdr_seg, nsegs, 552 IPW_NDATA * sizeof(struct ipw_hdr), (void **)&sc->hdr_list, 553 BUS_DMA_NOWAIT); 554 if (error != 0) { 555 aprint_error("%s: could not map hdr memory\n", 556 sc->sc_dev.dv_xname); 557 goto fail; 558 } 559 560 error = bus_dmamap_load(sc->sc_dmat, sc->hdr_map, sc->hdr_list, 561 IPW_NDATA * sizeof(struct ipw_hdr), NULL, BUS_DMA_NOWAIT); 562 if (error != 0) { 563 aprint_error("%s: could not load hdr memory\n", 564 sc->sc_dev.dv_xname); 565 goto fail; 566 } 567 568 (void)memset(sc->hdr_list, 0, IPW_HDR_SZ); 569 570 /* 571 * Create DMA hdrs tailq. 572 */ 573 TAILQ_INIT(&sc->sc_free_shdr); 574 for (i = 0; i < IPW_NDATA; i++) { 575 shdr = &sc->shdr_list[i]; 576 shdr->hdr = sc->hdr_list + i; 577 shdr->offset = sizeof(struct ipw_hdr) * i; 578 shdr->addr = sc->hdr_map->dm_segs[0].ds_addr + shdr->offset; 579 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 580 } 581 582 /* 583 * Allocate tx buffers DMA maps. 584 */ 585 TAILQ_INIT(&sc->sc_free_sbuf); 586 for (i = 0; i < IPW_NDATA; i++) { 587 sbuf = &sc->tx_sbuf_list[i]; 588 589 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 590 IPW_MAX_NSEG, MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 591 if (error != 0) { 592 aprint_error("%s: could not create txbuf dma map\n", 593 sc->sc_dev.dv_xname); 594 goto fail; 595 } 596 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 597 } 598 599 /* 600 * Initialize tx ring. 601 */ 602 for (i = 0; i < IPW_NTBD; i++) { 603 sbd = &sc->stbd_list[i]; 604 sbd->bd = &sc->tbd_list[i]; 605 sbd->type = IPW_SBD_TYPE_NOASSOC; 606 } 607 608 /* 609 * Pre-allocate rx buffers and DMA maps 610 */ 611 for (i = 0; i < IPW_NRBD; i++) { 612 sbd = &sc->srbd_list[i]; 613 sbuf = &sc->rx_sbuf_list[i]; 614 sbd->bd = &sc->rbd_list[i]; 615 616 MGETHDR(sbuf->m, M_DONTWAIT, MT_DATA); 617 if (sbuf->m == NULL) { 618 aprint_error("%s: could not allocate rx mbuf\n", 619 sc->sc_dev.dv_xname); 620 error = ENOMEM; 621 goto fail; 622 } 623 624 MCLGET(sbuf->m, M_DONTWAIT); 625 if (!(sbuf->m->m_flags & M_EXT)) { 626 m_freem(sbuf->m); 627 aprint_error("%s: could not allocate rx mbuf cluster\n", 628 sc->sc_dev.dv_xname); 629 error = ENOMEM; 630 goto fail; 631 } 632 633 sbuf->m->m_pkthdr.len = sbuf->m->m_len = sbuf->m->m_ext.ext_size; 634 635 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 636 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sbuf->map); 637 if (error != 0) { 638 aprint_error("%s: could not create rxbuf dma map\n", 639 sc->sc_dev.dv_xname); 640 m_freem(sbuf->m); 641 goto fail; 642 } 643 644 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, 645 sbuf->m, BUS_DMA_READ | BUS_DMA_NOWAIT); 646 if (error != 0) { 647 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 648 m_freem(sbuf->m); 649 aprint_error("%s: could not map rxbuf dma memory\n", 650 sc->sc_dev.dv_xname); 651 goto fail; 652 } 653 654 sbd->type = IPW_SBD_TYPE_DATA; 655 sbd->priv = sbuf; 656 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 657 sbd->bd->len = htole32(MCLBYTES); 658 659 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, 660 sbuf->map->dm_mapsize, BUS_DMASYNC_PREREAD); 661 662 } 663 664 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 0, IPW_RBD_SZ, 665 BUS_DMASYNC_PREREAD); 666 667 return 0; 668 669 fail: ipw_release(sc); 670 return error; 671 } 672 673 static void 674 ipw_release(struct ipw_softc *sc) 675 { 676 struct ipw_soft_buf *sbuf; 677 int i; 678 679 if (sc->tbd_map != NULL) { 680 if (sc->tbd_list != NULL) { 681 bus_dmamap_unload(sc->sc_dmat, sc->tbd_map); 682 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->tbd_list, 683 IPW_TBD_SZ); 684 bus_dmamem_free(sc->sc_dmat, &sc->tbd_seg, 1); 685 } 686 bus_dmamap_destroy(sc->sc_dmat, sc->tbd_map); 687 } 688 689 if (sc->rbd_map != NULL) { 690 if (sc->rbd_list != NULL) { 691 bus_dmamap_unload(sc->sc_dmat, sc->rbd_map); 692 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->rbd_list, 693 IPW_RBD_SZ); 694 bus_dmamem_free(sc->sc_dmat, &sc->rbd_seg, 1); 695 } 696 bus_dmamap_destroy(sc->sc_dmat, sc->rbd_map); 697 } 698 699 if (sc->status_map != NULL) { 700 if (sc->status_list != NULL) { 701 bus_dmamap_unload(sc->sc_dmat, sc->status_map); 702 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->status_list, 703 IPW_RBD_SZ); 704 bus_dmamem_free(sc->sc_dmat, &sc->status_seg, 1); 705 } 706 bus_dmamap_destroy(sc->sc_dmat, sc->status_map); 707 } 708 709 for (i = 0; i < IPW_NTBD; i++) 710 ipw_release_sbd(sc, &sc->stbd_list[i]); 711 712 if (sc->cmd_map != NULL) 713 bus_dmamap_destroy(sc->sc_dmat, sc->cmd_map); 714 715 if (sc->hdr_list != NULL) { 716 bus_dmamap_unload(sc->sc_dmat, sc->hdr_map); 717 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->hdr_list, 718 IPW_NDATA * sizeof(struct ipw_hdr)); 719 } 720 if (sc->hdr_map != NULL) { 721 bus_dmamem_free(sc->sc_dmat, &sc->hdr_seg, 1); 722 bus_dmamap_destroy(sc->sc_dmat, sc->hdr_map); 723 } 724 725 for (i = 0; i < IPW_NDATA; i++) 726 bus_dmamap_destroy(sc->sc_dmat, sc->tx_sbuf_list[i].map); 727 728 for (i = 0; i < IPW_NRBD; i++) { 729 sbuf = &sc->rx_sbuf_list[i]; 730 if (sbuf->map != NULL) { 731 if (sbuf->m != NULL) { 732 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 733 m_freem(sbuf->m); 734 } 735 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 736 } 737 } 738 739 } 740 741 static int 742 ipw_media_change(struct ifnet *ifp) 743 { 744 int error; 745 746 error = ieee80211_media_change(ifp); 747 if (error != ENETRESET) 748 return error; 749 750 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 751 ipw_init(ifp); 752 753 return 0; 754 } 755 756 /* 757 * The firmware automatically adapts the transmit speed. We report the current 758 * transmit speed here. 759 */ 760 static void 761 ipw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 762 { 763 #define N(a) (sizeof (a) / sizeof (a[0])) 764 struct ipw_softc *sc = ifp->if_softc; 765 struct ieee80211com *ic = &sc->sc_ic; 766 static const struct { 767 uint32_t val; 768 int rate; 769 } rates[] = { 770 { IPW_RATE_DS1, 2 }, 771 { IPW_RATE_DS2, 4 }, 772 { IPW_RATE_DS5, 11 }, 773 { IPW_RATE_DS11, 22 }, 774 }; 775 uint32_t val; 776 int rate, i; 777 778 imr->ifm_status = IFM_AVALID; 779 imr->ifm_active = IFM_IEEE80211; 780 if (ic->ic_state == IEEE80211_S_RUN) 781 imr->ifm_status |= IFM_ACTIVE; 782 783 /* read current transmission rate from adapter */ 784 val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE) & 0xf; 785 786 /* convert ipw rate to 802.11 rate */ 787 for (i = 0; i < N(rates) && rates[i].val != val; i++); 788 rate = (i < N(rates)) ? rates[i].rate : 0; 789 790 imr->ifm_active |= IFM_IEEE80211_11B; 791 imr->ifm_active |= ieee80211_rate2media(ic, rate, IEEE80211_MODE_11B); 792 switch (ic->ic_opmode) { 793 case IEEE80211_M_STA: 794 break; 795 796 case IEEE80211_M_IBSS: 797 imr->ifm_active |= IFM_IEEE80211_ADHOC; 798 break; 799 800 case IEEE80211_M_MONITOR: 801 imr->ifm_active |= IFM_IEEE80211_MONITOR; 802 break; 803 804 case IEEE80211_M_AHDEMO: 805 case IEEE80211_M_HOSTAP: 806 /* should not get there */ 807 break; 808 } 809 #undef N 810 } 811 812 static int 813 ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, 814 int arg) 815 { 816 struct ifnet *ifp = ic->ic_ifp; 817 struct ipw_softc *sc = ifp->if_softc; 818 struct ieee80211_node *ni; 819 uint8_t macaddr[IEEE80211_ADDR_LEN]; 820 uint32_t len; 821 822 switch (nstate) { 823 case IEEE80211_S_RUN: 824 DELAY(200); /* firmware needs a short delay here */ 825 826 len = IEEE80211_ADDR_LEN; 827 ipw_read_table2(sc, IPW_INFO_CURRENT_BSSID, macaddr, &len); 828 829 ni = ieee80211_find_node(&ic->ic_scan, macaddr); 830 if (ni == NULL) 831 break; 832 833 ieee80211_ref_node(ni); 834 ieee80211_sta_join(ic, ni); 835 ieee80211_node_authorize(ni); 836 837 if (ic->ic_opmode == IEEE80211_M_STA) 838 ieee80211_notify_node_join(ic, ni, 1); 839 break; 840 841 case IEEE80211_S_INIT: 842 case IEEE80211_S_SCAN: 843 case IEEE80211_S_AUTH: 844 case IEEE80211_S_ASSOC: 845 break; 846 } 847 848 ic->ic_state = nstate; 849 return 0; 850 } 851 852 /* 853 * Read 16 bits at address 'addr' from the serial EEPROM. 854 */ 855 static uint16_t 856 ipw_read_prom_word(struct ipw_softc *sc, uint8_t addr) 857 { 858 uint32_t tmp; 859 uint16_t val; 860 int n; 861 862 /* clock C once before the first command */ 863 IPW_EEPROM_CTL(sc, 0); 864 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 865 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 866 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 867 868 /* write start bit (1) */ 869 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 870 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 871 872 /* write READ opcode (10) */ 873 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 874 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 875 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 876 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 877 878 /* write address A7-A0 */ 879 for (n = 7; n >= 0; n--) { 880 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 881 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D)); 882 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 883 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D) | IPW_EEPROM_C); 884 } 885 886 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 887 888 /* read data Q15-Q0 */ 889 val = 0; 890 for (n = 15; n >= 0; n--) { 891 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 892 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 893 tmp = MEM_READ_4(sc, IPW_MEM_EEPROM_CTL); 894 val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n; 895 } 896 897 IPW_EEPROM_CTL(sc, 0); 898 899 /* clear Chip Select and clock C */ 900 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 901 IPW_EEPROM_CTL(sc, 0); 902 IPW_EEPROM_CTL(sc, IPW_EEPROM_C); 903 904 return le16toh(val); 905 } 906 907 static void 908 ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 909 { 910 struct ipw_cmd *cmd; 911 912 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof (struct ipw_cmd), 913 BUS_DMASYNC_POSTREAD); 914 915 cmd = mtod(sbuf->m, struct ipw_cmd *); 916 917 DPRINTFN(2, ("cmd ack'ed (%u, %u, %u, %u, %u)\n", le32toh(cmd->type), 918 le32toh(cmd->subtype), le32toh(cmd->seq), le32toh(cmd->len), 919 le32toh(cmd->status))); 920 921 wakeup(&sc->cmd); 922 } 923 924 static void 925 ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 926 { 927 struct ieee80211com *ic = &sc->sc_ic; 928 struct ifnet *ifp = sc->sc_ic.ic_ifp; 929 uint32_t state; 930 931 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof state, 932 BUS_DMASYNC_POSTREAD); 933 934 state = le32toh(*mtod(sbuf->m, uint32_t *)); 935 936 DPRINTFN(2, ("entering state %u\n", state)); 937 938 switch (state) { 939 case IPW_STATE_ASSOCIATED: 940 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 941 break; 942 943 case IPW_STATE_SCANNING: 944 /* don't leave run state on background scan */ 945 if (ic->ic_state != IEEE80211_S_RUN) 946 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 947 948 ic->ic_flags |= IEEE80211_F_SCAN; 949 break; 950 951 case IPW_STATE_SCAN_COMPLETE: 952 ieee80211_notify_scan_done(ic); 953 ic->ic_flags &= ~IEEE80211_F_SCAN; 954 break; 955 956 case IPW_STATE_ASSOCIATION_LOST: 957 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 958 break; 959 960 case IPW_STATE_RADIO_DISABLED: 961 ic->ic_ifp->if_flags &= ~IFF_UP; 962 ipw_stop(ifp, 1); 963 break; 964 } 965 } 966 967 /* 968 * XXX: Hack to set the current channel to the value advertised in beacons or 969 * probe responses. Only used during AP detection. 970 */ 971 static void 972 ipw_fix_channel(struct ieee80211com *ic, struct mbuf *m) 973 { 974 struct ieee80211_frame *wh; 975 uint8_t subtype; 976 uint8_t *frm, *efrm; 977 978 wh = mtod(m, struct ieee80211_frame *); 979 980 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_MGT) 981 return; 982 983 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 984 985 if (subtype != IEEE80211_FC0_SUBTYPE_BEACON && 986 subtype != IEEE80211_FC0_SUBTYPE_PROBE_RESP) 987 return; 988 989 frm = (uint8_t *)(wh + 1); 990 efrm = mtod(m, uint8_t *) + m->m_len; 991 992 frm += 12; /* skip tstamp, bintval and capinfo fields */ 993 while (frm < efrm) { 994 if (*frm == IEEE80211_ELEMID_DSPARMS) 995 #if IEEE80211_CHAN_MAX < 255 996 if (frm[2] <= IEEE80211_CHAN_MAX) 997 #endif 998 ic->ic_curchan = &ic->ic_channels[frm[2]]; 999 1000 frm += frm[1] + 2; 1001 } 1002 } 1003 1004 static void 1005 ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 1006 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 1007 { 1008 struct ieee80211com *ic = &sc->sc_ic; 1009 struct ifnet *ifp = &sc->sc_if; 1010 struct mbuf *mnew, *m; 1011 struct ieee80211_frame *wh; 1012 struct ieee80211_node *ni; 1013 int error; 1014 1015 DPRINTFN(5, ("received frame len=%u, rssi=%u\n", le32toh(status->len), 1016 status->rssi)); 1017 1018 if (le32toh(status->len) < sizeof (struct ieee80211_frame_min) || 1019 le32toh(status->len) > MCLBYTES) 1020 return; 1021 1022 /* 1023 * Try to allocate a new mbuf for this ring element and load it before 1024 * processing the current mbuf. If the ring element cannot be loaded, 1025 * drop the received packet and reuse the old mbuf. In the unlikely 1026 * case that the old mbuf can't be reloaded either, explicitly panic. 1027 */ 1028 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1029 if (mnew == NULL) { 1030 aprint_error("%s: could not allocate rx mbuf\n", 1031 sc->sc_dev.dv_xname); 1032 ifp->if_ierrors++; 1033 return; 1034 } 1035 1036 MCLGET(mnew, M_DONTWAIT); 1037 if (!(mnew->m_flags & M_EXT)) { 1038 aprint_error("%s: could not allocate rx mbuf cluster\n", 1039 sc->sc_dev.dv_xname); 1040 m_freem(mnew); 1041 ifp->if_ierrors++; 1042 return; 1043 } 1044 1045 mnew->m_pkthdr.len = mnew->m_len = mnew->m_ext.ext_size; 1046 1047 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, le32toh(status->len), 1048 BUS_DMASYNC_POSTREAD); 1049 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1050 1051 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, mnew, 1052 BUS_DMA_READ | BUS_DMA_NOWAIT); 1053 if (error != 0) { 1054 aprint_error("%s: could not load rx buf DMA map\n", 1055 sc->sc_dev.dv_xname); 1056 m_freem(mnew); 1057 1058 /* try to reload the old mbuf */ 1059 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, 1060 sbuf->m, BUS_DMA_READ | BUS_DMA_NOWAIT); 1061 if (error != 0) { 1062 /* very unlikely that it will fail... */ 1063 panic("%s: unable to remap rx buf", 1064 sc->sc_dev.dv_xname); 1065 } 1066 ifp->if_ierrors++; 1067 return; 1068 } 1069 1070 /* 1071 * New mbuf successfully loaded, update Rx ring and continue 1072 * processing. 1073 */ 1074 m = sbuf->m; 1075 sbuf->m = mnew; 1076 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 1077 1078 /* finalize mbuf */ 1079 m->m_pkthdr.rcvif = ifp; 1080 m->m_pkthdr.len = m->m_len = le32toh(status->len); 1081 1082 #if NBPFILTER > 0 1083 if (sc->sc_drvbpf != NULL) { 1084 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 1085 1086 tap->wr_flags = 0; 1087 tap->wr_antsignal = status->rssi; 1088 tap->wr_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 1089 tap->wr_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 1090 1091 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 1092 } 1093 #endif 1094 1095 if (ic->ic_state == IEEE80211_S_SCAN) 1096 ipw_fix_channel(ic, m); 1097 1098 wh = mtod(m, struct ieee80211_frame *); 1099 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 1100 1101 /* send the frame to the 802.11 layer */ 1102 ieee80211_input(ic, m, ni, status->rssi, 0); 1103 1104 /* node is no longer needed */ 1105 ieee80211_free_node(ni); 1106 1107 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, 1108 sbuf->map->dm_mapsize, BUS_DMASYNC_PREREAD); 1109 } 1110 1111 static void 1112 ipw_rx_intr(struct ipw_softc *sc) 1113 { 1114 struct ipw_status *status; 1115 struct ipw_soft_bd *sbd; 1116 struct ipw_soft_buf *sbuf; 1117 uint32_t r, i; 1118 1119 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1120 return; 1121 1122 r = CSR_READ_4(sc, IPW_CSR_RX_READ); 1123 1124 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 1125 1126 /* firmware was killed, stop processing received frames */ 1127 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1128 return; 1129 1130 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 1131 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1132 BUS_DMASYNC_POSTREAD); 1133 1134 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 1135 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 1136 BUS_DMASYNC_POSTREAD); 1137 1138 status = &sc->status_list[i]; 1139 sbd = &sc->srbd_list[i]; 1140 sbuf = sbd->priv; 1141 1142 switch (le16toh(status->code) & 0xf) { 1143 case IPW_STATUS_CODE_COMMAND: 1144 ipw_command_intr(sc, sbuf); 1145 break; 1146 1147 case IPW_STATUS_CODE_NEWSTATE: 1148 ipw_newstate_intr(sc, sbuf); 1149 break; 1150 1151 case IPW_STATUS_CODE_DATA_802_3: 1152 case IPW_STATUS_CODE_DATA_802_11: 1153 ipw_data_intr(sc, status, sbd, sbuf); 1154 break; 1155 1156 case IPW_STATUS_CODE_NOTIFICATION: 1157 DPRINTFN(2, ("received notification\n")); 1158 break; 1159 1160 default: 1161 aprint_error("%s: unknown status code %u\n", 1162 sc->sc_dev.dv_xname, le16toh(status->code)); 1163 } 1164 1165 sbd->bd->flags = 0; 1166 1167 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 1168 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1169 BUS_DMASYNC_PREREAD); 1170 1171 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 1172 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 1173 BUS_DMASYNC_PREREAD); 1174 } 1175 1176 /* Tell the firmware what we have processed */ 1177 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 1178 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 1179 } 1180 1181 static void 1182 ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 1183 { 1184 struct ieee80211com *ic; 1185 struct ipw_soft_hdr *shdr; 1186 struct ipw_soft_buf *sbuf; 1187 1188 switch (sbd->type) { 1189 case IPW_SBD_TYPE_COMMAND: 1190 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 1191 0, sizeof(struct ipw_cmd), BUS_DMASYNC_POSTWRITE); 1192 /* bus_dmamap_unload(sc->sc_dmat, sc->cmd_map); */ 1193 break; 1194 1195 case IPW_SBD_TYPE_HEADER: 1196 shdr = sbd->priv; 1197 bus_dmamap_sync(sc->sc_dmat, sc->hdr_map, 1198 shdr->offset, sizeof(struct ipw_hdr), BUS_DMASYNC_POSTWRITE); 1199 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 1200 break; 1201 1202 case IPW_SBD_TYPE_DATA: 1203 ic = &sc->sc_ic; 1204 sbuf = sbd->priv; 1205 1206 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 1207 0, MCLBYTES, BUS_DMASYNC_POSTWRITE); 1208 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1209 m_freem(sbuf->m); 1210 if (sbuf->ni != NULL) 1211 ieee80211_free_node(sbuf->ni); 1212 /* kill watchdog timer */ 1213 sc->sc_tx_timer = 0; 1214 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 1215 break; 1216 } 1217 sbd->type = IPW_SBD_TYPE_NOASSOC; 1218 } 1219 1220 static void 1221 ipw_tx_intr(struct ipw_softc *sc) 1222 { 1223 struct ifnet *ifp = &sc->sc_if; 1224 struct ipw_soft_bd *sbd; 1225 uint32_t r, i; 1226 1227 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1228 return; 1229 1230 r = CSR_READ_4(sc, IPW_CSR_TX_READ); 1231 1232 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) { 1233 sbd = &sc->stbd_list[i]; 1234 1235 if (sbd->type == IPW_SBD_TYPE_DATA) 1236 ifp->if_opackets++; 1237 1238 ipw_release_sbd(sc, sbd); 1239 sc->txfree++; 1240 } 1241 1242 /* remember what the firmware has processed */ 1243 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 1244 1245 /* Call start() since some buffer descriptors have been released */ 1246 ifp->if_flags &= ~IFF_OACTIVE; 1247 (*ifp->if_start)(ifp); 1248 } 1249 1250 static int 1251 ipw_intr(void *arg) 1252 { 1253 struct ipw_softc *sc = arg; 1254 uint32_t r; 1255 1256 r = CSR_READ_4(sc, IPW_CSR_INTR); 1257 if (r == 0 || r == 0xffffffff) 1258 return 0; 1259 1260 /* Disable interrupts */ 1261 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1262 1263 if (r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR)) { 1264 aprint_error("%s: fatal error\n", 1265 sc->sc_dev.dv_xname); 1266 sc->sc_ic.ic_ifp->if_flags &= ~IFF_UP; 1267 ipw_stop(&sc->sc_if, 1); 1268 } 1269 1270 if (r & IPW_INTR_FW_INIT_DONE) { 1271 if (!(r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR))) 1272 wakeup(sc); 1273 } 1274 1275 if (r & IPW_INTR_RX_TRANSFER) 1276 ipw_rx_intr(sc); 1277 1278 if (r & IPW_INTR_TX_TRANSFER) 1279 ipw_tx_intr(sc); 1280 1281 /* Acknowledge all interrupts */ 1282 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 1283 1284 /* Re-enable interrupts */ 1285 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1286 1287 return 0; 1288 } 1289 1290 /* 1291 * Send a command to the firmware and wait for the acknowledgement. 1292 */ 1293 static int 1294 ipw_cmd(struct ipw_softc *sc, uint32_t type, void *data, uint32_t len) 1295 { 1296 struct ipw_soft_bd *sbd; 1297 1298 sbd = &sc->stbd_list[sc->txcur]; 1299 1300 sc->cmd.type = htole32(type); 1301 sc->cmd.subtype = 0; 1302 sc->cmd.len = htole32(len); 1303 sc->cmd.seq = 0; 1304 1305 (void)memcpy(sc->cmd.data, data, len); 1306 1307 sbd->type = IPW_SBD_TYPE_COMMAND; 1308 sbd->bd->physaddr = htole32(sc->cmd_map->dm_segs[0].ds_addr); 1309 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 1310 sbd->bd->nfrag = 1; 1311 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 1312 IPW_BD_FLAG_TX_LAST_FRAGMENT; 1313 1314 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 0, sizeof (struct ipw_cmd), 1315 BUS_DMASYNC_PREWRITE); 1316 1317 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1318 sc->txcur * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1319 BUS_DMASYNC_PREWRITE); 1320 1321 DPRINTFN(2, ("sending command (%u, %u, %u, %u)\n", type, 0, 0, len)); 1322 1323 /* kick firmware */ 1324 sc->txfree--; 1325 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1326 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1327 1328 /* Wait at most one second for command to complete */ 1329 return tsleep(&sc->cmd, 0, "ipwcmd", hz); 1330 } 1331 1332 static int 1333 ipw_tx_start(struct ifnet *ifp, struct mbuf *m0, struct ieee80211_node *ni) 1334 { 1335 struct ipw_softc *sc = ifp->if_softc; 1336 struct ieee80211com *ic = &sc->sc_ic; 1337 struct ieee80211_frame *wh; 1338 struct ipw_soft_bd *sbd; 1339 struct ipw_soft_hdr *shdr; 1340 struct ipw_soft_buf *sbuf; 1341 struct ieee80211_key *k; 1342 struct mbuf *mnew; 1343 int error, i; 1344 1345 wh = mtod(m0, struct ieee80211_frame *); 1346 1347 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1348 k = ieee80211_crypto_encap(ic, ni, m0); 1349 if (k == NULL) { 1350 m_freem(m0); 1351 return ENOBUFS; 1352 } 1353 1354 /* packet header may have moved, reset our local pointer */ 1355 wh = mtod(m0, struct ieee80211_frame *); 1356 } 1357 1358 #if NBPFILTER > 0 1359 if (sc->sc_drvbpf != NULL) { 1360 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 1361 1362 tap->wt_flags = 0; 1363 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 1364 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 1365 1366 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 1367 } 1368 #endif 1369 1370 shdr = TAILQ_FIRST(&sc->sc_free_shdr); 1371 sbuf = TAILQ_FIRST(&sc->sc_free_sbuf); 1372 KASSERT(shdr != NULL && sbuf != NULL); 1373 1374 shdr->hdr->type = htole32(IPW_HDR_TYPE_SEND); 1375 shdr->hdr->subtype = 0; 1376 shdr->hdr->encrypted = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0; 1377 shdr->hdr->encrypt = 0; 1378 shdr->hdr->keyidx = 0; 1379 shdr->hdr->keysz = 0; 1380 shdr->hdr->fragmentsz = 0; 1381 IEEE80211_ADDR_COPY(shdr->hdr->src_addr, wh->i_addr2); 1382 if (ic->ic_opmode == IEEE80211_M_STA) 1383 IEEE80211_ADDR_COPY(shdr->hdr->dst_addr, wh->i_addr3); 1384 else 1385 IEEE80211_ADDR_COPY(shdr->hdr->dst_addr, wh->i_addr1); 1386 1387 /* trim IEEE802.11 header */ 1388 m_adj(m0, sizeof (struct ieee80211_frame)); 1389 1390 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m0, BUS_DMA_NOWAIT); 1391 if (error != 0 && error != EFBIG) { 1392 aprint_error("%s: could not map mbuf (error %d)\n", 1393 sc->sc_dev.dv_xname, error); 1394 m_freem(m0); 1395 return error; 1396 } 1397 1398 if (error != 0) { 1399 /* too many fragments, linearize */ 1400 1401 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1402 if (mnew == NULL) { 1403 m_freem(m0); 1404 return ENOMEM; 1405 } 1406 1407 M_COPY_PKTHDR(mnew, m0); 1408 1409 /* If the data won't fit in the header, get a cluster */ 1410 if (m0->m_pkthdr.len > MHLEN) { 1411 MCLGET(mnew, M_DONTWAIT); 1412 if (!(mnew->m_flags & M_EXT)) { 1413 m_freem(m0); 1414 m_freem(mnew); 1415 return ENOMEM; 1416 } 1417 } 1418 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(mnew, void *)); 1419 m_freem(m0); 1420 mnew->m_len = mnew->m_pkthdr.len; 1421 m0 = mnew; 1422 1423 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m0, 1424 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1425 if (error != 0) { 1426 aprint_error("%s: could not map mbuf (error %d)\n", 1427 sc->sc_dev.dv_xname, error); 1428 m_freem(m0); 1429 return error; 1430 } 1431 } 1432 1433 TAILQ_REMOVE(&sc->sc_free_sbuf, sbuf, next); 1434 TAILQ_REMOVE(&sc->sc_free_shdr, shdr, next); 1435 1436 sbd = &sc->stbd_list[sc->txcur]; 1437 sbd->type = IPW_SBD_TYPE_HEADER; 1438 sbd->priv = shdr; 1439 sbd->bd->physaddr = htole32(shdr->addr); 1440 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 1441 sbd->bd->nfrag = 1 + sbuf->map->dm_nsegs; 1442 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 1443 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1444 1445 DPRINTFN(5, ("sending tx hdr (%u, %u, %u, %u, )\n", 1446 shdr->hdr->type, shdr->hdr->subtype, shdr->hdr->encrypted, 1447 shdr->hdr->encrypt)); 1448 DPRINTFN(5, ("%s->", ether_sprintf(shdr->hdr->src_addr))); 1449 DPRINTFN(5, ("%s\n", ether_sprintf(shdr->hdr->dst_addr))); 1450 1451 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1452 sc->txcur * sizeof (struct ipw_bd), 1453 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1454 1455 sc->txfree--; 1456 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1457 1458 sbuf->m = m0; 1459 sbuf->ni = ni; 1460 1461 for (i = 0; i < sbuf->map->dm_nsegs; i++) { 1462 sbd = &sc->stbd_list[sc->txcur]; 1463 1464 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[i].ds_addr); 1465 sbd->bd->len = htole32(sbuf->map->dm_segs[i].ds_len); 1466 sbd->bd->nfrag = 0; 1467 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 1468 if (i == sbuf->map->dm_nsegs - 1) { 1469 sbd->type = IPW_SBD_TYPE_DATA; 1470 sbd->priv = sbuf; 1471 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 1472 } else { 1473 sbd->type = IPW_SBD_TYPE_NOASSOC; 1474 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1475 } 1476 1477 DPRINTFN(5, ("sending fragment (%d, %d)\n", i, 1478 (int)sbuf->map->dm_segs[i].ds_len)); 1479 1480 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1481 sc->txcur * sizeof (struct ipw_bd), 1482 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1483 1484 sc->txfree--; 1485 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1486 } 1487 1488 bus_dmamap_sync(sc->sc_dmat, sc->hdr_map, shdr->offset, 1489 sizeof (struct ipw_hdr), BUS_DMASYNC_PREWRITE); 1490 1491 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, MCLBYTES, 1492 BUS_DMASYNC_PREWRITE); 1493 1494 /* Inform firmware about this new packet */ 1495 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1496 1497 return 0; 1498 } 1499 1500 static void 1501 ipw_start(struct ifnet *ifp) 1502 { 1503 struct ipw_softc *sc = ifp->if_softc; 1504 struct ieee80211com *ic = &sc->sc_ic; 1505 struct mbuf *m0; 1506 struct ether_header *eh; 1507 struct ieee80211_node *ni; 1508 1509 1510 if (ic->ic_state != IEEE80211_S_RUN) 1511 return; 1512 1513 for (;;) { 1514 IF_DEQUEUE(&ifp->if_snd, m0); 1515 if (m0 == NULL) 1516 break; 1517 1518 if (sc->txfree < 1 + IPW_MAX_NSEG) { 1519 IF_PREPEND(&ifp->if_snd, m0); 1520 ifp->if_flags |= IFF_OACTIVE; 1521 break; 1522 } 1523 1524 if (m0->m_len < sizeof (struct ether_header) && 1525 (m0 = m_pullup(m0, sizeof (struct ether_header))) == NULL) 1526 continue; 1527 1528 eh = mtod(m0, struct ether_header *); 1529 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1530 if (ni == NULL) { 1531 m_freem(m0); 1532 continue; 1533 } 1534 1535 #if NBPFILTER > 0 1536 if (ifp->if_bpf != NULL) 1537 bpf_mtap(ifp->if_bpf, m0); 1538 #endif 1539 1540 m0 = ieee80211_encap(ic, m0, ni); 1541 if (m0 == NULL) { 1542 ieee80211_free_node(ni); 1543 continue; 1544 } 1545 1546 #if NBPFILTER > 0 1547 if (ic->ic_rawbpf != NULL) 1548 bpf_mtap(ic->ic_rawbpf, m0); 1549 #endif 1550 1551 if (ipw_tx_start(ifp, m0, ni) != 0) { 1552 ieee80211_free_node(ni); 1553 ifp->if_oerrors++; 1554 break; 1555 } 1556 1557 /* start watchdog timer */ 1558 sc->sc_tx_timer = 5; 1559 ifp->if_timer = 1; 1560 } 1561 } 1562 1563 static void 1564 ipw_watchdog(struct ifnet *ifp) 1565 { 1566 struct ipw_softc *sc = ifp->if_softc; 1567 1568 ifp->if_timer = 0; 1569 1570 if (sc->sc_tx_timer > 0) { 1571 if (--sc->sc_tx_timer == 0) { 1572 aprint_error("%s: device timeout\n", 1573 sc->sc_dev.dv_xname); 1574 ifp->if_oerrors++; 1575 ifp->if_flags &= ~IFF_UP; 1576 ipw_stop(ifp, 1); 1577 return; 1578 } 1579 ifp->if_timer = 1; 1580 } 1581 1582 ieee80211_watchdog(&sc->sc_ic); 1583 } 1584 1585 static int 1586 ipw_get_table1(struct ipw_softc *sc, uint32_t *tbl) 1587 { 1588 uint32_t addr, size, i; 1589 1590 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1591 return ENOTTY; 1592 1593 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, sc->table1_base); 1594 1595 size = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 1596 if (suword(tbl, size) != 0) 1597 return EFAULT; 1598 1599 for (i = 1, ++tbl; i < size; i++, tbl++) { 1600 addr = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 1601 if (suword(tbl, MEM_READ_4(sc, addr)) != 0) 1602 return EFAULT; 1603 } 1604 return 0; 1605 } 1606 1607 static int 1608 ipw_get_radio(struct ipw_softc *sc, int *ret) 1609 { 1610 uint32_t addr; 1611 1612 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1613 return ENOTTY; 1614 1615 addr = ipw_read_table1(sc, IPW_INFO_EEPROM_ADDRESS); 1616 if ((MEM_READ_4(sc, addr + 32) >> 24) & 1) { 1617 suword(ret, -1); 1618 return 0; 1619 } 1620 1621 if (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED) 1622 suword(ret, 0); 1623 else 1624 suword(ret, 1); 1625 1626 return 0; 1627 } 1628 1629 static int 1630 ipw_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1631 { 1632 #define IS_RUNNING(ifp) \ 1633 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 1634 1635 struct ipw_softc *sc = ifp->if_softc; 1636 struct ieee80211com *ic = &sc->sc_ic; 1637 struct ifreq *ifr = (struct ifreq *)data; 1638 int s, error = 0; 1639 1640 s = splnet(); 1641 1642 switch (cmd) { 1643 case SIOCSIFFLAGS: 1644 if (ifp->if_flags & IFF_UP) { 1645 if (!(ifp->if_flags & IFF_RUNNING)) 1646 ipw_init(ifp); 1647 } else { 1648 if (ifp->if_flags & IFF_RUNNING) 1649 ipw_stop(ifp, 1); 1650 } 1651 break; 1652 1653 case SIOCADDMULTI: 1654 case SIOCDELMULTI: 1655 /* XXX no h/w multicast filter? --dyoung */ 1656 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1657 /* setup multicast filter, etc */ 1658 error = 0; 1659 } 1660 break; 1661 1662 case SIOCGTABLE1: 1663 error = ipw_get_table1(sc, (uint32_t *)ifr->ifr_data); 1664 break; 1665 1666 case SIOCGRADIO: 1667 error = ipw_get_radio(sc, (int *)ifr->ifr_data); 1668 break; 1669 1670 case SIOCSIFMEDIA: 1671 if (ifr->ifr_media & IFM_IEEE80211_ADHOC) 1672 strlcpy(sc->sc_fwname, "ipw2100-1.2-i.fw", 1673 sizeof(sc->sc_fwname)); 1674 else if (ifr->ifr_media & IFM_IEEE80211_MONITOR) 1675 strlcpy(sc->sc_fwname, "ipw2100-1.2-p.fw", 1676 sizeof(sc->sc_fwname)); 1677 else 1678 strlcpy(sc->sc_fwname, "ipw2100-1.2.fw", 1679 sizeof(sc->sc_fwname)); 1680 1681 ipw_free_firmware(sc); 1682 /* FALLTRHOUGH */ 1683 default: 1684 error = ieee80211_ioctl(&sc->sc_ic, cmd, data); 1685 if (error != ENETRESET) 1686 break; 1687 1688 if (error == ENETRESET) { 1689 if (IS_RUNNING(ifp) && 1690 (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)) 1691 ipw_init(ifp); 1692 error = 0; 1693 } 1694 1695 } 1696 1697 splx(s); 1698 return error; 1699 #undef IS_RUNNING 1700 } 1701 1702 static uint32_t 1703 ipw_read_table1(struct ipw_softc *sc, uint32_t off) 1704 { 1705 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 1706 } 1707 1708 static void 1709 ipw_write_table1(struct ipw_softc *sc, uint32_t off, uint32_t info) 1710 { 1711 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 1712 } 1713 1714 static int 1715 ipw_read_table2(struct ipw_softc *sc, uint32_t off, void *buf, uint32_t *len) 1716 { 1717 uint32_t addr, info; 1718 uint16_t count, size; 1719 uint32_t total; 1720 1721 /* addr[4] + count[2] + size[2] */ 1722 addr = MEM_READ_4(sc, sc->table2_base + off); 1723 info = MEM_READ_4(sc, sc->table2_base + off + 4); 1724 1725 count = info >> 16; 1726 size = info & 0xffff; 1727 total = count * size; 1728 1729 if (total > *len) { 1730 *len = total; 1731 return EINVAL; 1732 } 1733 1734 *len = total; 1735 ipw_read_mem_1(sc, addr, buf, total); 1736 1737 return 0; 1738 } 1739 1740 static void 1741 ipw_stop_master(struct ipw_softc *sc) 1742 { 1743 int ntries; 1744 1745 /* disable interrupts */ 1746 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1747 1748 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1749 for (ntries = 0; ntries < 50; ntries++) { 1750 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1751 break; 1752 DELAY(10); 1753 } 1754 if (ntries == 50) 1755 aprint_error("%s: timeout waiting for master\n", 1756 sc->sc_dev.dv_xname); 1757 1758 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1759 IPW_RST_PRINCETON_RESET); 1760 1761 sc->flags &= ~IPW_FLAG_FW_INITED; 1762 } 1763 1764 static int 1765 ipw_reset(struct ipw_softc *sc) 1766 { 1767 int ntries; 1768 1769 ipw_stop_master(sc); 1770 1771 /* move adapter to D0 state */ 1772 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1773 IPW_CTL_INIT); 1774 1775 /* wait for clock stabilization */ 1776 for (ntries = 0; ntries < 1000; ntries++) { 1777 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY) 1778 break; 1779 DELAY(200); 1780 } 1781 if (ntries == 1000) 1782 return EIO; 1783 1784 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1785 IPW_RST_SW_RESET); 1786 1787 DELAY(10); 1788 1789 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1790 IPW_CTL_INIT); 1791 1792 return 0; 1793 } 1794 1795 /* 1796 * Upload the microcode to the device. 1797 */ 1798 static int 1799 ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size) 1800 { 1801 int ntries; 1802 1803 MEM_WRITE_4(sc, 0x3000e0, 0x80000000); 1804 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1805 1806 MEM_WRITE_2(sc, 0x220000, 0x0703); 1807 MEM_WRITE_2(sc, 0x220000, 0x0707); 1808 1809 MEM_WRITE_1(sc, 0x210014, 0x72); 1810 MEM_WRITE_1(sc, 0x210014, 0x72); 1811 1812 MEM_WRITE_1(sc, 0x210000, 0x40); 1813 MEM_WRITE_1(sc, 0x210000, 0x00); 1814 MEM_WRITE_1(sc, 0x210000, 0x40); 1815 1816 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1817 1818 MEM_WRITE_1(sc, 0x210000, 0x00); 1819 MEM_WRITE_1(sc, 0x210000, 0x00); 1820 MEM_WRITE_1(sc, 0x210000, 0x80); 1821 1822 MEM_WRITE_2(sc, 0x220000, 0x0703); 1823 MEM_WRITE_2(sc, 0x220000, 0x0707); 1824 1825 MEM_WRITE_1(sc, 0x210014, 0x72); 1826 MEM_WRITE_1(sc, 0x210014, 0x72); 1827 1828 MEM_WRITE_1(sc, 0x210000, 0x00); 1829 MEM_WRITE_1(sc, 0x210000, 0x80); 1830 1831 for (ntries = 0; ntries < 10; ntries++) { 1832 if (MEM_READ_1(sc, 0x210000) & 1) 1833 break; 1834 DELAY(10); 1835 } 1836 if (ntries == 10) { 1837 aprint_error("%s: timeout waiting for ucode to initialize\n", 1838 sc->sc_dev.dv_xname); 1839 return EIO; 1840 } 1841 1842 MEM_WRITE_4(sc, 0x3000e0, 0); 1843 1844 return 0; 1845 } 1846 1847 /* set of macros to handle unaligned little endian data in firmware image */ 1848 #define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1849 #define GETLE16(p) ((p)[0] | (p)[1] << 8) 1850 static int 1851 ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size) 1852 { 1853 u_char *p, *end; 1854 uint32_t dst; 1855 uint16_t len; 1856 int error; 1857 1858 p = fw; 1859 end = fw + size; 1860 while (p < end) { 1861 dst = GETLE32(p); p += 4; 1862 len = GETLE16(p); p += 2; 1863 1864 ipw_write_mem_1(sc, dst, p, len); 1865 p += len; 1866 } 1867 1868 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1869 IPW_IO_LED_OFF); 1870 1871 /* enable interrupts */ 1872 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1873 1874 /* kick the firmware */ 1875 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1876 1877 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1878 IPW_CTL_ALLOW_STANDBY); 1879 1880 /* wait at most one second for firmware initialization to complete */ 1881 if ((error = tsleep(sc, 0, "ipwinit", hz)) != 0) { 1882 aprint_error("%s: timeout waiting for firmware initialization " 1883 "to complete\n", sc->sc_dev.dv_xname); 1884 return error; 1885 } 1886 1887 CSR_WRITE_4(sc, IPW_CSR_IO, CSR_READ_4(sc, IPW_CSR_IO) | 1888 IPW_IO_GPIO1_MASK | IPW_IO_GPIO3_MASK); 1889 1890 return 0; 1891 } 1892 1893 /* 1894 * Store firmware into kernel memory so we can download it when we need to, 1895 * e.g when the adapter wakes up from suspend mode. 1896 */ 1897 static int 1898 ipw_cache_firmware(struct ipw_softc *sc) 1899 { 1900 struct ipw_firmware *fw = &sc->fw; 1901 struct ipw_firmware_hdr hdr; 1902 firmware_handle_t fwh; 1903 off_t fwsz, p; 1904 int error; 1905 1906 ipw_free_firmware(sc); 1907 1908 if ((error = firmware_open("if_ipw", sc->sc_fwname, &fwh)) != 0) 1909 goto fail0; 1910 1911 fwsz = firmware_get_size(fwh); 1912 1913 if (fwsz < sizeof(hdr)) 1914 goto fail2; 1915 1916 if ((error = firmware_read(fwh, 0, &hdr, sizeof(hdr))) != 0) 1917 goto fail2; 1918 1919 fw->main_size = le32toh(hdr.main_size); 1920 fw->ucode_size = le32toh(hdr.ucode_size); 1921 1922 fw->main = firmware_malloc(fw->main_size); 1923 if (fw->main == NULL) { 1924 error = ENOMEM; 1925 goto fail1; 1926 } 1927 1928 fw->ucode = firmware_malloc(fw->ucode_size); 1929 if (fw->ucode == NULL) { 1930 error = ENOMEM; 1931 goto fail2; 1932 } 1933 1934 p = sizeof(hdr); 1935 if ((error = firmware_read(fwh, p, fw->main, fw->main_size)) != 0) 1936 goto fail3; 1937 1938 p += fw->main_size; 1939 if ((error = firmware_read(fwh, p, fw->ucode, fw->ucode_size)) != 0) 1940 goto fail3; 1941 1942 DPRINTF(("Firmware cached: main %u, ucode %u\n", fw->main_size, 1943 fw->ucode_size)); 1944 1945 sc->flags |= IPW_FLAG_FW_CACHED; 1946 1947 firmware_close(fwh); 1948 1949 return 0; 1950 1951 fail3: firmware_free(fw->ucode, 0); 1952 fail2: firmware_free(fw->main, 0); 1953 fail1: firmware_close(fwh); 1954 fail0: 1955 return error; 1956 } 1957 1958 static void 1959 ipw_free_firmware(struct ipw_softc *sc) 1960 { 1961 if (!(sc->flags & IPW_FLAG_FW_CACHED)) 1962 return; 1963 1964 firmware_free(sc->fw.main, 0); 1965 firmware_free(sc->fw.ucode, 0); 1966 1967 sc->flags &= ~IPW_FLAG_FW_CACHED; 1968 } 1969 1970 static int 1971 ipw_config(struct ipw_softc *sc) 1972 { 1973 struct ieee80211com *ic = &sc->sc_ic; 1974 struct ifnet *ifp = &sc->sc_if; 1975 struct ipw_security security; 1976 struct ieee80211_key *k; 1977 struct ipw_wep_key wepkey; 1978 struct ipw_scan_options options; 1979 struct ipw_configuration config; 1980 uint32_t data; 1981 int error, i; 1982 1983 switch (ic->ic_opmode) { 1984 case IEEE80211_M_STA: 1985 case IEEE80211_M_HOSTAP: 1986 data = htole32(IPW_MODE_BSS); 1987 break; 1988 1989 case IEEE80211_M_IBSS: 1990 case IEEE80211_M_AHDEMO: 1991 data = htole32(IPW_MODE_IBSS); 1992 break; 1993 1994 case IEEE80211_M_MONITOR: 1995 data = htole32(IPW_MODE_MONITOR); 1996 break; 1997 } 1998 DPRINTF(("Setting mode to %u\n", le32toh(data))); 1999 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 2000 if (error != 0) 2001 return error; 2002 2003 if (ic->ic_opmode == IEEE80211_M_IBSS || 2004 ic->ic_opmode == IEEE80211_M_MONITOR) { 2005 data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); 2006 DPRINTF(("Setting channel to %u\n", le32toh(data))); 2007 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 2008 if (error != 0) 2009 return error; 2010 } 2011 2012 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2013 DPRINTF(("Enabling adapter\n")); 2014 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 2015 } 2016 2017 DPRINTF(("Setting MAC to %s\n", ether_sprintf(ic->ic_myaddr))); 2018 if_set_sadl(ifp, ic->ic_myaddr, IEEE80211_ADDR_LEN); 2019 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 2020 IEEE80211_ADDR_LEN); 2021 if (error != 0) 2022 return error; 2023 2024 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 2025 IPW_CFG_PREAMBLE_AUTO | IPW_CFG_802_1x_ENABLE); 2026 2027 if (ic->ic_opmode == IEEE80211_M_IBSS) 2028 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 2029 if (ifp->if_flags & IFF_PROMISC) 2030 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 2031 config.bss_chan = htole32(0x3fff); /* channels 1-14 */ 2032 config.ibss_chan = htole32(0x7ff); /* channels 1-11 */ 2033 DPRINTF(("Setting adapter configuration 0x%08x\n", config.flags)); 2034 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 2035 if (error != 0) 2036 return error; 2037 2038 data = htole32(0x3); /* 1, 2 */ 2039 DPRINTF(("Setting basic tx rates to 0x%x\n", le32toh(data))); 2040 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 2041 if (error != 0) 2042 return error; 2043 2044 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 2045 DPRINTF(("Setting tx rates to 0x%x\n", le32toh(data))); 2046 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 2047 if (error != 0) 2048 return error; 2049 2050 data = htole32(IPW_POWER_MODE_CAM); 2051 DPRINTF(("Setting power mode to %u\n", le32toh(data))); 2052 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 2053 if (error != 0) 2054 return error; 2055 2056 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2057 data = htole32(32); /* default value */ 2058 DPRINTF(("Setting tx power index to %u\n", le32toh(data))); 2059 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 2060 sizeof data); 2061 if (error != 0) 2062 return error; 2063 } 2064 2065 data = htole32(ic->ic_rtsthreshold); 2066 DPRINTF(("Setting RTS threshold to %u\n", le32toh(data))); 2067 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 2068 if (error != 0) 2069 return error; 2070 2071 data = htole32(ic->ic_fragthreshold); 2072 DPRINTF(("Setting frag threshold to %u\n", le32toh(data))); 2073 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 2074 if (error != 0) 2075 return error; 2076 2077 #ifdef IPW_DEBUG 2078 if (ipw_debug > 0) { 2079 printf("Setting ESSID to "); 2080 ieee80211_print_essid(ic->ic_des_essid, ic->ic_des_esslen); 2081 printf("\n"); 2082 } 2083 #endif 2084 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ic->ic_des_essid, 2085 ic->ic_des_esslen); 2086 if (error != 0) 2087 return error; 2088 2089 /* no mandatory BSSID */ 2090 DPRINTF(("Setting mandatory BSSID to null\n")); 2091 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 2092 if (error != 0) 2093 return error; 2094 2095 if (ic->ic_flags & IEEE80211_F_DESBSSID) { 2096 DPRINTF(("Setting desired BSSID to %s\n", 2097 ether_sprintf(ic->ic_des_bssid))); 2098 error = ipw_cmd(sc, IPW_CMD_SET_DESIRED_BSSID, 2099 ic->ic_des_bssid, IEEE80211_ADDR_LEN); 2100 if (error != 0) 2101 return error; 2102 } 2103 2104 (void)memset(&security, 0, sizeof(security)); 2105 security.authmode = (ic->ic_bss->ni_authmode == IEEE80211_AUTH_SHARED) ? 2106 IPW_AUTH_SHARED : IPW_AUTH_OPEN; 2107 security.ciphers = htole32(IPW_CIPHER_NONE); 2108 DPRINTF(("Setting authmode to %u\n", security.authmode)); 2109 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 2110 sizeof security); 2111 if (error != 0) 2112 return error; 2113 2114 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 2115 k = ic->ic_crypto.cs_nw_keys; 2116 for (i = 0; i < IEEE80211_WEP_NKID; i++, k++) { 2117 if (k->wk_keylen == 0) 2118 continue; 2119 2120 wepkey.idx = i; 2121 wepkey.len = k->wk_keylen; 2122 memset(wepkey.key, 0, sizeof(wepkey.key)); 2123 memcpy(wepkey.key, k->wk_key, k->wk_keylen); 2124 DPRINTF(("Setting wep key index %u len %u\n", 2125 wepkey.idx, wepkey.len)); 2126 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY, &wepkey, 2127 sizeof wepkey); 2128 if (error != 0) 2129 return error; 2130 } 2131 2132 data = htole32(ic->ic_crypto.cs_def_txkey); 2133 DPRINTF(("Setting tx key index to %u\n", le32toh(data))); 2134 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY_INDEX, &data, 2135 sizeof data); 2136 if (error != 0) 2137 return error; 2138 } 2139 2140 data = htole32((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) ? IPW_WEPON : 0); 2141 DPRINTF(("Setting wep flags to 0x%x\n", le32toh(data))); 2142 error = ipw_cmd(sc, IPW_CMD_SET_WEP_FLAGS, &data, sizeof data); 2143 if (error != 0) 2144 return error; 2145 2146 #if 0 2147 struct ipw_wpa_ie ie; 2148 2149 memset(&ie, 0 sizeof(ie)); 2150 ie.len = htole32(sizeof (struct ieee80211_ie_wpa)); 2151 DPRINTF(("Setting wpa ie\n")); 2152 error = ipw_cmd(sc, IPW_CMD_SET_WPA_IE, &ie, sizeof ie); 2153 if (error != 0) 2154 return error; 2155 #endif 2156 2157 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2158 data = htole32(ic->ic_bintval); 2159 DPRINTF(("Setting beacon interval to %u\n", le32toh(data))); 2160 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 2161 sizeof data); 2162 if (error != 0) 2163 return error; 2164 } 2165 2166 options.flags = 0; 2167 options.channels = htole32(0x3fff); /* scan channels 1-14 */ 2168 DPRINTF(("Setting scan options to 0x%x\n", le32toh(options.flags))); 2169 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &options, sizeof options); 2170 if (error != 0) 2171 return error; 2172 2173 /* finally, enable adapter (start scanning for an access point) */ 2174 DPRINTF(("Enabling adapter\n")); 2175 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 2176 } 2177 2178 static int 2179 ipw_init(struct ifnet *ifp) 2180 { 2181 struct ipw_softc *sc = ifp->if_softc; 2182 struct ipw_firmware *fw = &sc->fw; 2183 2184 if (!(sc->flags & IPW_FLAG_FW_CACHED)) { 2185 if (ipw_cache_firmware(sc) != 0) { 2186 aprint_error("%s: could not cache the firmware (%s)\n", 2187 sc->sc_dev.dv_xname, sc->sc_fwname); 2188 goto fail; 2189 } 2190 } 2191 2192 ipw_stop(ifp, 0); 2193 2194 if (ipw_reset(sc) != 0) { 2195 aprint_error("%s: could not reset adapter\n", 2196 sc->sc_dev.dv_xname); 2197 goto fail; 2198 } 2199 2200 if (ipw_load_ucode(sc, fw->ucode, fw->ucode_size) != 0) { 2201 aprint_error("%s: could not load microcode\n", 2202 sc->sc_dev.dv_xname); 2203 goto fail; 2204 } 2205 2206 ipw_stop_master(sc); 2207 2208 /* 2209 * Setup tx, rx and status rings. 2210 */ 2211 sc->txold = IPW_NTBD - 1; 2212 sc->txcur = 0; 2213 sc->txfree = IPW_NTBD - 2; 2214 sc->rxcur = IPW_NRBD - 1; 2215 2216 CSR_WRITE_4(sc, IPW_CSR_TX_BASE, sc->tbd_map->dm_segs[0].ds_addr); 2217 CSR_WRITE_4(sc, IPW_CSR_TX_SIZE, IPW_NTBD); 2218 CSR_WRITE_4(sc, IPW_CSR_TX_READ, 0); 2219 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 2220 2221 CSR_WRITE_4(sc, IPW_CSR_RX_BASE, sc->rbd_map->dm_segs[0].ds_addr); 2222 CSR_WRITE_4(sc, IPW_CSR_RX_SIZE, IPW_NRBD); 2223 CSR_WRITE_4(sc, IPW_CSR_RX_READ, 0); 2224 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 2225 2226 CSR_WRITE_4(sc, IPW_CSR_STATUS_BASE, sc->status_map->dm_segs[0].ds_addr); 2227 2228 if (ipw_load_firmware(sc, fw->main, fw->main_size) != 0) { 2229 aprint_error("%s: could not load firmware\n", 2230 sc->sc_dev.dv_xname); 2231 goto fail; 2232 } 2233 2234 sc->flags |= IPW_FLAG_FW_INITED; 2235 2236 /* retrieve information tables base addresses */ 2237 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 2238 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 2239 2240 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 2241 2242 if (ipw_config(sc) != 0) { 2243 aprint_error("%s: device configuration failed\n", 2244 sc->sc_dev.dv_xname); 2245 goto fail; 2246 } 2247 2248 ifp->if_flags &= ~IFF_OACTIVE; 2249 ifp->if_flags |= IFF_RUNNING; 2250 2251 return 0; 2252 2253 fail: ifp->if_flags &= ~IFF_UP; 2254 ipw_stop(ifp, 0); 2255 2256 return EIO; 2257 } 2258 2259 static void 2260 ipw_stop(struct ifnet *ifp, int disable) 2261 { 2262 struct ipw_softc *sc = ifp->if_softc; 2263 struct ieee80211com *ic = &sc->sc_ic; 2264 int i; 2265 2266 ipw_stop_master(sc); 2267 2268 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 2269 2270 /* 2271 * Release tx buffers. 2272 */ 2273 for (i = 0; i < IPW_NTBD; i++) 2274 ipw_release_sbd(sc, &sc->stbd_list[i]); 2275 2276 sc->sc_tx_timer = 0; 2277 ifp->if_timer = 0; 2278 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2279 2280 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2281 } 2282 2283 static void 2284 ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2285 bus_size_t count) 2286 { 2287 for (; count > 0; offset++, datap++, count--) { 2288 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2289 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 2290 } 2291 } 2292 2293 static void 2294 ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2295 bus_size_t count) 2296 { 2297 for (; count > 0; offset++, datap++, count--) { 2298 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2299 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 2300 } 2301 } 2302
Indexes created Tue Sep 30 17:09:57 GMT 2025