if_ipw.c revision 1.37
1 /* $NetBSD: if_ipw.c,v 1.37 2008/02/29 06:13:39 dyoung Exp $ */ 2 /* FreeBSD: src/sys/dev/ipw/if_ipw.c,v 1.15 2005/11/13 17:17:40 damien Exp */ 3 4 /*- 5 * Copyright (c) 2004, 2005 6 * Damien Bergamini <damien.bergamini (at) free.fr>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: if_ipw.c,v 1.37 2008/02/29 06:13:39 dyoung Exp $"); 33 34 /*- 35 * Intel(R) PRO/Wireless 2100 MiniPCI driver 36 * http://www.intel.com/network/connectivity/products/wireless/prowireless_mobile.htm 37 */ 38 39 #include "bpfilter.h" 40 41 #include <sys/param.h> 42 #include <sys/sockio.h> 43 #include <sys/sysctl.h> 44 #include <sys/mbuf.h> 45 #include <sys/kernel.h> 46 #include <sys/socket.h> 47 #include <sys/systm.h> 48 #include <sys/malloc.h> 49 #include <sys/conf.h> 50 51 #include <sys/bus.h> 52 #include <machine/endian.h> 53 #include <sys/intr.h> 54 55 #include <dev/pci/pcireg.h> 56 #include <dev/pci/pcivar.h> 57 #include <dev/pci/pcidevs.h> 58 59 #if NBPFILTER > 0 60 #include <net/bpf.h> 61 #endif 62 #include <net/if.h> 63 #include <net/if_arp.h> 64 #include <net/if_dl.h> 65 #include <net/if_ether.h> 66 #include <net/if_media.h> 67 #include <net/if_types.h> 68 69 #include <net80211/ieee80211_var.h> 70 #include <net80211/ieee80211_radiotap.h> 71 72 #include <netinet/in.h> 73 #include <netinet/in_systm.h> 74 #include <netinet/in_var.h> 75 #include <netinet/ip.h> 76 77 #include <dev/firmload.h> 78 79 #include <dev/pci/if_ipwreg.h> 80 #include <dev/pci/if_ipwvar.h> 81 82 #ifdef IPW_DEBUG 83 #define DPRINTF(x) if (ipw_debug > 0) printf x 84 #define DPRINTFN(n, x) if (ipw_debug >= (n)) printf x 85 int ipw_debug = 0; 86 #else 87 #define DPRINTF(x) 88 #define DPRINTFN(n, x) 89 #endif 90 91 static int ipw_dma_alloc(struct ipw_softc *); 92 static void ipw_release(struct ipw_softc *); 93 static int ipw_match(struct device *, struct cfdata *, void *); 94 static void ipw_attach(struct device *, struct device *, void *); 95 static int ipw_detach(struct device *, int); 96 97 static bool ipw_resume(device_t PMF_FN_PROTO); 98 99 static int ipw_media_change(struct ifnet *); 100 static void ipw_media_status(struct ifnet *, struct ifmediareq *); 101 static int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 102 static uint16_t ipw_read_prom_word(struct ipw_softc *, uint8_t); 103 static void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 104 static void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 105 static void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 106 struct ipw_soft_bd *, struct ipw_soft_buf *); 107 static void ipw_rx_intr(struct ipw_softc *); 108 static void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 109 static void ipw_tx_intr(struct ipw_softc *); 110 static int ipw_intr(void *); 111 static int ipw_cmd(struct ipw_softc *, uint32_t, void *, uint32_t); 112 static int ipw_tx_start(struct ifnet *, struct mbuf *, 113 struct ieee80211_node *); 114 static void ipw_start(struct ifnet *); 115 static void ipw_watchdog(struct ifnet *); 116 static int ipw_ioctl(struct ifnet *, u_long, void *); 117 static int ipw_get_table1(struct ipw_softc *, uint32_t *); 118 static int ipw_get_radio(struct ipw_softc *, int *); 119 static void ipw_stop_master(struct ipw_softc *); 120 static int ipw_reset(struct ipw_softc *); 121 static int ipw_load_ucode(struct ipw_softc *, u_char *, int); 122 static int ipw_load_firmware(struct ipw_softc *, u_char *, int); 123 static int ipw_cache_firmware(struct ipw_softc *); 124 static void ipw_free_firmware(struct ipw_softc *); 125 static int ipw_config(struct ipw_softc *); 126 static int ipw_init(struct ifnet *); 127 static void ipw_stop(struct ifnet *, int); 128 static uint32_t ipw_read_table1(struct ipw_softc *, uint32_t); 129 static void ipw_write_table1(struct ipw_softc *, uint32_t, uint32_t); 130 static int ipw_read_table2(struct ipw_softc *, uint32_t, void *, uint32_t *); 131 static void ipw_read_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 132 bus_size_t); 133 static void ipw_write_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 134 bus_size_t); 135 136 /* 137 * Supported rates for 802.11b mode (in 500Kbps unit). 138 */ 139 static const struct ieee80211_rateset ipw_rateset_11b = 140 { 4, { 2, 4, 11, 22 } }; 141 142 static inline uint8_t 143 MEM_READ_1(struct ipw_softc *sc, uint32_t addr) 144 { 145 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 146 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); 147 } 148 149 static inline uint32_t 150 MEM_READ_4(struct ipw_softc *sc, uint32_t addr) 151 { 152 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 153 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); 154 } 155 156 CFATTACH_DECL(ipw, sizeof (struct ipw_softc), ipw_match, ipw_attach, 157 ipw_detach, NULL); 158 159 static int 160 ipw_match(struct device *parent, struct cfdata *match, 161 void *aux) 162 { 163 struct pci_attach_args *pa = aux; 164 165 if (PCI_VENDOR (pa->pa_id) == PCI_VENDOR_INTEL && 166 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_PRO_WL_2100) 167 return 1; 168 169 return 0; 170 } 171 172 /* Base Address Register */ 173 #define IPW_PCI_BAR0 0x10 174 175 static void 176 ipw_attach(struct device *parent, struct device *self, void *aux) 177 { 178 struct ipw_softc *sc = (struct ipw_softc *)self; 179 struct ieee80211com *ic = &sc->sc_ic; 180 struct ifnet *ifp = &sc->sc_if; 181 struct pci_attach_args *pa = aux; 182 const char *intrstr; 183 char devinfo[256]; 184 bus_space_tag_t memt; 185 bus_space_handle_t memh; 186 bus_addr_t base; 187 pci_intr_handle_t ih; 188 uint32_t data; 189 uint16_t val; 190 int i, revision, error; 191 192 sc->sc_pct = pa->pa_pc; 193 sc->sc_pcitag = pa->pa_tag; 194 195 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof devinfo); 196 revision = PCI_REVISION(pa->pa_class); 197 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, revision); 198 199 /* enable bus-mastering */ 200 data = pci_conf_read(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG); 201 data |= PCI_COMMAND_MASTER_ENABLE; 202 pci_conf_write(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG, data); 203 204 pci_disable_retry(sc->sc_pct, sc->sc_pcitag); 205 206 /* map the register window */ 207 error = pci_mapreg_map(pa, IPW_PCI_BAR0, PCI_MAPREG_TYPE_MEM | 208 PCI_MAPREG_MEM_TYPE_32BIT, 0, &memt, &memh, &base, &sc->sc_sz); 209 if (error != 0) { 210 aprint_error("%s: could not map memory space\n", 211 sc->sc_dev.dv_xname); 212 return; 213 } 214 215 sc->sc_st = memt; 216 sc->sc_sh = memh; 217 sc->sc_dmat = pa->pa_dmat; 218 strlcpy(sc->sc_fwname, "ipw2100-1.2.fw", sizeof(sc->sc_fwname)); 219 220 /* disable interrupts */ 221 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 222 223 if (pci_intr_map(pa, &ih) != 0) { 224 aprint_error("%s: could not map interrupt\n", 225 sc->sc_dev.dv_xname); 226 return; 227 } 228 229 intrstr = pci_intr_string(sc->sc_pct, ih); 230 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, ipw_intr, sc); 231 if (sc->sc_ih == NULL) { 232 aprint_error("%s: could not establish interrupt", 233 sc->sc_dev.dv_xname); 234 if (intrstr != NULL) 235 aprint_error(" at %s", intrstr); 236 aprint_error("\n"); 237 return; 238 } 239 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 240 241 if (ipw_reset(sc) != 0) { 242 aprint_error("%s: could not reset adapter\n", 243 sc->sc_dev.dv_xname); 244 goto fail; 245 } 246 247 if (ipw_dma_alloc(sc) != 0) { 248 aprint_error("%s: could not allocate DMA resources\n", 249 sc->sc_dev.dv_xname); 250 goto fail; 251 } 252 253 ifp->if_softc = sc; 254 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 255 ifp->if_init = ipw_init; 256 ifp->if_stop = ipw_stop; 257 ifp->if_ioctl = ipw_ioctl; 258 ifp->if_start = ipw_start; 259 ifp->if_watchdog = ipw_watchdog; 260 IFQ_SET_READY(&ifp->if_snd); 261 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 262 263 ic->ic_ifp = ifp; 264 ic->ic_phytype = IEEE80211_T_DS; 265 ic->ic_opmode = IEEE80211_M_STA; 266 ic->ic_state = IEEE80211_S_INIT; 267 268 /* set device capabilities */ 269 ic->ic_caps = 270 IEEE80211_C_SHPREAMBLE /* short preamble supported */ 271 | IEEE80211_C_TXPMGT /* tx power management */ 272 | IEEE80211_C_IBSS /* ibss mode */ 273 | IEEE80211_C_MONITOR /* monitor mode */ 274 ; 275 276 /* read MAC address from EEPROM */ 277 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0); 278 ic->ic_myaddr[0] = val >> 8; 279 ic->ic_myaddr[1] = val & 0xff; 280 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 1); 281 ic->ic_myaddr[2] = val >> 8; 282 ic->ic_myaddr[3] = val & 0xff; 283 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 2); 284 ic->ic_myaddr[4] = val >> 8; 285 ic->ic_myaddr[5] = val & 0xff; 286 287 /* set supported .11b rates */ 288 ic->ic_sup_rates[IEEE80211_MODE_11B] = ipw_rateset_11b; 289 290 /* set supported .11b channels (read from EEPROM) */ 291 if ((val = ipw_read_prom_word(sc, IPW_EEPROM_CHANNEL_LIST)) == 0) 292 val = 0x7ff; /* default to channels 1-11 */ 293 val <<= 1; 294 for (i = 1; i < 16; i++) { 295 if (val & (1 << i)) { 296 ic->ic_channels[i].ic_freq = 297 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 298 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 299 } 300 } 301 302 /* check support for radio transmitter switch in EEPROM */ 303 if (!(ipw_read_prom_word(sc, IPW_EEPROM_RADIO) & 8)) 304 sc->flags |= IPW_FLAG_HAS_RADIO_SWITCH; 305 306 aprint_normal("%s: 802.11 address %s\n", sc->sc_dev.dv_xname, 307 ether_sprintf(ic->ic_myaddr)); 308 309 if_attach(ifp); 310 ieee80211_ifattach(ic); 311 312 /* override state transition machine */ 313 sc->sc_newstate = ic->ic_newstate; 314 ic->ic_newstate = ipw_newstate; 315 316 ieee80211_media_init(ic, ipw_media_change, ipw_media_status); 317 318 #if NBPFILTER > 0 319 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 320 sizeof (struct ieee80211_frame) + 64, &sc->sc_drvbpf); 321 322 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 323 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 324 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 325 326 sc->sc_txtap_len = sizeof sc->sc_txtapu; 327 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 328 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 329 #endif 330 331 /* 332 * Add a few sysctl knobs. 333 * XXX: Not yet 334 */ 335 sc->dwelltime = 100; 336 337 if (!pmf_device_register(self, NULL, ipw_resume)) 338 aprint_error_dev(self, "couldn't establish power handler\n"); 339 else 340 pmf_class_network_register(self, ifp); 341 342 ieee80211_announce(ic); 343 344 return; 345 346 fail: ipw_detach(self, 0); 347 } 348 349 static int 350 ipw_detach(struct device* self, int flags) 351 { 352 struct ipw_softc *sc = (struct ipw_softc *)self; 353 struct ifnet *ifp = &sc->sc_if; 354 355 if (ifp->if_softc) { 356 ipw_stop(ifp, 1); 357 ipw_free_firmware(sc); 358 359 #if NBPFILTER > 0 360 bpfdetach(ifp); 361 #endif 362 ieee80211_ifdetach(&sc->sc_ic); 363 if_detach(ifp); 364 365 ipw_release(sc); 366 } 367 368 if (sc->sc_ih != NULL) { 369 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 370 sc->sc_ih = NULL; 371 } 372 373 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 374 375 return 0; 376 } 377 378 static int 379 ipw_dma_alloc(struct ipw_softc *sc) 380 { 381 struct ipw_soft_bd *sbd; 382 struct ipw_soft_hdr *shdr; 383 struct ipw_soft_buf *sbuf; 384 int error, i, nsegs; 385 386 /* 387 * Allocate and map tx ring. 388 */ 389 error = bus_dmamap_create(sc->sc_dmat, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, 390 BUS_DMA_NOWAIT, &sc->tbd_map); 391 if (error != 0) { 392 aprint_error("%s: could not create tbd dma map\n", 393 sc->sc_dev.dv_xname); 394 goto fail; 395 } 396 397 error = bus_dmamem_alloc(sc->sc_dmat, IPW_TBD_SZ, PAGE_SIZE, 0, 398 &sc->tbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 399 if (error != 0) { 400 aprint_error("%s: could not allocate tbd dma memory\n", 401 sc->sc_dev.dv_xname); 402 goto fail; 403 } 404 405 error = bus_dmamem_map(sc->sc_dmat, &sc->tbd_seg, nsegs, IPW_TBD_SZ, 406 (void **)&sc->tbd_list, BUS_DMA_NOWAIT); 407 if (error != 0) { 408 aprint_error("%s: could not map tbd dma memory\n", 409 sc->sc_dev.dv_xname); 410 goto fail; 411 } 412 413 error = bus_dmamap_load(sc->sc_dmat, sc->tbd_map, sc->tbd_list, 414 IPW_TBD_SZ, NULL, BUS_DMA_NOWAIT); 415 if (error != 0) { 416 aprint_error("%s: could not load tbd dma memory\n", 417 sc->sc_dev.dv_xname); 418 goto fail; 419 } 420 421 (void)memset(sc->tbd_list, 0, IPW_TBD_SZ); 422 423 /* 424 * Allocate and map rx ring. 425 */ 426 error = bus_dmamap_create(sc->sc_dmat, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, 427 BUS_DMA_NOWAIT, &sc->rbd_map); 428 if (error != 0) { 429 aprint_error("%s: could not create rbd dma map\n", 430 sc->sc_dev.dv_xname); 431 goto fail; 432 } 433 434 error = bus_dmamem_alloc(sc->sc_dmat, IPW_RBD_SZ, PAGE_SIZE, 0, 435 &sc->rbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 436 if (error != 0) { 437 aprint_error("%s: could not allocate rbd dma memory\n", 438 sc->sc_dev.dv_xname); 439 goto fail; 440 } 441 442 error = bus_dmamem_map(sc->sc_dmat, &sc->rbd_seg, nsegs, IPW_RBD_SZ, 443 (void **)&sc->rbd_list, BUS_DMA_NOWAIT); 444 if (error != 0) { 445 aprint_error("%s: could not map rbd dma memory\n", 446 sc->sc_dev.dv_xname); 447 goto fail; 448 } 449 450 error = bus_dmamap_load(sc->sc_dmat, sc->rbd_map, sc->rbd_list, 451 IPW_RBD_SZ, NULL, BUS_DMA_NOWAIT); 452 if (error != 0) { 453 aprint_error("%s: could not load rbd dma memory\n", 454 sc->sc_dev.dv_xname); 455 goto fail; 456 } 457 458 (void)memset(sc->rbd_list, 0, IPW_RBD_SZ); 459 460 /* 461 * Allocate and map status ring. 462 */ 463 error = bus_dmamap_create(sc->sc_dmat, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 464 0, BUS_DMA_NOWAIT, &sc->status_map); 465 if (error != 0) { 466 aprint_error("%s: could not create status dma map\n", 467 sc->sc_dev.dv_xname); 468 goto fail; 469 } 470 471 error = bus_dmamem_alloc(sc->sc_dmat, IPW_STATUS_SZ, PAGE_SIZE, 0, 472 &sc->status_seg, 1, &nsegs, BUS_DMA_NOWAIT); 473 if (error != 0) { 474 aprint_error("%s: could not allocate status dma memory\n", 475 sc->sc_dev.dv_xname); 476 goto fail; 477 } 478 479 error = bus_dmamem_map(sc->sc_dmat, &sc->status_seg, nsegs, 480 IPW_STATUS_SZ, (void **)&sc->status_list, BUS_DMA_NOWAIT); 481 if (error != 0) { 482 aprint_error("%s: could not map status dma memory\n", 483 sc->sc_dev.dv_xname); 484 goto fail; 485 } 486 487 error = bus_dmamap_load(sc->sc_dmat, sc->status_map, sc->status_list, 488 IPW_STATUS_SZ, NULL, BUS_DMA_NOWAIT); 489 if (error != 0) { 490 aprint_error("%s: could not load status dma memory\n", 491 sc->sc_dev.dv_xname); 492 goto fail; 493 } 494 495 (void)memset(sc->status_list, 0, IPW_STATUS_SZ); 496 497 /* 498 * Allocate command DMA map. 499 */ 500 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_cmd), 501 1, sizeof (struct ipw_cmd), 0, BUS_DMA_NOWAIT, &sc->cmd_map); 502 if (error != 0) { 503 aprint_error("%s: could not create cmd dma map\n", 504 sc->sc_dev.dv_xname); 505 goto fail; 506 } 507 508 error = bus_dmamem_alloc(sc->sc_dmat, sizeof (struct ipw_cmd), 509 PAGE_SIZE, 0, &sc->cmd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 510 if (error != 0) { 511 aprint_error("%s: could not allocate cmd dma memory\n", 512 sc->sc_dev.dv_xname); 513 goto fail; 514 } 515 516 error = bus_dmamem_map(sc->sc_dmat, &sc->cmd_seg, nsegs, 517 sizeof (struct ipw_cmd), (void **)&sc->cmd, BUS_DMA_NOWAIT); 518 if (error != 0) { 519 aprint_error("%s: could not map cmd dma memory\n", 520 sc->sc_dev.dv_xname); 521 goto fail; 522 } 523 524 error = bus_dmamap_load(sc->sc_dmat, sc->cmd_map, &sc->cmd, 525 sizeof (struct ipw_cmd), NULL, BUS_DMA_NOWAIT); 526 if (error != 0) { 527 aprint_error("%s: could not map cmd dma memory\n", 528 sc->sc_dev.dv_xname); 529 return error; 530 } 531 532 /* 533 * Allocate and map hdr list. 534 */ 535 536 error = bus_dmamap_create(sc->sc_dmat, 537 IPW_NDATA * sizeof(struct ipw_hdr), 1, 538 sizeof(struct ipw_hdr), 0, BUS_DMA_NOWAIT, 539 &sc->hdr_map); 540 if (error != 0) { 541 aprint_error("%s: could not create hdr dma map\n", 542 sc->sc_dev.dv_xname); 543 goto fail; 544 } 545 546 error = bus_dmamem_alloc(sc->sc_dmat, 547 IPW_NDATA * sizeof(struct ipw_hdr), PAGE_SIZE, 0, &sc->hdr_seg, 548 1, &nsegs, BUS_DMA_NOWAIT); 549 if (error != 0) { 550 aprint_error("%s: could not allocate hdr memory\n", 551 sc->sc_dev.dv_xname); 552 goto fail; 553 } 554 555 error = bus_dmamem_map(sc->sc_dmat, &sc->hdr_seg, nsegs, 556 IPW_NDATA * sizeof(struct ipw_hdr), (void **)&sc->hdr_list, 557 BUS_DMA_NOWAIT); 558 if (error != 0) { 559 aprint_error("%s: could not map hdr memory\n", 560 sc->sc_dev.dv_xname); 561 goto fail; 562 } 563 564 error = bus_dmamap_load(sc->sc_dmat, sc->hdr_map, sc->hdr_list, 565 IPW_NDATA * sizeof(struct ipw_hdr), NULL, BUS_DMA_NOWAIT); 566 if (error != 0) { 567 aprint_error("%s: could not load hdr memory\n", 568 sc->sc_dev.dv_xname); 569 goto fail; 570 } 571 572 (void)memset(sc->hdr_list, 0, IPW_HDR_SZ); 573 574 /* 575 * Create DMA hdrs tailq. 576 */ 577 TAILQ_INIT(&sc->sc_free_shdr); 578 for (i = 0; i < IPW_NDATA; i++) { 579 shdr = &sc->shdr_list[i]; 580 shdr->hdr = sc->hdr_list + i; 581 shdr->offset = sizeof(struct ipw_hdr) * i; 582 shdr->addr = sc->hdr_map->dm_segs[0].ds_addr + shdr->offset; 583 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 584 } 585 586 /* 587 * Allocate tx buffers DMA maps. 588 */ 589 TAILQ_INIT(&sc->sc_free_sbuf); 590 for (i = 0; i < IPW_NDATA; i++) { 591 sbuf = &sc->tx_sbuf_list[i]; 592 593 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 594 IPW_MAX_NSEG, MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 595 if (error != 0) { 596 aprint_error("%s: could not create txbuf dma map\n", 597 sc->sc_dev.dv_xname); 598 goto fail; 599 } 600 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 601 } 602 603 /* 604 * Initialize tx ring. 605 */ 606 for (i = 0; i < IPW_NTBD; i++) { 607 sbd = &sc->stbd_list[i]; 608 sbd->bd = &sc->tbd_list[i]; 609 sbd->type = IPW_SBD_TYPE_NOASSOC; 610 } 611 612 /* 613 * Pre-allocate rx buffers and DMA maps 614 */ 615 for (i = 0; i < IPW_NRBD; i++) { 616 sbd = &sc->srbd_list[i]; 617 sbuf = &sc->rx_sbuf_list[i]; 618 sbd->bd = &sc->rbd_list[i]; 619 620 MGETHDR(sbuf->m, M_DONTWAIT, MT_DATA); 621 if (sbuf->m == NULL) { 622 aprint_error("%s: could not allocate rx mbuf\n", 623 sc->sc_dev.dv_xname); 624 error = ENOMEM; 625 goto fail; 626 } 627 628 MCLGET(sbuf->m, M_DONTWAIT); 629 if (!(sbuf->m->m_flags & M_EXT)) { 630 m_freem(sbuf->m); 631 aprint_error("%s: could not allocate rx mbuf cluster\n", 632 sc->sc_dev.dv_xname); 633 error = ENOMEM; 634 goto fail; 635 } 636 637 sbuf->m->m_pkthdr.len = sbuf->m->m_len = sbuf->m->m_ext.ext_size; 638 639 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 640 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sbuf->map); 641 if (error != 0) { 642 aprint_error("%s: could not create rxbuf dma map\n", 643 sc->sc_dev.dv_xname); 644 m_freem(sbuf->m); 645 goto fail; 646 } 647 648 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, 649 sbuf->m, BUS_DMA_READ | BUS_DMA_NOWAIT); 650 if (error != 0) { 651 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 652 m_freem(sbuf->m); 653 aprint_error("%s: could not map rxbuf dma memory\n", 654 sc->sc_dev.dv_xname); 655 goto fail; 656 } 657 658 sbd->type = IPW_SBD_TYPE_DATA; 659 sbd->priv = sbuf; 660 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 661 sbd->bd->len = htole32(MCLBYTES); 662 663 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, 664 sbuf->map->dm_mapsize, BUS_DMASYNC_PREREAD); 665 666 } 667 668 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 0, IPW_RBD_SZ, 669 BUS_DMASYNC_PREREAD); 670 671 return 0; 672 673 fail: ipw_release(sc); 674 return error; 675 } 676 677 static void 678 ipw_release(struct ipw_softc *sc) 679 { 680 struct ipw_soft_buf *sbuf; 681 int i; 682 683 if (sc->tbd_map != NULL) { 684 if (sc->tbd_list != NULL) { 685 bus_dmamap_unload(sc->sc_dmat, sc->tbd_map); 686 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->tbd_list, 687 IPW_TBD_SZ); 688 bus_dmamem_free(sc->sc_dmat, &sc->tbd_seg, 1); 689 } 690 bus_dmamap_destroy(sc->sc_dmat, sc->tbd_map); 691 } 692 693 if (sc->rbd_map != NULL) { 694 if (sc->rbd_list != NULL) { 695 bus_dmamap_unload(sc->sc_dmat, sc->rbd_map); 696 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->rbd_list, 697 IPW_RBD_SZ); 698 bus_dmamem_free(sc->sc_dmat, &sc->rbd_seg, 1); 699 } 700 bus_dmamap_destroy(sc->sc_dmat, sc->rbd_map); 701 } 702 703 if (sc->status_map != NULL) { 704 if (sc->status_list != NULL) { 705 bus_dmamap_unload(sc->sc_dmat, sc->status_map); 706 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->status_list, 707 IPW_RBD_SZ); 708 bus_dmamem_free(sc->sc_dmat, &sc->status_seg, 1); 709 } 710 bus_dmamap_destroy(sc->sc_dmat, sc->status_map); 711 } 712 713 for (i = 0; i < IPW_NTBD; i++) 714 ipw_release_sbd(sc, &sc->stbd_list[i]); 715 716 if (sc->cmd_map != NULL) 717 bus_dmamap_destroy(sc->sc_dmat, sc->cmd_map); 718 719 if (sc->hdr_list != NULL) { 720 bus_dmamap_unload(sc->sc_dmat, sc->hdr_map); 721 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->hdr_list, 722 IPW_NDATA * sizeof(struct ipw_hdr)); 723 } 724 if (sc->hdr_map != NULL) { 725 bus_dmamem_free(sc->sc_dmat, &sc->hdr_seg, 1); 726 bus_dmamap_destroy(sc->sc_dmat, sc->hdr_map); 727 } 728 729 for (i = 0; i < IPW_NDATA; i++) 730 bus_dmamap_destroy(sc->sc_dmat, sc->tx_sbuf_list[i].map); 731 732 for (i = 0; i < IPW_NRBD; i++) { 733 sbuf = &sc->rx_sbuf_list[i]; 734 if (sbuf->map != NULL) { 735 if (sbuf->m != NULL) { 736 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 737 m_freem(sbuf->m); 738 } 739 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 740 } 741 } 742 743 } 744 745 static bool 746 ipw_resume(device_t dv PMF_FN_ARGS) 747 { 748 struct ipw_softc *sc = device_private(dv); 749 750 pci_disable_retry(sc->sc_pct, sc->sc_pcitag); 751 752 return true; 753 } 754 755 static int 756 ipw_media_change(struct ifnet *ifp) 757 { 758 int error; 759 760 error = ieee80211_media_change(ifp); 761 if (error != ENETRESET) 762 return error; 763 764 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 765 ipw_init(ifp); 766 767 return 0; 768 } 769 770 /* 771 * The firmware automatically adapts the transmit speed. We report the current 772 * transmit speed here. 773 */ 774 static void 775 ipw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 776 { 777 #define N(a) (sizeof (a) / sizeof (a[0])) 778 struct ipw_softc *sc = ifp->if_softc; 779 struct ieee80211com *ic = &sc->sc_ic; 780 static const struct { 781 uint32_t val; 782 int rate; 783 } rates[] = { 784 { IPW_RATE_DS1, 2 }, 785 { IPW_RATE_DS2, 4 }, 786 { IPW_RATE_DS5, 11 }, 787 { IPW_RATE_DS11, 22 }, 788 }; 789 uint32_t val; 790 int rate, i; 791 792 imr->ifm_status = IFM_AVALID; 793 imr->ifm_active = IFM_IEEE80211; 794 if (ic->ic_state == IEEE80211_S_RUN) 795 imr->ifm_status |= IFM_ACTIVE; 796 797 /* read current transmission rate from adapter */ 798 val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE) & 0xf; 799 800 /* convert ipw rate to 802.11 rate */ 801 for (i = 0; i < N(rates) && rates[i].val != val; i++); 802 rate = (i < N(rates)) ? rates[i].rate : 0; 803 804 imr->ifm_active |= IFM_IEEE80211_11B; 805 imr->ifm_active |= ieee80211_rate2media(ic, rate, IEEE80211_MODE_11B); 806 switch (ic->ic_opmode) { 807 case IEEE80211_M_STA: 808 break; 809 810 case IEEE80211_M_IBSS: 811 imr->ifm_active |= IFM_IEEE80211_ADHOC; 812 break; 813 814 case IEEE80211_M_MONITOR: 815 imr->ifm_active |= IFM_IEEE80211_MONITOR; 816 break; 817 818 case IEEE80211_M_AHDEMO: 819 case IEEE80211_M_HOSTAP: 820 /* should not get there */ 821 break; 822 } 823 #undef N 824 } 825 826 static int 827 ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, 828 int arg) 829 { 830 struct ifnet *ifp = ic->ic_ifp; 831 struct ipw_softc *sc = ifp->if_softc; 832 struct ieee80211_node *ni; 833 uint8_t macaddr[IEEE80211_ADDR_LEN]; 834 uint32_t len; 835 836 switch (nstate) { 837 case IEEE80211_S_RUN: 838 DELAY(200); /* firmware needs a short delay here */ 839 840 len = IEEE80211_ADDR_LEN; 841 ipw_read_table2(sc, IPW_INFO_CURRENT_BSSID, macaddr, &len); 842 843 ni = ieee80211_find_node(&ic->ic_scan, macaddr); 844 if (ni == NULL) 845 break; 846 847 ieee80211_ref_node(ni); 848 ieee80211_sta_join(ic, ni); 849 ieee80211_node_authorize(ni); 850 851 if (ic->ic_opmode == IEEE80211_M_STA) 852 ieee80211_notify_node_join(ic, ni, 1); 853 break; 854 855 case IEEE80211_S_INIT: 856 case IEEE80211_S_SCAN: 857 case IEEE80211_S_AUTH: 858 case IEEE80211_S_ASSOC: 859 break; 860 } 861 862 ic->ic_state = nstate; 863 return 0; 864 } 865 866 /* 867 * Read 16 bits at address 'addr' from the serial EEPROM. 868 */ 869 static uint16_t 870 ipw_read_prom_word(struct ipw_softc *sc, uint8_t addr) 871 { 872 uint32_t tmp; 873 uint16_t val; 874 int n; 875 876 /* clock C once before the first command */ 877 IPW_EEPROM_CTL(sc, 0); 878 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 879 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 880 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 881 882 /* write start bit (1) */ 883 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 884 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 885 886 /* write READ opcode (10) */ 887 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 888 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 889 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 890 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 891 892 /* write address A7-A0 */ 893 for (n = 7; n >= 0; n--) { 894 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 895 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D)); 896 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 897 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D) | IPW_EEPROM_C); 898 } 899 900 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 901 902 /* read data Q15-Q0 */ 903 val = 0; 904 for (n = 15; n >= 0; n--) { 905 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 906 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 907 tmp = MEM_READ_4(sc, IPW_MEM_EEPROM_CTL); 908 val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n; 909 } 910 911 IPW_EEPROM_CTL(sc, 0); 912 913 /* clear Chip Select and clock C */ 914 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 915 IPW_EEPROM_CTL(sc, 0); 916 IPW_EEPROM_CTL(sc, IPW_EEPROM_C); 917 918 return le16toh(val); 919 } 920 921 static void 922 ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 923 { 924 struct ipw_cmd *cmd; 925 926 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof (struct ipw_cmd), 927 BUS_DMASYNC_POSTREAD); 928 929 cmd = mtod(sbuf->m, struct ipw_cmd *); 930 931 DPRINTFN(2, ("cmd ack'ed (%u, %u, %u, %u, %u)\n", le32toh(cmd->type), 932 le32toh(cmd->subtype), le32toh(cmd->seq), le32toh(cmd->len), 933 le32toh(cmd->status))); 934 935 wakeup(&sc->cmd); 936 } 937 938 static void 939 ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 940 { 941 struct ieee80211com *ic = &sc->sc_ic; 942 struct ifnet *ifp = sc->sc_ic.ic_ifp; 943 uint32_t state; 944 945 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof state, 946 BUS_DMASYNC_POSTREAD); 947 948 state = le32toh(*mtod(sbuf->m, uint32_t *)); 949 950 DPRINTFN(2, ("entering state %u\n", state)); 951 952 switch (state) { 953 case IPW_STATE_ASSOCIATED: 954 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 955 break; 956 957 case IPW_STATE_SCANNING: 958 /* don't leave run state on background scan */ 959 if (ic->ic_state != IEEE80211_S_RUN) 960 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 961 962 ic->ic_flags |= IEEE80211_F_SCAN; 963 break; 964 965 case IPW_STATE_SCAN_COMPLETE: 966 ieee80211_notify_scan_done(ic); 967 ic->ic_flags &= ~IEEE80211_F_SCAN; 968 break; 969 970 case IPW_STATE_ASSOCIATION_LOST: 971 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 972 break; 973 974 case IPW_STATE_RADIO_DISABLED: 975 ic->ic_ifp->if_flags &= ~IFF_UP; 976 ipw_stop(ifp, 1); 977 break; 978 } 979 } 980 981 /* 982 * XXX: Hack to set the current channel to the value advertised in beacons or 983 * probe responses. Only used during AP detection. 984 */ 985 static void 986 ipw_fix_channel(struct ieee80211com *ic, struct mbuf *m) 987 { 988 struct ieee80211_frame *wh; 989 uint8_t subtype; 990 uint8_t *frm, *efrm; 991 992 wh = mtod(m, struct ieee80211_frame *); 993 994 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_MGT) 995 return; 996 997 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 998 999 if (subtype != IEEE80211_FC0_SUBTYPE_BEACON && 1000 subtype != IEEE80211_FC0_SUBTYPE_PROBE_RESP) 1001 return; 1002 1003 frm = (uint8_t *)(wh + 1); 1004 efrm = mtod(m, uint8_t *) + m->m_len; 1005 1006 frm += 12; /* skip tstamp, bintval and capinfo fields */ 1007 while (frm < efrm) { 1008 if (*frm == IEEE80211_ELEMID_DSPARMS) 1009 #if IEEE80211_CHAN_MAX < 255 1010 if (frm[2] <= IEEE80211_CHAN_MAX) 1011 #endif 1012 ic->ic_curchan = &ic->ic_channels[frm[2]]; 1013 1014 frm += frm[1] + 2; 1015 } 1016 } 1017 1018 static void 1019 ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 1020 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 1021 { 1022 struct ieee80211com *ic = &sc->sc_ic; 1023 struct ifnet *ifp = &sc->sc_if; 1024 struct mbuf *mnew, *m; 1025 struct ieee80211_frame *wh; 1026 struct ieee80211_node *ni; 1027 int error; 1028 1029 DPRINTFN(5, ("received frame len=%u, rssi=%u\n", le32toh(status->len), 1030 status->rssi)); 1031 1032 if (le32toh(status->len) < sizeof (struct ieee80211_frame_min) || 1033 le32toh(status->len) > MCLBYTES) 1034 return; 1035 1036 /* 1037 * Try to allocate a new mbuf for this ring element and load it before 1038 * processing the current mbuf. If the ring element cannot be loaded, 1039 * drop the received packet and reuse the old mbuf. In the unlikely 1040 * case that the old mbuf can't be reloaded either, explicitly panic. 1041 */ 1042 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1043 if (mnew == NULL) { 1044 aprint_error("%s: could not allocate rx mbuf\n", 1045 sc->sc_dev.dv_xname); 1046 ifp->if_ierrors++; 1047 return; 1048 } 1049 1050 MCLGET(mnew, M_DONTWAIT); 1051 if (!(mnew->m_flags & M_EXT)) { 1052 aprint_error("%s: could not allocate rx mbuf cluster\n", 1053 sc->sc_dev.dv_xname); 1054 m_freem(mnew); 1055 ifp->if_ierrors++; 1056 return; 1057 } 1058 1059 mnew->m_pkthdr.len = mnew->m_len = mnew->m_ext.ext_size; 1060 1061 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, le32toh(status->len), 1062 BUS_DMASYNC_POSTREAD); 1063 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1064 1065 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, mnew, 1066 BUS_DMA_READ | BUS_DMA_NOWAIT); 1067 if (error != 0) { 1068 aprint_error("%s: could not load rx buf DMA map\n", 1069 sc->sc_dev.dv_xname); 1070 m_freem(mnew); 1071 1072 /* try to reload the old mbuf */ 1073 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, 1074 sbuf->m, BUS_DMA_READ | BUS_DMA_NOWAIT); 1075 if (error != 0) { 1076 /* very unlikely that it will fail... */ 1077 panic("%s: unable to remap rx buf", 1078 sc->sc_dev.dv_xname); 1079 } 1080 ifp->if_ierrors++; 1081 return; 1082 } 1083 1084 /* 1085 * New mbuf successfully loaded, update Rx ring and continue 1086 * processing. 1087 */ 1088 m = sbuf->m; 1089 sbuf->m = mnew; 1090 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 1091 1092 /* finalize mbuf */ 1093 m->m_pkthdr.rcvif = ifp; 1094 m->m_pkthdr.len = m->m_len = le32toh(status->len); 1095 1096 #if NBPFILTER > 0 1097 if (sc->sc_drvbpf != NULL) { 1098 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 1099 1100 tap->wr_flags = 0; 1101 tap->wr_antsignal = status->rssi; 1102 tap->wr_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 1103 tap->wr_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 1104 1105 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 1106 } 1107 #endif 1108 1109 if (ic->ic_state == IEEE80211_S_SCAN) 1110 ipw_fix_channel(ic, m); 1111 1112 wh = mtod(m, struct ieee80211_frame *); 1113 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 1114 1115 /* send the frame to the 802.11 layer */ 1116 ieee80211_input(ic, m, ni, status->rssi, 0); 1117 1118 /* node is no longer needed */ 1119 ieee80211_free_node(ni); 1120 1121 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, 1122 sbuf->map->dm_mapsize, BUS_DMASYNC_PREREAD); 1123 } 1124 1125 static void 1126 ipw_rx_intr(struct ipw_softc *sc) 1127 { 1128 struct ipw_status *status; 1129 struct ipw_soft_bd *sbd; 1130 struct ipw_soft_buf *sbuf; 1131 uint32_t r, i; 1132 1133 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1134 return; 1135 1136 r = CSR_READ_4(sc, IPW_CSR_RX_READ); 1137 1138 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 1139 1140 /* firmware was killed, stop processing received frames */ 1141 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1142 return; 1143 1144 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 1145 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1146 BUS_DMASYNC_POSTREAD); 1147 1148 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 1149 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 1150 BUS_DMASYNC_POSTREAD); 1151 1152 status = &sc->status_list[i]; 1153 sbd = &sc->srbd_list[i]; 1154 sbuf = sbd->priv; 1155 1156 switch (le16toh(status->code) & 0xf) { 1157 case IPW_STATUS_CODE_COMMAND: 1158 ipw_command_intr(sc, sbuf); 1159 break; 1160 1161 case IPW_STATUS_CODE_NEWSTATE: 1162 ipw_newstate_intr(sc, sbuf); 1163 break; 1164 1165 case IPW_STATUS_CODE_DATA_802_3: 1166 case IPW_STATUS_CODE_DATA_802_11: 1167 ipw_data_intr(sc, status, sbd, sbuf); 1168 break; 1169 1170 case IPW_STATUS_CODE_NOTIFICATION: 1171 DPRINTFN(2, ("received notification\n")); 1172 break; 1173 1174 default: 1175 aprint_error("%s: unknown status code %u\n", 1176 sc->sc_dev.dv_xname, le16toh(status->code)); 1177 } 1178 1179 sbd->bd->flags = 0; 1180 1181 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 1182 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1183 BUS_DMASYNC_PREREAD); 1184 1185 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 1186 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 1187 BUS_DMASYNC_PREREAD); 1188 } 1189 1190 /* Tell the firmware what we have processed */ 1191 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 1192 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 1193 } 1194 1195 static void 1196 ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 1197 { 1198 struct ieee80211com *ic; 1199 struct ipw_soft_hdr *shdr; 1200 struct ipw_soft_buf *sbuf; 1201 1202 switch (sbd->type) { 1203 case IPW_SBD_TYPE_COMMAND: 1204 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 1205 0, sizeof(struct ipw_cmd), BUS_DMASYNC_POSTWRITE); 1206 /* bus_dmamap_unload(sc->sc_dmat, sc->cmd_map); */ 1207 break; 1208 1209 case IPW_SBD_TYPE_HEADER: 1210 shdr = sbd->priv; 1211 bus_dmamap_sync(sc->sc_dmat, sc->hdr_map, 1212 shdr->offset, sizeof(struct ipw_hdr), BUS_DMASYNC_POSTWRITE); 1213 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 1214 break; 1215 1216 case IPW_SBD_TYPE_DATA: 1217 ic = &sc->sc_ic; 1218 sbuf = sbd->priv; 1219 1220 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 1221 0, MCLBYTES, BUS_DMASYNC_POSTWRITE); 1222 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1223 m_freem(sbuf->m); 1224 if (sbuf->ni != NULL) 1225 ieee80211_free_node(sbuf->ni); 1226 /* kill watchdog timer */ 1227 sc->sc_tx_timer = 0; 1228 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 1229 break; 1230 } 1231 sbd->type = IPW_SBD_TYPE_NOASSOC; 1232 } 1233 1234 static void 1235 ipw_tx_intr(struct ipw_softc *sc) 1236 { 1237 struct ifnet *ifp = &sc->sc_if; 1238 struct ipw_soft_bd *sbd; 1239 uint32_t r, i; 1240 1241 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1242 return; 1243 1244 r = CSR_READ_4(sc, IPW_CSR_TX_READ); 1245 1246 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) { 1247 sbd = &sc->stbd_list[i]; 1248 1249 if (sbd->type == IPW_SBD_TYPE_DATA) 1250 ifp->if_opackets++; 1251 1252 ipw_release_sbd(sc, sbd); 1253 sc->txfree++; 1254 } 1255 1256 /* remember what the firmware has processed */ 1257 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 1258 1259 /* Call start() since some buffer descriptors have been released */ 1260 ifp->if_flags &= ~IFF_OACTIVE; 1261 (*ifp->if_start)(ifp); 1262 } 1263 1264 static int 1265 ipw_intr(void *arg) 1266 { 1267 struct ipw_softc *sc = arg; 1268 uint32_t r; 1269 1270 r = CSR_READ_4(sc, IPW_CSR_INTR); 1271 if (r == 0 || r == 0xffffffff) 1272 return 0; 1273 1274 /* Disable interrupts */ 1275 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1276 1277 if (r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR)) { 1278 aprint_error("%s: fatal error\n", 1279 sc->sc_dev.dv_xname); 1280 sc->sc_ic.ic_ifp->if_flags &= ~IFF_UP; 1281 ipw_stop(&sc->sc_if, 1); 1282 } 1283 1284 if (r & IPW_INTR_FW_INIT_DONE) { 1285 if (!(r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR))) 1286 wakeup(sc); 1287 } 1288 1289 if (r & IPW_INTR_RX_TRANSFER) 1290 ipw_rx_intr(sc); 1291 1292 if (r & IPW_INTR_TX_TRANSFER) 1293 ipw_tx_intr(sc); 1294 1295 /* Acknowledge all interrupts */ 1296 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 1297 1298 /* Re-enable interrupts */ 1299 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1300 1301 return 0; 1302 } 1303 1304 /* 1305 * Send a command to the firmware and wait for the acknowledgement. 1306 */ 1307 static int 1308 ipw_cmd(struct ipw_softc *sc, uint32_t type, void *data, uint32_t len) 1309 { 1310 struct ipw_soft_bd *sbd; 1311 1312 sbd = &sc->stbd_list[sc->txcur]; 1313 1314 sc->cmd.type = htole32(type); 1315 sc->cmd.subtype = 0; 1316 sc->cmd.len = htole32(len); 1317 sc->cmd.seq = 0; 1318 1319 (void)memcpy(sc->cmd.data, data, len); 1320 1321 sbd->type = IPW_SBD_TYPE_COMMAND; 1322 sbd->bd->physaddr = htole32(sc->cmd_map->dm_segs[0].ds_addr); 1323 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 1324 sbd->bd->nfrag = 1; 1325 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 1326 IPW_BD_FLAG_TX_LAST_FRAGMENT; 1327 1328 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 0, sizeof (struct ipw_cmd), 1329 BUS_DMASYNC_PREWRITE); 1330 1331 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1332 sc->txcur * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1333 BUS_DMASYNC_PREWRITE); 1334 1335 DPRINTFN(2, ("sending command (%u, %u, %u, %u)\n", type, 0, 0, len)); 1336 1337 /* kick firmware */ 1338 sc->txfree--; 1339 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1340 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1341 1342 /* Wait at most one second for command to complete */ 1343 return tsleep(&sc->cmd, 0, "ipwcmd", hz); 1344 } 1345 1346 static int 1347 ipw_tx_start(struct ifnet *ifp, struct mbuf *m0, struct ieee80211_node *ni) 1348 { 1349 struct ipw_softc *sc = ifp->if_softc; 1350 struct ieee80211com *ic = &sc->sc_ic; 1351 struct ieee80211_frame *wh; 1352 struct ipw_soft_bd *sbd; 1353 struct ipw_soft_hdr *shdr; 1354 struct ipw_soft_buf *sbuf; 1355 struct ieee80211_key *k; 1356 struct mbuf *mnew; 1357 int error, i; 1358 1359 wh = mtod(m0, struct ieee80211_frame *); 1360 1361 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1362 k = ieee80211_crypto_encap(ic, ni, m0); 1363 if (k == NULL) { 1364 m_freem(m0); 1365 return ENOBUFS; 1366 } 1367 1368 /* packet header may have moved, reset our local pointer */ 1369 wh = mtod(m0, struct ieee80211_frame *); 1370 } 1371 1372 #if NBPFILTER > 0 1373 if (sc->sc_drvbpf != NULL) { 1374 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 1375 1376 tap->wt_flags = 0; 1377 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 1378 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 1379 1380 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 1381 } 1382 #endif 1383 1384 shdr = TAILQ_FIRST(&sc->sc_free_shdr); 1385 sbuf = TAILQ_FIRST(&sc->sc_free_sbuf); 1386 KASSERT(shdr != NULL && sbuf != NULL); 1387 1388 shdr->hdr->type = htole32(IPW_HDR_TYPE_SEND); 1389 shdr->hdr->subtype = 0; 1390 shdr->hdr->encrypted = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0; 1391 shdr->hdr->encrypt = 0; 1392 shdr->hdr->keyidx = 0; 1393 shdr->hdr->keysz = 0; 1394 shdr->hdr->fragmentsz = 0; 1395 IEEE80211_ADDR_COPY(shdr->hdr->src_addr, wh->i_addr2); 1396 if (ic->ic_opmode == IEEE80211_M_STA) 1397 IEEE80211_ADDR_COPY(shdr->hdr->dst_addr, wh->i_addr3); 1398 else 1399 IEEE80211_ADDR_COPY(shdr->hdr->dst_addr, wh->i_addr1); 1400 1401 /* trim IEEE802.11 header */ 1402 m_adj(m0, sizeof (struct ieee80211_frame)); 1403 1404 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m0, BUS_DMA_NOWAIT); 1405 if (error != 0 && error != EFBIG) { 1406 aprint_error("%s: could not map mbuf (error %d)\n", 1407 sc->sc_dev.dv_xname, error); 1408 m_freem(m0); 1409 return error; 1410 } 1411 1412 if (error != 0) { 1413 /* too many fragments, linearize */ 1414 1415 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1416 if (mnew == NULL) { 1417 m_freem(m0); 1418 return ENOMEM; 1419 } 1420 1421 M_COPY_PKTHDR(mnew, m0); 1422 1423 /* If the data won't fit in the header, get a cluster */ 1424 if (m0->m_pkthdr.len > MHLEN) { 1425 MCLGET(mnew, M_DONTWAIT); 1426 if (!(mnew->m_flags & M_EXT)) { 1427 m_freem(m0); 1428 m_freem(mnew); 1429 return ENOMEM; 1430 } 1431 } 1432 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(mnew, void *)); 1433 m_freem(m0); 1434 mnew->m_len = mnew->m_pkthdr.len; 1435 m0 = mnew; 1436 1437 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m0, 1438 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1439 if (error != 0) { 1440 aprint_error("%s: could not map mbuf (error %d)\n", 1441 sc->sc_dev.dv_xname, error); 1442 m_freem(m0); 1443 return error; 1444 } 1445 } 1446 1447 TAILQ_REMOVE(&sc->sc_free_sbuf, sbuf, next); 1448 TAILQ_REMOVE(&sc->sc_free_shdr, shdr, next); 1449 1450 sbd = &sc->stbd_list[sc->txcur]; 1451 sbd->type = IPW_SBD_TYPE_HEADER; 1452 sbd->priv = shdr; 1453 sbd->bd->physaddr = htole32(shdr->addr); 1454 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 1455 sbd->bd->nfrag = 1 + sbuf->map->dm_nsegs; 1456 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 1457 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1458 1459 DPRINTFN(5, ("sending tx hdr (%u, %u, %u, %u, )\n", 1460 shdr->hdr->type, shdr->hdr->subtype, shdr->hdr->encrypted, 1461 shdr->hdr->encrypt)); 1462 DPRINTFN(5, ("%s->", ether_sprintf(shdr->hdr->src_addr))); 1463 DPRINTFN(5, ("%s\n", ether_sprintf(shdr->hdr->dst_addr))); 1464 1465 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1466 sc->txcur * sizeof (struct ipw_bd), 1467 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1468 1469 sc->txfree--; 1470 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1471 1472 sbuf->m = m0; 1473 sbuf->ni = ni; 1474 1475 for (i = 0; i < sbuf->map->dm_nsegs; i++) { 1476 sbd = &sc->stbd_list[sc->txcur]; 1477 1478 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[i].ds_addr); 1479 sbd->bd->len = htole32(sbuf->map->dm_segs[i].ds_len); 1480 sbd->bd->nfrag = 0; 1481 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 1482 if (i == sbuf->map->dm_nsegs - 1) { 1483 sbd->type = IPW_SBD_TYPE_DATA; 1484 sbd->priv = sbuf; 1485 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 1486 } else { 1487 sbd->type = IPW_SBD_TYPE_NOASSOC; 1488 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1489 } 1490 1491 DPRINTFN(5, ("sending fragment (%d, %d)\n", i, 1492 (int)sbuf->map->dm_segs[i].ds_len)); 1493 1494 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1495 sc->txcur * sizeof (struct ipw_bd), 1496 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1497 1498 sc->txfree--; 1499 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1500 } 1501 1502 bus_dmamap_sync(sc->sc_dmat, sc->hdr_map, shdr->offset, 1503 sizeof (struct ipw_hdr), BUS_DMASYNC_PREWRITE); 1504 1505 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, MCLBYTES, 1506 BUS_DMASYNC_PREWRITE); 1507 1508 /* Inform firmware about this new packet */ 1509 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1510 1511 return 0; 1512 } 1513 1514 static void 1515 ipw_start(struct ifnet *ifp) 1516 { 1517 struct ipw_softc *sc = ifp->if_softc; 1518 struct ieee80211com *ic = &sc->sc_ic; 1519 struct mbuf *m0; 1520 struct ether_header *eh; 1521 struct ieee80211_node *ni; 1522 1523 1524 if (ic->ic_state != IEEE80211_S_RUN) 1525 return; 1526 1527 for (;;) { 1528 IF_DEQUEUE(&ifp->if_snd, m0); 1529 if (m0 == NULL) 1530 break; 1531 1532 if (sc->txfree < 1 + IPW_MAX_NSEG) { 1533 IF_PREPEND(&ifp->if_snd, m0); 1534 ifp->if_flags |= IFF_OACTIVE; 1535 break; 1536 } 1537 1538 if (m0->m_len < sizeof (struct ether_header) && 1539 (m0 = m_pullup(m0, sizeof (struct ether_header))) == NULL) 1540 continue; 1541 1542 eh = mtod(m0, struct ether_header *); 1543 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1544 if (ni == NULL) { 1545 m_freem(m0); 1546 continue; 1547 } 1548 1549 #if NBPFILTER > 0 1550 if (ifp->if_bpf != NULL) 1551 bpf_mtap(ifp->if_bpf, m0); 1552 #endif 1553 1554 m0 = ieee80211_encap(ic, m0, ni); 1555 if (m0 == NULL) { 1556 ieee80211_free_node(ni); 1557 continue; 1558 } 1559 1560 #if NBPFILTER > 0 1561 if (ic->ic_rawbpf != NULL) 1562 bpf_mtap(ic->ic_rawbpf, m0); 1563 #endif 1564 1565 if (ipw_tx_start(ifp, m0, ni) != 0) { 1566 ieee80211_free_node(ni); 1567 ifp->if_oerrors++; 1568 break; 1569 } 1570 1571 /* start watchdog timer */ 1572 sc->sc_tx_timer = 5; 1573 ifp->if_timer = 1; 1574 } 1575 } 1576 1577 static void 1578 ipw_watchdog(struct ifnet *ifp) 1579 { 1580 struct ipw_softc *sc = ifp->if_softc; 1581 1582 ifp->if_timer = 0; 1583 1584 if (sc->sc_tx_timer > 0) { 1585 if (--sc->sc_tx_timer == 0) { 1586 aprint_error("%s: device timeout\n", 1587 sc->sc_dev.dv_xname); 1588 ifp->if_oerrors++; 1589 ifp->if_flags &= ~IFF_UP; 1590 ipw_stop(ifp, 1); 1591 return; 1592 } 1593 ifp->if_timer = 1; 1594 } 1595 1596 ieee80211_watchdog(&sc->sc_ic); 1597 } 1598 1599 static int 1600 ipw_get_table1(struct ipw_softc *sc, uint32_t *tbl) 1601 { 1602 uint32_t addr, size, i; 1603 1604 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1605 return ENOTTY; 1606 1607 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, sc->table1_base); 1608 1609 size = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 1610 if (suword(tbl, size) != 0) 1611 return EFAULT; 1612 1613 for (i = 1, ++tbl; i < size; i++, tbl++) { 1614 addr = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 1615 if (suword(tbl, MEM_READ_4(sc, addr)) != 0) 1616 return EFAULT; 1617 } 1618 return 0; 1619 } 1620 1621 static int 1622 ipw_get_radio(struct ipw_softc *sc, int *ret) 1623 { 1624 uint32_t addr; 1625 1626 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1627 return ENOTTY; 1628 1629 addr = ipw_read_table1(sc, IPW_INFO_EEPROM_ADDRESS); 1630 if ((MEM_READ_4(sc, addr + 32) >> 24) & 1) { 1631 suword(ret, -1); 1632 return 0; 1633 } 1634 1635 if (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED) 1636 suword(ret, 0); 1637 else 1638 suword(ret, 1); 1639 1640 return 0; 1641 } 1642 1643 static int 1644 ipw_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1645 { 1646 #define IS_RUNNING(ifp) \ 1647 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 1648 1649 struct ipw_softc *sc = ifp->if_softc; 1650 struct ieee80211com *ic = &sc->sc_ic; 1651 struct ifreq *ifr = (struct ifreq *)data; 1652 int s, error = 0; 1653 1654 s = splnet(); 1655 1656 switch (cmd) { 1657 case SIOCSIFFLAGS: 1658 if (ifp->if_flags & IFF_UP) { 1659 if (!(ifp->if_flags & IFF_RUNNING)) 1660 ipw_init(ifp); 1661 } else { 1662 if (ifp->if_flags & IFF_RUNNING) 1663 ipw_stop(ifp, 1); 1664 } 1665 break; 1666 1667 case SIOCADDMULTI: 1668 case SIOCDELMULTI: 1669 /* XXX no h/w multicast filter? --dyoung */ 1670 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1671 /* setup multicast filter, etc */ 1672 error = 0; 1673 } 1674 break; 1675 1676 case SIOCGTABLE1: 1677 error = ipw_get_table1(sc, (uint32_t *)ifr->ifr_data); 1678 break; 1679 1680 case SIOCGRADIO: 1681 error = ipw_get_radio(sc, (int *)ifr->ifr_data); 1682 break; 1683 1684 case SIOCSIFMEDIA: 1685 if (ifr->ifr_media & IFM_IEEE80211_ADHOC) 1686 strlcpy(sc->sc_fwname, "ipw2100-1.2-i.fw", 1687 sizeof(sc->sc_fwname)); 1688 else if (ifr->ifr_media & IFM_IEEE80211_MONITOR) 1689 strlcpy(sc->sc_fwname, "ipw2100-1.2-p.fw", 1690 sizeof(sc->sc_fwname)); 1691 else 1692 strlcpy(sc->sc_fwname, "ipw2100-1.2.fw", 1693 sizeof(sc->sc_fwname)); 1694 1695 ipw_free_firmware(sc); 1696 /* FALLTRHOUGH */ 1697 default: 1698 error = ieee80211_ioctl(&sc->sc_ic, cmd, data); 1699 if (error != ENETRESET) 1700 break; 1701 1702 if (error == ENETRESET) { 1703 if (IS_RUNNING(ifp) && 1704 (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)) 1705 ipw_init(ifp); 1706 error = 0; 1707 } 1708 1709 } 1710 1711 splx(s); 1712 return error; 1713 #undef IS_RUNNING 1714 } 1715 1716 static uint32_t 1717 ipw_read_table1(struct ipw_softc *sc, uint32_t off) 1718 { 1719 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 1720 } 1721 1722 static void 1723 ipw_write_table1(struct ipw_softc *sc, uint32_t off, uint32_t info) 1724 { 1725 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 1726 } 1727 1728 static int 1729 ipw_read_table2(struct ipw_softc *sc, uint32_t off, void *buf, uint32_t *len) 1730 { 1731 uint32_t addr, info; 1732 uint16_t count, size; 1733 uint32_t total; 1734 1735 /* addr[4] + count[2] + size[2] */ 1736 addr = MEM_READ_4(sc, sc->table2_base + off); 1737 info = MEM_READ_4(sc, sc->table2_base + off + 4); 1738 1739 count = info >> 16; 1740 size = info & 0xffff; 1741 total = count * size; 1742 1743 if (total > *len) { 1744 *len = total; 1745 return EINVAL; 1746 } 1747 1748 *len = total; 1749 ipw_read_mem_1(sc, addr, buf, total); 1750 1751 return 0; 1752 } 1753 1754 static void 1755 ipw_stop_master(struct ipw_softc *sc) 1756 { 1757 int ntries; 1758 1759 /* disable interrupts */ 1760 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1761 1762 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1763 for (ntries = 0; ntries < 50; ntries++) { 1764 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1765 break; 1766 DELAY(10); 1767 } 1768 if (ntries == 50) 1769 aprint_error("%s: timeout waiting for master\n", 1770 sc->sc_dev.dv_xname); 1771 1772 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1773 IPW_RST_PRINCETON_RESET); 1774 1775 sc->flags &= ~IPW_FLAG_FW_INITED; 1776 } 1777 1778 static int 1779 ipw_reset(struct ipw_softc *sc) 1780 { 1781 int ntries; 1782 1783 ipw_stop_master(sc); 1784 1785 /* move adapter to D0 state */ 1786 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1787 IPW_CTL_INIT); 1788 1789 /* wait for clock stabilization */ 1790 for (ntries = 0; ntries < 1000; ntries++) { 1791 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY) 1792 break; 1793 DELAY(200); 1794 } 1795 if (ntries == 1000) 1796 return EIO; 1797 1798 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1799 IPW_RST_SW_RESET); 1800 1801 DELAY(10); 1802 1803 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1804 IPW_CTL_INIT); 1805 1806 return 0; 1807 } 1808 1809 /* 1810 * Upload the microcode to the device. 1811 */ 1812 static int 1813 ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size) 1814 { 1815 int ntries; 1816 1817 MEM_WRITE_4(sc, 0x3000e0, 0x80000000); 1818 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1819 1820 MEM_WRITE_2(sc, 0x220000, 0x0703); 1821 MEM_WRITE_2(sc, 0x220000, 0x0707); 1822 1823 MEM_WRITE_1(sc, 0x210014, 0x72); 1824 MEM_WRITE_1(sc, 0x210014, 0x72); 1825 1826 MEM_WRITE_1(sc, 0x210000, 0x40); 1827 MEM_WRITE_1(sc, 0x210000, 0x00); 1828 MEM_WRITE_1(sc, 0x210000, 0x40); 1829 1830 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1831 1832 MEM_WRITE_1(sc, 0x210000, 0x00); 1833 MEM_WRITE_1(sc, 0x210000, 0x00); 1834 MEM_WRITE_1(sc, 0x210000, 0x80); 1835 1836 MEM_WRITE_2(sc, 0x220000, 0x0703); 1837 MEM_WRITE_2(sc, 0x220000, 0x0707); 1838 1839 MEM_WRITE_1(sc, 0x210014, 0x72); 1840 MEM_WRITE_1(sc, 0x210014, 0x72); 1841 1842 MEM_WRITE_1(sc, 0x210000, 0x00); 1843 MEM_WRITE_1(sc, 0x210000, 0x80); 1844 1845 for (ntries = 0; ntries < 10; ntries++) { 1846 if (MEM_READ_1(sc, 0x210000) & 1) 1847 break; 1848 DELAY(10); 1849 } 1850 if (ntries == 10) { 1851 aprint_error("%s: timeout waiting for ucode to initialize\n", 1852 sc->sc_dev.dv_xname); 1853 return EIO; 1854 } 1855 1856 MEM_WRITE_4(sc, 0x3000e0, 0); 1857 1858 return 0; 1859 } 1860 1861 /* set of macros to handle unaligned little endian data in firmware image */ 1862 #define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1863 #define GETLE16(p) ((p)[0] | (p)[1] << 8) 1864 static int 1865 ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size) 1866 { 1867 u_char *p, *end; 1868 uint32_t dst; 1869 uint16_t len; 1870 int error; 1871 1872 p = fw; 1873 end = fw + size; 1874 while (p < end) { 1875 dst = GETLE32(p); p += 4; 1876 len = GETLE16(p); p += 2; 1877 1878 ipw_write_mem_1(sc, dst, p, len); 1879 p += len; 1880 } 1881 1882 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1883 IPW_IO_LED_OFF); 1884 1885 /* enable interrupts */ 1886 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1887 1888 /* kick the firmware */ 1889 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1890 1891 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1892 IPW_CTL_ALLOW_STANDBY); 1893 1894 /* wait at most one second for firmware initialization to complete */ 1895 if ((error = tsleep(sc, 0, "ipwinit", hz)) != 0) { 1896 aprint_error("%s: timeout waiting for firmware initialization " 1897 "to complete\n", sc->sc_dev.dv_xname); 1898 return error; 1899 } 1900 1901 CSR_WRITE_4(sc, IPW_CSR_IO, CSR_READ_4(sc, IPW_CSR_IO) | 1902 IPW_IO_GPIO1_MASK | IPW_IO_GPIO3_MASK); 1903 1904 return 0; 1905 } 1906 1907 /* 1908 * Store firmware into kernel memory so we can download it when we need to, 1909 * e.g when the adapter wakes up from suspend mode. 1910 */ 1911 static int 1912 ipw_cache_firmware(struct ipw_softc *sc) 1913 { 1914 struct ipw_firmware *fw = &sc->fw; 1915 struct ipw_firmware_hdr hdr; 1916 firmware_handle_t fwh; 1917 off_t fwsz, p; 1918 int error; 1919 1920 ipw_free_firmware(sc); 1921 1922 if ((error = firmware_open("if_ipw", sc->sc_fwname, &fwh)) != 0) 1923 goto fail0; 1924 1925 fwsz = firmware_get_size(fwh); 1926 1927 if (fwsz < sizeof(hdr)) 1928 goto fail2; 1929 1930 if ((error = firmware_read(fwh, 0, &hdr, sizeof(hdr))) != 0) 1931 goto fail2; 1932 1933 fw->main_size = le32toh(hdr.main_size); 1934 fw->ucode_size = le32toh(hdr.ucode_size); 1935 1936 fw->main = firmware_malloc(fw->main_size); 1937 if (fw->main == NULL) { 1938 error = ENOMEM; 1939 goto fail1; 1940 } 1941 1942 fw->ucode = firmware_malloc(fw->ucode_size); 1943 if (fw->ucode == NULL) { 1944 error = ENOMEM; 1945 goto fail2; 1946 } 1947 1948 p = sizeof(hdr); 1949 if ((error = firmware_read(fwh, p, fw->main, fw->main_size)) != 0) 1950 goto fail3; 1951 1952 p += fw->main_size; 1953 if ((error = firmware_read(fwh, p, fw->ucode, fw->ucode_size)) != 0) 1954 goto fail3; 1955 1956 DPRINTF(("Firmware cached: main %u, ucode %u\n", fw->main_size, 1957 fw->ucode_size)); 1958 1959 sc->flags |= IPW_FLAG_FW_CACHED; 1960 1961 firmware_close(fwh); 1962 1963 return 0; 1964 1965 fail3: firmware_free(fw->ucode, 0); 1966 fail2: firmware_free(fw->main, 0); 1967 fail1: firmware_close(fwh); 1968 fail0: 1969 return error; 1970 } 1971 1972 static void 1973 ipw_free_firmware(struct ipw_softc *sc) 1974 { 1975 if (!(sc->flags & IPW_FLAG_FW_CACHED)) 1976 return; 1977 1978 firmware_free(sc->fw.main, 0); 1979 firmware_free(sc->fw.ucode, 0); 1980 1981 sc->flags &= ~IPW_FLAG_FW_CACHED; 1982 } 1983 1984 static int 1985 ipw_config(struct ipw_softc *sc) 1986 { 1987 struct ieee80211com *ic = &sc->sc_ic; 1988 struct ifnet *ifp = &sc->sc_if; 1989 struct ipw_security security; 1990 struct ieee80211_key *k; 1991 struct ipw_wep_key wepkey; 1992 struct ipw_scan_options options; 1993 struct ipw_configuration config; 1994 uint32_t data; 1995 int error, i; 1996 1997 switch (ic->ic_opmode) { 1998 case IEEE80211_M_STA: 1999 case IEEE80211_M_HOSTAP: 2000 data = htole32(IPW_MODE_BSS); 2001 break; 2002 2003 case IEEE80211_M_IBSS: 2004 case IEEE80211_M_AHDEMO: 2005 data = htole32(IPW_MODE_IBSS); 2006 break; 2007 2008 case IEEE80211_M_MONITOR: 2009 data = htole32(IPW_MODE_MONITOR); 2010 break; 2011 } 2012 DPRINTF(("Setting mode to %u\n", le32toh(data))); 2013 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 2014 if (error != 0) 2015 return error; 2016 2017 if (ic->ic_opmode == IEEE80211_M_IBSS || 2018 ic->ic_opmode == IEEE80211_M_MONITOR) { 2019 data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); 2020 DPRINTF(("Setting channel to %u\n", le32toh(data))); 2021 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 2022 if (error != 0) 2023 return error; 2024 } 2025 2026 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2027 DPRINTF(("Enabling adapter\n")); 2028 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 2029 } 2030 2031 DPRINTF(("Setting MAC to %s\n", ether_sprintf(ic->ic_myaddr))); 2032 if_set_sadl(ifp, ic->ic_myaddr, IEEE80211_ADDR_LEN); 2033 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 2034 IEEE80211_ADDR_LEN); 2035 if (error != 0) 2036 return error; 2037 2038 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 2039 IPW_CFG_PREAMBLE_AUTO | IPW_CFG_802_1x_ENABLE); 2040 2041 if (ic->ic_opmode == IEEE80211_M_IBSS) 2042 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 2043 if (ifp->if_flags & IFF_PROMISC) 2044 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 2045 config.bss_chan = htole32(0x3fff); /* channels 1-14 */ 2046 config.ibss_chan = htole32(0x7ff); /* channels 1-11 */ 2047 DPRINTF(("Setting adapter configuration 0x%08x\n", config.flags)); 2048 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 2049 if (error != 0) 2050 return error; 2051 2052 data = htole32(0x3); /* 1, 2 */ 2053 DPRINTF(("Setting basic tx rates to 0x%x\n", le32toh(data))); 2054 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 2055 if (error != 0) 2056 return error; 2057 2058 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 2059 DPRINTF(("Setting tx rates to 0x%x\n", le32toh(data))); 2060 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 2061 if (error != 0) 2062 return error; 2063 2064 data = htole32(IPW_POWER_MODE_CAM); 2065 DPRINTF(("Setting power mode to %u\n", le32toh(data))); 2066 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 2067 if (error != 0) 2068 return error; 2069 2070 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2071 data = htole32(32); /* default value */ 2072 DPRINTF(("Setting tx power index to %u\n", le32toh(data))); 2073 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 2074 sizeof data); 2075 if (error != 0) 2076 return error; 2077 } 2078 2079 data = htole32(ic->ic_rtsthreshold); 2080 DPRINTF(("Setting RTS threshold to %u\n", le32toh(data))); 2081 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 2082 if (error != 0) 2083 return error; 2084 2085 data = htole32(ic->ic_fragthreshold); 2086 DPRINTF(("Setting frag threshold to %u\n", le32toh(data))); 2087 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 2088 if (error != 0) 2089 return error; 2090 2091 #ifdef IPW_DEBUG 2092 if (ipw_debug > 0) { 2093 printf("Setting ESSID to "); 2094 ieee80211_print_essid(ic->ic_des_essid, ic->ic_des_esslen); 2095 printf("\n"); 2096 } 2097 #endif 2098 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ic->ic_des_essid, 2099 ic->ic_des_esslen); 2100 if (error != 0) 2101 return error; 2102 2103 /* no mandatory BSSID */ 2104 DPRINTF(("Setting mandatory BSSID to null\n")); 2105 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 2106 if (error != 0) 2107 return error; 2108 2109 if (ic->ic_flags & IEEE80211_F_DESBSSID) { 2110 DPRINTF(("Setting desired BSSID to %s\n", 2111 ether_sprintf(ic->ic_des_bssid))); 2112 error = ipw_cmd(sc, IPW_CMD_SET_DESIRED_BSSID, 2113 ic->ic_des_bssid, IEEE80211_ADDR_LEN); 2114 if (error != 0) 2115 return error; 2116 } 2117 2118 (void)memset(&security, 0, sizeof(security)); 2119 security.authmode = (ic->ic_bss->ni_authmode == IEEE80211_AUTH_SHARED) ? 2120 IPW_AUTH_SHARED : IPW_AUTH_OPEN; 2121 security.ciphers = htole32(IPW_CIPHER_NONE); 2122 DPRINTF(("Setting authmode to %u\n", security.authmode)); 2123 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 2124 sizeof security); 2125 if (error != 0) 2126 return error; 2127 2128 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 2129 k = ic->ic_crypto.cs_nw_keys; 2130 for (i = 0; i < IEEE80211_WEP_NKID; i++, k++) { 2131 if (k->wk_keylen == 0) 2132 continue; 2133 2134 wepkey.idx = i; 2135 wepkey.len = k->wk_keylen; 2136 memset(wepkey.key, 0, sizeof(wepkey.key)); 2137 memcpy(wepkey.key, k->wk_key, k->wk_keylen); 2138 DPRINTF(("Setting wep key index %u len %u\n", 2139 wepkey.idx, wepkey.len)); 2140 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY, &wepkey, 2141 sizeof wepkey); 2142 if (error != 0) 2143 return error; 2144 } 2145 2146 data = htole32(ic->ic_crypto.cs_def_txkey); 2147 DPRINTF(("Setting tx key index to %u\n", le32toh(data))); 2148 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY_INDEX, &data, 2149 sizeof data); 2150 if (error != 0) 2151 return error; 2152 } 2153 2154 data = htole32((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) ? IPW_WEPON : 0); 2155 DPRINTF(("Setting wep flags to 0x%x\n", le32toh(data))); 2156 error = ipw_cmd(sc, IPW_CMD_SET_WEP_FLAGS, &data, sizeof data); 2157 if (error != 0) 2158 return error; 2159 2160 #if 0 2161 struct ipw_wpa_ie ie; 2162 2163 memset(&ie, 0 sizeof(ie)); 2164 ie.len = htole32(sizeof (struct ieee80211_ie_wpa)); 2165 DPRINTF(("Setting wpa ie\n")); 2166 error = ipw_cmd(sc, IPW_CMD_SET_WPA_IE, &ie, sizeof ie); 2167 if (error != 0) 2168 return error; 2169 #endif 2170 2171 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2172 data = htole32(ic->ic_bintval); 2173 DPRINTF(("Setting beacon interval to %u\n", le32toh(data))); 2174 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 2175 sizeof data); 2176 if (error != 0) 2177 return error; 2178 } 2179 2180 options.flags = 0; 2181 options.channels = htole32(0x3fff); /* scan channels 1-14 */ 2182 DPRINTF(("Setting scan options to 0x%x\n", le32toh(options.flags))); 2183 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &options, sizeof options); 2184 if (error != 0) 2185 return error; 2186 2187 /* finally, enable adapter (start scanning for an access point) */ 2188 DPRINTF(("Enabling adapter\n")); 2189 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 2190 } 2191 2192 static int 2193 ipw_init(struct ifnet *ifp) 2194 { 2195 struct ipw_softc *sc = ifp->if_softc; 2196 struct ipw_firmware *fw = &sc->fw; 2197 2198 if (!(sc->flags & IPW_FLAG_FW_CACHED)) { 2199 if (ipw_cache_firmware(sc) != 0) { 2200 aprint_error("%s: could not cache the firmware (%s)\n", 2201 sc->sc_dev.dv_xname, sc->sc_fwname); 2202 goto fail; 2203 } 2204 } 2205 2206 ipw_stop(ifp, 0); 2207 2208 if (ipw_reset(sc) != 0) { 2209 aprint_error("%s: could not reset adapter\n", 2210 sc->sc_dev.dv_xname); 2211 goto fail; 2212 } 2213 2214 if (ipw_load_ucode(sc, fw->ucode, fw->ucode_size) != 0) { 2215 aprint_error("%s: could not load microcode\n", 2216 sc->sc_dev.dv_xname); 2217 goto fail; 2218 } 2219 2220 ipw_stop_master(sc); 2221 2222 /* 2223 * Setup tx, rx and status rings. 2224 */ 2225 sc->txold = IPW_NTBD - 1; 2226 sc->txcur = 0; 2227 sc->txfree = IPW_NTBD - 2; 2228 sc->rxcur = IPW_NRBD - 1; 2229 2230 CSR_WRITE_4(sc, IPW_CSR_TX_BASE, sc->tbd_map->dm_segs[0].ds_addr); 2231 CSR_WRITE_4(sc, IPW_CSR_TX_SIZE, IPW_NTBD); 2232 CSR_WRITE_4(sc, IPW_CSR_TX_READ, 0); 2233 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 2234 2235 CSR_WRITE_4(sc, IPW_CSR_RX_BASE, sc->rbd_map->dm_segs[0].ds_addr); 2236 CSR_WRITE_4(sc, IPW_CSR_RX_SIZE, IPW_NRBD); 2237 CSR_WRITE_4(sc, IPW_CSR_RX_READ, 0); 2238 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 2239 2240 CSR_WRITE_4(sc, IPW_CSR_STATUS_BASE, sc->status_map->dm_segs[0].ds_addr); 2241 2242 if (ipw_load_firmware(sc, fw->main, fw->main_size) != 0) { 2243 aprint_error("%s: could not load firmware\n", 2244 sc->sc_dev.dv_xname); 2245 goto fail; 2246 } 2247 2248 sc->flags |= IPW_FLAG_FW_INITED; 2249 2250 /* retrieve information tables base addresses */ 2251 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 2252 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 2253 2254 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 2255 2256 if (ipw_config(sc) != 0) { 2257 aprint_error("%s: device configuration failed\n", 2258 sc->sc_dev.dv_xname); 2259 goto fail; 2260 } 2261 2262 ifp->if_flags &= ~IFF_OACTIVE; 2263 ifp->if_flags |= IFF_RUNNING; 2264 2265 return 0; 2266 2267 fail: ifp->if_flags &= ~IFF_UP; 2268 ipw_stop(ifp, 0); 2269 2270 return EIO; 2271 } 2272 2273 static void 2274 ipw_stop(struct ifnet *ifp, int disable) 2275 { 2276 struct ipw_softc *sc = ifp->if_softc; 2277 struct ieee80211com *ic = &sc->sc_ic; 2278 int i; 2279 2280 ipw_stop_master(sc); 2281 2282 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 2283 2284 /* 2285 * Release tx buffers. 2286 */ 2287 for (i = 0; i < IPW_NTBD; i++) 2288 ipw_release_sbd(sc, &sc->stbd_list[i]); 2289 2290 sc->sc_tx_timer = 0; 2291 ifp->if_timer = 0; 2292 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2293 2294 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2295 } 2296 2297 static void 2298 ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2299 bus_size_t count) 2300 { 2301 for (; count > 0; offset++, datap++, count--) { 2302 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2303 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 2304 } 2305 } 2306 2307 static void 2308 ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2309 bus_size_t count) 2310 { 2311 for (; count > 0; offset++, datap++, count--) { 2312 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2313 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 2314 } 2315 } 2316
Indexes created Tue Sep 30 20:09:53 GMT 2025