if_ipw.c revision 1.39
1 /* $NetBSD: if_ipw.c,v 1.39 2008/04/10 19:13:37 cegger Exp $ */ 2 /* FreeBSD: src/sys/dev/ipw/if_ipw.c,v 1.15 2005/11/13 17:17:40 damien Exp */ 3 4 /*- 5 * Copyright (c) 2004, 2005 6 * Damien Bergamini <damien.bergamini (at) free.fr>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: if_ipw.c,v 1.39 2008/04/10 19:13:37 cegger Exp $"); 33 34 /*- 35 * Intel(R) PRO/Wireless 2100 MiniPCI driver 36 * http://www.intel.com/network/connectivity/products/wireless/prowireless_mobile.htm 37 */ 38 39 #include "bpfilter.h" 40 41 #include <sys/param.h> 42 #include <sys/sockio.h> 43 #include <sys/sysctl.h> 44 #include <sys/mbuf.h> 45 #include <sys/kernel.h> 46 #include <sys/socket.h> 47 #include <sys/systm.h> 48 #include <sys/malloc.h> 49 #include <sys/conf.h> 50 51 #include <sys/bus.h> 52 #include <machine/endian.h> 53 #include <sys/intr.h> 54 55 #include <dev/pci/pcireg.h> 56 #include <dev/pci/pcivar.h> 57 #include <dev/pci/pcidevs.h> 58 59 #if NBPFILTER > 0 60 #include <net/bpf.h> 61 #endif 62 #include <net/if.h> 63 #include <net/if_arp.h> 64 #include <net/if_dl.h> 65 #include <net/if_ether.h> 66 #include <net/if_media.h> 67 #include <net/if_types.h> 68 69 #include <net80211/ieee80211_var.h> 70 #include <net80211/ieee80211_radiotap.h> 71 72 #include <netinet/in.h> 73 #include <netinet/in_systm.h> 74 #include <netinet/in_var.h> 75 #include <netinet/ip.h> 76 77 #include <dev/firmload.h> 78 79 #include <dev/pci/if_ipwreg.h> 80 #include <dev/pci/if_ipwvar.h> 81 82 #ifdef IPW_DEBUG 83 #define DPRINTF(x) if (ipw_debug > 0) printf x 84 #define DPRINTFN(n, x) if (ipw_debug >= (n)) printf x 85 int ipw_debug = 0; 86 #else 87 #define DPRINTF(x) 88 #define DPRINTFN(n, x) 89 #endif 90 91 static int ipw_dma_alloc(struct ipw_softc *); 92 static void ipw_release(struct ipw_softc *); 93 static int ipw_match(struct device *, struct cfdata *, void *); 94 static void ipw_attach(struct device *, struct device *, void *); 95 static int ipw_detach(struct device *, int); 96 97 static int ipw_media_change(struct ifnet *); 98 static void ipw_media_status(struct ifnet *, struct ifmediareq *); 99 static int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 100 static uint16_t ipw_read_prom_word(struct ipw_softc *, uint8_t); 101 static void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 102 static void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 103 static void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 104 struct ipw_soft_bd *, struct ipw_soft_buf *); 105 static void ipw_rx_intr(struct ipw_softc *); 106 static void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 107 static void ipw_tx_intr(struct ipw_softc *); 108 static int ipw_intr(void *); 109 static int ipw_cmd(struct ipw_softc *, uint32_t, void *, uint32_t); 110 static int ipw_tx_start(struct ifnet *, struct mbuf *, 111 struct ieee80211_node *); 112 static void ipw_start(struct ifnet *); 113 static void ipw_watchdog(struct ifnet *); 114 static int ipw_ioctl(struct ifnet *, u_long, void *); 115 static int ipw_get_table1(struct ipw_softc *, uint32_t *); 116 static int ipw_get_radio(struct ipw_softc *, int *); 117 static void ipw_stop_master(struct ipw_softc *); 118 static int ipw_reset(struct ipw_softc *); 119 static int ipw_load_ucode(struct ipw_softc *, u_char *, int); 120 static int ipw_load_firmware(struct ipw_softc *, u_char *, int); 121 static int ipw_cache_firmware(struct ipw_softc *); 122 static void ipw_free_firmware(struct ipw_softc *); 123 static int ipw_config(struct ipw_softc *); 124 static int ipw_init(struct ifnet *); 125 static void ipw_stop(struct ifnet *, int); 126 static uint32_t ipw_read_table1(struct ipw_softc *, uint32_t); 127 static void ipw_write_table1(struct ipw_softc *, uint32_t, uint32_t); 128 static int ipw_read_table2(struct ipw_softc *, uint32_t, void *, uint32_t *); 129 static void ipw_read_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 130 bus_size_t); 131 static void ipw_write_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 132 bus_size_t); 133 134 /* 135 * Supported rates for 802.11b mode (in 500Kbps unit). 136 */ 137 static const struct ieee80211_rateset ipw_rateset_11b = 138 { 4, { 2, 4, 11, 22 } }; 139 140 static inline uint8_t 141 MEM_READ_1(struct ipw_softc *sc, uint32_t addr) 142 { 143 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 144 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); 145 } 146 147 static inline uint32_t 148 MEM_READ_4(struct ipw_softc *sc, uint32_t addr) 149 { 150 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 151 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); 152 } 153 154 CFATTACH_DECL(ipw, sizeof (struct ipw_softc), ipw_match, ipw_attach, 155 ipw_detach, NULL); 156 157 static int 158 ipw_match(struct device *parent, struct cfdata *match, 159 void *aux) 160 { 161 struct pci_attach_args *pa = aux; 162 163 if (PCI_VENDOR (pa->pa_id) == PCI_VENDOR_INTEL && 164 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_PRO_WL_2100) 165 return 1; 166 167 return 0; 168 } 169 170 /* Base Address Register */ 171 #define IPW_PCI_BAR0 0x10 172 173 static void 174 ipw_attach(struct device *parent, struct device *self, void *aux) 175 { 176 struct ipw_softc *sc = (struct ipw_softc *)self; 177 struct ieee80211com *ic = &sc->sc_ic; 178 struct ifnet *ifp = &sc->sc_if; 179 struct pci_attach_args *pa = aux; 180 const char *intrstr; 181 char devinfo[256]; 182 bus_space_tag_t memt; 183 bus_space_handle_t memh; 184 bus_addr_t base; 185 pci_intr_handle_t ih; 186 uint32_t data; 187 uint16_t val; 188 int i, revision, error; 189 190 sc->sc_pct = pa->pa_pc; 191 sc->sc_pcitag = pa->pa_tag; 192 193 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof devinfo); 194 revision = PCI_REVISION(pa->pa_class); 195 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, revision); 196 197 /* enable bus-mastering */ 198 data = pci_conf_read(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG); 199 data |= PCI_COMMAND_MASTER_ENABLE; 200 pci_conf_write(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG, data); 201 202 /* map the register window */ 203 error = pci_mapreg_map(pa, IPW_PCI_BAR0, PCI_MAPREG_TYPE_MEM | 204 PCI_MAPREG_MEM_TYPE_32BIT, 0, &memt, &memh, &base, &sc->sc_sz); 205 if (error != 0) { 206 aprint_error_dev(&sc->sc_dev, "could not map memory space\n"); 207 return; 208 } 209 210 sc->sc_st = memt; 211 sc->sc_sh = memh; 212 sc->sc_dmat = pa->pa_dmat; 213 strlcpy(sc->sc_fwname, "ipw2100-1.2.fw", sizeof(sc->sc_fwname)); 214 215 /* disable interrupts */ 216 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 217 218 if (pci_intr_map(pa, &ih) != 0) { 219 aprint_error_dev(&sc->sc_dev, "could not map interrupt\n"); 220 return; 221 } 222 223 intrstr = pci_intr_string(sc->sc_pct, ih); 224 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, ipw_intr, sc); 225 if (sc->sc_ih == NULL) { 226 aprint_error_dev(&sc->sc_dev, "could not establish interrupt"); 227 if (intrstr != NULL) 228 aprint_error(" at %s", intrstr); 229 aprint_error("\n"); 230 return; 231 } 232 aprint_normal_dev(&sc->sc_dev, "interrupting at %s\n", intrstr); 233 234 if (ipw_reset(sc) != 0) { 235 aprint_error_dev(&sc->sc_dev, "could not reset adapter\n"); 236 goto fail; 237 } 238 239 if (ipw_dma_alloc(sc) != 0) { 240 aprint_error_dev(&sc->sc_dev, "could not allocate DMA resources\n"); 241 goto fail; 242 } 243 244 ifp->if_softc = sc; 245 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 246 ifp->if_init = ipw_init; 247 ifp->if_stop = ipw_stop; 248 ifp->if_ioctl = ipw_ioctl; 249 ifp->if_start = ipw_start; 250 ifp->if_watchdog = ipw_watchdog; 251 IFQ_SET_READY(&ifp->if_snd); 252 strlcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 253 254 ic->ic_ifp = ifp; 255 ic->ic_phytype = IEEE80211_T_DS; 256 ic->ic_opmode = IEEE80211_M_STA; 257 ic->ic_state = IEEE80211_S_INIT; 258 259 /* set device capabilities */ 260 ic->ic_caps = 261 IEEE80211_C_SHPREAMBLE /* short preamble supported */ 262 | IEEE80211_C_TXPMGT /* tx power management */ 263 | IEEE80211_C_IBSS /* ibss mode */ 264 | IEEE80211_C_MONITOR /* monitor mode */ 265 ; 266 267 /* read MAC address from EEPROM */ 268 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0); 269 ic->ic_myaddr[0] = val >> 8; 270 ic->ic_myaddr[1] = val & 0xff; 271 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 1); 272 ic->ic_myaddr[2] = val >> 8; 273 ic->ic_myaddr[3] = val & 0xff; 274 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 2); 275 ic->ic_myaddr[4] = val >> 8; 276 ic->ic_myaddr[5] = val & 0xff; 277 278 /* set supported .11b rates */ 279 ic->ic_sup_rates[IEEE80211_MODE_11B] = ipw_rateset_11b; 280 281 /* set supported .11b channels (read from EEPROM) */ 282 if ((val = ipw_read_prom_word(sc, IPW_EEPROM_CHANNEL_LIST)) == 0) 283 val = 0x7ff; /* default to channels 1-11 */ 284 val <<= 1; 285 for (i = 1; i < 16; i++) { 286 if (val & (1 << i)) { 287 ic->ic_channels[i].ic_freq = 288 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 289 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 290 } 291 } 292 293 /* check support for radio transmitter switch in EEPROM */ 294 if (!(ipw_read_prom_word(sc, IPW_EEPROM_RADIO) & 8)) 295 sc->flags |= IPW_FLAG_HAS_RADIO_SWITCH; 296 297 aprint_normal_dev(&sc->sc_dev, "802.11 address %s\n", 298 ether_sprintf(ic->ic_myaddr)); 299 300 if_attach(ifp); 301 ieee80211_ifattach(ic); 302 303 /* override state transition machine */ 304 sc->sc_newstate = ic->ic_newstate; 305 ic->ic_newstate = ipw_newstate; 306 307 ieee80211_media_init(ic, ipw_media_change, ipw_media_status); 308 309 #if NBPFILTER > 0 310 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 311 sizeof (struct ieee80211_frame) + 64, &sc->sc_drvbpf); 312 313 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 314 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 315 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 316 317 sc->sc_txtap_len = sizeof sc->sc_txtapu; 318 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 319 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 320 #endif 321 322 /* 323 * Add a few sysctl knobs. 324 * XXX: Not yet 325 */ 326 sc->dwelltime = 100; 327 328 if (!pmf_device_register(self, NULL, NULL)) 329 aprint_error_dev(self, "couldn't establish power handler\n"); 330 else 331 pmf_class_network_register(self, ifp); 332 333 ieee80211_announce(ic); 334 335 return; 336 337 fail: ipw_detach(self, 0); 338 } 339 340 static int 341 ipw_detach(struct device* self, int flags) 342 { 343 struct ipw_softc *sc = (struct ipw_softc *)self; 344 struct ifnet *ifp = &sc->sc_if; 345 346 if (ifp->if_softc) { 347 ipw_stop(ifp, 1); 348 ipw_free_firmware(sc); 349 350 #if NBPFILTER > 0 351 bpfdetach(ifp); 352 #endif 353 ieee80211_ifdetach(&sc->sc_ic); 354 if_detach(ifp); 355 356 ipw_release(sc); 357 } 358 359 if (sc->sc_ih != NULL) { 360 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 361 sc->sc_ih = NULL; 362 } 363 364 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 365 366 return 0; 367 } 368 369 static int 370 ipw_dma_alloc(struct ipw_softc *sc) 371 { 372 struct ipw_soft_bd *sbd; 373 struct ipw_soft_hdr *shdr; 374 struct ipw_soft_buf *sbuf; 375 int error, i, nsegs; 376 377 /* 378 * Allocate and map tx ring. 379 */ 380 error = bus_dmamap_create(sc->sc_dmat, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, 381 BUS_DMA_NOWAIT, &sc->tbd_map); 382 if (error != 0) { 383 aprint_error_dev(&sc->sc_dev, "could not create tbd dma map\n"); 384 goto fail; 385 } 386 387 error = bus_dmamem_alloc(sc->sc_dmat, IPW_TBD_SZ, PAGE_SIZE, 0, 388 &sc->tbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 389 if (error != 0) { 390 aprint_error_dev(&sc->sc_dev, "could not allocate tbd dma memory\n"); 391 goto fail; 392 } 393 394 error = bus_dmamem_map(sc->sc_dmat, &sc->tbd_seg, nsegs, IPW_TBD_SZ, 395 (void **)&sc->tbd_list, BUS_DMA_NOWAIT); 396 if (error != 0) { 397 aprint_error_dev(&sc->sc_dev, "could not map tbd dma memory\n"); 398 goto fail; 399 } 400 401 error = bus_dmamap_load(sc->sc_dmat, sc->tbd_map, sc->tbd_list, 402 IPW_TBD_SZ, NULL, BUS_DMA_NOWAIT); 403 if (error != 0) { 404 aprint_error_dev(&sc->sc_dev, "could not load tbd dma memory\n"); 405 goto fail; 406 } 407 408 (void)memset(sc->tbd_list, 0, IPW_TBD_SZ); 409 410 /* 411 * Allocate and map rx ring. 412 */ 413 error = bus_dmamap_create(sc->sc_dmat, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, 414 BUS_DMA_NOWAIT, &sc->rbd_map); 415 if (error != 0) { 416 aprint_error_dev(&sc->sc_dev, "could not create rbd dma map\n"); 417 goto fail; 418 } 419 420 error = bus_dmamem_alloc(sc->sc_dmat, IPW_RBD_SZ, PAGE_SIZE, 0, 421 &sc->rbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 422 if (error != 0) { 423 aprint_error_dev(&sc->sc_dev, "could not allocate rbd dma memory\n"); 424 goto fail; 425 } 426 427 error = bus_dmamem_map(sc->sc_dmat, &sc->rbd_seg, nsegs, IPW_RBD_SZ, 428 (void **)&sc->rbd_list, BUS_DMA_NOWAIT); 429 if (error != 0) { 430 aprint_error_dev(&sc->sc_dev, "could not map rbd dma memory\n"); 431 goto fail; 432 } 433 434 error = bus_dmamap_load(sc->sc_dmat, sc->rbd_map, sc->rbd_list, 435 IPW_RBD_SZ, NULL, BUS_DMA_NOWAIT); 436 if (error != 0) { 437 aprint_error_dev(&sc->sc_dev, "could not load rbd dma memory\n"); 438 goto fail; 439 } 440 441 (void)memset(sc->rbd_list, 0, IPW_RBD_SZ); 442 443 /* 444 * Allocate and map status ring. 445 */ 446 error = bus_dmamap_create(sc->sc_dmat, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 447 0, BUS_DMA_NOWAIT, &sc->status_map); 448 if (error != 0) { 449 aprint_error_dev(&sc->sc_dev, "could not create status dma map\n"); 450 goto fail; 451 } 452 453 error = bus_dmamem_alloc(sc->sc_dmat, IPW_STATUS_SZ, PAGE_SIZE, 0, 454 &sc->status_seg, 1, &nsegs, BUS_DMA_NOWAIT); 455 if (error != 0) { 456 aprint_error_dev(&sc->sc_dev, "could not allocate status dma memory\n"); 457 goto fail; 458 } 459 460 error = bus_dmamem_map(sc->sc_dmat, &sc->status_seg, nsegs, 461 IPW_STATUS_SZ, (void **)&sc->status_list, BUS_DMA_NOWAIT); 462 if (error != 0) { 463 aprint_error_dev(&sc->sc_dev, "could not map status dma memory\n"); 464 goto fail; 465 } 466 467 error = bus_dmamap_load(sc->sc_dmat, sc->status_map, sc->status_list, 468 IPW_STATUS_SZ, NULL, BUS_DMA_NOWAIT); 469 if (error != 0) { 470 aprint_error_dev(&sc->sc_dev, "could not load status dma memory\n"); 471 goto fail; 472 } 473 474 (void)memset(sc->status_list, 0, IPW_STATUS_SZ); 475 476 /* 477 * Allocate command DMA map. 478 */ 479 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_cmd), 480 1, sizeof (struct ipw_cmd), 0, BUS_DMA_NOWAIT, &sc->cmd_map); 481 if (error != 0) { 482 aprint_error_dev(&sc->sc_dev, "could not create cmd dma map\n"); 483 goto fail; 484 } 485 486 error = bus_dmamem_alloc(sc->sc_dmat, sizeof (struct ipw_cmd), 487 PAGE_SIZE, 0, &sc->cmd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 488 if (error != 0) { 489 aprint_error_dev(&sc->sc_dev, "could not allocate cmd dma memory\n"); 490 goto fail; 491 } 492 493 error = bus_dmamem_map(sc->sc_dmat, &sc->cmd_seg, nsegs, 494 sizeof (struct ipw_cmd), (void **)&sc->cmd, BUS_DMA_NOWAIT); 495 if (error != 0) { 496 aprint_error_dev(&sc->sc_dev, "could not map cmd dma memory\n"); 497 goto fail; 498 } 499 500 error = bus_dmamap_load(sc->sc_dmat, sc->cmd_map, &sc->cmd, 501 sizeof (struct ipw_cmd), NULL, BUS_DMA_NOWAIT); 502 if (error != 0) { 503 aprint_error_dev(&sc->sc_dev, "could not map cmd dma memory\n"); 504 return error; 505 } 506 507 /* 508 * Allocate and map hdr list. 509 */ 510 511 error = bus_dmamap_create(sc->sc_dmat, 512 IPW_NDATA * sizeof(struct ipw_hdr), 1, 513 sizeof(struct ipw_hdr), 0, BUS_DMA_NOWAIT, 514 &sc->hdr_map); 515 if (error != 0) { 516 aprint_error_dev(&sc->sc_dev, "could not create hdr dma map\n"); 517 goto fail; 518 } 519 520 error = bus_dmamem_alloc(sc->sc_dmat, 521 IPW_NDATA * sizeof(struct ipw_hdr), PAGE_SIZE, 0, &sc->hdr_seg, 522 1, &nsegs, BUS_DMA_NOWAIT); 523 if (error != 0) { 524 aprint_error_dev(&sc->sc_dev, "could not allocate hdr memory\n"); 525 goto fail; 526 } 527 528 error = bus_dmamem_map(sc->sc_dmat, &sc->hdr_seg, nsegs, 529 IPW_NDATA * sizeof(struct ipw_hdr), (void **)&sc->hdr_list, 530 BUS_DMA_NOWAIT); 531 if (error != 0) { 532 aprint_error_dev(&sc->sc_dev, "could not map hdr memory\n"); 533 goto fail; 534 } 535 536 error = bus_dmamap_load(sc->sc_dmat, sc->hdr_map, sc->hdr_list, 537 IPW_NDATA * sizeof(struct ipw_hdr), NULL, BUS_DMA_NOWAIT); 538 if (error != 0) { 539 aprint_error_dev(&sc->sc_dev, "could not load hdr memory\n"); 540 goto fail; 541 } 542 543 (void)memset(sc->hdr_list, 0, IPW_HDR_SZ); 544 545 /* 546 * Create DMA hdrs tailq. 547 */ 548 TAILQ_INIT(&sc->sc_free_shdr); 549 for (i = 0; i < IPW_NDATA; i++) { 550 shdr = &sc->shdr_list[i]; 551 shdr->hdr = sc->hdr_list + i; 552 shdr->offset = sizeof(struct ipw_hdr) * i; 553 shdr->addr = sc->hdr_map->dm_segs[0].ds_addr + shdr->offset; 554 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 555 } 556 557 /* 558 * Allocate tx buffers DMA maps. 559 */ 560 TAILQ_INIT(&sc->sc_free_sbuf); 561 for (i = 0; i < IPW_NDATA; i++) { 562 sbuf = &sc->tx_sbuf_list[i]; 563 564 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 565 IPW_MAX_NSEG, MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 566 if (error != 0) { 567 aprint_error_dev(&sc->sc_dev, "could not create txbuf dma map\n"); 568 goto fail; 569 } 570 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 571 } 572 573 /* 574 * Initialize tx ring. 575 */ 576 for (i = 0; i < IPW_NTBD; i++) { 577 sbd = &sc->stbd_list[i]; 578 sbd->bd = &sc->tbd_list[i]; 579 sbd->type = IPW_SBD_TYPE_NOASSOC; 580 } 581 582 /* 583 * Pre-allocate rx buffers and DMA maps 584 */ 585 for (i = 0; i < IPW_NRBD; i++) { 586 sbd = &sc->srbd_list[i]; 587 sbuf = &sc->rx_sbuf_list[i]; 588 sbd->bd = &sc->rbd_list[i]; 589 590 MGETHDR(sbuf->m, M_DONTWAIT, MT_DATA); 591 if (sbuf->m == NULL) { 592 aprint_error_dev(&sc->sc_dev, "could not allocate rx mbuf\n"); 593 error = ENOMEM; 594 goto fail; 595 } 596 597 MCLGET(sbuf->m, M_DONTWAIT); 598 if (!(sbuf->m->m_flags & M_EXT)) { 599 m_freem(sbuf->m); 600 aprint_error_dev(&sc->sc_dev, "could not allocate rx mbuf cluster\n"); 601 error = ENOMEM; 602 goto fail; 603 } 604 605 sbuf->m->m_pkthdr.len = sbuf->m->m_len = sbuf->m->m_ext.ext_size; 606 607 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 608 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sbuf->map); 609 if (error != 0) { 610 aprint_error_dev(&sc->sc_dev, "could not create rxbuf dma map\n"); 611 m_freem(sbuf->m); 612 goto fail; 613 } 614 615 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, 616 sbuf->m, BUS_DMA_READ | BUS_DMA_NOWAIT); 617 if (error != 0) { 618 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 619 m_freem(sbuf->m); 620 aprint_error_dev(&sc->sc_dev, "could not map rxbuf dma memory\n"); 621 goto fail; 622 } 623 624 sbd->type = IPW_SBD_TYPE_DATA; 625 sbd->priv = sbuf; 626 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 627 sbd->bd->len = htole32(MCLBYTES); 628 629 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, 630 sbuf->map->dm_mapsize, BUS_DMASYNC_PREREAD); 631 632 } 633 634 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 0, IPW_RBD_SZ, 635 BUS_DMASYNC_PREREAD); 636 637 return 0; 638 639 fail: ipw_release(sc); 640 return error; 641 } 642 643 static void 644 ipw_release(struct ipw_softc *sc) 645 { 646 struct ipw_soft_buf *sbuf; 647 int i; 648 649 if (sc->tbd_map != NULL) { 650 if (sc->tbd_list != NULL) { 651 bus_dmamap_unload(sc->sc_dmat, sc->tbd_map); 652 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->tbd_list, 653 IPW_TBD_SZ); 654 bus_dmamem_free(sc->sc_dmat, &sc->tbd_seg, 1); 655 } 656 bus_dmamap_destroy(sc->sc_dmat, sc->tbd_map); 657 } 658 659 if (sc->rbd_map != NULL) { 660 if (sc->rbd_list != NULL) { 661 bus_dmamap_unload(sc->sc_dmat, sc->rbd_map); 662 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->rbd_list, 663 IPW_RBD_SZ); 664 bus_dmamem_free(sc->sc_dmat, &sc->rbd_seg, 1); 665 } 666 bus_dmamap_destroy(sc->sc_dmat, sc->rbd_map); 667 } 668 669 if (sc->status_map != NULL) { 670 if (sc->status_list != NULL) { 671 bus_dmamap_unload(sc->sc_dmat, sc->status_map); 672 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->status_list, 673 IPW_RBD_SZ); 674 bus_dmamem_free(sc->sc_dmat, &sc->status_seg, 1); 675 } 676 bus_dmamap_destroy(sc->sc_dmat, sc->status_map); 677 } 678 679 for (i = 0; i < IPW_NTBD; i++) 680 ipw_release_sbd(sc, &sc->stbd_list[i]); 681 682 if (sc->cmd_map != NULL) 683 bus_dmamap_destroy(sc->sc_dmat, sc->cmd_map); 684 685 if (sc->hdr_list != NULL) { 686 bus_dmamap_unload(sc->sc_dmat, sc->hdr_map); 687 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->hdr_list, 688 IPW_NDATA * sizeof(struct ipw_hdr)); 689 } 690 if (sc->hdr_map != NULL) { 691 bus_dmamem_free(sc->sc_dmat, &sc->hdr_seg, 1); 692 bus_dmamap_destroy(sc->sc_dmat, sc->hdr_map); 693 } 694 695 for (i = 0; i < IPW_NDATA; i++) 696 bus_dmamap_destroy(sc->sc_dmat, sc->tx_sbuf_list[i].map); 697 698 for (i = 0; i < IPW_NRBD; i++) { 699 sbuf = &sc->rx_sbuf_list[i]; 700 if (sbuf->map != NULL) { 701 if (sbuf->m != NULL) { 702 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 703 m_freem(sbuf->m); 704 } 705 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 706 } 707 } 708 709 } 710 711 static int 712 ipw_media_change(struct ifnet *ifp) 713 { 714 int error; 715 716 error = ieee80211_media_change(ifp); 717 if (error != ENETRESET) 718 return error; 719 720 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 721 ipw_init(ifp); 722 723 return 0; 724 } 725 726 /* 727 * The firmware automatically adapts the transmit speed. We report the current 728 * transmit speed here. 729 */ 730 static void 731 ipw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 732 { 733 #define N(a) (sizeof (a) / sizeof (a[0])) 734 struct ipw_softc *sc = ifp->if_softc; 735 struct ieee80211com *ic = &sc->sc_ic; 736 static const struct { 737 uint32_t val; 738 int rate; 739 } rates[] = { 740 { IPW_RATE_DS1, 2 }, 741 { IPW_RATE_DS2, 4 }, 742 { IPW_RATE_DS5, 11 }, 743 { IPW_RATE_DS11, 22 }, 744 }; 745 uint32_t val; 746 int rate, i; 747 748 imr->ifm_status = IFM_AVALID; 749 imr->ifm_active = IFM_IEEE80211; 750 if (ic->ic_state == IEEE80211_S_RUN) 751 imr->ifm_status |= IFM_ACTIVE; 752 753 /* read current transmission rate from adapter */ 754 val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE) & 0xf; 755 756 /* convert ipw rate to 802.11 rate */ 757 for (i = 0; i < N(rates) && rates[i].val != val; i++); 758 rate = (i < N(rates)) ? rates[i].rate : 0; 759 760 imr->ifm_active |= IFM_IEEE80211_11B; 761 imr->ifm_active |= ieee80211_rate2media(ic, rate, IEEE80211_MODE_11B); 762 switch (ic->ic_opmode) { 763 case IEEE80211_M_STA: 764 break; 765 766 case IEEE80211_M_IBSS: 767 imr->ifm_active |= IFM_IEEE80211_ADHOC; 768 break; 769 770 case IEEE80211_M_MONITOR: 771 imr->ifm_active |= IFM_IEEE80211_MONITOR; 772 break; 773 774 case IEEE80211_M_AHDEMO: 775 case IEEE80211_M_HOSTAP: 776 /* should not get there */ 777 break; 778 } 779 #undef N 780 } 781 782 static int 783 ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, 784 int arg) 785 { 786 struct ifnet *ifp = ic->ic_ifp; 787 struct ipw_softc *sc = ifp->if_softc; 788 struct ieee80211_node *ni; 789 uint8_t macaddr[IEEE80211_ADDR_LEN]; 790 uint32_t len; 791 792 switch (nstate) { 793 case IEEE80211_S_RUN: 794 DELAY(200); /* firmware needs a short delay here */ 795 796 len = IEEE80211_ADDR_LEN; 797 ipw_read_table2(sc, IPW_INFO_CURRENT_BSSID, macaddr, &len); 798 799 ni = ieee80211_find_node(&ic->ic_scan, macaddr); 800 if (ni == NULL) 801 break; 802 803 ieee80211_ref_node(ni); 804 ieee80211_sta_join(ic, ni); 805 ieee80211_node_authorize(ni); 806 807 if (ic->ic_opmode == IEEE80211_M_STA) 808 ieee80211_notify_node_join(ic, ni, 1); 809 break; 810 811 case IEEE80211_S_INIT: 812 case IEEE80211_S_SCAN: 813 case IEEE80211_S_AUTH: 814 case IEEE80211_S_ASSOC: 815 break; 816 } 817 818 ic->ic_state = nstate; 819 return 0; 820 } 821 822 /* 823 * Read 16 bits at address 'addr' from the serial EEPROM. 824 */ 825 static uint16_t 826 ipw_read_prom_word(struct ipw_softc *sc, uint8_t addr) 827 { 828 uint32_t tmp; 829 uint16_t val; 830 int n; 831 832 /* clock C once before the first command */ 833 IPW_EEPROM_CTL(sc, 0); 834 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 835 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 836 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 837 838 /* write start bit (1) */ 839 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 840 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 841 842 /* write READ opcode (10) */ 843 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 844 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 845 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 846 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 847 848 /* write address A7-A0 */ 849 for (n = 7; n >= 0; n--) { 850 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 851 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D)); 852 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 853 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D) | IPW_EEPROM_C); 854 } 855 856 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 857 858 /* read data Q15-Q0 */ 859 val = 0; 860 for (n = 15; n >= 0; n--) { 861 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 862 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 863 tmp = MEM_READ_4(sc, IPW_MEM_EEPROM_CTL); 864 val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n; 865 } 866 867 IPW_EEPROM_CTL(sc, 0); 868 869 /* clear Chip Select and clock C */ 870 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 871 IPW_EEPROM_CTL(sc, 0); 872 IPW_EEPROM_CTL(sc, IPW_EEPROM_C); 873 874 return le16toh(val); 875 } 876 877 static void 878 ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 879 { 880 struct ipw_cmd *cmd; 881 882 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof (struct ipw_cmd), 883 BUS_DMASYNC_POSTREAD); 884 885 cmd = mtod(sbuf->m, struct ipw_cmd *); 886 887 DPRINTFN(2, ("cmd ack'ed (%u, %u, %u, %u, %u)\n", le32toh(cmd->type), 888 le32toh(cmd->subtype), le32toh(cmd->seq), le32toh(cmd->len), 889 le32toh(cmd->status))); 890 891 wakeup(&sc->cmd); 892 } 893 894 static void 895 ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 896 { 897 struct ieee80211com *ic = &sc->sc_ic; 898 struct ifnet *ifp = sc->sc_ic.ic_ifp; 899 uint32_t state; 900 901 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof state, 902 BUS_DMASYNC_POSTREAD); 903 904 state = le32toh(*mtod(sbuf->m, uint32_t *)); 905 906 DPRINTFN(2, ("entering state %u\n", state)); 907 908 switch (state) { 909 case IPW_STATE_ASSOCIATED: 910 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 911 break; 912 913 case IPW_STATE_SCANNING: 914 /* don't leave run state on background scan */ 915 if (ic->ic_state != IEEE80211_S_RUN) 916 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 917 918 ic->ic_flags |= IEEE80211_F_SCAN; 919 break; 920 921 case IPW_STATE_SCAN_COMPLETE: 922 ieee80211_notify_scan_done(ic); 923 ic->ic_flags &= ~IEEE80211_F_SCAN; 924 break; 925 926 case IPW_STATE_ASSOCIATION_LOST: 927 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 928 break; 929 930 case IPW_STATE_RADIO_DISABLED: 931 ic->ic_ifp->if_flags &= ~IFF_UP; 932 ipw_stop(ifp, 1); 933 break; 934 } 935 } 936 937 /* 938 * XXX: Hack to set the current channel to the value advertised in beacons or 939 * probe responses. Only used during AP detection. 940 */ 941 static void 942 ipw_fix_channel(struct ieee80211com *ic, struct mbuf *m) 943 { 944 struct ieee80211_frame *wh; 945 uint8_t subtype; 946 uint8_t *frm, *efrm; 947 948 wh = mtod(m, struct ieee80211_frame *); 949 950 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_MGT) 951 return; 952 953 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 954 955 if (subtype != IEEE80211_FC0_SUBTYPE_BEACON && 956 subtype != IEEE80211_FC0_SUBTYPE_PROBE_RESP) 957 return; 958 959 frm = (uint8_t *)(wh + 1); 960 efrm = mtod(m, uint8_t *) + m->m_len; 961 962 frm += 12; /* skip tstamp, bintval and capinfo fields */ 963 while (frm < efrm) { 964 if (*frm == IEEE80211_ELEMID_DSPARMS) 965 #if IEEE80211_CHAN_MAX < 255 966 if (frm[2] <= IEEE80211_CHAN_MAX) 967 #endif 968 ic->ic_curchan = &ic->ic_channels[frm[2]]; 969 970 frm += frm[1] + 2; 971 } 972 } 973 974 static void 975 ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 976 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 977 { 978 struct ieee80211com *ic = &sc->sc_ic; 979 struct ifnet *ifp = &sc->sc_if; 980 struct mbuf *mnew, *m; 981 struct ieee80211_frame *wh; 982 struct ieee80211_node *ni; 983 int error; 984 985 DPRINTFN(5, ("received frame len=%u, rssi=%u\n", le32toh(status->len), 986 status->rssi)); 987 988 if (le32toh(status->len) < sizeof (struct ieee80211_frame_min) || 989 le32toh(status->len) > MCLBYTES) 990 return; 991 992 /* 993 * Try to allocate a new mbuf for this ring element and load it before 994 * processing the current mbuf. If the ring element cannot be loaded, 995 * drop the received packet and reuse the old mbuf. In the unlikely 996 * case that the old mbuf can't be reloaded either, explicitly panic. 997 */ 998 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 999 if (mnew == NULL) { 1000 aprint_error_dev(&sc->sc_dev, "could not allocate rx mbuf\n"); 1001 ifp->if_ierrors++; 1002 return; 1003 } 1004 1005 MCLGET(mnew, M_DONTWAIT); 1006 if (!(mnew->m_flags & M_EXT)) { 1007 aprint_error_dev(&sc->sc_dev, "could not allocate rx mbuf cluster\n"); 1008 m_freem(mnew); 1009 ifp->if_ierrors++; 1010 return; 1011 } 1012 1013 mnew->m_pkthdr.len = mnew->m_len = mnew->m_ext.ext_size; 1014 1015 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, le32toh(status->len), 1016 BUS_DMASYNC_POSTREAD); 1017 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1018 1019 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, mnew, 1020 BUS_DMA_READ | BUS_DMA_NOWAIT); 1021 if (error != 0) { 1022 aprint_error_dev(&sc->sc_dev, "could not load rx buf DMA map\n"); 1023 m_freem(mnew); 1024 1025 /* try to reload the old mbuf */ 1026 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, 1027 sbuf->m, BUS_DMA_READ | BUS_DMA_NOWAIT); 1028 if (error != 0) { 1029 /* very unlikely that it will fail... */ 1030 panic("%s: unable to remap rx buf", 1031 device_xname(&sc->sc_dev)); 1032 } 1033 ifp->if_ierrors++; 1034 return; 1035 } 1036 1037 /* 1038 * New mbuf successfully loaded, update Rx ring and continue 1039 * processing. 1040 */ 1041 m = sbuf->m; 1042 sbuf->m = mnew; 1043 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 1044 1045 /* finalize mbuf */ 1046 m->m_pkthdr.rcvif = ifp; 1047 m->m_pkthdr.len = m->m_len = le32toh(status->len); 1048 1049 #if NBPFILTER > 0 1050 if (sc->sc_drvbpf != NULL) { 1051 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 1052 1053 tap->wr_flags = 0; 1054 tap->wr_antsignal = status->rssi; 1055 tap->wr_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 1056 tap->wr_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 1057 1058 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 1059 } 1060 #endif 1061 1062 if (ic->ic_state == IEEE80211_S_SCAN) 1063 ipw_fix_channel(ic, m); 1064 1065 wh = mtod(m, struct ieee80211_frame *); 1066 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 1067 1068 /* send the frame to the 802.11 layer */ 1069 ieee80211_input(ic, m, ni, status->rssi, 0); 1070 1071 /* node is no longer needed */ 1072 ieee80211_free_node(ni); 1073 1074 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, 1075 sbuf->map->dm_mapsize, BUS_DMASYNC_PREREAD); 1076 } 1077 1078 static void 1079 ipw_rx_intr(struct ipw_softc *sc) 1080 { 1081 struct ipw_status *status; 1082 struct ipw_soft_bd *sbd; 1083 struct ipw_soft_buf *sbuf; 1084 uint32_t r, i; 1085 1086 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1087 return; 1088 1089 r = CSR_READ_4(sc, IPW_CSR_RX_READ); 1090 1091 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 1092 1093 /* firmware was killed, stop processing received frames */ 1094 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1095 return; 1096 1097 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 1098 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1099 BUS_DMASYNC_POSTREAD); 1100 1101 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 1102 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 1103 BUS_DMASYNC_POSTREAD); 1104 1105 status = &sc->status_list[i]; 1106 sbd = &sc->srbd_list[i]; 1107 sbuf = sbd->priv; 1108 1109 switch (le16toh(status->code) & 0xf) { 1110 case IPW_STATUS_CODE_COMMAND: 1111 ipw_command_intr(sc, sbuf); 1112 break; 1113 1114 case IPW_STATUS_CODE_NEWSTATE: 1115 ipw_newstate_intr(sc, sbuf); 1116 break; 1117 1118 case IPW_STATUS_CODE_DATA_802_3: 1119 case IPW_STATUS_CODE_DATA_802_11: 1120 ipw_data_intr(sc, status, sbd, sbuf); 1121 break; 1122 1123 case IPW_STATUS_CODE_NOTIFICATION: 1124 DPRINTFN(2, ("received notification\n")); 1125 break; 1126 1127 default: 1128 aprint_error_dev(&sc->sc_dev, "unknown status code %u\n", 1129 le16toh(status->code)); 1130 } 1131 1132 sbd->bd->flags = 0; 1133 1134 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 1135 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1136 BUS_DMASYNC_PREREAD); 1137 1138 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 1139 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 1140 BUS_DMASYNC_PREREAD); 1141 } 1142 1143 /* Tell the firmware what we have processed */ 1144 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 1145 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 1146 } 1147 1148 static void 1149 ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 1150 { 1151 struct ieee80211com *ic; 1152 struct ipw_soft_hdr *shdr; 1153 struct ipw_soft_buf *sbuf; 1154 1155 switch (sbd->type) { 1156 case IPW_SBD_TYPE_COMMAND: 1157 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 1158 0, sizeof(struct ipw_cmd), BUS_DMASYNC_POSTWRITE); 1159 /* bus_dmamap_unload(sc->sc_dmat, sc->cmd_map); */ 1160 break; 1161 1162 case IPW_SBD_TYPE_HEADER: 1163 shdr = sbd->priv; 1164 bus_dmamap_sync(sc->sc_dmat, sc->hdr_map, 1165 shdr->offset, sizeof(struct ipw_hdr), BUS_DMASYNC_POSTWRITE); 1166 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 1167 break; 1168 1169 case IPW_SBD_TYPE_DATA: 1170 ic = &sc->sc_ic; 1171 sbuf = sbd->priv; 1172 1173 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 1174 0, MCLBYTES, BUS_DMASYNC_POSTWRITE); 1175 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1176 m_freem(sbuf->m); 1177 if (sbuf->ni != NULL) 1178 ieee80211_free_node(sbuf->ni); 1179 /* kill watchdog timer */ 1180 sc->sc_tx_timer = 0; 1181 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 1182 break; 1183 } 1184 sbd->type = IPW_SBD_TYPE_NOASSOC; 1185 } 1186 1187 static void 1188 ipw_tx_intr(struct ipw_softc *sc) 1189 { 1190 struct ifnet *ifp = &sc->sc_if; 1191 struct ipw_soft_bd *sbd; 1192 uint32_t r, i; 1193 1194 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1195 return; 1196 1197 r = CSR_READ_4(sc, IPW_CSR_TX_READ); 1198 1199 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) { 1200 sbd = &sc->stbd_list[i]; 1201 1202 if (sbd->type == IPW_SBD_TYPE_DATA) 1203 ifp->if_opackets++; 1204 1205 ipw_release_sbd(sc, sbd); 1206 sc->txfree++; 1207 } 1208 1209 /* remember what the firmware has processed */ 1210 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 1211 1212 /* Call start() since some buffer descriptors have been released */ 1213 ifp->if_flags &= ~IFF_OACTIVE; 1214 (*ifp->if_start)(ifp); 1215 } 1216 1217 static int 1218 ipw_intr(void *arg) 1219 { 1220 struct ipw_softc *sc = arg; 1221 uint32_t r; 1222 1223 r = CSR_READ_4(sc, IPW_CSR_INTR); 1224 if (r == 0 || r == 0xffffffff) 1225 return 0; 1226 1227 /* Disable interrupts */ 1228 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1229 1230 if (r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR)) { 1231 aprint_error_dev(&sc->sc_dev, "fatal error\n"); 1232 sc->sc_ic.ic_ifp->if_flags &= ~IFF_UP; 1233 ipw_stop(&sc->sc_if, 1); 1234 } 1235 1236 if (r & IPW_INTR_FW_INIT_DONE) { 1237 if (!(r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR))) 1238 wakeup(sc); 1239 } 1240 1241 if (r & IPW_INTR_RX_TRANSFER) 1242 ipw_rx_intr(sc); 1243 1244 if (r & IPW_INTR_TX_TRANSFER) 1245 ipw_tx_intr(sc); 1246 1247 /* Acknowledge all interrupts */ 1248 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 1249 1250 /* Re-enable interrupts */ 1251 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1252 1253 return 0; 1254 } 1255 1256 /* 1257 * Send a command to the firmware and wait for the acknowledgement. 1258 */ 1259 static int 1260 ipw_cmd(struct ipw_softc *sc, uint32_t type, void *data, uint32_t len) 1261 { 1262 struct ipw_soft_bd *sbd; 1263 1264 sbd = &sc->stbd_list[sc->txcur]; 1265 1266 sc->cmd.type = htole32(type); 1267 sc->cmd.subtype = 0; 1268 sc->cmd.len = htole32(len); 1269 sc->cmd.seq = 0; 1270 1271 (void)memcpy(sc->cmd.data, data, len); 1272 1273 sbd->type = IPW_SBD_TYPE_COMMAND; 1274 sbd->bd->physaddr = htole32(sc->cmd_map->dm_segs[0].ds_addr); 1275 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 1276 sbd->bd->nfrag = 1; 1277 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 1278 IPW_BD_FLAG_TX_LAST_FRAGMENT; 1279 1280 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 0, sizeof (struct ipw_cmd), 1281 BUS_DMASYNC_PREWRITE); 1282 1283 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1284 sc->txcur * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1285 BUS_DMASYNC_PREWRITE); 1286 1287 DPRINTFN(2, ("sending command (%u, %u, %u, %u)\n", type, 0, 0, len)); 1288 1289 /* kick firmware */ 1290 sc->txfree--; 1291 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1292 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1293 1294 /* Wait at most one second for command to complete */ 1295 return tsleep(&sc->cmd, 0, "ipwcmd", hz); 1296 } 1297 1298 static int 1299 ipw_tx_start(struct ifnet *ifp, struct mbuf *m0, struct ieee80211_node *ni) 1300 { 1301 struct ipw_softc *sc = ifp->if_softc; 1302 struct ieee80211com *ic = &sc->sc_ic; 1303 struct ieee80211_frame *wh; 1304 struct ipw_soft_bd *sbd; 1305 struct ipw_soft_hdr *shdr; 1306 struct ipw_soft_buf *sbuf; 1307 struct ieee80211_key *k; 1308 struct mbuf *mnew; 1309 int error, i; 1310 1311 wh = mtod(m0, struct ieee80211_frame *); 1312 1313 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1314 k = ieee80211_crypto_encap(ic, ni, m0); 1315 if (k == NULL) { 1316 m_freem(m0); 1317 return ENOBUFS; 1318 } 1319 1320 /* packet header may have moved, reset our local pointer */ 1321 wh = mtod(m0, struct ieee80211_frame *); 1322 } 1323 1324 #if NBPFILTER > 0 1325 if (sc->sc_drvbpf != NULL) { 1326 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 1327 1328 tap->wt_flags = 0; 1329 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 1330 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 1331 1332 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 1333 } 1334 #endif 1335 1336 shdr = TAILQ_FIRST(&sc->sc_free_shdr); 1337 sbuf = TAILQ_FIRST(&sc->sc_free_sbuf); 1338 KASSERT(shdr != NULL && sbuf != NULL); 1339 1340 shdr->hdr->type = htole32(IPW_HDR_TYPE_SEND); 1341 shdr->hdr->subtype = 0; 1342 shdr->hdr->encrypted = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0; 1343 shdr->hdr->encrypt = 0; 1344 shdr->hdr->keyidx = 0; 1345 shdr->hdr->keysz = 0; 1346 shdr->hdr->fragmentsz = 0; 1347 IEEE80211_ADDR_COPY(shdr->hdr->src_addr, wh->i_addr2); 1348 if (ic->ic_opmode == IEEE80211_M_STA) 1349 IEEE80211_ADDR_COPY(shdr->hdr->dst_addr, wh->i_addr3); 1350 else 1351 IEEE80211_ADDR_COPY(shdr->hdr->dst_addr, wh->i_addr1); 1352 1353 /* trim IEEE802.11 header */ 1354 m_adj(m0, sizeof (struct ieee80211_frame)); 1355 1356 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m0, BUS_DMA_NOWAIT); 1357 if (error != 0 && error != EFBIG) { 1358 aprint_error_dev(&sc->sc_dev, "could not map mbuf (error %d)\n", 1359 error); 1360 m_freem(m0); 1361 return error; 1362 } 1363 1364 if (error != 0) { 1365 /* too many fragments, linearize */ 1366 1367 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1368 if (mnew == NULL) { 1369 m_freem(m0); 1370 return ENOMEM; 1371 } 1372 1373 M_COPY_PKTHDR(mnew, m0); 1374 1375 /* If the data won't fit in the header, get a cluster */ 1376 if (m0->m_pkthdr.len > MHLEN) { 1377 MCLGET(mnew, M_DONTWAIT); 1378 if (!(mnew->m_flags & M_EXT)) { 1379 m_freem(m0); 1380 m_freem(mnew); 1381 return ENOMEM; 1382 } 1383 } 1384 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(mnew, void *)); 1385 m_freem(m0); 1386 mnew->m_len = mnew->m_pkthdr.len; 1387 m0 = mnew; 1388 1389 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m0, 1390 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1391 if (error != 0) { 1392 aprint_error_dev(&sc->sc_dev, "could not map mbuf (error %d)\n", error); 1393 m_freem(m0); 1394 return error; 1395 } 1396 } 1397 1398 TAILQ_REMOVE(&sc->sc_free_sbuf, sbuf, next); 1399 TAILQ_REMOVE(&sc->sc_free_shdr, shdr, next); 1400 1401 sbd = &sc->stbd_list[sc->txcur]; 1402 sbd->type = IPW_SBD_TYPE_HEADER; 1403 sbd->priv = shdr; 1404 sbd->bd->physaddr = htole32(shdr->addr); 1405 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 1406 sbd->bd->nfrag = 1 + sbuf->map->dm_nsegs; 1407 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 1408 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1409 1410 DPRINTFN(5, ("sending tx hdr (%u, %u, %u, %u, )\n", 1411 shdr->hdr->type, shdr->hdr->subtype, shdr->hdr->encrypted, 1412 shdr->hdr->encrypt)); 1413 DPRINTFN(5, ("%s->", ether_sprintf(shdr->hdr->src_addr))); 1414 DPRINTFN(5, ("%s\n", ether_sprintf(shdr->hdr->dst_addr))); 1415 1416 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1417 sc->txcur * sizeof (struct ipw_bd), 1418 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1419 1420 sc->txfree--; 1421 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1422 1423 sbuf->m = m0; 1424 sbuf->ni = ni; 1425 1426 for (i = 0; i < sbuf->map->dm_nsegs; i++) { 1427 sbd = &sc->stbd_list[sc->txcur]; 1428 1429 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[i].ds_addr); 1430 sbd->bd->len = htole32(sbuf->map->dm_segs[i].ds_len); 1431 sbd->bd->nfrag = 0; 1432 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 1433 if (i == sbuf->map->dm_nsegs - 1) { 1434 sbd->type = IPW_SBD_TYPE_DATA; 1435 sbd->priv = sbuf; 1436 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 1437 } else { 1438 sbd->type = IPW_SBD_TYPE_NOASSOC; 1439 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1440 } 1441 1442 DPRINTFN(5, ("sending fragment (%d, %d)\n", i, 1443 (int)sbuf->map->dm_segs[i].ds_len)); 1444 1445 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1446 sc->txcur * sizeof (struct ipw_bd), 1447 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1448 1449 sc->txfree--; 1450 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1451 } 1452 1453 bus_dmamap_sync(sc->sc_dmat, sc->hdr_map, shdr->offset, 1454 sizeof (struct ipw_hdr), BUS_DMASYNC_PREWRITE); 1455 1456 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, MCLBYTES, 1457 BUS_DMASYNC_PREWRITE); 1458 1459 /* Inform firmware about this new packet */ 1460 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1461 1462 return 0; 1463 } 1464 1465 static void 1466 ipw_start(struct ifnet *ifp) 1467 { 1468 struct ipw_softc *sc = ifp->if_softc; 1469 struct ieee80211com *ic = &sc->sc_ic; 1470 struct mbuf *m0; 1471 struct ether_header *eh; 1472 struct ieee80211_node *ni; 1473 1474 1475 if (ic->ic_state != IEEE80211_S_RUN) 1476 return; 1477 1478 for (;;) { 1479 IF_DEQUEUE(&ifp->if_snd, m0); 1480 if (m0 == NULL) 1481 break; 1482 1483 if (sc->txfree < 1 + IPW_MAX_NSEG) { 1484 IF_PREPEND(&ifp->if_snd, m0); 1485 ifp->if_flags |= IFF_OACTIVE; 1486 break; 1487 } 1488 1489 if (m0->m_len < sizeof (struct ether_header) && 1490 (m0 = m_pullup(m0, sizeof (struct ether_header))) == NULL) 1491 continue; 1492 1493 eh = mtod(m0, struct ether_header *); 1494 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1495 if (ni == NULL) { 1496 m_freem(m0); 1497 continue; 1498 } 1499 1500 #if NBPFILTER > 0 1501 if (ifp->if_bpf != NULL) 1502 bpf_mtap(ifp->if_bpf, m0); 1503 #endif 1504 1505 m0 = ieee80211_encap(ic, m0, ni); 1506 if (m0 == NULL) { 1507 ieee80211_free_node(ni); 1508 continue; 1509 } 1510 1511 #if NBPFILTER > 0 1512 if (ic->ic_rawbpf != NULL) 1513 bpf_mtap(ic->ic_rawbpf, m0); 1514 #endif 1515 1516 if (ipw_tx_start(ifp, m0, ni) != 0) { 1517 ieee80211_free_node(ni); 1518 ifp->if_oerrors++; 1519 break; 1520 } 1521 1522 /* start watchdog timer */ 1523 sc->sc_tx_timer = 5; 1524 ifp->if_timer = 1; 1525 } 1526 } 1527 1528 static void 1529 ipw_watchdog(struct ifnet *ifp) 1530 { 1531 struct ipw_softc *sc = ifp->if_softc; 1532 1533 ifp->if_timer = 0; 1534 1535 if (sc->sc_tx_timer > 0) { 1536 if (--sc->sc_tx_timer == 0) { 1537 aprint_error_dev(&sc->sc_dev, "device timeout\n"); 1538 ifp->if_oerrors++; 1539 ifp->if_flags &= ~IFF_UP; 1540 ipw_stop(ifp, 1); 1541 return; 1542 } 1543 ifp->if_timer = 1; 1544 } 1545 1546 ieee80211_watchdog(&sc->sc_ic); 1547 } 1548 1549 static int 1550 ipw_get_table1(struct ipw_softc *sc, uint32_t *tbl) 1551 { 1552 uint32_t addr, size, i; 1553 1554 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1555 return ENOTTY; 1556 1557 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, sc->table1_base); 1558 1559 size = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 1560 if (suword(tbl, size) != 0) 1561 return EFAULT; 1562 1563 for (i = 1, ++tbl; i < size; i++, tbl++) { 1564 addr = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 1565 if (suword(tbl, MEM_READ_4(sc, addr)) != 0) 1566 return EFAULT; 1567 } 1568 return 0; 1569 } 1570 1571 static int 1572 ipw_get_radio(struct ipw_softc *sc, int *ret) 1573 { 1574 uint32_t addr; 1575 1576 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1577 return ENOTTY; 1578 1579 addr = ipw_read_table1(sc, IPW_INFO_EEPROM_ADDRESS); 1580 if ((MEM_READ_4(sc, addr + 32) >> 24) & 1) { 1581 suword(ret, -1); 1582 return 0; 1583 } 1584 1585 if (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED) 1586 suword(ret, 0); 1587 else 1588 suword(ret, 1); 1589 1590 return 0; 1591 } 1592 1593 static int 1594 ipw_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1595 { 1596 #define IS_RUNNING(ifp) \ 1597 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 1598 1599 struct ipw_softc *sc = ifp->if_softc; 1600 struct ieee80211com *ic = &sc->sc_ic; 1601 struct ifreq *ifr = (struct ifreq *)data; 1602 int s, error = 0; 1603 1604 s = splnet(); 1605 1606 switch (cmd) { 1607 case SIOCSIFFLAGS: 1608 if (ifp->if_flags & IFF_UP) { 1609 if (!(ifp->if_flags & IFF_RUNNING)) 1610 ipw_init(ifp); 1611 } else { 1612 if (ifp->if_flags & IFF_RUNNING) 1613 ipw_stop(ifp, 1); 1614 } 1615 break; 1616 1617 case SIOCADDMULTI: 1618 case SIOCDELMULTI: 1619 /* XXX no h/w multicast filter? --dyoung */ 1620 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1621 /* setup multicast filter, etc */ 1622 error = 0; 1623 } 1624 break; 1625 1626 case SIOCGTABLE1: 1627 error = ipw_get_table1(sc, (uint32_t *)ifr->ifr_data); 1628 break; 1629 1630 case SIOCGRADIO: 1631 error = ipw_get_radio(sc, (int *)ifr->ifr_data); 1632 break; 1633 1634 case SIOCSIFMEDIA: 1635 if (ifr->ifr_media & IFM_IEEE80211_ADHOC) 1636 strlcpy(sc->sc_fwname, "ipw2100-1.2-i.fw", 1637 sizeof(sc->sc_fwname)); 1638 else if (ifr->ifr_media & IFM_IEEE80211_MONITOR) 1639 strlcpy(sc->sc_fwname, "ipw2100-1.2-p.fw", 1640 sizeof(sc->sc_fwname)); 1641 else 1642 strlcpy(sc->sc_fwname, "ipw2100-1.2.fw", 1643 sizeof(sc->sc_fwname)); 1644 1645 ipw_free_firmware(sc); 1646 /* FALLTRHOUGH */ 1647 default: 1648 error = ieee80211_ioctl(&sc->sc_ic, cmd, data); 1649 if (error != ENETRESET) 1650 break; 1651 1652 if (error == ENETRESET) { 1653 if (IS_RUNNING(ifp) && 1654 (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)) 1655 ipw_init(ifp); 1656 error = 0; 1657 } 1658 1659 } 1660 1661 splx(s); 1662 return error; 1663 #undef IS_RUNNING 1664 } 1665 1666 static uint32_t 1667 ipw_read_table1(struct ipw_softc *sc, uint32_t off) 1668 { 1669 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 1670 } 1671 1672 static void 1673 ipw_write_table1(struct ipw_softc *sc, uint32_t off, uint32_t info) 1674 { 1675 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 1676 } 1677 1678 static int 1679 ipw_read_table2(struct ipw_softc *sc, uint32_t off, void *buf, uint32_t *len) 1680 { 1681 uint32_t addr, info; 1682 uint16_t count, size; 1683 uint32_t total; 1684 1685 /* addr[4] + count[2] + size[2] */ 1686 addr = MEM_READ_4(sc, sc->table2_base + off); 1687 info = MEM_READ_4(sc, sc->table2_base + off + 4); 1688 1689 count = info >> 16; 1690 size = info & 0xffff; 1691 total = count * size; 1692 1693 if (total > *len) { 1694 *len = total; 1695 return EINVAL; 1696 } 1697 1698 *len = total; 1699 ipw_read_mem_1(sc, addr, buf, total); 1700 1701 return 0; 1702 } 1703 1704 static void 1705 ipw_stop_master(struct ipw_softc *sc) 1706 { 1707 int ntries; 1708 1709 /* disable interrupts */ 1710 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1711 1712 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1713 for (ntries = 0; ntries < 50; ntries++) { 1714 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1715 break; 1716 DELAY(10); 1717 } 1718 if (ntries == 50) 1719 aprint_error_dev(&sc->sc_dev, "timeout waiting for master\n"); 1720 1721 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1722 IPW_RST_PRINCETON_RESET); 1723 1724 sc->flags &= ~IPW_FLAG_FW_INITED; 1725 } 1726 1727 static int 1728 ipw_reset(struct ipw_softc *sc) 1729 { 1730 int ntries; 1731 1732 ipw_stop_master(sc); 1733 1734 /* move adapter to D0 state */ 1735 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1736 IPW_CTL_INIT); 1737 1738 /* wait for clock stabilization */ 1739 for (ntries = 0; ntries < 1000; ntries++) { 1740 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY) 1741 break; 1742 DELAY(200); 1743 } 1744 if (ntries == 1000) 1745 return EIO; 1746 1747 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1748 IPW_RST_SW_RESET); 1749 1750 DELAY(10); 1751 1752 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1753 IPW_CTL_INIT); 1754 1755 return 0; 1756 } 1757 1758 /* 1759 * Upload the microcode to the device. 1760 */ 1761 static int 1762 ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size) 1763 { 1764 int ntries; 1765 1766 MEM_WRITE_4(sc, 0x3000e0, 0x80000000); 1767 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1768 1769 MEM_WRITE_2(sc, 0x220000, 0x0703); 1770 MEM_WRITE_2(sc, 0x220000, 0x0707); 1771 1772 MEM_WRITE_1(sc, 0x210014, 0x72); 1773 MEM_WRITE_1(sc, 0x210014, 0x72); 1774 1775 MEM_WRITE_1(sc, 0x210000, 0x40); 1776 MEM_WRITE_1(sc, 0x210000, 0x00); 1777 MEM_WRITE_1(sc, 0x210000, 0x40); 1778 1779 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1780 1781 MEM_WRITE_1(sc, 0x210000, 0x00); 1782 MEM_WRITE_1(sc, 0x210000, 0x00); 1783 MEM_WRITE_1(sc, 0x210000, 0x80); 1784 1785 MEM_WRITE_2(sc, 0x220000, 0x0703); 1786 MEM_WRITE_2(sc, 0x220000, 0x0707); 1787 1788 MEM_WRITE_1(sc, 0x210014, 0x72); 1789 MEM_WRITE_1(sc, 0x210014, 0x72); 1790 1791 MEM_WRITE_1(sc, 0x210000, 0x00); 1792 MEM_WRITE_1(sc, 0x210000, 0x80); 1793 1794 for (ntries = 0; ntries < 10; ntries++) { 1795 if (MEM_READ_1(sc, 0x210000) & 1) 1796 break; 1797 DELAY(10); 1798 } 1799 if (ntries == 10) { 1800 aprint_error_dev(&sc->sc_dev, "timeout waiting for ucode to initialize\n"); 1801 return EIO; 1802 } 1803 1804 MEM_WRITE_4(sc, 0x3000e0, 0); 1805 1806 return 0; 1807 } 1808 1809 /* set of macros to handle unaligned little endian data in firmware image */ 1810 #define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1811 #define GETLE16(p) ((p)[0] | (p)[1] << 8) 1812 static int 1813 ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size) 1814 { 1815 u_char *p, *end; 1816 uint32_t dst; 1817 uint16_t len; 1818 int error; 1819 1820 p = fw; 1821 end = fw + size; 1822 while (p < end) { 1823 dst = GETLE32(p); p += 4; 1824 len = GETLE16(p); p += 2; 1825 1826 ipw_write_mem_1(sc, dst, p, len); 1827 p += len; 1828 } 1829 1830 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1831 IPW_IO_LED_OFF); 1832 1833 /* enable interrupts */ 1834 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1835 1836 /* kick the firmware */ 1837 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1838 1839 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1840 IPW_CTL_ALLOW_STANDBY); 1841 1842 /* wait at most one second for firmware initialization to complete */ 1843 if ((error = tsleep(sc, 0, "ipwinit", hz)) != 0) { 1844 aprint_error_dev(&sc->sc_dev, "timeout waiting for firmware initialization " 1845 "to complete\n"); 1846 return error; 1847 } 1848 1849 CSR_WRITE_4(sc, IPW_CSR_IO, CSR_READ_4(sc, IPW_CSR_IO) | 1850 IPW_IO_GPIO1_MASK | IPW_IO_GPIO3_MASK); 1851 1852 return 0; 1853 } 1854 1855 /* 1856 * Store firmware into kernel memory so we can download it when we need to, 1857 * e.g when the adapter wakes up from suspend mode. 1858 */ 1859 static int 1860 ipw_cache_firmware(struct ipw_softc *sc) 1861 { 1862 struct ipw_firmware *fw = &sc->fw; 1863 struct ipw_firmware_hdr hdr; 1864 firmware_handle_t fwh; 1865 off_t fwsz, p; 1866 int error; 1867 1868 ipw_free_firmware(sc); 1869 1870 if ((error = firmware_open("if_ipw", sc->sc_fwname, &fwh)) != 0) 1871 goto fail0; 1872 1873 fwsz = firmware_get_size(fwh); 1874 1875 if (fwsz < sizeof(hdr)) 1876 goto fail2; 1877 1878 if ((error = firmware_read(fwh, 0, &hdr, sizeof(hdr))) != 0) 1879 goto fail2; 1880 1881 fw->main_size = le32toh(hdr.main_size); 1882 fw->ucode_size = le32toh(hdr.ucode_size); 1883 1884 fw->main = firmware_malloc(fw->main_size); 1885 if (fw->main == NULL) { 1886 error = ENOMEM; 1887 goto fail1; 1888 } 1889 1890 fw->ucode = firmware_malloc(fw->ucode_size); 1891 if (fw->ucode == NULL) { 1892 error = ENOMEM; 1893 goto fail2; 1894 } 1895 1896 p = sizeof(hdr); 1897 if ((error = firmware_read(fwh, p, fw->main, fw->main_size)) != 0) 1898 goto fail3; 1899 1900 p += fw->main_size; 1901 if ((error = firmware_read(fwh, p, fw->ucode, fw->ucode_size)) != 0) 1902 goto fail3; 1903 1904 DPRINTF(("Firmware cached: main %u, ucode %u\n", fw->main_size, 1905 fw->ucode_size)); 1906 1907 sc->flags |= IPW_FLAG_FW_CACHED; 1908 1909 firmware_close(fwh); 1910 1911 return 0; 1912 1913 fail3: firmware_free(fw->ucode, 0); 1914 fail2: firmware_free(fw->main, 0); 1915 fail1: firmware_close(fwh); 1916 fail0: 1917 return error; 1918 } 1919 1920 static void 1921 ipw_free_firmware(struct ipw_softc *sc) 1922 { 1923 if (!(sc->flags & IPW_FLAG_FW_CACHED)) 1924 return; 1925 1926 firmware_free(sc->fw.main, 0); 1927 firmware_free(sc->fw.ucode, 0); 1928 1929 sc->flags &= ~IPW_FLAG_FW_CACHED; 1930 } 1931 1932 static int 1933 ipw_config(struct ipw_softc *sc) 1934 { 1935 struct ieee80211com *ic = &sc->sc_ic; 1936 struct ifnet *ifp = &sc->sc_if; 1937 struct ipw_security security; 1938 struct ieee80211_key *k; 1939 struct ipw_wep_key wepkey; 1940 struct ipw_scan_options options; 1941 struct ipw_configuration config; 1942 uint32_t data; 1943 int error, i; 1944 1945 switch (ic->ic_opmode) { 1946 case IEEE80211_M_STA: 1947 case IEEE80211_M_HOSTAP: 1948 data = htole32(IPW_MODE_BSS); 1949 break; 1950 1951 case IEEE80211_M_IBSS: 1952 case IEEE80211_M_AHDEMO: 1953 data = htole32(IPW_MODE_IBSS); 1954 break; 1955 1956 case IEEE80211_M_MONITOR: 1957 data = htole32(IPW_MODE_MONITOR); 1958 break; 1959 } 1960 DPRINTF(("Setting mode to %u\n", le32toh(data))); 1961 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 1962 if (error != 0) 1963 return error; 1964 1965 if (ic->ic_opmode == IEEE80211_M_IBSS || 1966 ic->ic_opmode == IEEE80211_M_MONITOR) { 1967 data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); 1968 DPRINTF(("Setting channel to %u\n", le32toh(data))); 1969 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 1970 if (error != 0) 1971 return error; 1972 } 1973 1974 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1975 DPRINTF(("Enabling adapter\n")); 1976 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1977 } 1978 1979 DPRINTF(("Setting MAC to %s\n", ether_sprintf(ic->ic_myaddr))); 1980 if_set_sadl(ifp, ic->ic_myaddr, IEEE80211_ADDR_LEN); 1981 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 1982 IEEE80211_ADDR_LEN); 1983 if (error != 0) 1984 return error; 1985 1986 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 1987 IPW_CFG_PREAMBLE_AUTO | IPW_CFG_802_1x_ENABLE); 1988 1989 if (ic->ic_opmode == IEEE80211_M_IBSS) 1990 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 1991 if (ifp->if_flags & IFF_PROMISC) 1992 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 1993 config.bss_chan = htole32(0x3fff); /* channels 1-14 */ 1994 config.ibss_chan = htole32(0x7ff); /* channels 1-11 */ 1995 DPRINTF(("Setting adapter configuration 0x%08x\n", config.flags)); 1996 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 1997 if (error != 0) 1998 return error; 1999 2000 data = htole32(0x3); /* 1, 2 */ 2001 DPRINTF(("Setting basic tx rates to 0x%x\n", le32toh(data))); 2002 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 2003 if (error != 0) 2004 return error; 2005 2006 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 2007 DPRINTF(("Setting tx rates to 0x%x\n", le32toh(data))); 2008 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 2009 if (error != 0) 2010 return error; 2011 2012 data = htole32(IPW_POWER_MODE_CAM); 2013 DPRINTF(("Setting power mode to %u\n", le32toh(data))); 2014 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 2015 if (error != 0) 2016 return error; 2017 2018 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2019 data = htole32(32); /* default value */ 2020 DPRINTF(("Setting tx power index to %u\n", le32toh(data))); 2021 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 2022 sizeof data); 2023 if (error != 0) 2024 return error; 2025 } 2026 2027 data = htole32(ic->ic_rtsthreshold); 2028 DPRINTF(("Setting RTS threshold to %u\n", le32toh(data))); 2029 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 2030 if (error != 0) 2031 return error; 2032 2033 data = htole32(ic->ic_fragthreshold); 2034 DPRINTF(("Setting frag threshold to %u\n", le32toh(data))); 2035 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 2036 if (error != 0) 2037 return error; 2038 2039 #ifdef IPW_DEBUG 2040 if (ipw_debug > 0) { 2041 printf("Setting ESSID to "); 2042 ieee80211_print_essid(ic->ic_des_essid, ic->ic_des_esslen); 2043 printf("\n"); 2044 } 2045 #endif 2046 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ic->ic_des_essid, 2047 ic->ic_des_esslen); 2048 if (error != 0) 2049 return error; 2050 2051 /* no mandatory BSSID */ 2052 DPRINTF(("Setting mandatory BSSID to null\n")); 2053 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 2054 if (error != 0) 2055 return error; 2056 2057 if (ic->ic_flags & IEEE80211_F_DESBSSID) { 2058 DPRINTF(("Setting desired BSSID to %s\n", 2059 ether_sprintf(ic->ic_des_bssid))); 2060 error = ipw_cmd(sc, IPW_CMD_SET_DESIRED_BSSID, 2061 ic->ic_des_bssid, IEEE80211_ADDR_LEN); 2062 if (error != 0) 2063 return error; 2064 } 2065 2066 (void)memset(&security, 0, sizeof(security)); 2067 security.authmode = (ic->ic_bss->ni_authmode == IEEE80211_AUTH_SHARED) ? 2068 IPW_AUTH_SHARED : IPW_AUTH_OPEN; 2069 security.ciphers = htole32(IPW_CIPHER_NONE); 2070 DPRINTF(("Setting authmode to %u\n", security.authmode)); 2071 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 2072 sizeof security); 2073 if (error != 0) 2074 return error; 2075 2076 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 2077 k = ic->ic_crypto.cs_nw_keys; 2078 for (i = 0; i < IEEE80211_WEP_NKID; i++, k++) { 2079 if (k->wk_keylen == 0) 2080 continue; 2081 2082 wepkey.idx = i; 2083 wepkey.len = k->wk_keylen; 2084 memset(wepkey.key, 0, sizeof(wepkey.key)); 2085 memcpy(wepkey.key, k->wk_key, k->wk_keylen); 2086 DPRINTF(("Setting wep key index %u len %u\n", 2087 wepkey.idx, wepkey.len)); 2088 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY, &wepkey, 2089 sizeof wepkey); 2090 if (error != 0) 2091 return error; 2092 } 2093 2094 data = htole32(ic->ic_crypto.cs_def_txkey); 2095 DPRINTF(("Setting tx key index to %u\n", le32toh(data))); 2096 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY_INDEX, &data, 2097 sizeof data); 2098 if (error != 0) 2099 return error; 2100 } 2101 2102 data = htole32((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) ? IPW_WEPON : 0); 2103 DPRINTF(("Setting wep flags to 0x%x\n", le32toh(data))); 2104 error = ipw_cmd(sc, IPW_CMD_SET_WEP_FLAGS, &data, sizeof data); 2105 if (error != 0) 2106 return error; 2107 2108 #if 0 2109 struct ipw_wpa_ie ie; 2110 2111 memset(&ie, 0 sizeof(ie)); 2112 ie.len = htole32(sizeof (struct ieee80211_ie_wpa)); 2113 DPRINTF(("Setting wpa ie\n")); 2114 error = ipw_cmd(sc, IPW_CMD_SET_WPA_IE, &ie, sizeof ie); 2115 if (error != 0) 2116 return error; 2117 #endif 2118 2119 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2120 data = htole32(ic->ic_bintval); 2121 DPRINTF(("Setting beacon interval to %u\n", le32toh(data))); 2122 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 2123 sizeof data); 2124 if (error != 0) 2125 return error; 2126 } 2127 2128 options.flags = 0; 2129 options.channels = htole32(0x3fff); /* scan channels 1-14 */ 2130 DPRINTF(("Setting scan options to 0x%x\n", le32toh(options.flags))); 2131 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &options, sizeof options); 2132 if (error != 0) 2133 return error; 2134 2135 /* finally, enable adapter (start scanning for an access point) */ 2136 DPRINTF(("Enabling adapter\n")); 2137 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 2138 } 2139 2140 static int 2141 ipw_init(struct ifnet *ifp) 2142 { 2143 struct ipw_softc *sc = ifp->if_softc; 2144 struct ipw_firmware *fw = &sc->fw; 2145 2146 if (!(sc->flags & IPW_FLAG_FW_CACHED)) { 2147 if (ipw_cache_firmware(sc) != 0) { 2148 aprint_error_dev(&sc->sc_dev, "could not cache the firmware (%s)\n", 2149 sc->sc_fwname); 2150 goto fail; 2151 } 2152 } 2153 2154 ipw_stop(ifp, 0); 2155 2156 if (ipw_reset(sc) != 0) { 2157 aprint_error_dev(&sc->sc_dev, "could not reset adapter\n"); 2158 goto fail; 2159 } 2160 2161 if (ipw_load_ucode(sc, fw->ucode, fw->ucode_size) != 0) { 2162 aprint_error_dev(&sc->sc_dev, "could not load microcode\n"); 2163 goto fail; 2164 } 2165 2166 ipw_stop_master(sc); 2167 2168 /* 2169 * Setup tx, rx and status rings. 2170 */ 2171 sc->txold = IPW_NTBD - 1; 2172 sc->txcur = 0; 2173 sc->txfree = IPW_NTBD - 2; 2174 sc->rxcur = IPW_NRBD - 1; 2175 2176 CSR_WRITE_4(sc, IPW_CSR_TX_BASE, sc->tbd_map->dm_segs[0].ds_addr); 2177 CSR_WRITE_4(sc, IPW_CSR_TX_SIZE, IPW_NTBD); 2178 CSR_WRITE_4(sc, IPW_CSR_TX_READ, 0); 2179 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 2180 2181 CSR_WRITE_4(sc, IPW_CSR_RX_BASE, sc->rbd_map->dm_segs[0].ds_addr); 2182 CSR_WRITE_4(sc, IPW_CSR_RX_SIZE, IPW_NRBD); 2183 CSR_WRITE_4(sc, IPW_CSR_RX_READ, 0); 2184 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 2185 2186 CSR_WRITE_4(sc, IPW_CSR_STATUS_BASE, sc->status_map->dm_segs[0].ds_addr); 2187 2188 if (ipw_load_firmware(sc, fw->main, fw->main_size) != 0) { 2189 aprint_error_dev(&sc->sc_dev, "could not load firmware\n"); 2190 goto fail; 2191 } 2192 2193 sc->flags |= IPW_FLAG_FW_INITED; 2194 2195 /* retrieve information tables base addresses */ 2196 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 2197 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 2198 2199 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 2200 2201 if (ipw_config(sc) != 0) { 2202 aprint_error_dev(&sc->sc_dev, "device configuration failed\n"); 2203 goto fail; 2204 } 2205 2206 ifp->if_flags &= ~IFF_OACTIVE; 2207 ifp->if_flags |= IFF_RUNNING; 2208 2209 return 0; 2210 2211 fail: ifp->if_flags &= ~IFF_UP; 2212 ipw_stop(ifp, 0); 2213 2214 return EIO; 2215 } 2216 2217 static void 2218 ipw_stop(struct ifnet *ifp, int disable) 2219 { 2220 struct ipw_softc *sc = ifp->if_softc; 2221 struct ieee80211com *ic = &sc->sc_ic; 2222 int i; 2223 2224 ipw_stop_master(sc); 2225 2226 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 2227 2228 /* 2229 * Release tx buffers. 2230 */ 2231 for (i = 0; i < IPW_NTBD; i++) 2232 ipw_release_sbd(sc, &sc->stbd_list[i]); 2233 2234 sc->sc_tx_timer = 0; 2235 ifp->if_timer = 0; 2236 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2237 2238 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2239 } 2240 2241 static void 2242 ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2243 bus_size_t count) 2244 { 2245 for (; count > 0; offset++, datap++, count--) { 2246 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2247 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 2248 } 2249 } 2250 2251 static void 2252 ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2253 bus_size_t count) 2254 { 2255 for (; count > 0; offset++, datap++, count--) { 2256 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2257 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 2258 } 2259 } 2260
Indexes created Mon Sep 29 21:09:56 GMT 2025