if_ipw.c revision 1.4
1 /* $NetBSD: if_ipw.c,v 1.4 2004/09/14 00:31:20 lukem Exp $ */ 2 /* Id: if_ipw.c,v 1.1.2.7 2004/08/20 11:20:11 damien Exp */ 3 4 /*- 5 * Copyright (c) 2004 6 * Damien Bergamini <damien.bergamini (at) free.fr>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: if_ipw.c,v 1.4 2004/09/14 00:31:20 lukem Exp $"); 33 34 /*- 35 * Intel(R) PRO/Wireless 2100 MiniPCI driver 36 * http://www.intel.com/products/mobiletechnology/prowireless.htm 37 */ 38 39 #include "bpfilter.h" 40 41 #include <sys/param.h> 42 #include <sys/sockio.h> 43 #include <sys/sysctl.h> 44 #include <sys/mbuf.h> 45 #include <sys/kernel.h> 46 #include <sys/socket.h> 47 #include <sys/systm.h> 48 #include <sys/malloc.h> 49 #include <sys/conf.h> 50 51 #include <machine/bus.h> 52 #include <machine/endian.h> 53 #include <machine/intr.h> 54 55 #include <dev/pci/pcireg.h> 56 #include <dev/pci/pcivar.h> 57 #include <dev/pci/pcidevs.h> 58 59 #if NBPFILTER > 0 60 #include <net/bpf.h> 61 #endif 62 #include <net/if.h> 63 #include <net/if_arp.h> 64 #include <net/if_dl.h> 65 #include <net/if_ether.h> 66 #include <net/if_media.h> 67 #include <net/if_types.h> 68 69 #include <net80211/ieee80211_var.h> 70 #include <net80211/ieee80211_radiotap.h> 71 72 #include <netinet/in.h> 73 #include <netinet/in_systm.h> 74 #include <netinet/in_var.h> 75 #include <netinet/ip.h> 76 77 #include <dev/pci/if_ipwreg.h> 78 #include <dev/pci/if_ipwvar.h> 79 80 static int ipw_match(struct device *, struct cfdata *, void *); 81 static void ipw_attach(struct device *, struct device *, void *); 82 static int ipw_detach(struct device *, int); 83 static int ipw_media_change(struct ifnet *); 84 static int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 85 static void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 86 static void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 87 static void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 88 struct ipw_soft_bd *, struct ipw_soft_buf *); 89 static void ipw_notification_intr(struct ipw_softc *, struct ipw_soft_buf *); 90 static void ipw_rx_intr(struct ipw_softc *); 91 static void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 92 static void ipw_tx_intr(struct ipw_softc *); 93 static int ipw_intr(void *); 94 static int ipw_cmd(struct ipw_softc *, u_int32_t, void *, u_int32_t); 95 static int ipw_tx_start(struct ifnet *, struct mbuf *, struct ieee80211_node *); 96 static void ipw_start(struct ifnet *); 97 static void ipw_watchdog(struct ifnet *); 98 static int ipw_get_table1(struct ipw_softc *, u_int32_t *); 99 static int ipw_get_radio(struct ipw_softc *, int *); 100 static int ipw_ioctl(struct ifnet *, u_long, caddr_t); 101 static u_int32_t ipw_read_table1(struct ipw_softc *, u_int32_t); 102 static void ipw_write_table1(struct ipw_softc *, u_int32_t, u_int32_t); 103 static int ipw_read_table2(struct ipw_softc *, u_int32_t, void *, u_int32_t *); 104 static int ipw_tx_init(struct ipw_softc *); 105 static void ipw_tx_stop(struct ipw_softc *); 106 static int ipw_rx_init(struct ipw_softc *); 107 static void ipw_rx_stop(struct ipw_softc *); 108 static void ipw_reset(struct ipw_softc *); 109 static int ipw_clock_sync(struct ipw_softc *); 110 static int ipw_load_ucode(struct ipw_softc *, u_char *, int); 111 static int ipw_load_firmware(struct ipw_softc *, u_char *, int); 112 static int ipw_firmware_init(struct ipw_softc *, u_char *); 113 static int ipw_config(struct ipw_softc *); 114 static int ipw_init(struct ifnet *); 115 static void ipw_stop(struct ifnet *, int); 116 static void ipw_read_mem_1(struct ipw_softc *, bus_size_t, u_int8_t *, 117 bus_size_t); 118 static void ipw_write_mem_1(struct ipw_softc *, bus_size_t, u_int8_t *, 119 bus_size_t); 120 static void ipw_zero_mem_4(struct ipw_softc *, bus_size_t, bus_size_t); 121 122 static inline u_int8_t MEM_READ_1(struct ipw_softc *sc, u_int32_t addr) 123 { 124 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 125 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); 126 } 127 128 static inline u_int16_t MEM_READ_2(struct ipw_softc *sc, u_int32_t addr) 129 { 130 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 131 return CSR_READ_2(sc, IPW_CSR_INDIRECT_DATA); 132 } 133 134 static inline u_int32_t MEM_READ_4(struct ipw_softc *sc, u_int32_t addr) 135 { 136 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 137 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); 138 } 139 140 #ifdef IPW_DEBUG 141 #define DPRINTF(x) if (ipw_debug > 0) printf x 142 #define DPRINTFN(n, x) if (ipw_debug >= (n)) printf x 143 int ipw_debug = 0; 144 #else 145 #define DPRINTF(x) 146 #define DPRINTFN(n, x) 147 #endif 148 149 CFATTACH_DECL(ipw, sizeof (struct ipw_softc), ipw_match, ipw_attach, 150 ipw_detach, NULL); 151 152 static int 153 ipw_match(struct device *parent, struct cfdata *match, void *aux) 154 { 155 struct pci_attach_args *pa = aux; 156 157 if (PCI_VENDOR (pa->pa_id) == PCI_VENDOR_INTEL && 158 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_PRO_WL_2100) 159 return 1; 160 161 return 0; 162 } 163 164 /* Base Address Register */ 165 #define IPW_PCI_BAR0 0x10 166 167 static void 168 ipw_attach(struct device *parent, struct device *self, void *aux) 169 { 170 struct ipw_softc *sc = (struct ipw_softc *)self; 171 struct ieee80211com *ic = &sc->sc_ic; 172 struct ifnet *ifp = &ic->ic_if; 173 struct ieee80211_rateset *rs; 174 struct pci_attach_args *pa = aux; 175 const char *intrstr; 176 char devinfo[256]; 177 bus_space_tag_t memt; 178 bus_space_handle_t memh; 179 bus_addr_t base; 180 pci_intr_handle_t ih; 181 u_int32_t data; 182 int i, revision, error; 183 184 sc->sc_pct = pa->pa_pc; 185 186 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof devinfo); 187 revision = PCI_REVISION(pa->pa_class); 188 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, revision); 189 190 /* enable bus-mastering */ 191 data = pci_conf_read(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG); 192 data |= PCI_COMMAND_MASTER_ENABLE; 193 pci_conf_write(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG, data); 194 195 /* map the register window */ 196 error = pci_mapreg_map(pa, IPW_PCI_BAR0, PCI_MAPREG_TYPE_MEM | 197 PCI_MAPREG_MEM_TYPE_32BIT, 0, &memt, &memh, &base, &sc->sc_sz); 198 if (error != 0) { 199 aprint_error("%s: could not map memory space\n", 200 sc->sc_dev.dv_xname); 201 return; 202 } 203 204 sc->sc_st = memt; 205 sc->sc_sh = memh; 206 sc->sc_dmat = pa->pa_dmat; 207 208 /* disable interrupts */ 209 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 210 211 if (pci_intr_map(pa, &ih) != 0) { 212 aprint_error("%s: could not map interrupt\n", 213 sc->sc_dev.dv_xname); 214 return; 215 } 216 217 intrstr = pci_intr_string(sc->sc_pct, ih); 218 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, ipw_intr, sc); 219 if (sc->sc_ih == NULL) { 220 aprint_error("%s: could not establish interrupt", 221 sc->sc_dev.dv_xname); 222 if (intrstr != NULL) 223 aprint_error(" at %s", intrstr); 224 aprint_error("\n"); 225 return; 226 } 227 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 228 229 ic->ic_phytype = IEEE80211_T_DS; 230 ic->ic_opmode = IEEE80211_M_STA; 231 ic->ic_state = IEEE80211_S_INIT; 232 233 /* set device capabilities */ 234 ic->ic_caps = IEEE80211_C_IBSS | IEEE80211_C_MONITOR | 235 IEEE80211_C_PMGT | IEEE80211_C_TXPMGT | IEEE80211_C_WEP; 236 237 /* set supported 11.b rates */ 238 rs = &ic->ic_sup_rates[IEEE80211_MODE_11B]; 239 rs->rs_nrates = 4; 240 rs->rs_rates[0] = 2; /* 1Mbps */ 241 rs->rs_rates[1] = 4; /* 2Mbps */ 242 rs->rs_rates[2] = 11; /* 5.5Mbps */ 243 rs->rs_rates[3] = 22; /* 11Mbps */ 244 245 /* set supported 11.b channels (1 through 14) */ 246 for (i = 1; i <= 14; i++) { 247 ic->ic_channels[i].ic_freq = 248 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 249 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 250 } 251 252 ic->ic_ibss_chan = &ic->ic_channels[0]; 253 254 ifp->if_softc = sc; 255 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 256 ifp->if_init = ipw_init; 257 ifp->if_stop = ipw_stop; 258 ifp->if_ioctl = ipw_ioctl; 259 ifp->if_start = ipw_start; 260 ifp->if_watchdog = ipw_watchdog; 261 IFQ_SET_READY(&ifp->if_snd); 262 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 263 264 if_attach(ifp); 265 ieee80211_ifattach(ifp); 266 /* override state transition machine */ 267 sc->sc_newstate = ic->ic_newstate; 268 ic->ic_newstate = ipw_newstate; 269 270 ieee80211_media_init(ifp, ipw_media_change, ieee80211_media_status); 271 272 #if NBPFILTER > 0 273 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 274 sizeof (struct ieee80211_frame) + 64, &sc->sc_drvbpf); 275 276 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 277 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 278 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 279 280 sc->sc_txtap_len = sizeof sc->sc_txtapu; 281 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 282 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 283 #endif 284 } 285 286 static int 287 ipw_detach(struct device* self, int flags) 288 { 289 struct ipw_softc *sc = (struct ipw_softc *)self; 290 struct ifnet *ifp = &sc->sc_ic.ic_if; 291 292 ipw_reset(sc); 293 294 #if NBPFILTER > 0 295 bpfdetach(ifp); 296 #endif 297 ieee80211_ifdetach(ifp); 298 if_detach(ifp); 299 300 if (sc->sc_ih != NULL) { 301 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 302 sc->sc_ih = NULL; 303 } 304 305 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 306 307 return 0; 308 } 309 310 static int 311 ipw_media_change(struct ifnet *ifp) 312 { 313 int error; 314 315 error = ieee80211_media_change(ifp); 316 if (error != ENETRESET) 317 return error; 318 319 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 320 ipw_init(ifp); 321 322 return 0; 323 } 324 325 static int 326 ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 327 { 328 struct ifnet *ifp = &ic->ic_if; 329 struct ipw_softc *sc = ifp->if_softc; 330 struct ieee80211_node *ni = ic->ic_bss; 331 u_int32_t val, len; 332 333 switch (nstate) { 334 case IEEE80211_S_INIT: 335 break; 336 337 case IEEE80211_S_RUN: 338 len = IEEE80211_NWID_LEN; 339 ipw_read_table2(sc, IPW_INFO_CURRENT_SSID, ni->ni_essid, &len); 340 ni->ni_esslen = len; 341 342 val = ipw_read_table1(sc, IPW_INFO_CURRENT_CHANNEL); 343 ni->ni_chan = &ic->ic_channels[val]; 344 345 DELAY(100); /* firmware needs a short delay here */ 346 347 len = IEEE80211_ADDR_LEN; 348 ipw_read_table2(sc, IPW_INFO_CURRENT_BSSID, ni->ni_bssid, &len); 349 break; 350 351 case IEEE80211_S_SCAN: 352 case IEEE80211_S_AUTH: 353 case IEEE80211_S_ASSOC: 354 break; 355 } 356 357 ic->ic_state = nstate; 358 return 0; 359 } 360 361 static void 362 ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 363 { 364 struct ipw_cmd *cmd; 365 366 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof (struct ipw_cmd), 367 BUS_DMASYNC_POSTREAD); 368 369 cmd = mtod(sbuf->m, struct ipw_cmd *); 370 371 DPRINTFN(2, ("RX!CMD!%u!%u!%u!%u!%u\n", 372 le32toh(cmd->type), le32toh(cmd->subtype), le32toh(cmd->seq), 373 le32toh(cmd->len), le32toh(cmd->status))); 374 375 /* 376 * Wake up processes waiting for command ack. In the case of the 377 * IPW_CMD_DISABLE command, wake up the process only when the adapter 378 * enters the IPW_STATE_DISABLED state. This is notified in 379 * ipw_newstate_intr(). 380 */ 381 if (le32toh(cmd->type) != IPW_CMD_DISABLE) 382 wakeup(sc->cmd); 383 } 384 385 static void 386 ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 387 { 388 struct ieee80211com *ic = &sc->sc_ic; 389 u_int32_t state; 390 391 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof state, 392 BUS_DMASYNC_POSTREAD); 393 394 state = le32toh(*mtod(sbuf->m, u_int32_t *)); 395 396 DPRINTFN(2, ("RX!NEWSTATE!%u\n", state)); 397 398 switch (state) { 399 case IPW_STATE_ASSOCIATED: 400 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 401 break; 402 403 case IPW_STATE_SCANNING: 404 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 405 break; 406 407 case IPW_STATE_ASSOCIATION_LOST: 408 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 409 break; 410 411 case IPW_STATE_DISABLED: 412 wakeup(sc->cmd); 413 break; 414 415 case IPW_STATE_RADIO_DISABLED: 416 /* XXX should turn the interface down */ 417 break; 418 } 419 } 420 421 static void 422 ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 423 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 424 { 425 struct ieee80211com *ic = &sc->sc_ic; 426 struct ifnet *ifp = &ic->ic_if; 427 struct mbuf *m; 428 struct ieee80211_frame *wh; 429 struct ieee80211_node *ni; 430 int error; 431 432 DPRINTFN(5, ("RX!DATA!%u!%u\n", le32toh(status->len), status->rssi)); 433 434 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, le32toh(status->len), 435 BUS_DMASYNC_POSTREAD); 436 437 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 438 439 /* Finalize mbuf */ 440 m = sbuf->m; 441 m->m_pkthdr.rcvif = ifp; 442 m->m_pkthdr.len = m->m_len = le32toh(status->len); 443 444 #if NBPFILTER > 0 445 if (sc->sc_drvbpf != NULL) { 446 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 447 448 tap->wr_flags = 0; 449 tap->wr_antsignal = status->rssi; 450 tap->wr_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 451 tap->wr_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 452 453 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 454 } 455 #endif 456 457 wh = mtod(m, struct ieee80211_frame *); 458 459 if (ic->ic_opmode != IEEE80211_M_STA) { 460 ni = ieee80211_find_node(ic, wh->i_addr2); 461 if (ni == NULL) 462 ni = ieee80211_ref_node(ic->ic_bss); 463 } else 464 ni = ieee80211_ref_node(ic->ic_bss); 465 466 /* Send it up to the upper layer */ 467 ieee80211_input(ifp, m, ni, status->rssi, 0/*rstamp*/); 468 469 ieee80211_release_node(ic, ni); 470 471 MGETHDR(m, M_DONTWAIT, MT_DATA); 472 if (m == NULL) { 473 aprint_error("%s: could not allocate rx mbuf\n", 474 sc->sc_dev.dv_xname); 475 return; 476 } 477 MCLGET(m, M_DONTWAIT); 478 if (!(m->m_flags & M_EXT)) { 479 m_freem(m); 480 aprint_error("%s: could not allocate rx mbuf cluster\n", 481 sc->sc_dev.dv_xname); 482 return; 483 } 484 485 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, mtod(m, void *), 486 MCLBYTES, NULL, BUS_DMA_NOWAIT); 487 if (error != 0) { 488 aprint_error("%s: could not map rxbuf dma memory\n", 489 sc->sc_dev.dv_xname); 490 m_freem(m); 491 return; 492 } 493 494 sbuf->m = m; 495 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 496 } 497 498 static void 499 ipw_notification_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 500 { 501 DPRINTFN(2, ("RX!NOTIFICATION\n")); 502 } 503 504 static void 505 ipw_rx_intr(struct ipw_softc *sc) 506 { 507 struct ipw_status *status; 508 struct ipw_soft_bd *sbd; 509 struct ipw_soft_buf *sbuf; 510 u_int32_t r, i; 511 512 r = CSR_READ_4(sc, IPW_CSR_RX_READ_INDEX); 513 514 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 515 516 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 517 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 518 BUS_DMASYNC_POSTREAD); 519 520 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 521 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 522 BUS_DMASYNC_POSTREAD); 523 524 status = &sc->status_list[i]; 525 sbd = &sc->srbd_list[i]; 526 sbuf = sbd->priv; 527 528 switch (le16toh(status->code) & 0xf) { 529 case IPW_STATUS_CODE_COMMAND: 530 ipw_command_intr(sc, sbuf); 531 break; 532 533 case IPW_STATUS_CODE_NEWSTATE: 534 ipw_newstate_intr(sc, sbuf); 535 break; 536 537 case IPW_STATUS_CODE_DATA_802_3: 538 case IPW_STATUS_CODE_DATA_802_11: 539 ipw_data_intr(sc, status, sbd, sbuf); 540 break; 541 542 case IPW_STATUS_CODE_NOTIFICATION: 543 ipw_notification_intr(sc, sbuf); 544 break; 545 546 default: 547 aprint_debug("%s: unknown status code %u\n", 548 sc->sc_dev.dv_xname, le16toh(status->code)); 549 } 550 sbd->bd->flags = 0; 551 552 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 553 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 554 BUS_DMASYNC_PREWRITE); 555 } 556 557 /* Tell the firmware what we have processed */ 558 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 559 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE_INDEX, sc->rxcur); 560 } 561 562 static void 563 ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 564 { 565 struct ieee80211com *ic; 566 struct ipw_soft_hdr *shdr; 567 struct ipw_soft_buf *sbuf; 568 569 switch (sbd->type) { 570 case IPW_SBD_TYPE_COMMAND: 571 bus_dmamap_unload(sc->sc_dmat, sc->cmd_map); 572 break; 573 574 case IPW_SBD_TYPE_HEADER: 575 shdr = sbd->priv; 576 bus_dmamap_unload(sc->sc_dmat, shdr->map); 577 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 578 break; 579 580 case IPW_SBD_TYPE_DATA: 581 ic = &sc->sc_ic; 582 sbuf = sbd->priv; 583 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 584 m_freem(sbuf->m); 585 if (sbuf->ni != NULL) 586 ieee80211_release_node(ic, sbuf->ni); 587 /* kill watchdog timer */ 588 sc->sc_tx_timer = 0; 589 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 590 break; 591 } 592 sbd->type = IPW_SBD_TYPE_NOASSOC; 593 } 594 595 static void 596 ipw_tx_intr(struct ipw_softc *sc) 597 { 598 struct ifnet *ifp = &sc->sc_ic.ic_if; 599 u_int32_t r, i; 600 601 r = CSR_READ_4(sc, IPW_CSR_TX_READ_INDEX); 602 603 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) 604 ipw_release_sbd(sc, &sc->stbd_list[i]); 605 606 /* Remember what the firmware has processed */ 607 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 608 609 /* Call start() since some buffer descriptors have been released */ 610 ifp->if_flags &= ~IFF_OACTIVE; 611 (*ifp->if_start)(ifp); 612 } 613 614 static int 615 ipw_intr(void *arg) 616 { 617 struct ipw_softc *sc = arg; 618 u_int32_t r; 619 620 if ((r = CSR_READ_4(sc, IPW_CSR_INTR)) == 0) 621 return 0; 622 623 /* Disable interrupts */ 624 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 625 626 DPRINTFN(8, ("INTR!0x%08x\n", r)); 627 628 if (r & IPW_INTR_RX_TRANSFER) 629 ipw_rx_intr(sc); 630 631 if (r & IPW_INTR_TX_TRANSFER) 632 ipw_tx_intr(sc); 633 634 if (r & IPW_INTR_FW_INIT_DONE) { 635 if (!(r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR))) 636 wakeup(sc); 637 } 638 639 /* Acknowledge interrupts */ 640 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 641 642 /* Re-enable interrupts */ 643 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 644 645 return 0; 646 } 647 648 static int 649 ipw_cmd(struct ipw_softc *sc, u_int32_t type, void *data, u_int32_t len) 650 { 651 struct ipw_soft_bd *sbd; 652 int error; 653 654 sbd = &sc->stbd_list[sc->txcur]; 655 656 error = bus_dmamap_load(sc->sc_dmat, sc->cmd_map, sc->cmd, 657 sizeof (struct ipw_cmd), NULL, BUS_DMA_NOWAIT); 658 if (error != 0) { 659 aprint_error("%s: could not map cmd dma memory\n", 660 sc->sc_dev.dv_xname); 661 return error; 662 } 663 664 sc->cmd->type = htole32(type); 665 sc->cmd->subtype = htole32(0); 666 sc->cmd->len = htole32(len); 667 sc->cmd->seq = htole32(0); 668 if (data != NULL) 669 bcopy(data, sc->cmd->data, len); 670 671 sbd->type = IPW_SBD_TYPE_COMMAND; 672 sbd->bd->physaddr = htole32(sc->cmd_map->dm_segs[0].ds_addr); 673 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 674 sbd->bd->nfrag = 1; 675 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 676 IPW_BD_FLAG_TX_LAST_FRAGMENT; 677 678 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 0, sizeof (struct ipw_cmd), 679 BUS_DMASYNC_PREWRITE); 680 681 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 682 sc->txcur * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 683 BUS_DMASYNC_PREWRITE); 684 685 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 686 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, sc->txcur); 687 688 DPRINTFN(2, ("TX!CMD!%u!%u!%u!%u\n", type, 0, 0, len)); 689 690 /* Wait at most two seconds for command to complete */ 691 return tsleep(sc->cmd, 0, "ipwcmd", 2 * hz); 692 } 693 694 static int 695 ipw_tx_start(struct ifnet *ifp, struct mbuf *m, struct ieee80211_node *ni) 696 { 697 struct ipw_softc *sc = ifp->if_softc; 698 struct ieee80211com *ic = &sc->sc_ic; 699 struct ieee80211_frame *wh; 700 struct ipw_soft_bd *sbd; 701 struct ipw_soft_hdr *shdr; 702 struct ipw_soft_buf *sbuf; 703 int error, i; 704 705 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 706 m = ieee80211_wep_crypt(ifp, m, 1); 707 if (m == NULL) 708 return ENOBUFS; 709 } 710 711 #if NBPFILTER > 0 712 if (sc->sc_drvbpf != NULL) { 713 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 714 715 tap->wt_flags = 0; 716 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 717 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 718 719 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m); 720 } 721 #endif 722 723 wh = mtod(m, struct ieee80211_frame *); 724 725 shdr = TAILQ_FIRST(&sc->sc_free_shdr); 726 sbuf = TAILQ_FIRST(&sc->sc_free_sbuf); 727 728 shdr->hdr.type = htole32(IPW_HDR_TYPE_SEND); 729 shdr->hdr.subtype = htole32(0); 730 shdr->hdr.encrypted = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0; 731 shdr->hdr.encrypt = 0; 732 shdr->hdr.keyidx = 0; 733 shdr->hdr.keysz = 0; 734 shdr->hdr.fragmentsz = htole16(0); 735 IEEE80211_ADDR_COPY(shdr->hdr.src_addr, wh->i_addr2); 736 if (ic->ic_opmode == IEEE80211_M_STA) 737 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr3); 738 else 739 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr1); 740 741 /* trim IEEE802.11 header */ 742 m_adj(m, sizeof (struct ieee80211_frame)); 743 744 /* 745 * We need to map the mbuf first to know how many buffer descriptors 746 * are needed for this transfer. 747 */ 748 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m, BUS_DMA_NOWAIT); 749 if (error != 0) { 750 aprint_error("%s: could not map mbuf (error %d)\n", 751 sc->sc_dev.dv_xname, error); 752 m_freem(m); 753 return error; 754 } 755 756 error = bus_dmamap_load(sc->sc_dmat, shdr->map, &shdr->hdr, 757 sizeof (struct ipw_hdr), NULL, BUS_DMA_NOWAIT); 758 if (error != 0) { 759 aprint_error("%s: could not map hdr (error %d)\n", 760 sc->sc_dev.dv_xname, error); 761 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 762 m_freem(m); 763 return error; 764 } 765 766 TAILQ_REMOVE(&sc->sc_free_sbuf, sbuf, next); 767 TAILQ_REMOVE(&sc->sc_free_shdr, shdr, next); 768 769 sbd = &sc->stbd_list[sc->txcur]; 770 sbd->type = IPW_SBD_TYPE_HEADER; 771 sbd->priv = shdr; 772 sbd->bd->physaddr = htole32(shdr->map->dm_segs[0].ds_addr); 773 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 774 sbd->bd->nfrag = 1 + sbuf->map->dm_nsegs; 775 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 776 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 777 778 DPRINTFN(5, ("TX!HDR!%u!%u!%u!%u\n", shdr->hdr.type, shdr->hdr.subtype, 779 shdr->hdr.encrypted, shdr->hdr.encrypt)); 780 DPRINTFN(5, ("!%s", ether_sprintf(shdr->hdr.src_addr))); 781 DPRINTFN(5, ("!%s\n", ether_sprintf(shdr->hdr.dst_addr))); 782 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 783 784 sbuf->m = m; 785 sbuf->ni = ni; 786 787 for (i = 0; i < sbuf->map->dm_nsegs; i++) { 788 sbd = &sc->stbd_list[sc->txcur]; 789 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[i].ds_addr); 790 sbd->bd->len = htole32(sbuf->map->dm_segs[i].ds_len); 791 sbd->bd->nfrag = 0; /* used only in first bd */ 792 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 793 if (i == sbuf->map->dm_nsegs - 1) { 794 sbd->type = IPW_SBD_TYPE_DATA; 795 sbd->priv = sbuf; 796 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 797 } else { 798 sbd->type = IPW_SBD_TYPE_NOASSOC; 799 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 800 } 801 802 DPRINTFN(5, ("TX!FRAG!%d!%ld\n", i, 803 sbuf->map->dm_segs[i].ds_len)); 804 805 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 806 sc->txcur * sizeof (struct ipw_bd), 807 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 808 809 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 810 } 811 812 bus_dmamap_sync(sc->sc_dmat, shdr->map, 0, sizeof (struct ipw_hdr), 813 BUS_DMASYNC_PREWRITE); 814 815 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, MCLBYTES, 816 BUS_DMASYNC_PREWRITE); 817 818 /* Inform firmware about this new packet */ 819 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, sc->txcur); 820 821 return 0; 822 } 823 824 static void 825 ipw_start(struct ifnet *ifp) 826 { 827 struct ipw_softc *sc = ifp->if_softc; 828 struct ieee80211com *ic = &sc->sc_ic; 829 struct mbuf *m; 830 struct ieee80211_node *ni; 831 832 for (;;) { 833 IF_DEQUEUE(&ifp->if_snd, m); 834 if (m == NULL) 835 break; 836 837 #if NBPFILTER > 0 838 if (ifp->if_bpf != NULL) 839 bpf_mtap(ifp->if_bpf, m); 840 #endif 841 842 m = ieee80211_encap(ifp, m, &ni); 843 if (m == NULL) 844 continue; 845 846 #if NBPFILTER > 0 847 if (ic->ic_rawbpf != NULL) 848 bpf_mtap(ic->ic_rawbpf, m); 849 #endif 850 851 if (ipw_tx_start(ifp, m, ni) != 0) { 852 if (ni != NULL) 853 ieee80211_release_node(ic, ni); 854 break; 855 } 856 857 /* start watchdog timer */ 858 sc->sc_tx_timer = 5; 859 ifp->if_timer = 1; 860 } 861 } 862 863 static void 864 ipw_watchdog(struct ifnet *ifp) 865 { 866 struct ipw_softc *sc = ifp->if_softc; 867 868 ifp->if_timer = 0; 869 870 if (sc->sc_tx_timer > 0) { 871 if (--sc->sc_tx_timer == 0) { 872 aprint_error("%s: device timeout\n", 873 sc->sc_dev.dv_xname); 874 #ifdef notyet 875 ipw_init(ifp); 876 #endif 877 return; 878 } 879 ifp->if_timer = 1; 880 } 881 882 ieee80211_watchdog(ifp); 883 } 884 885 static int 886 ipw_get_table1(struct ipw_softc *sc, u_int32_t *tbl) 887 { 888 u_int32_t addr, size, i; 889 890 if (!(sc->flags & IPW_FLAG_FW_INITED)) 891 return ENOTTY; 892 893 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, sc->table1_base); 894 895 size = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 896 if (suword(tbl, size) != 0) 897 return EFAULT; 898 899 for (i = 1, ++tbl; i < size; i++, tbl++) { 900 addr = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 901 if (suword(tbl, MEM_READ_4(sc, addr)) != 0) 902 return EFAULT; 903 } 904 return 0; 905 } 906 907 static int 908 ipw_get_radio(struct ipw_softc *sc, int *ret) 909 { 910 u_int32_t addr; 911 912 if (!(sc->flags & IPW_FLAG_FW_INITED)) 913 return ENOTTY; 914 915 addr = ipw_read_table1(sc, IPW_INFO_EEPROM_ADDRESS); 916 if ((MEM_READ_4(sc, addr + 32) >> 24) & 1) { 917 suword(ret, -1); 918 return 0; 919 } 920 921 if (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED) 922 suword(ret, 0); 923 else 924 suword(ret, 1); 925 926 return 0; 927 } 928 929 static int 930 ipw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 931 { 932 struct ipw_softc *sc = ifp->if_softc; 933 struct ifreq *ifr; 934 int s, error = 0; 935 936 s = splnet(); 937 938 switch (cmd) { 939 case SIOCSIFFLAGS: 940 if (ifp->if_flags & IFF_UP) { 941 if (!(ifp->if_flags & IFF_RUNNING)) 942 ipw_init(ifp); 943 } else { 944 if (ifp->if_flags & IFF_RUNNING) 945 ipw_stop(ifp, 1); 946 } 947 break; 948 949 case SIOCGTABLE1: 950 ifr = (struct ifreq *)data; 951 error = ipw_get_table1(sc, (u_int32_t *)ifr->ifr_data); 952 break; 953 954 case SIOCGRADIO: 955 ifr = (struct ifreq *)data; 956 error = ipw_get_radio(sc, (int *)ifr->ifr_data); 957 break; 958 959 case SIOCSLOADFW: 960 /* only super-user can do that! */ 961 if ((error = suser(curproc->p_ucred, &curproc->p_acflag)) != 0) 962 break; 963 964 ifr = (struct ifreq *)data; 965 error = ipw_firmware_init(sc, (u_char *)ifr->ifr_data); 966 break; 967 968 case SIOCSKILLFW: 969 /* only super-user can do that! */ 970 if ((error = suser(curproc->p_ucred, &curproc->p_acflag)) != 0) 971 break; 972 973 ipw_reset(sc); 974 break; 975 976 default: 977 error = ieee80211_ioctl(ifp, cmd, data); 978 if (error != ENETRESET) 979 break; 980 981 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 982 (IFF_UP | IFF_RUNNING)) 983 ipw_init(ifp); 984 error = 0; 985 } 986 987 splx(s); 988 return error; 989 } 990 991 static u_int32_t 992 ipw_read_table1(struct ipw_softc *sc, u_int32_t off) 993 { 994 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 995 } 996 997 static void 998 ipw_write_table1(struct ipw_softc *sc, u_int32_t off, u_int32_t info) 999 { 1000 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 1001 } 1002 1003 static int 1004 ipw_read_table2(struct ipw_softc *sc, u_int32_t off, void *buf, u_int32_t *len) 1005 { 1006 u_int32_t addr, info; 1007 u_int16_t count, size; 1008 u_int32_t total; 1009 1010 /* addr[4] + count[2] + size[2] */ 1011 addr = MEM_READ_4(sc, sc->table2_base + off); 1012 info = MEM_READ_4(sc, sc->table2_base + off + 4); 1013 1014 count = info >> 16; 1015 size = info & 0xffff; 1016 total = count * size; 1017 1018 if (total > *len) { 1019 *len = total; 1020 return EINVAL; 1021 } 1022 1023 *len = total; 1024 ipw_read_mem_1(sc, addr, buf, total); 1025 1026 return 0; 1027 } 1028 1029 static int 1030 ipw_tx_init(struct ipw_softc *sc) 1031 { 1032 char *errmsg; 1033 struct ipw_bd *bd; 1034 struct ipw_soft_bd *sbd; 1035 struct ipw_soft_hdr *shdr; 1036 struct ipw_soft_buf *sbuf; 1037 int error, i, nsegs; 1038 1039 /* Allocate transmission buffer descriptors */ 1040 error = bus_dmamap_create(sc->sc_dmat, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, 1041 BUS_DMA_NOWAIT, &sc->tbd_map); 1042 if (error != 0) { 1043 errmsg = "could not create tbd dma map"; 1044 goto fail; 1045 } 1046 1047 error = bus_dmamem_alloc(sc->sc_dmat, IPW_TBD_SZ, PAGE_SIZE, 0, 1048 &sc->tbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 1049 if (error != 0) { 1050 errmsg = "could not allocate tbd dma memory"; 1051 goto fail; 1052 } 1053 1054 error = bus_dmamem_map(sc->sc_dmat, &sc->tbd_seg, nsegs, IPW_TBD_SZ, 1055 (caddr_t *)&sc->tbd_list, BUS_DMA_NOWAIT); 1056 if (error != 0) { 1057 errmsg = "could not map tbd dma memory"; 1058 goto fail; 1059 } 1060 1061 error = bus_dmamap_load(sc->sc_dmat, sc->tbd_map, sc->tbd_list, 1062 IPW_TBD_SZ, NULL, BUS_DMA_NOWAIT); 1063 if (error != 0) { 1064 errmsg = "could not load tbd dma memory"; 1065 goto fail; 1066 } 1067 1068 sc->stbd_list = malloc(IPW_NTBD * sizeof (struct ipw_soft_bd), 1069 M_DEVBUF, M_NOWAIT); 1070 if (sc->stbd_list == NULL) { 1071 errmsg = "could not allocate soft tbd"; 1072 error = ENOMEM; 1073 goto fail; 1074 } 1075 sbd = sc->stbd_list; 1076 bd = sc->tbd_list; 1077 for (i = 0; i < IPW_NTBD; i++, sbd++, bd++) { 1078 sbd->type = IPW_SBD_TYPE_NOASSOC; 1079 sbd->bd = bd; 1080 } 1081 1082 CSR_WRITE_4(sc, IPW_CSR_TX_BD_BASE, sc->tbd_map->dm_segs[0].ds_addr); 1083 CSR_WRITE_4(sc, IPW_CSR_TX_BD_SIZE, IPW_NTBD); 1084 CSR_WRITE_4(sc, IPW_CSR_TX_READ_INDEX, 0); 1085 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, 0); 1086 sc->txold = IPW_NTBD - 1; /* latest bd index ack'ed by firmware */ 1087 sc->txcur = 0; /* bd index to write to */ 1088 1089 /* Allocate a DMA-able command */ 1090 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_cmd), 1, 1091 sizeof (struct ipw_cmd), 0, BUS_DMA_NOWAIT, &sc->cmd_map); 1092 if (error != 0) { 1093 errmsg = "could not create cmd dma map"; 1094 goto fail; 1095 } 1096 1097 error = bus_dmamem_alloc(sc->sc_dmat, sizeof (struct ipw_cmd), 1098 PAGE_SIZE, 0, &sc->cmd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 1099 if (error != 0) { 1100 errmsg = "could not allocate cmd dma memory"; 1101 goto fail; 1102 } 1103 1104 error = bus_dmamem_map(sc->sc_dmat, &sc->cmd_seg, nsegs, 1105 sizeof (struct ipw_cmd), (caddr_t *)&sc->cmd, BUS_DMA_NOWAIT); 1106 if (error != 0) { 1107 errmsg = "could not map cmd dma memory"; 1108 goto fail; 1109 } 1110 1111 /* Allocate a pool of DMA-able headers */ 1112 sc->shdr_list = malloc(IPW_NDATA * sizeof (struct ipw_soft_hdr), 1113 M_DEVBUF, M_NOWAIT); 1114 if (sc->shdr_list == NULL) { 1115 errmsg = "could not allocate soft hdr"; 1116 error = ENOMEM; 1117 goto fail; 1118 } 1119 TAILQ_INIT(&sc->sc_free_shdr); 1120 for (i = 0, shdr = sc->shdr_list; i < IPW_NDATA; i++, shdr++) { 1121 error = bus_dmamap_create(sc->sc_dmat, 1122 sizeof (struct ipw_soft_hdr), 1, 1123 sizeof (struct ipw_soft_hdr), 0, BUS_DMA_NOWAIT, 1124 &shdr->map); 1125 if (error != 0) { 1126 errmsg = "could not create hdr dma map"; 1127 goto fail; 1128 } 1129 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 1130 } 1131 1132 /* Allocate a pool of DMA-able buffers */ 1133 sc->tx_sbuf_list = malloc(IPW_NDATA * sizeof (struct ipw_soft_buf), 1134 M_DEVBUF, M_NOWAIT); 1135 if (sc->tx_sbuf_list == NULL) { 1136 errmsg = "could not allocate soft txbuf"; 1137 error = ENOMEM; 1138 goto fail; 1139 } 1140 TAILQ_INIT(&sc->sc_free_sbuf); 1141 for (i = 0, sbuf = sc->tx_sbuf_list; i < IPW_NDATA; i++, sbuf++) { 1142 error = bus_dmamap_create(sc->sc_dmat, IPW_NDATA * MCLBYTES, 1143 IPW_NDATA, MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 1144 if (error != 0) { 1145 errmsg = "could not create txbuf dma map"; 1146 goto fail; 1147 } 1148 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 1149 } 1150 1151 return 0; 1152 1153 fail: aprint_error("%s: %s\n", sc->sc_dev.dv_xname, errmsg); 1154 ipw_tx_stop(sc); 1155 1156 return error; 1157 } 1158 1159 static void 1160 ipw_tx_stop(struct ipw_softc *sc) 1161 { 1162 struct ipw_soft_hdr *shdr; 1163 struct ipw_soft_buf *sbuf; 1164 int i; 1165 1166 if (sc->tbd_map != NULL) { 1167 if (sc->tbd_list != NULL) { 1168 bus_dmamap_unload(sc->sc_dmat, sc->tbd_map); 1169 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->tbd_list, 1170 IPW_TBD_SZ); 1171 bus_dmamem_free(sc->sc_dmat, &sc->tbd_seg, 1); 1172 sc->tbd_list = NULL; 1173 } 1174 bus_dmamap_destroy(sc->sc_dmat, sc->tbd_map); 1175 sc->tbd_map = NULL; 1176 } 1177 1178 if (sc->stbd_list != NULL) { 1179 for (i = 0; i < IPW_NTBD; i++) 1180 ipw_release_sbd(sc, &sc->stbd_list[i]); 1181 free(sc->stbd_list, M_DEVBUF); 1182 sc->stbd_list = NULL; 1183 } 1184 1185 if (sc->cmd_map != NULL) { 1186 if (sc->cmd != NULL) { 1187 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->cmd, 1188 sizeof (struct ipw_cmd)); 1189 bus_dmamem_free(sc->sc_dmat, &sc->cmd_seg, 1); 1190 sc->cmd = NULL; 1191 } 1192 bus_dmamap_destroy(sc->sc_dmat, sc->cmd_map); 1193 sc->cmd_map = NULL; 1194 } 1195 1196 if (sc->shdr_list != NULL) { 1197 TAILQ_FOREACH(shdr, &sc->sc_free_shdr, next) 1198 bus_dmamap_destroy(sc->sc_dmat, shdr->map); 1199 free(sc->shdr_list, M_DEVBUF); 1200 sc->shdr_list = NULL; 1201 } 1202 1203 1204 if (sc->tx_sbuf_list != NULL) { 1205 TAILQ_FOREACH(sbuf, &sc->sc_free_sbuf, next) 1206 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 1207 free(sc->tx_sbuf_list, M_DEVBUF); 1208 sc->tx_sbuf_list = NULL; 1209 } 1210 } 1211 1212 static int 1213 ipw_rx_init(struct ipw_softc *sc) 1214 { 1215 char *errmsg; 1216 struct ipw_bd *bd; 1217 struct ipw_soft_bd *sbd; 1218 struct ipw_soft_buf *sbuf; 1219 int error, i, nsegs; 1220 1221 /* Allocate reception buffer descriptors */ 1222 error = bus_dmamap_create(sc->sc_dmat, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, 1223 BUS_DMA_NOWAIT, &sc->rbd_map); 1224 if (error != 0) { 1225 errmsg = "could not create rbd dma map"; 1226 goto fail; 1227 } 1228 1229 error = bus_dmamem_alloc(sc->sc_dmat, IPW_RBD_SZ, PAGE_SIZE, 0, 1230 &sc->rbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 1231 if (error != 0) { 1232 errmsg = "could not allocate rbd dma memory"; 1233 goto fail; 1234 } 1235 1236 error = bus_dmamem_map(sc->sc_dmat, &sc->rbd_seg, nsegs, IPW_RBD_SZ, 1237 (caddr_t *)&sc->rbd_list, BUS_DMA_NOWAIT); 1238 if (error != 0) { 1239 errmsg = "could not map rbd dma memory"; 1240 goto fail; 1241 } 1242 1243 error = bus_dmamap_load(sc->sc_dmat, sc->rbd_map, sc->rbd_list, 1244 IPW_RBD_SZ, NULL, BUS_DMA_NOWAIT); 1245 if (error != 0) { 1246 errmsg = "could not load rbd dma memory"; 1247 goto fail; 1248 } 1249 1250 sc->srbd_list = malloc(IPW_NRBD * sizeof (struct ipw_soft_bd), 1251 M_DEVBUF, M_NOWAIT); 1252 if (sc->srbd_list == NULL) { 1253 errmsg = "could not allocate soft rbd"; 1254 error = ENOMEM; 1255 goto fail; 1256 } 1257 sbd = sc->srbd_list; 1258 bd = sc->rbd_list; 1259 for (i = 0; i < IPW_NRBD; i++, sbd++, bd++) { 1260 sbd->type = IPW_SBD_TYPE_NOASSOC; 1261 sbd->bd = bd; 1262 } 1263 1264 CSR_WRITE_4(sc, IPW_CSR_RX_BD_BASE, sc->rbd_map->dm_segs[0].ds_addr); 1265 CSR_WRITE_4(sc, IPW_CSR_RX_BD_SIZE, IPW_NRBD); 1266 CSR_WRITE_4(sc, IPW_CSR_RX_READ_INDEX, 0); 1267 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE_INDEX, IPW_NRBD - 1); 1268 sc->rxcur = IPW_NRBD - 1; /* latest bd index I've read */ 1269 1270 /* Allocate status descriptors */ 1271 error = bus_dmamap_create(sc->sc_dmat, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 1272 0, BUS_DMA_NOWAIT, &sc->status_map); 1273 if (error != 0) { 1274 errmsg = "could not create status dma map"; 1275 goto fail; 1276 } 1277 1278 error = bus_dmamem_alloc(sc->sc_dmat, IPW_STATUS_SZ, PAGE_SIZE, 0, 1279 &sc->status_seg, 1, &nsegs, BUS_DMA_NOWAIT); 1280 if (error != 0) { 1281 errmsg = "could not allocate status dma memory"; 1282 goto fail; 1283 } 1284 1285 error = bus_dmamem_map(sc->sc_dmat, &sc->status_seg, nsegs, 1286 IPW_STATUS_SZ, (caddr_t *)&sc->status_list, BUS_DMA_NOWAIT); 1287 if (error != 0) { 1288 errmsg = "could not map status dma memory"; 1289 goto fail; 1290 } 1291 1292 error = bus_dmamap_load(sc->sc_dmat, sc->status_map, sc->status_list, 1293 IPW_STATUS_SZ, NULL, BUS_DMA_NOWAIT); 1294 if (error != 0) { 1295 errmsg = "could not load status dma memory"; 1296 goto fail; 1297 } 1298 1299 CSR_WRITE_4(sc, IPW_CSR_RX_STATUS_BASE, 1300 sc->status_map->dm_segs[0].ds_addr); 1301 1302 sc->rx_sbuf_list = malloc(IPW_NRBD * sizeof (struct ipw_soft_buf), 1303 M_DEVBUF, M_NOWAIT); 1304 if (sc->rx_sbuf_list == NULL) { 1305 errmsg = "could not allocate soft rxbuf"; 1306 error = ENOMEM; 1307 goto fail; 1308 } 1309 1310 sbuf = sc->rx_sbuf_list; 1311 sbd = sc->srbd_list; 1312 for (i = 0; i < IPW_NRBD; i++, sbuf++, sbd++) { 1313 1314 MGETHDR(sbuf->m, M_DONTWAIT, MT_DATA); 1315 if (sbuf->m == NULL) { 1316 errmsg = "could not allocate rx mbuf"; 1317 error = ENOMEM; 1318 goto fail; 1319 } 1320 MCLGET(sbuf->m, M_DONTWAIT); 1321 if (!(sbuf->m->m_flags & M_EXT)) { 1322 m_freem(sbuf->m); 1323 errmsg = "could not allocate rx mbuf cluster"; 1324 error = ENOMEM; 1325 goto fail; 1326 } 1327 1328 error = bus_dmamap_create(sc->sc_dmat, IPW_NRBD * MCLBYTES, 1329 IPW_NRBD, MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 1330 if (error != 0) { 1331 m_freem(sbuf->m); 1332 errmsg = "could not create rxbuf dma map"; 1333 goto fail; 1334 } 1335 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, 1336 mtod(sbuf->m, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 1337 if (error != 0) { 1338 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 1339 m_freem(sbuf->m); 1340 errmsg = "could not map rxbuf dma memory"; 1341 goto fail; 1342 } 1343 sbd->type = IPW_SBD_TYPE_DATA; 1344 sbd->priv = sbuf; 1345 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 1346 sbd->bd->len = htole32(MCLBYTES); 1347 } 1348 1349 return 0; 1350 1351 fail: aprint_error("%s: %s\n", sc->sc_dev.dv_xname, errmsg); 1352 ipw_rx_stop(sc); 1353 1354 return error; 1355 } 1356 1357 static void 1358 ipw_rx_stop(struct ipw_softc *sc) 1359 { 1360 struct ipw_soft_bd *sbd; 1361 struct ipw_soft_buf *sbuf; 1362 int i; 1363 1364 if (sc->rbd_map != NULL) { 1365 if (sc->rbd_list != NULL) { 1366 bus_dmamap_unload(sc->sc_dmat, sc->rbd_map); 1367 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->rbd_list, 1368 IPW_RBD_SZ); 1369 bus_dmamem_free(sc->sc_dmat, &sc->rbd_seg, 1); 1370 sc->rbd_list = NULL; 1371 } 1372 bus_dmamap_destroy(sc->sc_dmat, sc->rbd_map); 1373 sc->rbd_map = NULL; 1374 } 1375 1376 if (sc->status_map != NULL) { 1377 if (sc->status_list != NULL) { 1378 bus_dmamap_unload(sc->sc_dmat, sc->status_map); 1379 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->status_list, 1380 IPW_STATUS_SZ); 1381 bus_dmamem_free(sc->sc_dmat, &sc->status_seg, 1); 1382 sc->status_list = NULL; 1383 } 1384 bus_dmamap_destroy(sc->sc_dmat, sc->status_map); 1385 sc->status_map = NULL; 1386 } 1387 1388 if (sc->srbd_list != NULL) { 1389 for (i = 0, sbd = sc->srbd_list; i < IPW_NRBD; i++, sbd++) { 1390 if (sbd->type == IPW_SBD_TYPE_NOASSOC) 1391 continue; 1392 1393 sbuf = sbd->priv; 1394 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1395 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 1396 m_freem(sbuf->m); 1397 } 1398 free(sc->srbd_list, M_DEVBUF); 1399 sc->srbd_list = NULL; 1400 } 1401 1402 if (sc->rx_sbuf_list != NULL) { 1403 free(sc->rx_sbuf_list, M_DEVBUF); 1404 sc->rx_sbuf_list = NULL; 1405 } 1406 } 1407 1408 static void 1409 ipw_reset(struct ipw_softc *sc) 1410 { 1411 struct ifnet *ifp = &sc->sc_ic.ic_if; 1412 int ntries; 1413 1414 ipw_stop(ifp, 1); 1415 1416 if (sc->flags & IPW_FLAG_FW_INITED) { 1417 ipw_cmd(sc, IPW_CMD_DISABLE_PHY, NULL, 0); 1418 ipw_cmd(sc, IPW_CMD_PREPARE_POWER_DOWN, NULL, 0); 1419 1420 sc->flags &= ~IPW_FLAG_FW_INITED; 1421 } 1422 1423 /* Disable interrupts */ 1424 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1425 1426 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1427 for (ntries = 0; ntries < 5; ntries++) { 1428 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1429 break; 1430 DELAY(10); 1431 } 1432 1433 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 1434 1435 ipw_rx_stop(sc); 1436 ipw_tx_stop(sc); 1437 1438 ifp->if_flags &= ~IFF_UP; 1439 } 1440 1441 static int 1442 ipw_clock_sync(struct ipw_softc *sc) 1443 { 1444 int ntries; 1445 u_int32_t r; 1446 1447 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 1448 for (ntries = 0; ntries < 1000; ntries++) { 1449 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_PRINCETON_RESET) 1450 break; 1451 DELAY(10); 1452 } 1453 if (ntries == 1000) 1454 return EIO; 1455 1456 CSR_WRITE_4(sc, IPW_CSR_CTL, IPW_CTL_INIT_DONE); 1457 for (ntries = 0; ntries < 1000; ntries++) { 1458 if ((r = CSR_READ_4(sc, IPW_CSR_CTL)) & IPW_CTL_CLOCK_READY) 1459 break; 1460 DELAY(200); 1461 } 1462 if (ntries == 1000) 1463 return EIO; 1464 1465 CSR_WRITE_4(sc, IPW_CSR_CTL, r | IPW_CTL_ALLOW_STANDBY); 1466 1467 return 0; 1468 } 1469 1470 static int 1471 ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size) 1472 { 1473 int ntries; 1474 1475 MEM_WRITE_2(sc, 0x220000, 0x0703); 1476 MEM_WRITE_2(sc, 0x220000, 0x0707); 1477 1478 MEM_WRITE_1(sc, 0x210014, 0x72); 1479 MEM_WRITE_1(sc, 0x210014, 0x72); 1480 1481 MEM_WRITE_1(sc, 0x210000, 0x40); 1482 MEM_WRITE_1(sc, 0x210000, 0x00); 1483 MEM_WRITE_1(sc, 0x210000, 0x40); 1484 1485 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1486 1487 MEM_WRITE_1(sc, 0x210000, 0x00); 1488 MEM_WRITE_1(sc, 0x210000, 0x00); 1489 MEM_WRITE_1(sc, 0x210000, 0x80); 1490 1491 MEM_WRITE_2(sc, 0x220000, 0x0703); 1492 MEM_WRITE_2(sc, 0x220000, 0x0707); 1493 1494 MEM_WRITE_1(sc, 0x210014, 0x72); 1495 MEM_WRITE_1(sc, 0x210014, 0x72); 1496 1497 MEM_WRITE_1(sc, 0x210000, 0x00); 1498 MEM_WRITE_1(sc, 0x210000, 0x80); 1499 1500 for (ntries = 0; ntries < 10; ntries++) { 1501 if (MEM_READ_1(sc, 0x210000) & 1) 1502 break; 1503 DELAY(10); 1504 } 1505 if (ntries == 10) 1506 return EIO; 1507 1508 return 0; 1509 } 1510 1511 /* set of macros to handle unaligned little endian data in firmware image */ 1512 #define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1513 #define GETLE16(p) ((p)[0] | (p)[1] << 8) 1514 static int 1515 ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size) 1516 { 1517 u_char *p, *end; 1518 u_int32_t addr; 1519 u_int16_t len; 1520 1521 p = fw; 1522 end = fw + size; 1523 while (p < end) { 1524 if (p + 6 > end) 1525 return EINVAL; 1526 1527 addr = GETLE32(p); 1528 p += 4; 1529 len = GETLE16(p); 1530 p += 2; 1531 1532 if (p + len > end) 1533 return EINVAL; 1534 1535 ipw_write_mem_1(sc, addr, p, len); 1536 p += len; 1537 } 1538 return 0; 1539 } 1540 1541 static int 1542 ipw_firmware_init(struct ipw_softc *sc, u_char *data) 1543 { 1544 struct ieee80211com *ic = &sc->sc_ic; 1545 struct ifnet *ifp = &ic->ic_if; 1546 struct ipw_fw_hdr hdr; 1547 u_int32_t r, len, fw_size, uc_size; 1548 u_char *fw, *uc; 1549 int error; 1550 1551 ipw_reset(sc); 1552 1553 if ((error = copyin(data, &hdr, sizeof hdr)) != 0) 1554 goto fail1; 1555 1556 fw_size = le32toh(hdr.fw_size); 1557 uc_size = le32toh(hdr.uc_size); 1558 data += sizeof hdr; 1559 1560 if ((fw = malloc(fw_size, M_DEVBUF, M_NOWAIT)) == NULL) { 1561 error = ENOMEM; 1562 goto fail1; 1563 } 1564 1565 if ((error = copyin(data, fw, fw_size)) != 0) 1566 goto fail2; 1567 1568 data += fw_size; 1569 1570 if ((uc = malloc(uc_size, M_DEVBUF, M_NOWAIT)) == NULL) { 1571 error = ENOMEM; 1572 goto fail2; 1573 } 1574 1575 if ((error = copyin(data, uc, uc_size)) != 0) 1576 goto fail3; 1577 1578 if ((error = ipw_clock_sync(sc)) != 0) { 1579 aprint_error("%s: clock synchronization failed\n", 1580 sc->sc_dev.dv_xname); 1581 goto fail3; 1582 } 1583 1584 MEM_WRITE_4(sc, 0x003000e0, 0x80000000); 1585 1586 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1587 1588 if ((error = ipw_load_ucode(sc, uc, uc_size)) != 0) { 1589 aprint_error("%s: could not load microcode\n", 1590 sc->sc_dev.dv_xname); 1591 goto fail3; 1592 } 1593 1594 MEM_WRITE_4(sc, 0x003000e0, 0); 1595 1596 if ((error = ipw_clock_sync(sc)) != 0) { 1597 aprint_error("%s: clock synchronization failed\n", 1598 sc->sc_dev.dv_xname); 1599 goto fail3; 1600 } 1601 1602 if ((error = ipw_load_firmware(sc, fw, fw_size))) { 1603 aprint_error("%s: could not load firmware\n", 1604 sc->sc_dev.dv_xname); 1605 goto fail3; 1606 } 1607 1608 ipw_zero_mem_4(sc, 0x0002f200, 196); 1609 ipw_zero_mem_4(sc, 0x0002f610, 8); 1610 ipw_zero_mem_4(sc, 0x0002fa00, 8); 1611 ipw_zero_mem_4(sc, 0x0002fc00, 4); 1612 ipw_zero_mem_4(sc, 0x0002ff80, 32); 1613 1614 if ((error = ipw_rx_init(sc)) != 0) { 1615 aprint_error("%s: could not initialize rx queue\n", 1616 sc->sc_dev.dv_xname); 1617 goto fail3; 1618 } 1619 1620 if ((error = ipw_tx_init(sc)) != 0) { 1621 aprint_error("%s: could not initialize tx queue\n", 1622 sc->sc_dev.dv_xname); 1623 goto fail3; 1624 } 1625 1626 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1627 IPW_IO_LED_OFF); 1628 1629 /* Enable interrupts */ 1630 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1631 1632 /* Let's go! */ 1633 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1634 1635 /* Wait at most 5 seconds for firmware initialization to complete */ 1636 if ((error = tsleep(sc, 0, "ipwinit", 5 * hz)) != 0) { 1637 aprint_error("%s: timeout waiting for firmware initialization " 1638 "to complete\n", sc->sc_dev.dv_xname); 1639 goto fail3; 1640 } 1641 1642 /* Firmware initialization completed */ 1643 sc->flags |= IPW_FLAG_FW_INITED; 1644 1645 free(uc, M_DEVBUF); 1646 free(fw, M_DEVBUF); 1647 1648 r = CSR_READ_4(sc, IPW_CSR_IO); 1649 CSR_WRITE_4(sc, IPW_CSR_IO, r | IPW_IO_GPIO1_MASK | IPW_IO_GPIO3_MASK); 1650 1651 /* Retrieve information tables base addresses */ 1652 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 1653 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 1654 1655 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 1656 1657 /* Retrieve adapter MAC address */ 1658 len = IEEE80211_ADDR_LEN; 1659 ipw_read_table2(sc, IPW_INFO_ADAPTER_MAC, ic->ic_myaddr, &len); 1660 1661 IEEE80211_ADDR_COPY(LLADDR(ifp->if_sadl), ic->ic_myaddr); 1662 1663 return 0; 1664 1665 fail3: free(uc, M_DEVBUF); 1666 fail2: free(fw, M_DEVBUF); 1667 fail1: ipw_reset(sc); 1668 1669 return error; 1670 } 1671 1672 static int 1673 ipw_config(struct ipw_softc *sc) 1674 { 1675 struct ieee80211com *ic = &sc->sc_ic; 1676 struct ifnet *ifp = &ic->ic_if; 1677 struct ipw_security security; 1678 struct ieee80211_wepkey *k; 1679 struct ipw_wep_key wepkey; 1680 struct ipw_scan_options options; 1681 struct ipw_configuration config; 1682 u_int32_t data; 1683 int error, i; 1684 1685 DPRINTF(("Setting adapter MAC to %s\n", ether_sprintf(ic->ic_myaddr))); 1686 IEEE80211_ADDR_COPY(LLADDR(ifp->if_sadl), ic->ic_myaddr); 1687 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 1688 IEEE80211_ADDR_LEN); 1689 if (error != 0) 1690 return error; 1691 1692 switch (ic->ic_opmode) { 1693 case IEEE80211_M_STA: 1694 case IEEE80211_M_HOSTAP: 1695 data = htole32(IPW_MODE_BSS); 1696 break; 1697 1698 case IEEE80211_M_IBSS: 1699 case IEEE80211_M_AHDEMO: 1700 data = htole32(IPW_MODE_IBSS); 1701 break; 1702 1703 case IEEE80211_M_MONITOR: 1704 data = htole32(IPW_MODE_MONITOR); 1705 break; 1706 } 1707 DPRINTF(("Setting adapter mode to %u\n", data)); 1708 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 1709 if (error != 0) 1710 return error; 1711 1712 if (ic->ic_opmode == IEEE80211_M_IBSS || 1713 ic->ic_opmode == IEEE80211_M_MONITOR) { 1714 data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); 1715 DPRINTF(("Setting adapter channel to %u\n", data)); 1716 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 1717 if (error != 0) 1718 return error; 1719 } 1720 1721 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 1722 IPW_CFG_PREAMBLE_LEN | IPW_CFG_802_1x_ENABLE); 1723 if (ic->ic_opmode == IEEE80211_M_IBSS) 1724 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 1725 if (ifp->if_flags & IFF_PROMISC) 1726 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 1727 config.channels = htole32(0x3fff); /* channels 1-14 */ 1728 config.ibss_chan = htole32(0x7ff); 1729 DPRINTF(("Setting adapter configuration 0x%08x\n", config.flags)); 1730 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 1731 if (error != 0) 1732 return error; 1733 1734 data = htole32(0x3); /* 1, 2 */ 1735 DPRINTF(("Setting adapter basic tx rates to 0x%x\n", data)); 1736 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 1737 if (error != 0) 1738 return error; 1739 1740 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 1741 DPRINTF(("Setting adapter tx rates to 0x%x\n", data)); 1742 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 1743 if (error != 0) 1744 return error; 1745 1746 data = htole32(IPW_POWER_MODE_CAM); 1747 DPRINTF(("Setting adapter power mode to %u\n", data)); 1748 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 1749 if (error != 0) 1750 return error; 1751 1752 if (ic->ic_opmode == IEEE80211_M_IBSS) { 1753 data = htole32(ic->ic_txpower); 1754 DPRINTF(("Setting adapter tx power index to %u\n", data)); 1755 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 1756 sizeof data); 1757 if (error != 0) 1758 return error; 1759 } 1760 1761 data = htole32(ic->ic_rtsthreshold); 1762 DPRINTF(("Setting adapter RTS threshold to %u\n", data)); 1763 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 1764 if (error != 0) 1765 return error; 1766 1767 data = htole32(ic->ic_fragthreshold); 1768 DPRINTF(("Setting adapter frag threshold to %u\n", data)); 1769 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 1770 if (error != 0) 1771 return error; 1772 1773 #ifdef IPW_DEBUG 1774 if (ipw_debug > 0) { 1775 printf("Setting adapter ESSID to "); 1776 ieee80211_print_essid(ic->ic_des_essid, ic->ic_des_esslen); 1777 printf("\n"); 1778 } 1779 #endif 1780 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ic->ic_des_essid, 1781 ic->ic_des_esslen); 1782 if (error != 0) 1783 return error; 1784 1785 /* no mandatory BSSID */ 1786 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 1787 if (error != 0) 1788 return error; 1789 1790 if (ic->ic_flags & IEEE80211_F_DESBSSID) { 1791 DPRINTF(("Setting adapter desired BSSID to %s\n", 1792 ether_sprintf(ic->ic_des_bssid))); 1793 error = ipw_cmd(sc, IPW_CMD_SET_DESIRED_BSSID, 1794 ic->ic_des_bssid, IEEE80211_ADDR_LEN); 1795 if (error != 0) 1796 return error; 1797 } 1798 1799 security.authmode = IPW_AUTH_OPEN; 1800 security.ciphers = htole32(IPW_CIPHER_NONE); 1801 security.version = htole16(0); 1802 security.replay_counters_number = 0; 1803 security.unicast_using_group = 0; 1804 DPRINTF(("Setting adapter authmode to %u\n", security.authmode)); 1805 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 1806 sizeof security); 1807 if (error != 0) 1808 return error; 1809 1810 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 1811 k = ic->ic_nw_keys; 1812 for (i = 0; i < IEEE80211_WEP_NKID; i++, k++) { 1813 if (k->wk_len == 0) 1814 continue; 1815 1816 wepkey.idx = i; 1817 wepkey.len = k->wk_len; 1818 bzero(wepkey.key, sizeof wepkey.key); 1819 bcopy(k->wk_key, wepkey.key, k->wk_len); 1820 DPRINTF(("Setting wep key index %d len %d\n", 1821 wepkey.idx, wepkey.len)); 1822 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY, &wepkey, 1823 sizeof wepkey); 1824 if (error != 0) 1825 return error; 1826 } 1827 1828 data = htole32(ic->ic_wep_txkey); 1829 DPRINTF(("Setting adapter tx key index to %u\n", data)); 1830 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY_INDEX, &data, 1831 sizeof data); 1832 if (error != 0) 1833 return error; 1834 } 1835 1836 data = htole32((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) ? 0x8 : 0); 1837 DPRINTF(("Setting adapter wep flags to 0x%x\n", data)); 1838 error = ipw_cmd(sc, IPW_CMD_SET_WEP_FLAGS, &data, sizeof data); 1839 if (error != 0) 1840 return error; 1841 1842 if (ic->ic_opmode == IEEE80211_M_IBSS || 1843 ic->ic_opmode == IEEE80211_M_HOSTAP) { 1844 data = htole32(ic->ic_lintval); 1845 DPRINTF(("Setting adapter beacon interval to %u\n", data)); 1846 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 1847 sizeof data); 1848 if (error != 0) 1849 return error; 1850 } 1851 1852 options.flags = htole32(0); 1853 options.channels = htole32(0x3fff); /* scan channels 1-14 */ 1854 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &options, sizeof options); 1855 if (error != 0) 1856 return error; 1857 1858 /* finally, enable adapter (start scanning for an access point) */ 1859 DPRINTF(("Enabling adapter\n")); 1860 error = ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1861 if (error != 0) 1862 return error; 1863 1864 return 0; 1865 } 1866 1867 static int 1868 ipw_init(struct ifnet *ifp) 1869 { 1870 struct ipw_softc *sc = ifp->if_softc; 1871 struct ieee80211com *ic = &sc->sc_ic; 1872 1873 /* exit immediately if firmware has not been ioctl'd */ 1874 if (!(sc->flags & IPW_FLAG_FW_INITED)) { 1875 ifp->if_flags &= ~IFF_UP; 1876 return EIO; 1877 } 1878 1879 ipw_stop(ifp, 0); 1880 1881 if (ipw_config(sc) != 0) { 1882 aprint_error("%s: device configuration failed\n", 1883 sc->sc_dev.dv_xname); 1884 goto fail; 1885 } 1886 1887 ifp->if_flags &= ~IFF_OACTIVE; 1888 ifp->if_flags |= IFF_RUNNING; 1889 1890 ic->ic_bss->ni_chan = ic->ic_channels; 1891 1892 return 0; 1893 1894 fail: ipw_stop(ifp, 0); 1895 1896 return EIO; 1897 } 1898 1899 static void 1900 ipw_stop(struct ifnet *ifp, int disable) 1901 { 1902 struct ipw_softc *sc = ifp->if_softc; 1903 struct ieee80211com *ic = &sc->sc_ic; 1904 1905 if (ifp->if_flags & IFF_RUNNING) { 1906 DPRINTF(("Disabling adapter\n")); 1907 ipw_cmd(sc, IPW_CMD_DISABLE, NULL, 0); 1908 } 1909 1910 ifp->if_timer = 0; 1911 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1912 1913 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1914 } 1915 1916 static void 1917 ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, u_int8_t *datap, 1918 bus_size_t count) 1919 { 1920 for (; count > 0; offset++, datap++, count--) { 1921 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 1922 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 1923 } 1924 } 1925 1926 static void 1927 ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, u_int8_t *datap, 1928 bus_size_t count) 1929 { 1930 for (; count > 0; offset++, datap++, count--) { 1931 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 1932 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 1933 } 1934 } 1935 1936 static void 1937 ipw_zero_mem_4(struct ipw_softc *sc, bus_size_t offset, bus_size_t count) 1938 { 1939 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, offset); 1940 while (count-- > 0) 1941 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_DATA, 0); 1942 } 1943 1944
Indexes created Tue Sep 30 11:09:46 GMT 2025