if_ipw.c revision 1.41
1 /* $NetBSD: if_ipw.c,v 1.41 2008/05/27 21:41:01 dyoung Exp $ */ 2 /* FreeBSD: src/sys/dev/ipw/if_ipw.c,v 1.15 2005/11/13 17:17:40 damien Exp */ 3 4 /*- 5 * Copyright (c) 2004, 2005 6 * Damien Bergamini <damien.bergamini (at) free.fr>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: if_ipw.c,v 1.41 2008/05/27 21:41:01 dyoung Exp $"); 33 34 /*- 35 * Intel(R) PRO/Wireless 2100 MiniPCI driver 36 * http://www.intel.com/network/connectivity/products/wireless/prowireless_mobile.htm 37 */ 38 39 #include "bpfilter.h" 40 41 #include <sys/param.h> 42 #include <sys/sockio.h> 43 #include <sys/sysctl.h> 44 #include <sys/mbuf.h> 45 #include <sys/kernel.h> 46 #include <sys/socket.h> 47 #include <sys/systm.h> 48 #include <sys/malloc.h> 49 #include <sys/conf.h> 50 51 #include <sys/bus.h> 52 #include <machine/endian.h> 53 #include <sys/intr.h> 54 55 #include <dev/pci/pcireg.h> 56 #include <dev/pci/pcivar.h> 57 #include <dev/pci/pcidevs.h> 58 59 #if NBPFILTER > 0 60 #include <net/bpf.h> 61 #endif 62 #include <net/if.h> 63 #include <net/if_arp.h> 64 #include <net/if_dl.h> 65 #include <net/if_ether.h> 66 #include <net/if_media.h> 67 #include <net/if_types.h> 68 69 #include <net80211/ieee80211_var.h> 70 #include <net80211/ieee80211_radiotap.h> 71 72 #include <netinet/in.h> 73 #include <netinet/in_systm.h> 74 #include <netinet/in_var.h> 75 #include <netinet/ip.h> 76 77 #include <dev/firmload.h> 78 79 #include <dev/pci/if_ipwreg.h> 80 #include <dev/pci/if_ipwvar.h> 81 82 #ifdef IPW_DEBUG 83 #define DPRINTF(x) if (ipw_debug > 0) printf x 84 #define DPRINTFN(n, x) if (ipw_debug >= (n)) printf x 85 int ipw_debug = 0; 86 #else 87 #define DPRINTF(x) 88 #define DPRINTFN(n, x) 89 #endif 90 91 static int ipw_dma_alloc(struct ipw_softc *); 92 static void ipw_release(struct ipw_softc *); 93 static int ipw_match(struct device *, struct cfdata *, void *); 94 static void ipw_attach(struct device *, struct device *, void *); 95 static int ipw_detach(struct device *, int); 96 97 static int ipw_media_change(struct ifnet *); 98 static void ipw_media_status(struct ifnet *, struct ifmediareq *); 99 static int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 100 static uint16_t ipw_read_prom_word(struct ipw_softc *, uint8_t); 101 static void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 102 static void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 103 static void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 104 struct ipw_soft_bd *, struct ipw_soft_buf *); 105 static void ipw_rx_intr(struct ipw_softc *); 106 static void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 107 static void ipw_tx_intr(struct ipw_softc *); 108 static int ipw_intr(void *); 109 static int ipw_cmd(struct ipw_softc *, uint32_t, void *, uint32_t); 110 static int ipw_tx_start(struct ifnet *, struct mbuf *, 111 struct ieee80211_node *); 112 static void ipw_start(struct ifnet *); 113 static void ipw_watchdog(struct ifnet *); 114 static int ipw_ioctl(struct ifnet *, u_long, void *); 115 static int ipw_get_table1(struct ipw_softc *, uint32_t *); 116 static int ipw_get_radio(struct ipw_softc *, int *); 117 static void ipw_stop_master(struct ipw_softc *); 118 static int ipw_reset(struct ipw_softc *); 119 static int ipw_load_ucode(struct ipw_softc *, u_char *, int); 120 static int ipw_load_firmware(struct ipw_softc *, u_char *, int); 121 static int ipw_cache_firmware(struct ipw_softc *); 122 static void ipw_free_firmware(struct ipw_softc *); 123 static int ipw_config(struct ipw_softc *); 124 static int ipw_init(struct ifnet *); 125 static void ipw_stop(struct ifnet *, int); 126 static uint32_t ipw_read_table1(struct ipw_softc *, uint32_t); 127 static void ipw_write_table1(struct ipw_softc *, uint32_t, uint32_t); 128 static int ipw_read_table2(struct ipw_softc *, uint32_t, void *, uint32_t *); 129 static void ipw_read_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 130 bus_size_t); 131 static void ipw_write_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 132 bus_size_t); 133 134 /* 135 * Supported rates for 802.11b mode (in 500Kbps unit). 136 */ 137 static const struct ieee80211_rateset ipw_rateset_11b = 138 { 4, { 2, 4, 11, 22 } }; 139 140 static inline uint8_t 141 MEM_READ_1(struct ipw_softc *sc, uint32_t addr) 142 { 143 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 144 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); 145 } 146 147 static inline uint32_t 148 MEM_READ_4(struct ipw_softc *sc, uint32_t addr) 149 { 150 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 151 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); 152 } 153 154 CFATTACH_DECL(ipw, sizeof (struct ipw_softc), ipw_match, ipw_attach, 155 ipw_detach, NULL); 156 157 static int 158 ipw_match(struct device *parent, struct cfdata *match, 159 void *aux) 160 { 161 struct pci_attach_args *pa = aux; 162 163 if (PCI_VENDOR (pa->pa_id) == PCI_VENDOR_INTEL && 164 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_PRO_WL_2100) 165 return 1; 166 167 return 0; 168 } 169 170 /* Base Address Register */ 171 #define IPW_PCI_BAR0 0x10 172 173 static void 174 ipw_attach(struct device *parent, struct device *self, void *aux) 175 { 176 struct ipw_softc *sc = (struct ipw_softc *)self; 177 struct ieee80211com *ic = &sc->sc_ic; 178 struct ifnet *ifp = &sc->sc_if; 179 struct pci_attach_args *pa = aux; 180 const char *intrstr; 181 char devinfo[256]; 182 bus_space_tag_t memt; 183 bus_space_handle_t memh; 184 bus_addr_t base; 185 pci_intr_handle_t ih; 186 uint32_t data; 187 uint16_t val; 188 int i, revision, error; 189 190 sc->sc_pct = pa->pa_pc; 191 sc->sc_pcitag = pa->pa_tag; 192 193 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof devinfo); 194 revision = PCI_REVISION(pa->pa_class); 195 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, revision); 196 197 /* enable bus-mastering */ 198 data = pci_conf_read(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG); 199 data |= PCI_COMMAND_MASTER_ENABLE; 200 pci_conf_write(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG, data); 201 202 /* map the register window */ 203 error = pci_mapreg_map(pa, IPW_PCI_BAR0, PCI_MAPREG_TYPE_MEM | 204 PCI_MAPREG_MEM_TYPE_32BIT, 0, &memt, &memh, &base, &sc->sc_sz); 205 if (error != 0) { 206 aprint_error_dev(&sc->sc_dev, "could not map memory space\n"); 207 return; 208 } 209 210 sc->sc_st = memt; 211 sc->sc_sh = memh; 212 sc->sc_dmat = pa->pa_dmat; 213 strlcpy(sc->sc_fwname, "ipw2100-1.2.fw", sizeof(sc->sc_fwname)); 214 215 /* disable interrupts */ 216 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 217 218 if (pci_intr_map(pa, &ih) != 0) { 219 aprint_error_dev(&sc->sc_dev, "could not map interrupt\n"); 220 return; 221 } 222 223 intrstr = pci_intr_string(sc->sc_pct, ih); 224 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, ipw_intr, sc); 225 if (sc->sc_ih == NULL) { 226 aprint_error_dev(&sc->sc_dev, "could not establish interrupt"); 227 if (intrstr != NULL) 228 aprint_error(" at %s", intrstr); 229 aprint_error("\n"); 230 return; 231 } 232 aprint_normal_dev(&sc->sc_dev, "interrupting at %s\n", intrstr); 233 234 if (ipw_reset(sc) != 0) { 235 aprint_error_dev(&sc->sc_dev, "could not reset adapter\n"); 236 goto fail; 237 } 238 239 if (ipw_dma_alloc(sc) != 0) { 240 aprint_error_dev(&sc->sc_dev, "could not allocate DMA resources\n"); 241 goto fail; 242 } 243 244 ifp->if_softc = sc; 245 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 246 ifp->if_init = ipw_init; 247 ifp->if_stop = ipw_stop; 248 ifp->if_ioctl = ipw_ioctl; 249 ifp->if_start = ipw_start; 250 ifp->if_watchdog = ipw_watchdog; 251 IFQ_SET_READY(&ifp->if_snd); 252 strlcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 253 254 ic->ic_ifp = ifp; 255 ic->ic_phytype = IEEE80211_T_DS; 256 ic->ic_opmode = IEEE80211_M_STA; 257 ic->ic_state = IEEE80211_S_INIT; 258 259 /* set device capabilities */ 260 ic->ic_caps = 261 IEEE80211_C_SHPREAMBLE /* short preamble supported */ 262 | IEEE80211_C_TXPMGT /* tx power management */ 263 | IEEE80211_C_IBSS /* ibss mode */ 264 | IEEE80211_C_MONITOR /* monitor mode */ 265 ; 266 267 /* read MAC address from EEPROM */ 268 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0); 269 ic->ic_myaddr[0] = val >> 8; 270 ic->ic_myaddr[1] = val & 0xff; 271 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 1); 272 ic->ic_myaddr[2] = val >> 8; 273 ic->ic_myaddr[3] = val & 0xff; 274 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 2); 275 ic->ic_myaddr[4] = val >> 8; 276 ic->ic_myaddr[5] = val & 0xff; 277 278 /* set supported .11b rates */ 279 ic->ic_sup_rates[IEEE80211_MODE_11B] = ipw_rateset_11b; 280 281 /* set supported .11b channels (read from EEPROM) */ 282 if ((val = ipw_read_prom_word(sc, IPW_EEPROM_CHANNEL_LIST)) == 0) 283 val = 0x7ff; /* default to channels 1-11 */ 284 val <<= 1; 285 for (i = 1; i < 16; i++) { 286 if (val & (1 << i)) { 287 ic->ic_channels[i].ic_freq = 288 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 289 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 290 } 291 } 292 293 /* check support for radio transmitter switch in EEPROM */ 294 if (!(ipw_read_prom_word(sc, IPW_EEPROM_RADIO) & 8)) 295 sc->flags |= IPW_FLAG_HAS_RADIO_SWITCH; 296 297 aprint_normal_dev(&sc->sc_dev, "802.11 address %s\n", 298 ether_sprintf(ic->ic_myaddr)); 299 300 if_attach(ifp); 301 ieee80211_ifattach(ic); 302 303 /* override state transition machine */ 304 sc->sc_newstate = ic->ic_newstate; 305 ic->ic_newstate = ipw_newstate; 306 307 ieee80211_media_init(ic, ipw_media_change, ipw_media_status); 308 309 #if NBPFILTER > 0 310 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 311 sizeof (struct ieee80211_frame) + 64, &sc->sc_drvbpf); 312 313 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 314 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 315 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 316 317 sc->sc_txtap_len = sizeof sc->sc_txtapu; 318 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 319 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 320 #endif 321 322 /* 323 * Add a few sysctl knobs. 324 * XXX: Not yet 325 */ 326 sc->dwelltime = 100; 327 328 if (!pmf_device_register(self, NULL, NULL)) 329 aprint_error_dev(self, "couldn't establish power handler\n"); 330 else 331 pmf_class_network_register(self, ifp); 332 333 ieee80211_announce(ic); 334 335 return; 336 337 fail: ipw_detach(self, 0); 338 } 339 340 static int 341 ipw_detach(struct device* self, int flags) 342 { 343 struct ipw_softc *sc = (struct ipw_softc *)self; 344 struct ifnet *ifp = &sc->sc_if; 345 346 if (ifp->if_softc) { 347 ipw_stop(ifp, 1); 348 ipw_free_firmware(sc); 349 350 #if NBPFILTER > 0 351 bpfdetach(ifp); 352 #endif 353 ieee80211_ifdetach(&sc->sc_ic); 354 if_detach(ifp); 355 356 ipw_release(sc); 357 } 358 359 if (sc->sc_ih != NULL) { 360 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 361 sc->sc_ih = NULL; 362 } 363 364 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 365 366 return 0; 367 } 368 369 static int 370 ipw_dma_alloc(struct ipw_softc *sc) 371 { 372 struct ipw_soft_bd *sbd; 373 struct ipw_soft_hdr *shdr; 374 struct ipw_soft_buf *sbuf; 375 int error, i, nsegs; 376 377 /* 378 * Allocate and map tx ring. 379 */ 380 error = bus_dmamap_create(sc->sc_dmat, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, 381 BUS_DMA_NOWAIT, &sc->tbd_map); 382 if (error != 0) { 383 aprint_error_dev(&sc->sc_dev, "could not create tbd dma map\n"); 384 goto fail; 385 } 386 387 error = bus_dmamem_alloc(sc->sc_dmat, IPW_TBD_SZ, PAGE_SIZE, 0, 388 &sc->tbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 389 if (error != 0) { 390 aprint_error_dev(&sc->sc_dev, "could not allocate tbd dma memory\n"); 391 goto fail; 392 } 393 394 error = bus_dmamem_map(sc->sc_dmat, &sc->tbd_seg, nsegs, IPW_TBD_SZ, 395 (void **)&sc->tbd_list, BUS_DMA_NOWAIT); 396 if (error != 0) { 397 aprint_error_dev(&sc->sc_dev, "could not map tbd dma memory\n"); 398 goto fail; 399 } 400 401 error = bus_dmamap_load(sc->sc_dmat, sc->tbd_map, sc->tbd_list, 402 IPW_TBD_SZ, NULL, BUS_DMA_NOWAIT); 403 if (error != 0) { 404 aprint_error_dev(&sc->sc_dev, "could not load tbd dma memory\n"); 405 goto fail; 406 } 407 408 (void)memset(sc->tbd_list, 0, IPW_TBD_SZ); 409 410 /* 411 * Allocate and map rx ring. 412 */ 413 error = bus_dmamap_create(sc->sc_dmat, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, 414 BUS_DMA_NOWAIT, &sc->rbd_map); 415 if (error != 0) { 416 aprint_error_dev(&sc->sc_dev, "could not create rbd dma map\n"); 417 goto fail; 418 } 419 420 error = bus_dmamem_alloc(sc->sc_dmat, IPW_RBD_SZ, PAGE_SIZE, 0, 421 &sc->rbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 422 if (error != 0) { 423 aprint_error_dev(&sc->sc_dev, "could not allocate rbd dma memory\n"); 424 goto fail; 425 } 426 427 error = bus_dmamem_map(sc->sc_dmat, &sc->rbd_seg, nsegs, IPW_RBD_SZ, 428 (void **)&sc->rbd_list, BUS_DMA_NOWAIT); 429 if (error != 0) { 430 aprint_error_dev(&sc->sc_dev, "could not map rbd dma memory\n"); 431 goto fail; 432 } 433 434 error = bus_dmamap_load(sc->sc_dmat, sc->rbd_map, sc->rbd_list, 435 IPW_RBD_SZ, NULL, BUS_DMA_NOWAIT); 436 if (error != 0) { 437 aprint_error_dev(&sc->sc_dev, "could not load rbd dma memory\n"); 438 goto fail; 439 } 440 441 (void)memset(sc->rbd_list, 0, IPW_RBD_SZ); 442 443 /* 444 * Allocate and map status ring. 445 */ 446 error = bus_dmamap_create(sc->sc_dmat, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 447 0, BUS_DMA_NOWAIT, &sc->status_map); 448 if (error != 0) { 449 aprint_error_dev(&sc->sc_dev, "could not create status dma map\n"); 450 goto fail; 451 } 452 453 error = bus_dmamem_alloc(sc->sc_dmat, IPW_STATUS_SZ, PAGE_SIZE, 0, 454 &sc->status_seg, 1, &nsegs, BUS_DMA_NOWAIT); 455 if (error != 0) { 456 aprint_error_dev(&sc->sc_dev, "could not allocate status dma memory\n"); 457 goto fail; 458 } 459 460 error = bus_dmamem_map(sc->sc_dmat, &sc->status_seg, nsegs, 461 IPW_STATUS_SZ, (void **)&sc->status_list, BUS_DMA_NOWAIT); 462 if (error != 0) { 463 aprint_error_dev(&sc->sc_dev, "could not map status dma memory\n"); 464 goto fail; 465 } 466 467 error = bus_dmamap_load(sc->sc_dmat, sc->status_map, sc->status_list, 468 IPW_STATUS_SZ, NULL, BUS_DMA_NOWAIT); 469 if (error != 0) { 470 aprint_error_dev(&sc->sc_dev, "could not load status dma memory\n"); 471 goto fail; 472 } 473 474 (void)memset(sc->status_list, 0, IPW_STATUS_SZ); 475 476 /* 477 * Allocate command DMA map. 478 */ 479 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_cmd), 480 1, sizeof (struct ipw_cmd), 0, BUS_DMA_NOWAIT, &sc->cmd_map); 481 if (error != 0) { 482 aprint_error_dev(&sc->sc_dev, "could not create cmd dma map\n"); 483 goto fail; 484 } 485 486 error = bus_dmamem_alloc(sc->sc_dmat, sizeof (struct ipw_cmd), 487 PAGE_SIZE, 0, &sc->cmd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 488 if (error != 0) { 489 aprint_error_dev(&sc->sc_dev, "could not allocate cmd dma memory\n"); 490 goto fail; 491 } 492 493 error = bus_dmamem_map(sc->sc_dmat, &sc->cmd_seg, nsegs, 494 sizeof (struct ipw_cmd), (void **)&sc->cmd, BUS_DMA_NOWAIT); 495 if (error != 0) { 496 aprint_error_dev(&sc->sc_dev, "could not map cmd dma memory\n"); 497 goto fail; 498 } 499 500 error = bus_dmamap_load(sc->sc_dmat, sc->cmd_map, &sc->cmd, 501 sizeof (struct ipw_cmd), NULL, BUS_DMA_NOWAIT); 502 if (error != 0) { 503 aprint_error_dev(&sc->sc_dev, "could not map cmd dma memory\n"); 504 return error; 505 } 506 507 /* 508 * Allocate and map hdr list. 509 */ 510 511 error = bus_dmamap_create(sc->sc_dmat, 512 IPW_NDATA * sizeof(struct ipw_hdr), 1, 513 sizeof(struct ipw_hdr), 0, BUS_DMA_NOWAIT, 514 &sc->hdr_map); 515 if (error != 0) { 516 aprint_error_dev(&sc->sc_dev, "could not create hdr dma map\n"); 517 goto fail; 518 } 519 520 error = bus_dmamem_alloc(sc->sc_dmat, 521 IPW_NDATA * sizeof(struct ipw_hdr), PAGE_SIZE, 0, &sc->hdr_seg, 522 1, &nsegs, BUS_DMA_NOWAIT); 523 if (error != 0) { 524 aprint_error_dev(&sc->sc_dev, "could not allocate hdr memory\n"); 525 goto fail; 526 } 527 528 error = bus_dmamem_map(sc->sc_dmat, &sc->hdr_seg, nsegs, 529 IPW_NDATA * sizeof(struct ipw_hdr), (void **)&sc->hdr_list, 530 BUS_DMA_NOWAIT); 531 if (error != 0) { 532 aprint_error_dev(&sc->sc_dev, "could not map hdr memory\n"); 533 goto fail; 534 } 535 536 error = bus_dmamap_load(sc->sc_dmat, sc->hdr_map, sc->hdr_list, 537 IPW_NDATA * sizeof(struct ipw_hdr), NULL, BUS_DMA_NOWAIT); 538 if (error != 0) { 539 aprint_error_dev(&sc->sc_dev, "could not load hdr memory\n"); 540 goto fail; 541 } 542 543 (void)memset(sc->hdr_list, 0, IPW_HDR_SZ); 544 545 /* 546 * Create DMA hdrs tailq. 547 */ 548 TAILQ_INIT(&sc->sc_free_shdr); 549 for (i = 0; i < IPW_NDATA; i++) { 550 shdr = &sc->shdr_list[i]; 551 shdr->hdr = sc->hdr_list + i; 552 shdr->offset = sizeof(struct ipw_hdr) * i; 553 shdr->addr = sc->hdr_map->dm_segs[0].ds_addr + shdr->offset; 554 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 555 } 556 557 /* 558 * Allocate tx buffers DMA maps. 559 */ 560 TAILQ_INIT(&sc->sc_free_sbuf); 561 for (i = 0; i < IPW_NDATA; i++) { 562 sbuf = &sc->tx_sbuf_list[i]; 563 564 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 565 IPW_MAX_NSEG, MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 566 if (error != 0) { 567 aprint_error_dev(&sc->sc_dev, "could not create txbuf dma map\n"); 568 goto fail; 569 } 570 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 571 } 572 573 /* 574 * Initialize tx ring. 575 */ 576 for (i = 0; i < IPW_NTBD; i++) { 577 sbd = &sc->stbd_list[i]; 578 sbd->bd = &sc->tbd_list[i]; 579 sbd->type = IPW_SBD_TYPE_NOASSOC; 580 } 581 582 /* 583 * Pre-allocate rx buffers and DMA maps 584 */ 585 for (i = 0; i < IPW_NRBD; i++) { 586 sbd = &sc->srbd_list[i]; 587 sbuf = &sc->rx_sbuf_list[i]; 588 sbd->bd = &sc->rbd_list[i]; 589 590 MGETHDR(sbuf->m, M_DONTWAIT, MT_DATA); 591 if (sbuf->m == NULL) { 592 aprint_error_dev(&sc->sc_dev, "could not allocate rx mbuf\n"); 593 error = ENOMEM; 594 goto fail; 595 } 596 597 MCLGET(sbuf->m, M_DONTWAIT); 598 if (!(sbuf->m->m_flags & M_EXT)) { 599 m_freem(sbuf->m); 600 aprint_error_dev(&sc->sc_dev, "could not allocate rx mbuf cluster\n"); 601 error = ENOMEM; 602 goto fail; 603 } 604 605 sbuf->m->m_pkthdr.len = sbuf->m->m_len = sbuf->m->m_ext.ext_size; 606 607 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 608 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sbuf->map); 609 if (error != 0) { 610 aprint_error_dev(&sc->sc_dev, "could not create rxbuf dma map\n"); 611 m_freem(sbuf->m); 612 goto fail; 613 } 614 615 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, 616 sbuf->m, BUS_DMA_READ | BUS_DMA_NOWAIT); 617 if (error != 0) { 618 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 619 m_freem(sbuf->m); 620 aprint_error_dev(&sc->sc_dev, "could not map rxbuf dma memory\n"); 621 goto fail; 622 } 623 624 sbd->type = IPW_SBD_TYPE_DATA; 625 sbd->priv = sbuf; 626 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 627 sbd->bd->len = htole32(MCLBYTES); 628 629 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, 630 sbuf->map->dm_mapsize, BUS_DMASYNC_PREREAD); 631 632 } 633 634 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 0, IPW_RBD_SZ, 635 BUS_DMASYNC_PREREAD); 636 637 return 0; 638 639 fail: ipw_release(sc); 640 return error; 641 } 642 643 static void 644 ipw_release(struct ipw_softc *sc) 645 { 646 struct ipw_soft_buf *sbuf; 647 int i; 648 649 if (sc->tbd_map != NULL) { 650 if (sc->tbd_list != NULL) { 651 bus_dmamap_unload(sc->sc_dmat, sc->tbd_map); 652 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->tbd_list, 653 IPW_TBD_SZ); 654 bus_dmamem_free(sc->sc_dmat, &sc->tbd_seg, 1); 655 } 656 bus_dmamap_destroy(sc->sc_dmat, sc->tbd_map); 657 } 658 659 if (sc->rbd_map != NULL) { 660 if (sc->rbd_list != NULL) { 661 bus_dmamap_unload(sc->sc_dmat, sc->rbd_map); 662 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->rbd_list, 663 IPW_RBD_SZ); 664 bus_dmamem_free(sc->sc_dmat, &sc->rbd_seg, 1); 665 } 666 bus_dmamap_destroy(sc->sc_dmat, sc->rbd_map); 667 } 668 669 if (sc->status_map != NULL) { 670 if (sc->status_list != NULL) { 671 bus_dmamap_unload(sc->sc_dmat, sc->status_map); 672 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->status_list, 673 IPW_RBD_SZ); 674 bus_dmamem_free(sc->sc_dmat, &sc->status_seg, 1); 675 } 676 bus_dmamap_destroy(sc->sc_dmat, sc->status_map); 677 } 678 679 for (i = 0; i < IPW_NTBD; i++) 680 ipw_release_sbd(sc, &sc->stbd_list[i]); 681 682 if (sc->cmd_map != NULL) 683 bus_dmamap_destroy(sc->sc_dmat, sc->cmd_map); 684 685 if (sc->hdr_list != NULL) { 686 bus_dmamap_unload(sc->sc_dmat, sc->hdr_map); 687 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->hdr_list, 688 IPW_NDATA * sizeof(struct ipw_hdr)); 689 } 690 if (sc->hdr_map != NULL) { 691 bus_dmamem_free(sc->sc_dmat, &sc->hdr_seg, 1); 692 bus_dmamap_destroy(sc->sc_dmat, sc->hdr_map); 693 } 694 695 for (i = 0; i < IPW_NDATA; i++) 696 bus_dmamap_destroy(sc->sc_dmat, sc->tx_sbuf_list[i].map); 697 698 for (i = 0; i < IPW_NRBD; i++) { 699 sbuf = &sc->rx_sbuf_list[i]; 700 if (sbuf->map != NULL) { 701 if (sbuf->m != NULL) { 702 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 703 m_freem(sbuf->m); 704 } 705 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 706 } 707 } 708 709 } 710 711 static int 712 ipw_media_change(struct ifnet *ifp) 713 { 714 int error; 715 716 error = ieee80211_media_change(ifp); 717 if (error != ENETRESET) 718 return error; 719 720 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 721 ipw_init(ifp); 722 723 return 0; 724 } 725 726 /* 727 * The firmware automatically adapts the transmit speed. We report the current 728 * transmit speed here. 729 */ 730 static void 731 ipw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 732 { 733 #define N(a) (sizeof (a) / sizeof (a[0])) 734 struct ipw_softc *sc = ifp->if_softc; 735 struct ieee80211com *ic = &sc->sc_ic; 736 static const struct { 737 uint32_t val; 738 int rate; 739 } rates[] = { 740 { IPW_RATE_DS1, 2 }, 741 { IPW_RATE_DS2, 4 }, 742 { IPW_RATE_DS5, 11 }, 743 { IPW_RATE_DS11, 22 }, 744 }; 745 uint32_t val; 746 int rate, i; 747 748 imr->ifm_status = IFM_AVALID; 749 imr->ifm_active = IFM_IEEE80211; 750 if (ic->ic_state == IEEE80211_S_RUN) 751 imr->ifm_status |= IFM_ACTIVE; 752 753 /* read current transmission rate from adapter */ 754 val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE) & 0xf; 755 756 /* convert ipw rate to 802.11 rate */ 757 for (i = 0; i < N(rates) && rates[i].val != val; i++); 758 rate = (i < N(rates)) ? rates[i].rate : 0; 759 760 imr->ifm_active |= IFM_IEEE80211_11B; 761 imr->ifm_active |= ieee80211_rate2media(ic, rate, IEEE80211_MODE_11B); 762 switch (ic->ic_opmode) { 763 case IEEE80211_M_STA: 764 break; 765 766 case IEEE80211_M_IBSS: 767 imr->ifm_active |= IFM_IEEE80211_ADHOC; 768 break; 769 770 case IEEE80211_M_MONITOR: 771 imr->ifm_active |= IFM_IEEE80211_MONITOR; 772 break; 773 774 case IEEE80211_M_AHDEMO: 775 case IEEE80211_M_HOSTAP: 776 /* should not get there */ 777 break; 778 } 779 #undef N 780 } 781 782 static int 783 ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, 784 int arg) 785 { 786 struct ifnet *ifp = ic->ic_ifp; 787 struct ipw_softc *sc = ifp->if_softc; 788 struct ieee80211_node *ni; 789 uint8_t macaddr[IEEE80211_ADDR_LEN]; 790 uint32_t len; 791 struct ipw_rx_radiotap_header *wr = &sc->sc_rxtap; 792 struct ipw_tx_radiotap_header *wt = &sc->sc_txtap; 793 794 switch (nstate) { 795 case IEEE80211_S_INIT: 796 break; 797 default: 798 KASSERT(ic->ic_curchan != IEEE80211_CHAN_ANYC); 799 KASSERT(ic->ic_curchan != NULL); 800 wt->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 801 wt->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 802 wr->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 803 wr->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 804 break; 805 } 806 807 switch (nstate) { 808 case IEEE80211_S_RUN: 809 DELAY(200); /* firmware needs a short delay here */ 810 811 len = IEEE80211_ADDR_LEN; 812 ipw_read_table2(sc, IPW_INFO_CURRENT_BSSID, macaddr, &len); 813 814 ni = ieee80211_find_node(&ic->ic_scan, macaddr); 815 if (ni == NULL) 816 break; 817 818 ieee80211_ref_node(ni); 819 ieee80211_sta_join(ic, ni); 820 ieee80211_node_authorize(ni); 821 822 if (ic->ic_opmode == IEEE80211_M_STA) 823 ieee80211_notify_node_join(ic, ni, 1); 824 break; 825 826 case IEEE80211_S_INIT: 827 case IEEE80211_S_SCAN: 828 case IEEE80211_S_AUTH: 829 case IEEE80211_S_ASSOC: 830 break; 831 } 832 833 ic->ic_state = nstate; 834 return 0; 835 } 836 837 /* 838 * Read 16 bits at address 'addr' from the serial EEPROM. 839 */ 840 static uint16_t 841 ipw_read_prom_word(struct ipw_softc *sc, uint8_t addr) 842 { 843 uint32_t tmp; 844 uint16_t val; 845 int n; 846 847 /* clock C once before the first command */ 848 IPW_EEPROM_CTL(sc, 0); 849 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 850 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 851 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 852 853 /* write start bit (1) */ 854 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 855 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 856 857 /* write READ opcode (10) */ 858 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 859 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 860 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 861 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 862 863 /* write address A7-A0 */ 864 for (n = 7; n >= 0; n--) { 865 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 866 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D)); 867 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 868 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D) | IPW_EEPROM_C); 869 } 870 871 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 872 873 /* read data Q15-Q0 */ 874 val = 0; 875 for (n = 15; n >= 0; n--) { 876 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 877 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 878 tmp = MEM_READ_4(sc, IPW_MEM_EEPROM_CTL); 879 val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n; 880 } 881 882 IPW_EEPROM_CTL(sc, 0); 883 884 /* clear Chip Select and clock C */ 885 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 886 IPW_EEPROM_CTL(sc, 0); 887 IPW_EEPROM_CTL(sc, IPW_EEPROM_C); 888 889 return le16toh(val); 890 } 891 892 static void 893 ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 894 { 895 struct ipw_cmd *cmd; 896 897 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof (struct ipw_cmd), 898 BUS_DMASYNC_POSTREAD); 899 900 cmd = mtod(sbuf->m, struct ipw_cmd *); 901 902 DPRINTFN(2, ("cmd ack'ed (%u, %u, %u, %u, %u)\n", le32toh(cmd->type), 903 le32toh(cmd->subtype), le32toh(cmd->seq), le32toh(cmd->len), 904 le32toh(cmd->status))); 905 906 wakeup(&sc->cmd); 907 } 908 909 static void 910 ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 911 { 912 struct ieee80211com *ic = &sc->sc_ic; 913 struct ifnet *ifp = sc->sc_ic.ic_ifp; 914 uint32_t state; 915 916 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof state, 917 BUS_DMASYNC_POSTREAD); 918 919 state = le32toh(*mtod(sbuf->m, uint32_t *)); 920 921 DPRINTFN(2, ("entering state %u\n", state)); 922 923 switch (state) { 924 case IPW_STATE_ASSOCIATED: 925 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 926 break; 927 928 case IPW_STATE_SCANNING: 929 /* don't leave run state on background scan */ 930 if (ic->ic_state != IEEE80211_S_RUN) 931 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 932 933 ic->ic_flags |= IEEE80211_F_SCAN; 934 break; 935 936 case IPW_STATE_SCAN_COMPLETE: 937 ieee80211_notify_scan_done(ic); 938 ic->ic_flags &= ~IEEE80211_F_SCAN; 939 break; 940 941 case IPW_STATE_ASSOCIATION_LOST: 942 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 943 break; 944 945 case IPW_STATE_RADIO_DISABLED: 946 ic->ic_ifp->if_flags &= ~IFF_UP; 947 ipw_stop(ifp, 1); 948 break; 949 } 950 } 951 952 /* 953 * XXX: Hack to set the current channel to the value advertised in beacons or 954 * probe responses. Only used during AP detection. 955 */ 956 static void 957 ipw_fix_channel(struct ieee80211com *ic, struct mbuf *m) 958 { 959 struct ieee80211_frame *wh; 960 uint8_t subtype; 961 uint8_t *frm, *efrm; 962 963 wh = mtod(m, struct ieee80211_frame *); 964 965 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_MGT) 966 return; 967 968 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 969 970 if (subtype != IEEE80211_FC0_SUBTYPE_BEACON && 971 subtype != IEEE80211_FC0_SUBTYPE_PROBE_RESP) 972 return; 973 974 frm = (uint8_t *)(wh + 1); 975 efrm = mtod(m, uint8_t *) + m->m_len; 976 977 frm += 12; /* skip tstamp, bintval and capinfo fields */ 978 while (frm < efrm) { 979 if (*frm == IEEE80211_ELEMID_DSPARMS) 980 #if IEEE80211_CHAN_MAX < 255 981 if (frm[2] <= IEEE80211_CHAN_MAX) 982 #endif 983 ic->ic_curchan = &ic->ic_channels[frm[2]]; 984 985 frm += frm[1] + 2; 986 } 987 } 988 989 static void 990 ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 991 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 992 { 993 struct ieee80211com *ic = &sc->sc_ic; 994 struct ifnet *ifp = &sc->sc_if; 995 struct mbuf *mnew, *m; 996 struct ieee80211_frame *wh; 997 struct ieee80211_node *ni; 998 int error; 999 1000 DPRINTFN(5, ("received frame len=%u, rssi=%u\n", le32toh(status->len), 1001 status->rssi)); 1002 1003 if (le32toh(status->len) < sizeof (struct ieee80211_frame_min) || 1004 le32toh(status->len) > MCLBYTES) 1005 return; 1006 1007 /* 1008 * Try to allocate a new mbuf for this ring element and load it before 1009 * processing the current mbuf. If the ring element cannot be loaded, 1010 * drop the received packet and reuse the old mbuf. In the unlikely 1011 * case that the old mbuf can't be reloaded either, explicitly panic. 1012 */ 1013 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1014 if (mnew == NULL) { 1015 aprint_error_dev(&sc->sc_dev, "could not allocate rx mbuf\n"); 1016 ifp->if_ierrors++; 1017 return; 1018 } 1019 1020 MCLGET(mnew, M_DONTWAIT); 1021 if (!(mnew->m_flags & M_EXT)) { 1022 aprint_error_dev(&sc->sc_dev, "could not allocate rx mbuf cluster\n"); 1023 m_freem(mnew); 1024 ifp->if_ierrors++; 1025 return; 1026 } 1027 1028 mnew->m_pkthdr.len = mnew->m_len = mnew->m_ext.ext_size; 1029 1030 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, le32toh(status->len), 1031 BUS_DMASYNC_POSTREAD); 1032 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1033 1034 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, mnew, 1035 BUS_DMA_READ | BUS_DMA_NOWAIT); 1036 if (error != 0) { 1037 aprint_error_dev(&sc->sc_dev, "could not load rx buf DMA map\n"); 1038 m_freem(mnew); 1039 1040 /* try to reload the old mbuf */ 1041 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, 1042 sbuf->m, BUS_DMA_READ | BUS_DMA_NOWAIT); 1043 if (error != 0) { 1044 /* very unlikely that it will fail... */ 1045 panic("%s: unable to remap rx buf", 1046 device_xname(&sc->sc_dev)); 1047 } 1048 ifp->if_ierrors++; 1049 return; 1050 } 1051 1052 /* 1053 * New mbuf successfully loaded, update Rx ring and continue 1054 * processing. 1055 */ 1056 m = sbuf->m; 1057 sbuf->m = mnew; 1058 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 1059 1060 /* finalize mbuf */ 1061 m->m_pkthdr.rcvif = ifp; 1062 m->m_pkthdr.len = m->m_len = le32toh(status->len); 1063 1064 #if NBPFILTER > 0 1065 if (sc->sc_drvbpf != NULL) { 1066 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 1067 1068 tap->wr_antsignal = status->rssi; 1069 1070 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 1071 } 1072 #endif 1073 1074 if (ic->ic_state == IEEE80211_S_SCAN) 1075 ipw_fix_channel(ic, m); 1076 1077 wh = mtod(m, struct ieee80211_frame *); 1078 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 1079 1080 /* send the frame to the 802.11 layer */ 1081 ieee80211_input(ic, m, ni, status->rssi, 0); 1082 1083 /* node is no longer needed */ 1084 ieee80211_free_node(ni); 1085 1086 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, 1087 sbuf->map->dm_mapsize, BUS_DMASYNC_PREREAD); 1088 } 1089 1090 static void 1091 ipw_rx_intr(struct ipw_softc *sc) 1092 { 1093 struct ipw_status *status; 1094 struct ipw_soft_bd *sbd; 1095 struct ipw_soft_buf *sbuf; 1096 uint32_t r, i; 1097 1098 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1099 return; 1100 1101 r = CSR_READ_4(sc, IPW_CSR_RX_READ); 1102 1103 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 1104 1105 /* firmware was killed, stop processing received frames */ 1106 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1107 return; 1108 1109 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 1110 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1111 BUS_DMASYNC_POSTREAD); 1112 1113 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 1114 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 1115 BUS_DMASYNC_POSTREAD); 1116 1117 status = &sc->status_list[i]; 1118 sbd = &sc->srbd_list[i]; 1119 sbuf = sbd->priv; 1120 1121 switch (le16toh(status->code) & 0xf) { 1122 case IPW_STATUS_CODE_COMMAND: 1123 ipw_command_intr(sc, sbuf); 1124 break; 1125 1126 case IPW_STATUS_CODE_NEWSTATE: 1127 ipw_newstate_intr(sc, sbuf); 1128 break; 1129 1130 case IPW_STATUS_CODE_DATA_802_3: 1131 case IPW_STATUS_CODE_DATA_802_11: 1132 ipw_data_intr(sc, status, sbd, sbuf); 1133 break; 1134 1135 case IPW_STATUS_CODE_NOTIFICATION: 1136 DPRINTFN(2, ("received notification\n")); 1137 break; 1138 1139 default: 1140 aprint_error_dev(&sc->sc_dev, "unknown status code %u\n", 1141 le16toh(status->code)); 1142 } 1143 1144 sbd->bd->flags = 0; 1145 1146 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 1147 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1148 BUS_DMASYNC_PREREAD); 1149 1150 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 1151 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 1152 BUS_DMASYNC_PREREAD); 1153 } 1154 1155 /* Tell the firmware what we have processed */ 1156 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 1157 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 1158 } 1159 1160 static void 1161 ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 1162 { 1163 struct ieee80211com *ic; 1164 struct ipw_soft_hdr *shdr; 1165 struct ipw_soft_buf *sbuf; 1166 1167 switch (sbd->type) { 1168 case IPW_SBD_TYPE_COMMAND: 1169 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 1170 0, sizeof(struct ipw_cmd), BUS_DMASYNC_POSTWRITE); 1171 /* bus_dmamap_unload(sc->sc_dmat, sc->cmd_map); */ 1172 break; 1173 1174 case IPW_SBD_TYPE_HEADER: 1175 shdr = sbd->priv; 1176 bus_dmamap_sync(sc->sc_dmat, sc->hdr_map, 1177 shdr->offset, sizeof(struct ipw_hdr), BUS_DMASYNC_POSTWRITE); 1178 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 1179 break; 1180 1181 case IPW_SBD_TYPE_DATA: 1182 ic = &sc->sc_ic; 1183 sbuf = sbd->priv; 1184 1185 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 1186 0, MCLBYTES, BUS_DMASYNC_POSTWRITE); 1187 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1188 m_freem(sbuf->m); 1189 if (sbuf->ni != NULL) 1190 ieee80211_free_node(sbuf->ni); 1191 /* kill watchdog timer */ 1192 sc->sc_tx_timer = 0; 1193 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 1194 break; 1195 } 1196 sbd->type = IPW_SBD_TYPE_NOASSOC; 1197 } 1198 1199 static void 1200 ipw_tx_intr(struct ipw_softc *sc) 1201 { 1202 struct ifnet *ifp = &sc->sc_if; 1203 struct ipw_soft_bd *sbd; 1204 uint32_t r, i; 1205 1206 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1207 return; 1208 1209 r = CSR_READ_4(sc, IPW_CSR_TX_READ); 1210 1211 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) { 1212 sbd = &sc->stbd_list[i]; 1213 1214 if (sbd->type == IPW_SBD_TYPE_DATA) 1215 ifp->if_opackets++; 1216 1217 ipw_release_sbd(sc, sbd); 1218 sc->txfree++; 1219 } 1220 1221 /* remember what the firmware has processed */ 1222 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 1223 1224 /* Call start() since some buffer descriptors have been released */ 1225 ifp->if_flags &= ~IFF_OACTIVE; 1226 (*ifp->if_start)(ifp); 1227 } 1228 1229 static int 1230 ipw_intr(void *arg) 1231 { 1232 struct ipw_softc *sc = arg; 1233 uint32_t r; 1234 1235 r = CSR_READ_4(sc, IPW_CSR_INTR); 1236 if (r == 0 || r == 0xffffffff) 1237 return 0; 1238 1239 /* Disable interrupts */ 1240 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1241 1242 if (r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR)) { 1243 aprint_error_dev(&sc->sc_dev, "fatal error\n"); 1244 sc->sc_ic.ic_ifp->if_flags &= ~IFF_UP; 1245 ipw_stop(&sc->sc_if, 1); 1246 } 1247 1248 if (r & IPW_INTR_FW_INIT_DONE) { 1249 if (!(r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR))) 1250 wakeup(sc); 1251 } 1252 1253 if (r & IPW_INTR_RX_TRANSFER) 1254 ipw_rx_intr(sc); 1255 1256 if (r & IPW_INTR_TX_TRANSFER) 1257 ipw_tx_intr(sc); 1258 1259 /* Acknowledge all interrupts */ 1260 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 1261 1262 /* Re-enable interrupts */ 1263 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1264 1265 return 0; 1266 } 1267 1268 /* 1269 * Send a command to the firmware and wait for the acknowledgement. 1270 */ 1271 static int 1272 ipw_cmd(struct ipw_softc *sc, uint32_t type, void *data, uint32_t len) 1273 { 1274 struct ipw_soft_bd *sbd; 1275 1276 sbd = &sc->stbd_list[sc->txcur]; 1277 1278 sc->cmd.type = htole32(type); 1279 sc->cmd.subtype = 0; 1280 sc->cmd.len = htole32(len); 1281 sc->cmd.seq = 0; 1282 1283 (void)memcpy(sc->cmd.data, data, len); 1284 1285 sbd->type = IPW_SBD_TYPE_COMMAND; 1286 sbd->bd->physaddr = htole32(sc->cmd_map->dm_segs[0].ds_addr); 1287 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 1288 sbd->bd->nfrag = 1; 1289 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 1290 IPW_BD_FLAG_TX_LAST_FRAGMENT; 1291 1292 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 0, sizeof (struct ipw_cmd), 1293 BUS_DMASYNC_PREWRITE); 1294 1295 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1296 sc->txcur * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1297 BUS_DMASYNC_PREWRITE); 1298 1299 DPRINTFN(2, ("sending command (%u, %u, %u, %u)\n", type, 0, 0, len)); 1300 1301 /* kick firmware */ 1302 sc->txfree--; 1303 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1304 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1305 1306 /* Wait at most one second for command to complete */ 1307 return tsleep(&sc->cmd, 0, "ipwcmd", hz); 1308 } 1309 1310 static int 1311 ipw_tx_start(struct ifnet *ifp, struct mbuf *m0, struct ieee80211_node *ni) 1312 { 1313 struct ipw_softc *sc = ifp->if_softc; 1314 struct ieee80211com *ic = &sc->sc_ic; 1315 struct ieee80211_frame *wh; 1316 struct ipw_soft_bd *sbd; 1317 struct ipw_soft_hdr *shdr; 1318 struct ipw_soft_buf *sbuf; 1319 struct ieee80211_key *k; 1320 struct mbuf *mnew; 1321 int error, i; 1322 1323 wh = mtod(m0, struct ieee80211_frame *); 1324 1325 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1326 k = ieee80211_crypto_encap(ic, ni, m0); 1327 if (k == NULL) { 1328 m_freem(m0); 1329 return ENOBUFS; 1330 } 1331 1332 /* packet header may have moved, reset our local pointer */ 1333 wh = mtod(m0, struct ieee80211_frame *); 1334 } 1335 1336 #if NBPFILTER > 0 1337 if (sc->sc_drvbpf != NULL) { 1338 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 1339 1340 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 1341 } 1342 #endif 1343 1344 shdr = TAILQ_FIRST(&sc->sc_free_shdr); 1345 sbuf = TAILQ_FIRST(&sc->sc_free_sbuf); 1346 KASSERT(shdr != NULL && sbuf != NULL); 1347 1348 shdr->hdr->type = htole32(IPW_HDR_TYPE_SEND); 1349 shdr->hdr->subtype = 0; 1350 shdr->hdr->encrypted = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0; 1351 shdr->hdr->encrypt = 0; 1352 shdr->hdr->keyidx = 0; 1353 shdr->hdr->keysz = 0; 1354 shdr->hdr->fragmentsz = 0; 1355 IEEE80211_ADDR_COPY(shdr->hdr->src_addr, wh->i_addr2); 1356 if (ic->ic_opmode == IEEE80211_M_STA) 1357 IEEE80211_ADDR_COPY(shdr->hdr->dst_addr, wh->i_addr3); 1358 else 1359 IEEE80211_ADDR_COPY(shdr->hdr->dst_addr, wh->i_addr1); 1360 1361 /* trim IEEE802.11 header */ 1362 m_adj(m0, sizeof (struct ieee80211_frame)); 1363 1364 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m0, BUS_DMA_NOWAIT); 1365 if (error != 0 && error != EFBIG) { 1366 aprint_error_dev(&sc->sc_dev, "could not map mbuf (error %d)\n", 1367 error); 1368 m_freem(m0); 1369 return error; 1370 } 1371 1372 if (error != 0) { 1373 /* too many fragments, linearize */ 1374 1375 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1376 if (mnew == NULL) { 1377 m_freem(m0); 1378 return ENOMEM; 1379 } 1380 1381 M_COPY_PKTHDR(mnew, m0); 1382 1383 /* If the data won't fit in the header, get a cluster */ 1384 if (m0->m_pkthdr.len > MHLEN) { 1385 MCLGET(mnew, M_DONTWAIT); 1386 if (!(mnew->m_flags & M_EXT)) { 1387 m_freem(m0); 1388 m_freem(mnew); 1389 return ENOMEM; 1390 } 1391 } 1392 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(mnew, void *)); 1393 m_freem(m0); 1394 mnew->m_len = mnew->m_pkthdr.len; 1395 m0 = mnew; 1396 1397 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m0, 1398 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1399 if (error != 0) { 1400 aprint_error_dev(&sc->sc_dev, "could not map mbuf (error %d)\n", error); 1401 m_freem(m0); 1402 return error; 1403 } 1404 } 1405 1406 TAILQ_REMOVE(&sc->sc_free_sbuf, sbuf, next); 1407 TAILQ_REMOVE(&sc->sc_free_shdr, shdr, next); 1408 1409 sbd = &sc->stbd_list[sc->txcur]; 1410 sbd->type = IPW_SBD_TYPE_HEADER; 1411 sbd->priv = shdr; 1412 sbd->bd->physaddr = htole32(shdr->addr); 1413 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 1414 sbd->bd->nfrag = 1 + sbuf->map->dm_nsegs; 1415 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 1416 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1417 1418 DPRINTFN(5, ("sending tx hdr (%u, %u, %u, %u, )\n", 1419 shdr->hdr->type, shdr->hdr->subtype, shdr->hdr->encrypted, 1420 shdr->hdr->encrypt)); 1421 DPRINTFN(5, ("%s->", ether_sprintf(shdr->hdr->src_addr))); 1422 DPRINTFN(5, ("%s\n", ether_sprintf(shdr->hdr->dst_addr))); 1423 1424 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1425 sc->txcur * sizeof (struct ipw_bd), 1426 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1427 1428 sc->txfree--; 1429 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1430 1431 sbuf->m = m0; 1432 sbuf->ni = ni; 1433 1434 for (i = 0; i < sbuf->map->dm_nsegs; i++) { 1435 sbd = &sc->stbd_list[sc->txcur]; 1436 1437 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[i].ds_addr); 1438 sbd->bd->len = htole32(sbuf->map->dm_segs[i].ds_len); 1439 sbd->bd->nfrag = 0; 1440 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 1441 if (i == sbuf->map->dm_nsegs - 1) { 1442 sbd->type = IPW_SBD_TYPE_DATA; 1443 sbd->priv = sbuf; 1444 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 1445 } else { 1446 sbd->type = IPW_SBD_TYPE_NOASSOC; 1447 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1448 } 1449 1450 DPRINTFN(5, ("sending fragment (%d, %d)\n", i, 1451 (int)sbuf->map->dm_segs[i].ds_len)); 1452 1453 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1454 sc->txcur * sizeof (struct ipw_bd), 1455 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1456 1457 sc->txfree--; 1458 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1459 } 1460 1461 bus_dmamap_sync(sc->sc_dmat, sc->hdr_map, shdr->offset, 1462 sizeof (struct ipw_hdr), BUS_DMASYNC_PREWRITE); 1463 1464 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, MCLBYTES, 1465 BUS_DMASYNC_PREWRITE); 1466 1467 /* Inform firmware about this new packet */ 1468 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1469 1470 return 0; 1471 } 1472 1473 static void 1474 ipw_start(struct ifnet *ifp) 1475 { 1476 struct ipw_softc *sc = ifp->if_softc; 1477 struct ieee80211com *ic = &sc->sc_ic; 1478 struct mbuf *m0; 1479 struct ether_header *eh; 1480 struct ieee80211_node *ni; 1481 1482 1483 if (ic->ic_state != IEEE80211_S_RUN) 1484 return; 1485 1486 for (;;) { 1487 IF_DEQUEUE(&ifp->if_snd, m0); 1488 if (m0 == NULL) 1489 break; 1490 1491 if (sc->txfree < 1 + IPW_MAX_NSEG) { 1492 IF_PREPEND(&ifp->if_snd, m0); 1493 ifp->if_flags |= IFF_OACTIVE; 1494 break; 1495 } 1496 1497 if (m0->m_len < sizeof (struct ether_header) && 1498 (m0 = m_pullup(m0, sizeof (struct ether_header))) == NULL) 1499 continue; 1500 1501 eh = mtod(m0, struct ether_header *); 1502 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1503 if (ni == NULL) { 1504 m_freem(m0); 1505 continue; 1506 } 1507 1508 #if NBPFILTER > 0 1509 if (ifp->if_bpf != NULL) 1510 bpf_mtap(ifp->if_bpf, m0); 1511 #endif 1512 1513 m0 = ieee80211_encap(ic, m0, ni); 1514 if (m0 == NULL) { 1515 ieee80211_free_node(ni); 1516 continue; 1517 } 1518 1519 #if NBPFILTER > 0 1520 if (ic->ic_rawbpf != NULL) 1521 bpf_mtap(ic->ic_rawbpf, m0); 1522 #endif 1523 1524 if (ipw_tx_start(ifp, m0, ni) != 0) { 1525 ieee80211_free_node(ni); 1526 ifp->if_oerrors++; 1527 break; 1528 } 1529 1530 /* start watchdog timer */ 1531 sc->sc_tx_timer = 5; 1532 ifp->if_timer = 1; 1533 } 1534 } 1535 1536 static void 1537 ipw_watchdog(struct ifnet *ifp) 1538 { 1539 struct ipw_softc *sc = ifp->if_softc; 1540 1541 ifp->if_timer = 0; 1542 1543 if (sc->sc_tx_timer > 0) { 1544 if (--sc->sc_tx_timer == 0) { 1545 aprint_error_dev(&sc->sc_dev, "device timeout\n"); 1546 ifp->if_oerrors++; 1547 ifp->if_flags &= ~IFF_UP; 1548 ipw_stop(ifp, 1); 1549 return; 1550 } 1551 ifp->if_timer = 1; 1552 } 1553 1554 ieee80211_watchdog(&sc->sc_ic); 1555 } 1556 1557 static int 1558 ipw_get_table1(struct ipw_softc *sc, uint32_t *tbl) 1559 { 1560 uint32_t addr, size, i; 1561 1562 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1563 return ENOTTY; 1564 1565 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, sc->table1_base); 1566 1567 size = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 1568 if (suword(tbl, size) != 0) 1569 return EFAULT; 1570 1571 for (i = 1, ++tbl; i < size; i++, tbl++) { 1572 addr = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 1573 if (suword(tbl, MEM_READ_4(sc, addr)) != 0) 1574 return EFAULT; 1575 } 1576 return 0; 1577 } 1578 1579 static int 1580 ipw_get_radio(struct ipw_softc *sc, int *ret) 1581 { 1582 uint32_t addr; 1583 1584 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1585 return ENOTTY; 1586 1587 addr = ipw_read_table1(sc, IPW_INFO_EEPROM_ADDRESS); 1588 if ((MEM_READ_4(sc, addr + 32) >> 24) & 1) { 1589 suword(ret, -1); 1590 return 0; 1591 } 1592 1593 if (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED) 1594 suword(ret, 0); 1595 else 1596 suword(ret, 1); 1597 1598 return 0; 1599 } 1600 1601 static int 1602 ipw_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1603 { 1604 #define IS_RUNNING(ifp) \ 1605 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 1606 1607 struct ipw_softc *sc = ifp->if_softc; 1608 struct ieee80211com *ic = &sc->sc_ic; 1609 struct ifreq *ifr = (struct ifreq *)data; 1610 int s, error = 0; 1611 1612 s = splnet(); 1613 1614 switch (cmd) { 1615 case SIOCSIFFLAGS: 1616 if (ifp->if_flags & IFF_UP) { 1617 if (!(ifp->if_flags & IFF_RUNNING)) 1618 ipw_init(ifp); 1619 } else { 1620 if (ifp->if_flags & IFF_RUNNING) 1621 ipw_stop(ifp, 1); 1622 } 1623 break; 1624 1625 case SIOCADDMULTI: 1626 case SIOCDELMULTI: 1627 /* XXX no h/w multicast filter? --dyoung */ 1628 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1629 /* setup multicast filter, etc */ 1630 error = 0; 1631 } 1632 break; 1633 1634 case SIOCGTABLE1: 1635 error = ipw_get_table1(sc, (uint32_t *)ifr->ifr_data); 1636 break; 1637 1638 case SIOCGRADIO: 1639 error = ipw_get_radio(sc, (int *)ifr->ifr_data); 1640 break; 1641 1642 case SIOCSIFMEDIA: 1643 if (ifr->ifr_media & IFM_IEEE80211_ADHOC) 1644 strlcpy(sc->sc_fwname, "ipw2100-1.2-i.fw", 1645 sizeof(sc->sc_fwname)); 1646 else if (ifr->ifr_media & IFM_IEEE80211_MONITOR) 1647 strlcpy(sc->sc_fwname, "ipw2100-1.2-p.fw", 1648 sizeof(sc->sc_fwname)); 1649 else 1650 strlcpy(sc->sc_fwname, "ipw2100-1.2.fw", 1651 sizeof(sc->sc_fwname)); 1652 1653 ipw_free_firmware(sc); 1654 /* FALLTRHOUGH */ 1655 default: 1656 error = ieee80211_ioctl(&sc->sc_ic, cmd, data); 1657 if (error != ENETRESET) 1658 break; 1659 1660 if (error == ENETRESET) { 1661 if (IS_RUNNING(ifp) && 1662 (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)) 1663 ipw_init(ifp); 1664 error = 0; 1665 } 1666 1667 } 1668 1669 splx(s); 1670 return error; 1671 #undef IS_RUNNING 1672 } 1673 1674 static uint32_t 1675 ipw_read_table1(struct ipw_softc *sc, uint32_t off) 1676 { 1677 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 1678 } 1679 1680 static void 1681 ipw_write_table1(struct ipw_softc *sc, uint32_t off, uint32_t info) 1682 { 1683 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 1684 } 1685 1686 static int 1687 ipw_read_table2(struct ipw_softc *sc, uint32_t off, void *buf, uint32_t *len) 1688 { 1689 uint32_t addr, info; 1690 uint16_t count, size; 1691 uint32_t total; 1692 1693 /* addr[4] + count[2] + size[2] */ 1694 addr = MEM_READ_4(sc, sc->table2_base + off); 1695 info = MEM_READ_4(sc, sc->table2_base + off + 4); 1696 1697 count = info >> 16; 1698 size = info & 0xffff; 1699 total = count * size; 1700 1701 if (total > *len) { 1702 *len = total; 1703 return EINVAL; 1704 } 1705 1706 *len = total; 1707 ipw_read_mem_1(sc, addr, buf, total); 1708 1709 return 0; 1710 } 1711 1712 static void 1713 ipw_stop_master(struct ipw_softc *sc) 1714 { 1715 int ntries; 1716 1717 /* disable interrupts */ 1718 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1719 1720 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1721 for (ntries = 0; ntries < 50; ntries++) { 1722 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1723 break; 1724 DELAY(10); 1725 } 1726 if (ntries == 50) 1727 aprint_error_dev(&sc->sc_dev, "timeout waiting for master\n"); 1728 1729 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1730 IPW_RST_PRINCETON_RESET); 1731 1732 sc->flags &= ~IPW_FLAG_FW_INITED; 1733 } 1734 1735 static int 1736 ipw_reset(struct ipw_softc *sc) 1737 { 1738 int ntries; 1739 1740 ipw_stop_master(sc); 1741 1742 /* move adapter to D0 state */ 1743 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1744 IPW_CTL_INIT); 1745 1746 /* wait for clock stabilization */ 1747 for (ntries = 0; ntries < 1000; ntries++) { 1748 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY) 1749 break; 1750 DELAY(200); 1751 } 1752 if (ntries == 1000) 1753 return EIO; 1754 1755 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1756 IPW_RST_SW_RESET); 1757 1758 DELAY(10); 1759 1760 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1761 IPW_CTL_INIT); 1762 1763 return 0; 1764 } 1765 1766 /* 1767 * Upload the microcode to the device. 1768 */ 1769 static int 1770 ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size) 1771 { 1772 int ntries; 1773 1774 MEM_WRITE_4(sc, 0x3000e0, 0x80000000); 1775 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1776 1777 MEM_WRITE_2(sc, 0x220000, 0x0703); 1778 MEM_WRITE_2(sc, 0x220000, 0x0707); 1779 1780 MEM_WRITE_1(sc, 0x210014, 0x72); 1781 MEM_WRITE_1(sc, 0x210014, 0x72); 1782 1783 MEM_WRITE_1(sc, 0x210000, 0x40); 1784 MEM_WRITE_1(sc, 0x210000, 0x00); 1785 MEM_WRITE_1(sc, 0x210000, 0x40); 1786 1787 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1788 1789 MEM_WRITE_1(sc, 0x210000, 0x00); 1790 MEM_WRITE_1(sc, 0x210000, 0x00); 1791 MEM_WRITE_1(sc, 0x210000, 0x80); 1792 1793 MEM_WRITE_2(sc, 0x220000, 0x0703); 1794 MEM_WRITE_2(sc, 0x220000, 0x0707); 1795 1796 MEM_WRITE_1(sc, 0x210014, 0x72); 1797 MEM_WRITE_1(sc, 0x210014, 0x72); 1798 1799 MEM_WRITE_1(sc, 0x210000, 0x00); 1800 MEM_WRITE_1(sc, 0x210000, 0x80); 1801 1802 for (ntries = 0; ntries < 10; ntries++) { 1803 if (MEM_READ_1(sc, 0x210000) & 1) 1804 break; 1805 DELAY(10); 1806 } 1807 if (ntries == 10) { 1808 aprint_error_dev(&sc->sc_dev, "timeout waiting for ucode to initialize\n"); 1809 return EIO; 1810 } 1811 1812 MEM_WRITE_4(sc, 0x3000e0, 0); 1813 1814 return 0; 1815 } 1816 1817 /* set of macros to handle unaligned little endian data in firmware image */ 1818 #define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1819 #define GETLE16(p) ((p)[0] | (p)[1] << 8) 1820 static int 1821 ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size) 1822 { 1823 u_char *p, *end; 1824 uint32_t dst; 1825 uint16_t len; 1826 int error; 1827 1828 p = fw; 1829 end = fw + size; 1830 while (p < end) { 1831 dst = GETLE32(p); p += 4; 1832 len = GETLE16(p); p += 2; 1833 1834 ipw_write_mem_1(sc, dst, p, len); 1835 p += len; 1836 } 1837 1838 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1839 IPW_IO_LED_OFF); 1840 1841 /* enable interrupts */ 1842 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1843 1844 /* kick the firmware */ 1845 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1846 1847 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1848 IPW_CTL_ALLOW_STANDBY); 1849 1850 /* wait at most one second for firmware initialization to complete */ 1851 if ((error = tsleep(sc, 0, "ipwinit", hz)) != 0) { 1852 aprint_error_dev(&sc->sc_dev, "timeout waiting for firmware initialization " 1853 "to complete\n"); 1854 return error; 1855 } 1856 1857 CSR_WRITE_4(sc, IPW_CSR_IO, CSR_READ_4(sc, IPW_CSR_IO) | 1858 IPW_IO_GPIO1_MASK | IPW_IO_GPIO3_MASK); 1859 1860 return 0; 1861 } 1862 1863 /* 1864 * Store firmware into kernel memory so we can download it when we need to, 1865 * e.g when the adapter wakes up from suspend mode. 1866 */ 1867 static int 1868 ipw_cache_firmware(struct ipw_softc *sc) 1869 { 1870 struct ipw_firmware *fw = &sc->fw; 1871 struct ipw_firmware_hdr hdr; 1872 firmware_handle_t fwh; 1873 off_t fwsz, p; 1874 int error; 1875 1876 ipw_free_firmware(sc); 1877 1878 if ((error = firmware_open("if_ipw", sc->sc_fwname, &fwh)) != 0) 1879 goto fail0; 1880 1881 fwsz = firmware_get_size(fwh); 1882 1883 if (fwsz < sizeof(hdr)) 1884 goto fail2; 1885 1886 if ((error = firmware_read(fwh, 0, &hdr, sizeof(hdr))) != 0) 1887 goto fail2; 1888 1889 fw->main_size = le32toh(hdr.main_size); 1890 fw->ucode_size = le32toh(hdr.ucode_size); 1891 1892 fw->main = firmware_malloc(fw->main_size); 1893 if (fw->main == NULL) { 1894 error = ENOMEM; 1895 goto fail1; 1896 } 1897 1898 fw->ucode = firmware_malloc(fw->ucode_size); 1899 if (fw->ucode == NULL) { 1900 error = ENOMEM; 1901 goto fail2; 1902 } 1903 1904 p = sizeof(hdr); 1905 if ((error = firmware_read(fwh, p, fw->main, fw->main_size)) != 0) 1906 goto fail3; 1907 1908 p += fw->main_size; 1909 if ((error = firmware_read(fwh, p, fw->ucode, fw->ucode_size)) != 0) 1910 goto fail3; 1911 1912 DPRINTF(("Firmware cached: main %u, ucode %u\n", fw->main_size, 1913 fw->ucode_size)); 1914 1915 sc->flags |= IPW_FLAG_FW_CACHED; 1916 1917 firmware_close(fwh); 1918 1919 return 0; 1920 1921 fail3: firmware_free(fw->ucode, 0); 1922 fail2: firmware_free(fw->main, 0); 1923 fail1: firmware_close(fwh); 1924 fail0: 1925 return error; 1926 } 1927 1928 static void 1929 ipw_free_firmware(struct ipw_softc *sc) 1930 { 1931 if (!(sc->flags & IPW_FLAG_FW_CACHED)) 1932 return; 1933 1934 firmware_free(sc->fw.main, 0); 1935 firmware_free(sc->fw.ucode, 0); 1936 1937 sc->flags &= ~IPW_FLAG_FW_CACHED; 1938 } 1939 1940 static int 1941 ipw_config(struct ipw_softc *sc) 1942 { 1943 struct ieee80211com *ic = &sc->sc_ic; 1944 struct ifnet *ifp = &sc->sc_if; 1945 struct ipw_security security; 1946 struct ieee80211_key *k; 1947 struct ipw_wep_key wepkey; 1948 struct ipw_scan_options options; 1949 struct ipw_configuration config; 1950 uint32_t data; 1951 int error, i; 1952 1953 switch (ic->ic_opmode) { 1954 case IEEE80211_M_STA: 1955 case IEEE80211_M_HOSTAP: 1956 data = htole32(IPW_MODE_BSS); 1957 break; 1958 1959 case IEEE80211_M_IBSS: 1960 case IEEE80211_M_AHDEMO: 1961 data = htole32(IPW_MODE_IBSS); 1962 break; 1963 1964 case IEEE80211_M_MONITOR: 1965 data = htole32(IPW_MODE_MONITOR); 1966 break; 1967 } 1968 DPRINTF(("Setting mode to %u\n", le32toh(data))); 1969 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 1970 if (error != 0) 1971 return error; 1972 1973 if (ic->ic_opmode == IEEE80211_M_IBSS || 1974 ic->ic_opmode == IEEE80211_M_MONITOR) { 1975 data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); 1976 DPRINTF(("Setting channel to %u\n", le32toh(data))); 1977 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 1978 if (error != 0) 1979 return error; 1980 } 1981 1982 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1983 DPRINTF(("Enabling adapter\n")); 1984 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1985 } 1986 1987 DPRINTF(("Setting MAC to %s\n", ether_sprintf(ic->ic_myaddr))); 1988 if_set_sadl(ifp, ic->ic_myaddr, IEEE80211_ADDR_LEN); 1989 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 1990 IEEE80211_ADDR_LEN); 1991 if (error != 0) 1992 return error; 1993 1994 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 1995 IPW_CFG_PREAMBLE_AUTO | IPW_CFG_802_1x_ENABLE); 1996 1997 if (ic->ic_opmode == IEEE80211_M_IBSS) 1998 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 1999 if (ifp->if_flags & IFF_PROMISC) 2000 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 2001 config.bss_chan = htole32(0x3fff); /* channels 1-14 */ 2002 config.ibss_chan = htole32(0x7ff); /* channels 1-11 */ 2003 DPRINTF(("Setting adapter configuration 0x%08x\n", config.flags)); 2004 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 2005 if (error != 0) 2006 return error; 2007 2008 data = htole32(0x3); /* 1, 2 */ 2009 DPRINTF(("Setting basic tx rates to 0x%x\n", le32toh(data))); 2010 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 2011 if (error != 0) 2012 return error; 2013 2014 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 2015 DPRINTF(("Setting tx rates to 0x%x\n", le32toh(data))); 2016 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 2017 if (error != 0) 2018 return error; 2019 2020 data = htole32(IPW_POWER_MODE_CAM); 2021 DPRINTF(("Setting power mode to %u\n", le32toh(data))); 2022 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 2023 if (error != 0) 2024 return error; 2025 2026 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2027 data = htole32(32); /* default value */ 2028 DPRINTF(("Setting tx power index to %u\n", le32toh(data))); 2029 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 2030 sizeof data); 2031 if (error != 0) 2032 return error; 2033 } 2034 2035 data = htole32(ic->ic_rtsthreshold); 2036 DPRINTF(("Setting RTS threshold to %u\n", le32toh(data))); 2037 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 2038 if (error != 0) 2039 return error; 2040 2041 data = htole32(ic->ic_fragthreshold); 2042 DPRINTF(("Setting frag threshold to %u\n", le32toh(data))); 2043 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 2044 if (error != 0) 2045 return error; 2046 2047 #ifdef IPW_DEBUG 2048 if (ipw_debug > 0) { 2049 printf("Setting ESSID to "); 2050 ieee80211_print_essid(ic->ic_des_essid, ic->ic_des_esslen); 2051 printf("\n"); 2052 } 2053 #endif 2054 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ic->ic_des_essid, 2055 ic->ic_des_esslen); 2056 if (error != 0) 2057 return error; 2058 2059 /* no mandatory BSSID */ 2060 DPRINTF(("Setting mandatory BSSID to null\n")); 2061 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 2062 if (error != 0) 2063 return error; 2064 2065 if (ic->ic_flags & IEEE80211_F_DESBSSID) { 2066 DPRINTF(("Setting desired BSSID to %s\n", 2067 ether_sprintf(ic->ic_des_bssid))); 2068 error = ipw_cmd(sc, IPW_CMD_SET_DESIRED_BSSID, 2069 ic->ic_des_bssid, IEEE80211_ADDR_LEN); 2070 if (error != 0) 2071 return error; 2072 } 2073 2074 (void)memset(&security, 0, sizeof(security)); 2075 security.authmode = (ic->ic_bss->ni_authmode == IEEE80211_AUTH_SHARED) ? 2076 IPW_AUTH_SHARED : IPW_AUTH_OPEN; 2077 security.ciphers = htole32(IPW_CIPHER_NONE); 2078 DPRINTF(("Setting authmode to %u\n", security.authmode)); 2079 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 2080 sizeof security); 2081 if (error != 0) 2082 return error; 2083 2084 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 2085 k = ic->ic_crypto.cs_nw_keys; 2086 for (i = 0; i < IEEE80211_WEP_NKID; i++, k++) { 2087 if (k->wk_keylen == 0) 2088 continue; 2089 2090 wepkey.idx = i; 2091 wepkey.len = k->wk_keylen; 2092 memset(wepkey.key, 0, sizeof(wepkey.key)); 2093 memcpy(wepkey.key, k->wk_key, k->wk_keylen); 2094 DPRINTF(("Setting wep key index %u len %u\n", 2095 wepkey.idx, wepkey.len)); 2096 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY, &wepkey, 2097 sizeof wepkey); 2098 if (error != 0) 2099 return error; 2100 } 2101 2102 data = htole32(ic->ic_crypto.cs_def_txkey); 2103 DPRINTF(("Setting tx key index to %u\n", le32toh(data))); 2104 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY_INDEX, &data, 2105 sizeof data); 2106 if (error != 0) 2107 return error; 2108 } 2109 2110 data = htole32((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) ? IPW_WEPON : 0); 2111 DPRINTF(("Setting wep flags to 0x%x\n", le32toh(data))); 2112 error = ipw_cmd(sc, IPW_CMD_SET_WEP_FLAGS, &data, sizeof data); 2113 if (error != 0) 2114 return error; 2115 2116 #if 0 2117 struct ipw_wpa_ie ie; 2118 2119 memset(&ie, 0 sizeof(ie)); 2120 ie.len = htole32(sizeof (struct ieee80211_ie_wpa)); 2121 DPRINTF(("Setting wpa ie\n")); 2122 error = ipw_cmd(sc, IPW_CMD_SET_WPA_IE, &ie, sizeof ie); 2123 if (error != 0) 2124 return error; 2125 #endif 2126 2127 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2128 data = htole32(ic->ic_bintval); 2129 DPRINTF(("Setting beacon interval to %u\n", le32toh(data))); 2130 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 2131 sizeof data); 2132 if (error != 0) 2133 return error; 2134 } 2135 2136 options.flags = 0; 2137 options.channels = htole32(0x3fff); /* scan channels 1-14 */ 2138 DPRINTF(("Setting scan options to 0x%x\n", le32toh(options.flags))); 2139 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &options, sizeof options); 2140 if (error != 0) 2141 return error; 2142 2143 /* finally, enable adapter (start scanning for an access point) */ 2144 DPRINTF(("Enabling adapter\n")); 2145 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 2146 } 2147 2148 static int 2149 ipw_init(struct ifnet *ifp) 2150 { 2151 struct ipw_softc *sc = ifp->if_softc; 2152 struct ipw_firmware *fw = &sc->fw; 2153 2154 if (!(sc->flags & IPW_FLAG_FW_CACHED)) { 2155 if (ipw_cache_firmware(sc) != 0) { 2156 aprint_error_dev(&sc->sc_dev, "could not cache the firmware (%s)\n", 2157 sc->sc_fwname); 2158 goto fail; 2159 } 2160 } 2161 2162 ipw_stop(ifp, 0); 2163 2164 if (ipw_reset(sc) != 0) { 2165 aprint_error_dev(&sc->sc_dev, "could not reset adapter\n"); 2166 goto fail; 2167 } 2168 2169 if (ipw_load_ucode(sc, fw->ucode, fw->ucode_size) != 0) { 2170 aprint_error_dev(&sc->sc_dev, "could not load microcode\n"); 2171 goto fail; 2172 } 2173 2174 ipw_stop_master(sc); 2175 2176 /* 2177 * Setup tx, rx and status rings. 2178 */ 2179 sc->txold = IPW_NTBD - 1; 2180 sc->txcur = 0; 2181 sc->txfree = IPW_NTBD - 2; 2182 sc->rxcur = IPW_NRBD - 1; 2183 2184 CSR_WRITE_4(sc, IPW_CSR_TX_BASE, sc->tbd_map->dm_segs[0].ds_addr); 2185 CSR_WRITE_4(sc, IPW_CSR_TX_SIZE, IPW_NTBD); 2186 CSR_WRITE_4(sc, IPW_CSR_TX_READ, 0); 2187 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 2188 2189 CSR_WRITE_4(sc, IPW_CSR_RX_BASE, sc->rbd_map->dm_segs[0].ds_addr); 2190 CSR_WRITE_4(sc, IPW_CSR_RX_SIZE, IPW_NRBD); 2191 CSR_WRITE_4(sc, IPW_CSR_RX_READ, 0); 2192 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 2193 2194 CSR_WRITE_4(sc, IPW_CSR_STATUS_BASE, sc->status_map->dm_segs[0].ds_addr); 2195 2196 if (ipw_load_firmware(sc, fw->main, fw->main_size) != 0) { 2197 aprint_error_dev(&sc->sc_dev, "could not load firmware\n"); 2198 goto fail; 2199 } 2200 2201 sc->flags |= IPW_FLAG_FW_INITED; 2202 2203 /* retrieve information tables base addresses */ 2204 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 2205 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 2206 2207 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 2208 2209 if (ipw_config(sc) != 0) { 2210 aprint_error_dev(&sc->sc_dev, "device configuration failed\n"); 2211 goto fail; 2212 } 2213 2214 ifp->if_flags &= ~IFF_OACTIVE; 2215 ifp->if_flags |= IFF_RUNNING; 2216 2217 return 0; 2218 2219 fail: ifp->if_flags &= ~IFF_UP; 2220 ipw_stop(ifp, 0); 2221 2222 return EIO; 2223 } 2224 2225 static void 2226 ipw_stop(struct ifnet *ifp, int disable) 2227 { 2228 struct ipw_softc *sc = ifp->if_softc; 2229 struct ieee80211com *ic = &sc->sc_ic; 2230 int i; 2231 2232 ipw_stop_master(sc); 2233 2234 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 2235 2236 /* 2237 * Release tx buffers. 2238 */ 2239 for (i = 0; i < IPW_NTBD; i++) 2240 ipw_release_sbd(sc, &sc->stbd_list[i]); 2241 2242 sc->sc_tx_timer = 0; 2243 ifp->if_timer = 0; 2244 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2245 2246 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2247 } 2248 2249 static void 2250 ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2251 bus_size_t count) 2252 { 2253 for (; count > 0; offset++, datap++, count--) { 2254 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2255 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 2256 } 2257 } 2258 2259 static void 2260 ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2261 bus_size_t count) 2262 { 2263 for (; count > 0; offset++, datap++, count--) { 2264 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2265 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 2266 } 2267 } 2268
Indexes created Tue Sep 30 11:09:46 GMT 2025