if_ipw.c revision 1.43
1 /* $NetBSD: if_ipw.c,v 1.43 2008/11/07 00:20:07 dyoung Exp $ */ 2 /* FreeBSD: src/sys/dev/ipw/if_ipw.c,v 1.15 2005/11/13 17:17:40 damien Exp */ 3 4 /*- 5 * Copyright (c) 2004, 2005 6 * Damien Bergamini <damien.bergamini (at) free.fr>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: if_ipw.c,v 1.43 2008/11/07 00:20:07 dyoung Exp $"); 33 34 /*- 35 * Intel(R) PRO/Wireless 2100 MiniPCI driver 36 * http://www.intel.com/network/connectivity/products/wireless/prowireless_mobile.htm 37 */ 38 39 #include "bpfilter.h" 40 41 #include <sys/param.h> 42 #include <sys/sockio.h> 43 #include <sys/sysctl.h> 44 #include <sys/mbuf.h> 45 #include <sys/kernel.h> 46 #include <sys/socket.h> 47 #include <sys/systm.h> 48 #include <sys/malloc.h> 49 #include <sys/conf.h> 50 51 #include <sys/bus.h> 52 #include <machine/endian.h> 53 #include <sys/intr.h> 54 55 #include <dev/pci/pcireg.h> 56 #include <dev/pci/pcivar.h> 57 #include <dev/pci/pcidevs.h> 58 59 #if NBPFILTER > 0 60 #include <net/bpf.h> 61 #endif 62 #include <net/if.h> 63 #include <net/if_arp.h> 64 #include <net/if_dl.h> 65 #include <net/if_ether.h> 66 #include <net/if_media.h> 67 #include <net/if_types.h> 68 69 #include <net80211/ieee80211_var.h> 70 #include <net80211/ieee80211_radiotap.h> 71 72 #include <netinet/in.h> 73 #include <netinet/in_systm.h> 74 #include <netinet/in_var.h> 75 #include <netinet/ip.h> 76 77 #include <dev/firmload.h> 78 79 #include <dev/pci/if_ipwreg.h> 80 #include <dev/pci/if_ipwvar.h> 81 82 #ifdef IPW_DEBUG 83 #define DPRINTF(x) if (ipw_debug > 0) printf x 84 #define DPRINTFN(n, x) if (ipw_debug >= (n)) printf x 85 int ipw_debug = 0; 86 #else 87 #define DPRINTF(x) 88 #define DPRINTFN(n, x) 89 #endif 90 91 /* Permit loading the Intel firmware */ 92 static int ipw_accept_eula; 93 94 static int ipw_dma_alloc(struct ipw_softc *); 95 static void ipw_release(struct ipw_softc *); 96 static int ipw_match(struct device *, struct cfdata *, void *); 97 static void ipw_attach(struct device *, struct device *, void *); 98 static int ipw_detach(struct device *, int); 99 100 static int ipw_media_change(struct ifnet *); 101 static void ipw_media_status(struct ifnet *, struct ifmediareq *); 102 static int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 103 static uint16_t ipw_read_prom_word(struct ipw_softc *, uint8_t); 104 static void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 105 static void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 106 static void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 107 struct ipw_soft_bd *, struct ipw_soft_buf *); 108 static void ipw_rx_intr(struct ipw_softc *); 109 static void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 110 static void ipw_tx_intr(struct ipw_softc *); 111 static int ipw_intr(void *); 112 static int ipw_cmd(struct ipw_softc *, uint32_t, void *, uint32_t); 113 static int ipw_tx_start(struct ifnet *, struct mbuf *, 114 struct ieee80211_node *); 115 static void ipw_start(struct ifnet *); 116 static void ipw_watchdog(struct ifnet *); 117 static int ipw_ioctl(struct ifnet *, u_long, void *); 118 static int ipw_get_table1(struct ipw_softc *, uint32_t *); 119 static int ipw_get_radio(struct ipw_softc *, int *); 120 static void ipw_stop_master(struct ipw_softc *); 121 static int ipw_reset(struct ipw_softc *); 122 static int ipw_load_ucode(struct ipw_softc *, u_char *, int); 123 static int ipw_load_firmware(struct ipw_softc *, u_char *, int); 124 static int ipw_cache_firmware(struct ipw_softc *); 125 static void ipw_free_firmware(struct ipw_softc *); 126 static int ipw_config(struct ipw_softc *); 127 static int ipw_init(struct ifnet *); 128 static void ipw_stop(struct ifnet *, int); 129 static uint32_t ipw_read_table1(struct ipw_softc *, uint32_t); 130 static void ipw_write_table1(struct ipw_softc *, uint32_t, uint32_t); 131 static int ipw_read_table2(struct ipw_softc *, uint32_t, void *, uint32_t *); 132 static void ipw_read_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 133 bus_size_t); 134 static void ipw_write_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 135 bus_size_t); 136 137 /* 138 * Supported rates for 802.11b mode (in 500Kbps unit). 139 */ 140 static const struct ieee80211_rateset ipw_rateset_11b = 141 { 4, { 2, 4, 11, 22 } }; 142 143 static inline uint8_t 144 MEM_READ_1(struct ipw_softc *sc, uint32_t addr) 145 { 146 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 147 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); 148 } 149 150 static inline uint32_t 151 MEM_READ_4(struct ipw_softc *sc, uint32_t addr) 152 { 153 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 154 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); 155 } 156 157 CFATTACH_DECL(ipw, sizeof (struct ipw_softc), ipw_match, ipw_attach, 158 ipw_detach, NULL); 159 160 static int 161 ipw_match(struct device *parent, struct cfdata *match, 162 void *aux) 163 { 164 struct pci_attach_args *pa = aux; 165 166 if (PCI_VENDOR (pa->pa_id) == PCI_VENDOR_INTEL && 167 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_PRO_WL_2100) 168 return 1; 169 170 return 0; 171 } 172 173 /* Base Address Register */ 174 #define IPW_PCI_BAR0 0x10 175 176 static void 177 ipw_attach(struct device *parent, struct device *self, void *aux) 178 { 179 struct ipw_softc *sc = (struct ipw_softc *)self; 180 struct ieee80211com *ic = &sc->sc_ic; 181 struct ifnet *ifp = &sc->sc_if; 182 struct pci_attach_args *pa = aux; 183 const char *intrstr; 184 char devinfo[256]; 185 bus_space_tag_t memt; 186 bus_space_handle_t memh; 187 bus_addr_t base; 188 pci_intr_handle_t ih; 189 uint32_t data; 190 uint16_t val; 191 int i, revision, error; 192 193 sc->sc_pct = pa->pa_pc; 194 sc->sc_pcitag = pa->pa_tag; 195 196 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof devinfo); 197 revision = PCI_REVISION(pa->pa_class); 198 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, revision); 199 200 /* enable bus-mastering */ 201 data = pci_conf_read(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG); 202 data |= PCI_COMMAND_MASTER_ENABLE; 203 pci_conf_write(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG, data); 204 205 /* map the register window */ 206 error = pci_mapreg_map(pa, IPW_PCI_BAR0, PCI_MAPREG_TYPE_MEM | 207 PCI_MAPREG_MEM_TYPE_32BIT, 0, &memt, &memh, &base, &sc->sc_sz); 208 if (error != 0) { 209 aprint_error_dev(&sc->sc_dev, "could not map memory space\n"); 210 return; 211 } 212 213 sc->sc_st = memt; 214 sc->sc_sh = memh; 215 sc->sc_dmat = pa->pa_dmat; 216 strlcpy(sc->sc_fwname, "ipw2100-1.2.fw", sizeof(sc->sc_fwname)); 217 218 /* disable interrupts */ 219 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 220 221 if (pci_intr_map(pa, &ih) != 0) { 222 aprint_error_dev(&sc->sc_dev, "could not map interrupt\n"); 223 return; 224 } 225 226 intrstr = pci_intr_string(sc->sc_pct, ih); 227 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, ipw_intr, sc); 228 if (sc->sc_ih == NULL) { 229 aprint_error_dev(&sc->sc_dev, "could not establish interrupt"); 230 if (intrstr != NULL) 231 aprint_error(" at %s", intrstr); 232 aprint_error("\n"); 233 return; 234 } 235 aprint_normal_dev(&sc->sc_dev, "interrupting at %s\n", intrstr); 236 237 if (ipw_reset(sc) != 0) { 238 aprint_error_dev(&sc->sc_dev, "could not reset adapter\n"); 239 goto fail; 240 } 241 242 if (ipw_dma_alloc(sc) != 0) { 243 aprint_error_dev(&sc->sc_dev, "could not allocate DMA resources\n"); 244 goto fail; 245 } 246 247 ifp->if_softc = sc; 248 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 249 ifp->if_init = ipw_init; 250 ifp->if_stop = ipw_stop; 251 ifp->if_ioctl = ipw_ioctl; 252 ifp->if_start = ipw_start; 253 ifp->if_watchdog = ipw_watchdog; 254 IFQ_SET_READY(&ifp->if_snd); 255 strlcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 256 257 ic->ic_ifp = ifp; 258 ic->ic_phytype = IEEE80211_T_DS; 259 ic->ic_opmode = IEEE80211_M_STA; 260 ic->ic_state = IEEE80211_S_INIT; 261 262 /* set device capabilities */ 263 ic->ic_caps = 264 IEEE80211_C_SHPREAMBLE /* short preamble supported */ 265 | IEEE80211_C_TXPMGT /* tx power management */ 266 | IEEE80211_C_IBSS /* ibss mode */ 267 | IEEE80211_C_MONITOR /* monitor mode */ 268 ; 269 270 /* read MAC address from EEPROM */ 271 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0); 272 ic->ic_myaddr[0] = val >> 8; 273 ic->ic_myaddr[1] = val & 0xff; 274 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 1); 275 ic->ic_myaddr[2] = val >> 8; 276 ic->ic_myaddr[3] = val & 0xff; 277 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 2); 278 ic->ic_myaddr[4] = val >> 8; 279 ic->ic_myaddr[5] = val & 0xff; 280 281 /* set supported .11b rates */ 282 ic->ic_sup_rates[IEEE80211_MODE_11B] = ipw_rateset_11b; 283 284 /* set supported .11b channels (read from EEPROM) */ 285 if ((val = ipw_read_prom_word(sc, IPW_EEPROM_CHANNEL_LIST)) == 0) 286 val = 0x7ff; /* default to channels 1-11 */ 287 val <<= 1; 288 for (i = 1; i < 16; i++) { 289 if (val & (1 << i)) { 290 ic->ic_channels[i].ic_freq = 291 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 292 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 293 } 294 } 295 296 /* check support for radio transmitter switch in EEPROM */ 297 if (!(ipw_read_prom_word(sc, IPW_EEPROM_RADIO) & 8)) 298 sc->flags |= IPW_FLAG_HAS_RADIO_SWITCH; 299 300 aprint_normal_dev(&sc->sc_dev, "802.11 address %s\n", 301 ether_sprintf(ic->ic_myaddr)); 302 303 if_attach(ifp); 304 ieee80211_ifattach(ic); 305 306 /* override state transition machine */ 307 sc->sc_newstate = ic->ic_newstate; 308 ic->ic_newstate = ipw_newstate; 309 310 ieee80211_media_init(ic, ipw_media_change, ipw_media_status); 311 312 #if NBPFILTER > 0 313 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 314 sizeof (struct ieee80211_frame) + 64, &sc->sc_drvbpf); 315 316 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 317 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 318 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 319 320 sc->sc_txtap_len = sizeof sc->sc_txtapu; 321 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 322 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 323 #endif 324 325 /* 326 * Add a few sysctl knobs. 327 * XXX: Not yet 328 */ 329 sc->dwelltime = 100; 330 331 if (!pmf_device_register(self, NULL, NULL)) 332 aprint_error_dev(self, "couldn't establish power handler\n"); 333 else 334 pmf_class_network_register(self, ifp); 335 336 ieee80211_announce(ic); 337 338 return; 339 340 fail: ipw_detach(self, 0); 341 } 342 343 static int 344 ipw_detach(struct device* self, int flags) 345 { 346 struct ipw_softc *sc = (struct ipw_softc *)self; 347 struct ifnet *ifp = &sc->sc_if; 348 349 if (ifp->if_softc) { 350 ipw_stop(ifp, 1); 351 ipw_free_firmware(sc); 352 353 #if NBPFILTER > 0 354 bpfdetach(ifp); 355 #endif 356 ieee80211_ifdetach(&sc->sc_ic); 357 if_detach(ifp); 358 359 ipw_release(sc); 360 } 361 362 if (sc->sc_ih != NULL) { 363 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 364 sc->sc_ih = NULL; 365 } 366 367 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 368 369 return 0; 370 } 371 372 static int 373 ipw_dma_alloc(struct ipw_softc *sc) 374 { 375 struct ipw_soft_bd *sbd; 376 struct ipw_soft_hdr *shdr; 377 struct ipw_soft_buf *sbuf; 378 int error, i, nsegs; 379 380 /* 381 * Allocate and map tx ring. 382 */ 383 error = bus_dmamap_create(sc->sc_dmat, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, 384 BUS_DMA_NOWAIT, &sc->tbd_map); 385 if (error != 0) { 386 aprint_error_dev(&sc->sc_dev, "could not create tbd dma map\n"); 387 goto fail; 388 } 389 390 error = bus_dmamem_alloc(sc->sc_dmat, IPW_TBD_SZ, PAGE_SIZE, 0, 391 &sc->tbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 392 if (error != 0) { 393 aprint_error_dev(&sc->sc_dev, "could not allocate tbd dma memory\n"); 394 goto fail; 395 } 396 397 error = bus_dmamem_map(sc->sc_dmat, &sc->tbd_seg, nsegs, IPW_TBD_SZ, 398 (void **)&sc->tbd_list, BUS_DMA_NOWAIT); 399 if (error != 0) { 400 aprint_error_dev(&sc->sc_dev, "could not map tbd dma memory\n"); 401 goto fail; 402 } 403 404 error = bus_dmamap_load(sc->sc_dmat, sc->tbd_map, sc->tbd_list, 405 IPW_TBD_SZ, NULL, BUS_DMA_NOWAIT); 406 if (error != 0) { 407 aprint_error_dev(&sc->sc_dev, "could not load tbd dma memory\n"); 408 goto fail; 409 } 410 411 (void)memset(sc->tbd_list, 0, IPW_TBD_SZ); 412 413 /* 414 * Allocate and map rx ring. 415 */ 416 error = bus_dmamap_create(sc->sc_dmat, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, 417 BUS_DMA_NOWAIT, &sc->rbd_map); 418 if (error != 0) { 419 aprint_error_dev(&sc->sc_dev, "could not create rbd dma map\n"); 420 goto fail; 421 } 422 423 error = bus_dmamem_alloc(sc->sc_dmat, IPW_RBD_SZ, PAGE_SIZE, 0, 424 &sc->rbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 425 if (error != 0) { 426 aprint_error_dev(&sc->sc_dev, "could not allocate rbd dma memory\n"); 427 goto fail; 428 } 429 430 error = bus_dmamem_map(sc->sc_dmat, &sc->rbd_seg, nsegs, IPW_RBD_SZ, 431 (void **)&sc->rbd_list, BUS_DMA_NOWAIT); 432 if (error != 0) { 433 aprint_error_dev(&sc->sc_dev, "could not map rbd dma memory\n"); 434 goto fail; 435 } 436 437 error = bus_dmamap_load(sc->sc_dmat, sc->rbd_map, sc->rbd_list, 438 IPW_RBD_SZ, NULL, BUS_DMA_NOWAIT); 439 if (error != 0) { 440 aprint_error_dev(&sc->sc_dev, "could not load rbd dma memory\n"); 441 goto fail; 442 } 443 444 (void)memset(sc->rbd_list, 0, IPW_RBD_SZ); 445 446 /* 447 * Allocate and map status ring. 448 */ 449 error = bus_dmamap_create(sc->sc_dmat, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 450 0, BUS_DMA_NOWAIT, &sc->status_map); 451 if (error != 0) { 452 aprint_error_dev(&sc->sc_dev, "could not create status dma map\n"); 453 goto fail; 454 } 455 456 error = bus_dmamem_alloc(sc->sc_dmat, IPW_STATUS_SZ, PAGE_SIZE, 0, 457 &sc->status_seg, 1, &nsegs, BUS_DMA_NOWAIT); 458 if (error != 0) { 459 aprint_error_dev(&sc->sc_dev, "could not allocate status dma memory\n"); 460 goto fail; 461 } 462 463 error = bus_dmamem_map(sc->sc_dmat, &sc->status_seg, nsegs, 464 IPW_STATUS_SZ, (void **)&sc->status_list, BUS_DMA_NOWAIT); 465 if (error != 0) { 466 aprint_error_dev(&sc->sc_dev, "could not map status dma memory\n"); 467 goto fail; 468 } 469 470 error = bus_dmamap_load(sc->sc_dmat, sc->status_map, sc->status_list, 471 IPW_STATUS_SZ, NULL, BUS_DMA_NOWAIT); 472 if (error != 0) { 473 aprint_error_dev(&sc->sc_dev, "could not load status dma memory\n"); 474 goto fail; 475 } 476 477 (void)memset(sc->status_list, 0, IPW_STATUS_SZ); 478 479 /* 480 * Allocate command DMA map. 481 */ 482 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_cmd), 483 1, sizeof (struct ipw_cmd), 0, BUS_DMA_NOWAIT, &sc->cmd_map); 484 if (error != 0) { 485 aprint_error_dev(&sc->sc_dev, "could not create cmd dma map\n"); 486 goto fail; 487 } 488 489 error = bus_dmamem_alloc(sc->sc_dmat, sizeof (struct ipw_cmd), 490 PAGE_SIZE, 0, &sc->cmd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 491 if (error != 0) { 492 aprint_error_dev(&sc->sc_dev, "could not allocate cmd dma memory\n"); 493 goto fail; 494 } 495 496 error = bus_dmamem_map(sc->sc_dmat, &sc->cmd_seg, nsegs, 497 sizeof (struct ipw_cmd), (void **)&sc->cmd, BUS_DMA_NOWAIT); 498 if (error != 0) { 499 aprint_error_dev(&sc->sc_dev, "could not map cmd dma memory\n"); 500 goto fail; 501 } 502 503 error = bus_dmamap_load(sc->sc_dmat, sc->cmd_map, &sc->cmd, 504 sizeof (struct ipw_cmd), NULL, BUS_DMA_NOWAIT); 505 if (error != 0) { 506 aprint_error_dev(&sc->sc_dev, "could not map cmd dma memory\n"); 507 return error; 508 } 509 510 /* 511 * Allocate and map hdr list. 512 */ 513 514 error = bus_dmamap_create(sc->sc_dmat, 515 IPW_NDATA * sizeof(struct ipw_hdr), 1, 516 sizeof(struct ipw_hdr), 0, BUS_DMA_NOWAIT, 517 &sc->hdr_map); 518 if (error != 0) { 519 aprint_error_dev(&sc->sc_dev, "could not create hdr dma map\n"); 520 goto fail; 521 } 522 523 error = bus_dmamem_alloc(sc->sc_dmat, 524 IPW_NDATA * sizeof(struct ipw_hdr), PAGE_SIZE, 0, &sc->hdr_seg, 525 1, &nsegs, BUS_DMA_NOWAIT); 526 if (error != 0) { 527 aprint_error_dev(&sc->sc_dev, "could not allocate hdr memory\n"); 528 goto fail; 529 } 530 531 error = bus_dmamem_map(sc->sc_dmat, &sc->hdr_seg, nsegs, 532 IPW_NDATA * sizeof(struct ipw_hdr), (void **)&sc->hdr_list, 533 BUS_DMA_NOWAIT); 534 if (error != 0) { 535 aprint_error_dev(&sc->sc_dev, "could not map hdr memory\n"); 536 goto fail; 537 } 538 539 error = bus_dmamap_load(sc->sc_dmat, sc->hdr_map, sc->hdr_list, 540 IPW_NDATA * sizeof(struct ipw_hdr), NULL, BUS_DMA_NOWAIT); 541 if (error != 0) { 542 aprint_error_dev(&sc->sc_dev, "could not load hdr memory\n"); 543 goto fail; 544 } 545 546 (void)memset(sc->hdr_list, 0, IPW_HDR_SZ); 547 548 /* 549 * Create DMA hdrs tailq. 550 */ 551 TAILQ_INIT(&sc->sc_free_shdr); 552 for (i = 0; i < IPW_NDATA; i++) { 553 shdr = &sc->shdr_list[i]; 554 shdr->hdr = sc->hdr_list + i; 555 shdr->offset = sizeof(struct ipw_hdr) * i; 556 shdr->addr = sc->hdr_map->dm_segs[0].ds_addr + shdr->offset; 557 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 558 } 559 560 /* 561 * Allocate tx buffers DMA maps. 562 */ 563 TAILQ_INIT(&sc->sc_free_sbuf); 564 for (i = 0; i < IPW_NDATA; i++) { 565 sbuf = &sc->tx_sbuf_list[i]; 566 567 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 568 IPW_MAX_NSEG, MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 569 if (error != 0) { 570 aprint_error_dev(&sc->sc_dev, "could not create txbuf dma map\n"); 571 goto fail; 572 } 573 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 574 } 575 576 /* 577 * Initialize tx ring. 578 */ 579 for (i = 0; i < IPW_NTBD; i++) { 580 sbd = &sc->stbd_list[i]; 581 sbd->bd = &sc->tbd_list[i]; 582 sbd->type = IPW_SBD_TYPE_NOASSOC; 583 } 584 585 /* 586 * Pre-allocate rx buffers and DMA maps 587 */ 588 for (i = 0; i < IPW_NRBD; i++) { 589 sbd = &sc->srbd_list[i]; 590 sbuf = &sc->rx_sbuf_list[i]; 591 sbd->bd = &sc->rbd_list[i]; 592 593 MGETHDR(sbuf->m, M_DONTWAIT, MT_DATA); 594 if (sbuf->m == NULL) { 595 aprint_error_dev(&sc->sc_dev, "could not allocate rx mbuf\n"); 596 error = ENOMEM; 597 goto fail; 598 } 599 600 MCLGET(sbuf->m, M_DONTWAIT); 601 if (!(sbuf->m->m_flags & M_EXT)) { 602 m_freem(sbuf->m); 603 aprint_error_dev(&sc->sc_dev, "could not allocate rx mbuf cluster\n"); 604 error = ENOMEM; 605 goto fail; 606 } 607 608 sbuf->m->m_pkthdr.len = sbuf->m->m_len = sbuf->m->m_ext.ext_size; 609 610 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 611 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sbuf->map); 612 if (error != 0) { 613 aprint_error_dev(&sc->sc_dev, "could not create rxbuf dma map\n"); 614 m_freem(sbuf->m); 615 goto fail; 616 } 617 618 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, 619 sbuf->m, BUS_DMA_READ | BUS_DMA_NOWAIT); 620 if (error != 0) { 621 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 622 m_freem(sbuf->m); 623 aprint_error_dev(&sc->sc_dev, "could not map rxbuf dma memory\n"); 624 goto fail; 625 } 626 627 sbd->type = IPW_SBD_TYPE_DATA; 628 sbd->priv = sbuf; 629 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 630 sbd->bd->len = htole32(MCLBYTES); 631 632 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, 633 sbuf->map->dm_mapsize, BUS_DMASYNC_PREREAD); 634 635 } 636 637 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 0, IPW_RBD_SZ, 638 BUS_DMASYNC_PREREAD); 639 640 return 0; 641 642 fail: ipw_release(sc); 643 return error; 644 } 645 646 static void 647 ipw_release(struct ipw_softc *sc) 648 { 649 struct ipw_soft_buf *sbuf; 650 int i; 651 652 if (sc->tbd_map != NULL) { 653 if (sc->tbd_list != NULL) { 654 bus_dmamap_unload(sc->sc_dmat, sc->tbd_map); 655 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->tbd_list, 656 IPW_TBD_SZ); 657 bus_dmamem_free(sc->sc_dmat, &sc->tbd_seg, 1); 658 } 659 bus_dmamap_destroy(sc->sc_dmat, sc->tbd_map); 660 } 661 662 if (sc->rbd_map != NULL) { 663 if (sc->rbd_list != NULL) { 664 bus_dmamap_unload(sc->sc_dmat, sc->rbd_map); 665 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->rbd_list, 666 IPW_RBD_SZ); 667 bus_dmamem_free(sc->sc_dmat, &sc->rbd_seg, 1); 668 } 669 bus_dmamap_destroy(sc->sc_dmat, sc->rbd_map); 670 } 671 672 if (sc->status_map != NULL) { 673 if (sc->status_list != NULL) { 674 bus_dmamap_unload(sc->sc_dmat, sc->status_map); 675 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->status_list, 676 IPW_RBD_SZ); 677 bus_dmamem_free(sc->sc_dmat, &sc->status_seg, 1); 678 } 679 bus_dmamap_destroy(sc->sc_dmat, sc->status_map); 680 } 681 682 for (i = 0; i < IPW_NTBD; i++) 683 ipw_release_sbd(sc, &sc->stbd_list[i]); 684 685 if (sc->cmd_map != NULL) 686 bus_dmamap_destroy(sc->sc_dmat, sc->cmd_map); 687 688 if (sc->hdr_list != NULL) { 689 bus_dmamap_unload(sc->sc_dmat, sc->hdr_map); 690 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->hdr_list, 691 IPW_NDATA * sizeof(struct ipw_hdr)); 692 } 693 if (sc->hdr_map != NULL) { 694 bus_dmamem_free(sc->sc_dmat, &sc->hdr_seg, 1); 695 bus_dmamap_destroy(sc->sc_dmat, sc->hdr_map); 696 } 697 698 for (i = 0; i < IPW_NDATA; i++) 699 bus_dmamap_destroy(sc->sc_dmat, sc->tx_sbuf_list[i].map); 700 701 for (i = 0; i < IPW_NRBD; i++) { 702 sbuf = &sc->rx_sbuf_list[i]; 703 if (sbuf->map != NULL) { 704 if (sbuf->m != NULL) { 705 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 706 m_freem(sbuf->m); 707 } 708 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 709 } 710 } 711 712 } 713 714 static int 715 ipw_media_change(struct ifnet *ifp) 716 { 717 int error; 718 719 error = ieee80211_media_change(ifp); 720 if (error != ENETRESET) 721 return error; 722 723 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 724 ipw_init(ifp); 725 726 return 0; 727 } 728 729 /* 730 * The firmware automatically adapts the transmit speed. We report the current 731 * transmit speed here. 732 */ 733 static void 734 ipw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 735 { 736 #define N(a) (sizeof (a) / sizeof (a[0])) 737 struct ipw_softc *sc = ifp->if_softc; 738 struct ieee80211com *ic = &sc->sc_ic; 739 static const struct { 740 uint32_t val; 741 int rate; 742 } rates[] = { 743 { IPW_RATE_DS1, 2 }, 744 { IPW_RATE_DS2, 4 }, 745 { IPW_RATE_DS5, 11 }, 746 { IPW_RATE_DS11, 22 }, 747 }; 748 uint32_t val; 749 int rate, i; 750 751 imr->ifm_status = IFM_AVALID; 752 imr->ifm_active = IFM_IEEE80211; 753 if (ic->ic_state == IEEE80211_S_RUN) 754 imr->ifm_status |= IFM_ACTIVE; 755 756 /* read current transmission rate from adapter */ 757 val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE) & 0xf; 758 759 /* convert ipw rate to 802.11 rate */ 760 for (i = 0; i < N(rates) && rates[i].val != val; i++); 761 rate = (i < N(rates)) ? rates[i].rate : 0; 762 763 imr->ifm_active |= IFM_IEEE80211_11B; 764 imr->ifm_active |= ieee80211_rate2media(ic, rate, IEEE80211_MODE_11B); 765 switch (ic->ic_opmode) { 766 case IEEE80211_M_STA: 767 break; 768 769 case IEEE80211_M_IBSS: 770 imr->ifm_active |= IFM_IEEE80211_ADHOC; 771 break; 772 773 case IEEE80211_M_MONITOR: 774 imr->ifm_active |= IFM_IEEE80211_MONITOR; 775 break; 776 777 case IEEE80211_M_AHDEMO: 778 case IEEE80211_M_HOSTAP: 779 /* should not get there */ 780 break; 781 } 782 #undef N 783 } 784 785 static int 786 ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, 787 int arg) 788 { 789 struct ifnet *ifp = ic->ic_ifp; 790 struct ipw_softc *sc = ifp->if_softc; 791 struct ieee80211_node *ni; 792 uint8_t macaddr[IEEE80211_ADDR_LEN]; 793 uint32_t len; 794 struct ipw_rx_radiotap_header *wr = &sc->sc_rxtap; 795 struct ipw_tx_radiotap_header *wt = &sc->sc_txtap; 796 797 switch (nstate) { 798 case IEEE80211_S_INIT: 799 break; 800 default: 801 KASSERT(ic->ic_curchan != IEEE80211_CHAN_ANYC); 802 KASSERT(ic->ic_curchan != NULL); 803 wt->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 804 wt->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 805 wr->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 806 wr->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 807 break; 808 } 809 810 switch (nstate) { 811 case IEEE80211_S_RUN: 812 DELAY(200); /* firmware needs a short delay here */ 813 814 len = IEEE80211_ADDR_LEN; 815 ipw_read_table2(sc, IPW_INFO_CURRENT_BSSID, macaddr, &len); 816 817 ni = ieee80211_find_node(&ic->ic_scan, macaddr); 818 if (ni == NULL) 819 break; 820 821 ieee80211_ref_node(ni); 822 ieee80211_sta_join(ic, ni); 823 ieee80211_node_authorize(ni); 824 825 if (ic->ic_opmode == IEEE80211_M_STA) 826 ieee80211_notify_node_join(ic, ni, 1); 827 break; 828 829 case IEEE80211_S_INIT: 830 case IEEE80211_S_SCAN: 831 case IEEE80211_S_AUTH: 832 case IEEE80211_S_ASSOC: 833 break; 834 } 835 836 ic->ic_state = nstate; 837 return 0; 838 } 839 840 /* 841 * Read 16 bits at address 'addr' from the serial EEPROM. 842 */ 843 static uint16_t 844 ipw_read_prom_word(struct ipw_softc *sc, uint8_t addr) 845 { 846 uint32_t tmp; 847 uint16_t val; 848 int n; 849 850 /* clock C once before the first command */ 851 IPW_EEPROM_CTL(sc, 0); 852 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 853 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 854 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 855 856 /* write start bit (1) */ 857 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 858 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 859 860 /* write READ opcode (10) */ 861 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 862 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 863 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 864 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 865 866 /* write address A7-A0 */ 867 for (n = 7; n >= 0; n--) { 868 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 869 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D)); 870 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 871 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D) | IPW_EEPROM_C); 872 } 873 874 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 875 876 /* read data Q15-Q0 */ 877 val = 0; 878 for (n = 15; n >= 0; n--) { 879 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 880 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 881 tmp = MEM_READ_4(sc, IPW_MEM_EEPROM_CTL); 882 val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n; 883 } 884 885 IPW_EEPROM_CTL(sc, 0); 886 887 /* clear Chip Select and clock C */ 888 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 889 IPW_EEPROM_CTL(sc, 0); 890 IPW_EEPROM_CTL(sc, IPW_EEPROM_C); 891 892 return le16toh(val); 893 } 894 895 static void 896 ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 897 { 898 struct ipw_cmd *cmd; 899 900 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof (struct ipw_cmd), 901 BUS_DMASYNC_POSTREAD); 902 903 cmd = mtod(sbuf->m, struct ipw_cmd *); 904 905 DPRINTFN(2, ("cmd ack'ed (%u, %u, %u, %u, %u)\n", le32toh(cmd->type), 906 le32toh(cmd->subtype), le32toh(cmd->seq), le32toh(cmd->len), 907 le32toh(cmd->status))); 908 909 wakeup(&sc->cmd); 910 } 911 912 static void 913 ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 914 { 915 struct ieee80211com *ic = &sc->sc_ic; 916 struct ifnet *ifp = sc->sc_ic.ic_ifp; 917 uint32_t state; 918 919 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof state, 920 BUS_DMASYNC_POSTREAD); 921 922 state = le32toh(*mtod(sbuf->m, uint32_t *)); 923 924 DPRINTFN(2, ("entering state %u\n", state)); 925 926 switch (state) { 927 case IPW_STATE_ASSOCIATED: 928 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 929 break; 930 931 case IPW_STATE_SCANNING: 932 /* don't leave run state on background scan */ 933 if (ic->ic_state != IEEE80211_S_RUN) 934 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 935 936 ic->ic_flags |= IEEE80211_F_SCAN; 937 break; 938 939 case IPW_STATE_SCAN_COMPLETE: 940 ieee80211_notify_scan_done(ic); 941 ic->ic_flags &= ~IEEE80211_F_SCAN; 942 break; 943 944 case IPW_STATE_ASSOCIATION_LOST: 945 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 946 break; 947 948 case IPW_STATE_RADIO_DISABLED: 949 ic->ic_ifp->if_flags &= ~IFF_UP; 950 ipw_stop(ifp, 1); 951 break; 952 } 953 } 954 955 /* 956 * XXX: Hack to set the current channel to the value advertised in beacons or 957 * probe responses. Only used during AP detection. 958 */ 959 static void 960 ipw_fix_channel(struct ieee80211com *ic, struct mbuf *m) 961 { 962 struct ieee80211_frame *wh; 963 uint8_t subtype; 964 uint8_t *frm, *efrm; 965 966 wh = mtod(m, struct ieee80211_frame *); 967 968 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_MGT) 969 return; 970 971 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 972 973 if (subtype != IEEE80211_FC0_SUBTYPE_BEACON && 974 subtype != IEEE80211_FC0_SUBTYPE_PROBE_RESP) 975 return; 976 977 frm = (uint8_t *)(wh + 1); 978 efrm = mtod(m, uint8_t *) + m->m_len; 979 980 frm += 12; /* skip tstamp, bintval and capinfo fields */ 981 while (frm < efrm) { 982 if (*frm == IEEE80211_ELEMID_DSPARMS) 983 #if IEEE80211_CHAN_MAX < 255 984 if (frm[2] <= IEEE80211_CHAN_MAX) 985 #endif 986 ic->ic_curchan = &ic->ic_channels[frm[2]]; 987 988 frm += frm[1] + 2; 989 } 990 } 991 992 static void 993 ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 994 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 995 { 996 struct ieee80211com *ic = &sc->sc_ic; 997 struct ifnet *ifp = &sc->sc_if; 998 struct mbuf *mnew, *m; 999 struct ieee80211_frame *wh; 1000 struct ieee80211_node *ni; 1001 int error; 1002 1003 DPRINTFN(5, ("received frame len=%u, rssi=%u\n", le32toh(status->len), 1004 status->rssi)); 1005 1006 if (le32toh(status->len) < sizeof (struct ieee80211_frame_min) || 1007 le32toh(status->len) > MCLBYTES) 1008 return; 1009 1010 /* 1011 * Try to allocate a new mbuf for this ring element and load it before 1012 * processing the current mbuf. If the ring element cannot be loaded, 1013 * drop the received packet and reuse the old mbuf. In the unlikely 1014 * case that the old mbuf can't be reloaded either, explicitly panic. 1015 */ 1016 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1017 if (mnew == NULL) { 1018 aprint_error_dev(&sc->sc_dev, "could not allocate rx mbuf\n"); 1019 ifp->if_ierrors++; 1020 return; 1021 } 1022 1023 MCLGET(mnew, M_DONTWAIT); 1024 if (!(mnew->m_flags & M_EXT)) { 1025 aprint_error_dev(&sc->sc_dev, "could not allocate rx mbuf cluster\n"); 1026 m_freem(mnew); 1027 ifp->if_ierrors++; 1028 return; 1029 } 1030 1031 mnew->m_pkthdr.len = mnew->m_len = mnew->m_ext.ext_size; 1032 1033 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, le32toh(status->len), 1034 BUS_DMASYNC_POSTREAD); 1035 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1036 1037 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, mnew, 1038 BUS_DMA_READ | BUS_DMA_NOWAIT); 1039 if (error != 0) { 1040 aprint_error_dev(&sc->sc_dev, "could not load rx buf DMA map\n"); 1041 m_freem(mnew); 1042 1043 /* try to reload the old mbuf */ 1044 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, 1045 sbuf->m, BUS_DMA_READ | BUS_DMA_NOWAIT); 1046 if (error != 0) { 1047 /* very unlikely that it will fail... */ 1048 panic("%s: unable to remap rx buf", 1049 device_xname(&sc->sc_dev)); 1050 } 1051 ifp->if_ierrors++; 1052 return; 1053 } 1054 1055 /* 1056 * New mbuf successfully loaded, update Rx ring and continue 1057 * processing. 1058 */ 1059 m = sbuf->m; 1060 sbuf->m = mnew; 1061 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 1062 1063 /* finalize mbuf */ 1064 m->m_pkthdr.rcvif = ifp; 1065 m->m_pkthdr.len = m->m_len = le32toh(status->len); 1066 1067 #if NBPFILTER > 0 1068 if (sc->sc_drvbpf != NULL) { 1069 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 1070 1071 tap->wr_antsignal = status->rssi; 1072 1073 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 1074 } 1075 #endif 1076 1077 if (ic->ic_state == IEEE80211_S_SCAN) 1078 ipw_fix_channel(ic, m); 1079 1080 wh = mtod(m, struct ieee80211_frame *); 1081 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 1082 1083 /* send the frame to the 802.11 layer */ 1084 ieee80211_input(ic, m, ni, status->rssi, 0); 1085 1086 /* node is no longer needed */ 1087 ieee80211_free_node(ni); 1088 1089 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, 1090 sbuf->map->dm_mapsize, BUS_DMASYNC_PREREAD); 1091 } 1092 1093 static void 1094 ipw_rx_intr(struct ipw_softc *sc) 1095 { 1096 struct ipw_status *status; 1097 struct ipw_soft_bd *sbd; 1098 struct ipw_soft_buf *sbuf; 1099 uint32_t r, i; 1100 1101 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1102 return; 1103 1104 r = CSR_READ_4(sc, IPW_CSR_RX_READ); 1105 1106 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 1107 1108 /* firmware was killed, stop processing received frames */ 1109 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1110 return; 1111 1112 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 1113 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1114 BUS_DMASYNC_POSTREAD); 1115 1116 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 1117 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 1118 BUS_DMASYNC_POSTREAD); 1119 1120 status = &sc->status_list[i]; 1121 sbd = &sc->srbd_list[i]; 1122 sbuf = sbd->priv; 1123 1124 switch (le16toh(status->code) & 0xf) { 1125 case IPW_STATUS_CODE_COMMAND: 1126 ipw_command_intr(sc, sbuf); 1127 break; 1128 1129 case IPW_STATUS_CODE_NEWSTATE: 1130 ipw_newstate_intr(sc, sbuf); 1131 break; 1132 1133 case IPW_STATUS_CODE_DATA_802_3: 1134 case IPW_STATUS_CODE_DATA_802_11: 1135 ipw_data_intr(sc, status, sbd, sbuf); 1136 break; 1137 1138 case IPW_STATUS_CODE_NOTIFICATION: 1139 DPRINTFN(2, ("received notification\n")); 1140 break; 1141 1142 default: 1143 aprint_error_dev(&sc->sc_dev, "unknown status code %u\n", 1144 le16toh(status->code)); 1145 } 1146 1147 sbd->bd->flags = 0; 1148 1149 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 1150 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1151 BUS_DMASYNC_PREREAD); 1152 1153 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 1154 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 1155 BUS_DMASYNC_PREREAD); 1156 } 1157 1158 /* Tell the firmware what we have processed */ 1159 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 1160 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 1161 } 1162 1163 static void 1164 ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 1165 { 1166 struct ieee80211com *ic; 1167 struct ipw_soft_hdr *shdr; 1168 struct ipw_soft_buf *sbuf; 1169 1170 switch (sbd->type) { 1171 case IPW_SBD_TYPE_COMMAND: 1172 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 1173 0, sizeof(struct ipw_cmd), BUS_DMASYNC_POSTWRITE); 1174 /* bus_dmamap_unload(sc->sc_dmat, sc->cmd_map); */ 1175 break; 1176 1177 case IPW_SBD_TYPE_HEADER: 1178 shdr = sbd->priv; 1179 bus_dmamap_sync(sc->sc_dmat, sc->hdr_map, 1180 shdr->offset, sizeof(struct ipw_hdr), BUS_DMASYNC_POSTWRITE); 1181 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 1182 break; 1183 1184 case IPW_SBD_TYPE_DATA: 1185 ic = &sc->sc_ic; 1186 sbuf = sbd->priv; 1187 1188 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 1189 0, MCLBYTES, BUS_DMASYNC_POSTWRITE); 1190 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1191 m_freem(sbuf->m); 1192 if (sbuf->ni != NULL) 1193 ieee80211_free_node(sbuf->ni); 1194 /* kill watchdog timer */ 1195 sc->sc_tx_timer = 0; 1196 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 1197 break; 1198 } 1199 sbd->type = IPW_SBD_TYPE_NOASSOC; 1200 } 1201 1202 static void 1203 ipw_tx_intr(struct ipw_softc *sc) 1204 { 1205 struct ifnet *ifp = &sc->sc_if; 1206 struct ipw_soft_bd *sbd; 1207 uint32_t r, i; 1208 1209 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1210 return; 1211 1212 r = CSR_READ_4(sc, IPW_CSR_TX_READ); 1213 1214 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) { 1215 sbd = &sc->stbd_list[i]; 1216 1217 if (sbd->type == IPW_SBD_TYPE_DATA) 1218 ifp->if_opackets++; 1219 1220 ipw_release_sbd(sc, sbd); 1221 sc->txfree++; 1222 } 1223 1224 /* remember what the firmware has processed */ 1225 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 1226 1227 /* Call start() since some buffer descriptors have been released */ 1228 ifp->if_flags &= ~IFF_OACTIVE; 1229 (*ifp->if_start)(ifp); 1230 } 1231 1232 static int 1233 ipw_intr(void *arg) 1234 { 1235 struct ipw_softc *sc = arg; 1236 uint32_t r; 1237 1238 r = CSR_READ_4(sc, IPW_CSR_INTR); 1239 if (r == 0 || r == 0xffffffff) 1240 return 0; 1241 1242 /* Disable interrupts */ 1243 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1244 1245 if (r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR)) { 1246 aprint_error_dev(&sc->sc_dev, "fatal error\n"); 1247 sc->sc_ic.ic_ifp->if_flags &= ~IFF_UP; 1248 ipw_stop(&sc->sc_if, 1); 1249 } 1250 1251 if (r & IPW_INTR_FW_INIT_DONE) { 1252 if (!(r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR))) 1253 wakeup(sc); 1254 } 1255 1256 if (r & IPW_INTR_RX_TRANSFER) 1257 ipw_rx_intr(sc); 1258 1259 if (r & IPW_INTR_TX_TRANSFER) 1260 ipw_tx_intr(sc); 1261 1262 /* Acknowledge all interrupts */ 1263 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 1264 1265 /* Re-enable interrupts */ 1266 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1267 1268 return 0; 1269 } 1270 1271 /* 1272 * Send a command to the firmware and wait for the acknowledgement. 1273 */ 1274 static int 1275 ipw_cmd(struct ipw_softc *sc, uint32_t type, void *data, uint32_t len) 1276 { 1277 struct ipw_soft_bd *sbd; 1278 1279 sbd = &sc->stbd_list[sc->txcur]; 1280 1281 sc->cmd.type = htole32(type); 1282 sc->cmd.subtype = 0; 1283 sc->cmd.len = htole32(len); 1284 sc->cmd.seq = 0; 1285 1286 (void)memcpy(sc->cmd.data, data, len); 1287 1288 sbd->type = IPW_SBD_TYPE_COMMAND; 1289 sbd->bd->physaddr = htole32(sc->cmd_map->dm_segs[0].ds_addr); 1290 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 1291 sbd->bd->nfrag = 1; 1292 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 1293 IPW_BD_FLAG_TX_LAST_FRAGMENT; 1294 1295 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 0, sizeof (struct ipw_cmd), 1296 BUS_DMASYNC_PREWRITE); 1297 1298 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1299 sc->txcur * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1300 BUS_DMASYNC_PREWRITE); 1301 1302 DPRINTFN(2, ("sending command (%u, %u, %u, %u)\n", type, 0, 0, len)); 1303 1304 /* kick firmware */ 1305 sc->txfree--; 1306 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1307 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1308 1309 /* Wait at most one second for command to complete */ 1310 return tsleep(&sc->cmd, 0, "ipwcmd", hz); 1311 } 1312 1313 static int 1314 ipw_tx_start(struct ifnet *ifp, struct mbuf *m0, struct ieee80211_node *ni) 1315 { 1316 struct ipw_softc *sc = ifp->if_softc; 1317 struct ieee80211com *ic = &sc->sc_ic; 1318 struct ieee80211_frame *wh; 1319 struct ipw_soft_bd *sbd; 1320 struct ipw_soft_hdr *shdr; 1321 struct ipw_soft_buf *sbuf; 1322 struct ieee80211_key *k; 1323 struct mbuf *mnew; 1324 int error, i; 1325 1326 wh = mtod(m0, struct ieee80211_frame *); 1327 1328 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1329 k = ieee80211_crypto_encap(ic, ni, m0); 1330 if (k == NULL) { 1331 m_freem(m0); 1332 return ENOBUFS; 1333 } 1334 1335 /* packet header may have moved, reset our local pointer */ 1336 wh = mtod(m0, struct ieee80211_frame *); 1337 } 1338 1339 #if NBPFILTER > 0 1340 if (sc->sc_drvbpf != NULL) { 1341 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 1342 1343 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 1344 } 1345 #endif 1346 1347 shdr = TAILQ_FIRST(&sc->sc_free_shdr); 1348 sbuf = TAILQ_FIRST(&sc->sc_free_sbuf); 1349 KASSERT(shdr != NULL && sbuf != NULL); 1350 1351 shdr->hdr->type = htole32(IPW_HDR_TYPE_SEND); 1352 shdr->hdr->subtype = 0; 1353 shdr->hdr->encrypted = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0; 1354 shdr->hdr->encrypt = 0; 1355 shdr->hdr->keyidx = 0; 1356 shdr->hdr->keysz = 0; 1357 shdr->hdr->fragmentsz = 0; 1358 IEEE80211_ADDR_COPY(shdr->hdr->src_addr, wh->i_addr2); 1359 if (ic->ic_opmode == IEEE80211_M_STA) 1360 IEEE80211_ADDR_COPY(shdr->hdr->dst_addr, wh->i_addr3); 1361 else 1362 IEEE80211_ADDR_COPY(shdr->hdr->dst_addr, wh->i_addr1); 1363 1364 /* trim IEEE802.11 header */ 1365 m_adj(m0, sizeof (struct ieee80211_frame)); 1366 1367 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m0, BUS_DMA_NOWAIT); 1368 if (error != 0 && error != EFBIG) { 1369 aprint_error_dev(&sc->sc_dev, "could not map mbuf (error %d)\n", 1370 error); 1371 m_freem(m0); 1372 return error; 1373 } 1374 1375 if (error != 0) { 1376 /* too many fragments, linearize */ 1377 1378 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1379 if (mnew == NULL) { 1380 m_freem(m0); 1381 return ENOMEM; 1382 } 1383 1384 M_COPY_PKTHDR(mnew, m0); 1385 1386 /* If the data won't fit in the header, get a cluster */ 1387 if (m0->m_pkthdr.len > MHLEN) { 1388 MCLGET(mnew, M_DONTWAIT); 1389 if (!(mnew->m_flags & M_EXT)) { 1390 m_freem(m0); 1391 m_freem(mnew); 1392 return ENOMEM; 1393 } 1394 } 1395 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(mnew, void *)); 1396 m_freem(m0); 1397 mnew->m_len = mnew->m_pkthdr.len; 1398 m0 = mnew; 1399 1400 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m0, 1401 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1402 if (error != 0) { 1403 aprint_error_dev(&sc->sc_dev, "could not map mbuf (error %d)\n", error); 1404 m_freem(m0); 1405 return error; 1406 } 1407 } 1408 1409 TAILQ_REMOVE(&sc->sc_free_sbuf, sbuf, next); 1410 TAILQ_REMOVE(&sc->sc_free_shdr, shdr, next); 1411 1412 sbd = &sc->stbd_list[sc->txcur]; 1413 sbd->type = IPW_SBD_TYPE_HEADER; 1414 sbd->priv = shdr; 1415 sbd->bd->physaddr = htole32(shdr->addr); 1416 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 1417 sbd->bd->nfrag = 1 + sbuf->map->dm_nsegs; 1418 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 1419 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1420 1421 DPRINTFN(5, ("sending tx hdr (%u, %u, %u, %u, )\n", 1422 shdr->hdr->type, shdr->hdr->subtype, shdr->hdr->encrypted, 1423 shdr->hdr->encrypt)); 1424 DPRINTFN(5, ("%s->", ether_sprintf(shdr->hdr->src_addr))); 1425 DPRINTFN(5, ("%s\n", ether_sprintf(shdr->hdr->dst_addr))); 1426 1427 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1428 sc->txcur * sizeof (struct ipw_bd), 1429 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1430 1431 sc->txfree--; 1432 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1433 1434 sbuf->m = m0; 1435 sbuf->ni = ni; 1436 1437 for (i = 0; i < sbuf->map->dm_nsegs; i++) { 1438 sbd = &sc->stbd_list[sc->txcur]; 1439 1440 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[i].ds_addr); 1441 sbd->bd->len = htole32(sbuf->map->dm_segs[i].ds_len); 1442 sbd->bd->nfrag = 0; 1443 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 1444 if (i == sbuf->map->dm_nsegs - 1) { 1445 sbd->type = IPW_SBD_TYPE_DATA; 1446 sbd->priv = sbuf; 1447 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 1448 } else { 1449 sbd->type = IPW_SBD_TYPE_NOASSOC; 1450 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1451 } 1452 1453 DPRINTFN(5, ("sending fragment (%d, %d)\n", i, 1454 (int)sbuf->map->dm_segs[i].ds_len)); 1455 1456 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1457 sc->txcur * sizeof (struct ipw_bd), 1458 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1459 1460 sc->txfree--; 1461 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1462 } 1463 1464 bus_dmamap_sync(sc->sc_dmat, sc->hdr_map, shdr->offset, 1465 sizeof (struct ipw_hdr), BUS_DMASYNC_PREWRITE); 1466 1467 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, MCLBYTES, 1468 BUS_DMASYNC_PREWRITE); 1469 1470 /* Inform firmware about this new packet */ 1471 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1472 1473 return 0; 1474 } 1475 1476 static void 1477 ipw_start(struct ifnet *ifp) 1478 { 1479 struct ipw_softc *sc = ifp->if_softc; 1480 struct ieee80211com *ic = &sc->sc_ic; 1481 struct mbuf *m0; 1482 struct ether_header *eh; 1483 struct ieee80211_node *ni; 1484 1485 1486 if (ic->ic_state != IEEE80211_S_RUN) 1487 return; 1488 1489 for (;;) { 1490 IF_DEQUEUE(&ifp->if_snd, m0); 1491 if (m0 == NULL) 1492 break; 1493 1494 if (sc->txfree < 1 + IPW_MAX_NSEG) { 1495 IF_PREPEND(&ifp->if_snd, m0); 1496 ifp->if_flags |= IFF_OACTIVE; 1497 break; 1498 } 1499 1500 if (m0->m_len < sizeof (struct ether_header) && 1501 (m0 = m_pullup(m0, sizeof (struct ether_header))) == NULL) 1502 continue; 1503 1504 eh = mtod(m0, struct ether_header *); 1505 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1506 if (ni == NULL) { 1507 m_freem(m0); 1508 continue; 1509 } 1510 1511 #if NBPFILTER > 0 1512 if (ifp->if_bpf != NULL) 1513 bpf_mtap(ifp->if_bpf, m0); 1514 #endif 1515 1516 m0 = ieee80211_encap(ic, m0, ni); 1517 if (m0 == NULL) { 1518 ieee80211_free_node(ni); 1519 continue; 1520 } 1521 1522 #if NBPFILTER > 0 1523 if (ic->ic_rawbpf != NULL) 1524 bpf_mtap(ic->ic_rawbpf, m0); 1525 #endif 1526 1527 if (ipw_tx_start(ifp, m0, ni) != 0) { 1528 ieee80211_free_node(ni); 1529 ifp->if_oerrors++; 1530 break; 1531 } 1532 1533 /* start watchdog timer */ 1534 sc->sc_tx_timer = 5; 1535 ifp->if_timer = 1; 1536 } 1537 } 1538 1539 static void 1540 ipw_watchdog(struct ifnet *ifp) 1541 { 1542 struct ipw_softc *sc = ifp->if_softc; 1543 1544 ifp->if_timer = 0; 1545 1546 if (sc->sc_tx_timer > 0) { 1547 if (--sc->sc_tx_timer == 0) { 1548 aprint_error_dev(&sc->sc_dev, "device timeout\n"); 1549 ifp->if_oerrors++; 1550 ifp->if_flags &= ~IFF_UP; 1551 ipw_stop(ifp, 1); 1552 return; 1553 } 1554 ifp->if_timer = 1; 1555 } 1556 1557 ieee80211_watchdog(&sc->sc_ic); 1558 } 1559 1560 static int 1561 ipw_get_table1(struct ipw_softc *sc, uint32_t *tbl) 1562 { 1563 uint32_t addr, size, i; 1564 1565 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1566 return ENOTTY; 1567 1568 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, sc->table1_base); 1569 1570 size = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 1571 if (suword(tbl, size) != 0) 1572 return EFAULT; 1573 1574 for (i = 1, ++tbl; i < size; i++, tbl++) { 1575 addr = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 1576 if (suword(tbl, MEM_READ_4(sc, addr)) != 0) 1577 return EFAULT; 1578 } 1579 return 0; 1580 } 1581 1582 static int 1583 ipw_get_radio(struct ipw_softc *sc, int *ret) 1584 { 1585 uint32_t addr; 1586 1587 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1588 return ENOTTY; 1589 1590 addr = ipw_read_table1(sc, IPW_INFO_EEPROM_ADDRESS); 1591 if ((MEM_READ_4(sc, addr + 32) >> 24) & 1) { 1592 suword(ret, -1); 1593 return 0; 1594 } 1595 1596 if (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED) 1597 suword(ret, 0); 1598 else 1599 suword(ret, 1); 1600 1601 return 0; 1602 } 1603 1604 static int 1605 ipw_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1606 { 1607 #define IS_RUNNING(ifp) \ 1608 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 1609 1610 struct ipw_softc *sc = ifp->if_softc; 1611 struct ieee80211com *ic = &sc->sc_ic; 1612 struct ifreq *ifr = (struct ifreq *)data; 1613 int s, error = 0; 1614 1615 s = splnet(); 1616 1617 switch (cmd) { 1618 case SIOCSIFFLAGS: 1619 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 1620 break; 1621 if (ifp->if_flags & IFF_UP) { 1622 if (!(ifp->if_flags & IFF_RUNNING)) 1623 ipw_init(ifp); 1624 } else { 1625 if (ifp->if_flags & IFF_RUNNING) 1626 ipw_stop(ifp, 1); 1627 } 1628 break; 1629 1630 case SIOCADDMULTI: 1631 case SIOCDELMULTI: 1632 /* XXX no h/w multicast filter? --dyoung */ 1633 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1634 /* setup multicast filter, etc */ 1635 error = 0; 1636 } 1637 break; 1638 1639 case SIOCGTABLE1: 1640 error = ipw_get_table1(sc, (uint32_t *)ifr->ifr_data); 1641 break; 1642 1643 case SIOCGRADIO: 1644 error = ipw_get_radio(sc, (int *)ifr->ifr_data); 1645 break; 1646 1647 case SIOCSIFMEDIA: 1648 if (ifr->ifr_media & IFM_IEEE80211_ADHOC) 1649 strlcpy(sc->sc_fwname, "ipw2100-1.2-i.fw", 1650 sizeof(sc->sc_fwname)); 1651 else if (ifr->ifr_media & IFM_IEEE80211_MONITOR) 1652 strlcpy(sc->sc_fwname, "ipw2100-1.2-p.fw", 1653 sizeof(sc->sc_fwname)); 1654 else 1655 strlcpy(sc->sc_fwname, "ipw2100-1.2.fw", 1656 sizeof(sc->sc_fwname)); 1657 1658 ipw_free_firmware(sc); 1659 /* FALLTRHOUGH */ 1660 default: 1661 error = ieee80211_ioctl(&sc->sc_ic, cmd, data); 1662 if (error != ENETRESET) 1663 break; 1664 1665 if (error == ENETRESET) { 1666 if (IS_RUNNING(ifp) && 1667 (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)) 1668 ipw_init(ifp); 1669 error = 0; 1670 } 1671 1672 } 1673 1674 splx(s); 1675 return error; 1676 #undef IS_RUNNING 1677 } 1678 1679 static uint32_t 1680 ipw_read_table1(struct ipw_softc *sc, uint32_t off) 1681 { 1682 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 1683 } 1684 1685 static void 1686 ipw_write_table1(struct ipw_softc *sc, uint32_t off, uint32_t info) 1687 { 1688 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 1689 } 1690 1691 static int 1692 ipw_read_table2(struct ipw_softc *sc, uint32_t off, void *buf, uint32_t *len) 1693 { 1694 uint32_t addr, info; 1695 uint16_t count, size; 1696 uint32_t total; 1697 1698 /* addr[4] + count[2] + size[2] */ 1699 addr = MEM_READ_4(sc, sc->table2_base + off); 1700 info = MEM_READ_4(sc, sc->table2_base + off + 4); 1701 1702 count = info >> 16; 1703 size = info & 0xffff; 1704 total = count * size; 1705 1706 if (total > *len) { 1707 *len = total; 1708 return EINVAL; 1709 } 1710 1711 *len = total; 1712 ipw_read_mem_1(sc, addr, buf, total); 1713 1714 return 0; 1715 } 1716 1717 static void 1718 ipw_stop_master(struct ipw_softc *sc) 1719 { 1720 int ntries; 1721 1722 /* disable interrupts */ 1723 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1724 1725 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1726 for (ntries = 0; ntries < 50; ntries++) { 1727 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1728 break; 1729 DELAY(10); 1730 } 1731 if (ntries == 50) 1732 aprint_error_dev(&sc->sc_dev, "timeout waiting for master\n"); 1733 1734 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1735 IPW_RST_PRINCETON_RESET); 1736 1737 sc->flags &= ~IPW_FLAG_FW_INITED; 1738 } 1739 1740 static int 1741 ipw_reset(struct ipw_softc *sc) 1742 { 1743 int ntries; 1744 1745 ipw_stop_master(sc); 1746 1747 /* move adapter to D0 state */ 1748 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1749 IPW_CTL_INIT); 1750 1751 /* wait for clock stabilization */ 1752 for (ntries = 0; ntries < 1000; ntries++) { 1753 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY) 1754 break; 1755 DELAY(200); 1756 } 1757 if (ntries == 1000) 1758 return EIO; 1759 1760 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1761 IPW_RST_SW_RESET); 1762 1763 DELAY(10); 1764 1765 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1766 IPW_CTL_INIT); 1767 1768 return 0; 1769 } 1770 1771 /* 1772 * Upload the microcode to the device. 1773 */ 1774 static int 1775 ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size) 1776 { 1777 int ntries; 1778 1779 MEM_WRITE_4(sc, 0x3000e0, 0x80000000); 1780 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1781 1782 MEM_WRITE_2(sc, 0x220000, 0x0703); 1783 MEM_WRITE_2(sc, 0x220000, 0x0707); 1784 1785 MEM_WRITE_1(sc, 0x210014, 0x72); 1786 MEM_WRITE_1(sc, 0x210014, 0x72); 1787 1788 MEM_WRITE_1(sc, 0x210000, 0x40); 1789 MEM_WRITE_1(sc, 0x210000, 0x00); 1790 MEM_WRITE_1(sc, 0x210000, 0x40); 1791 1792 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1793 1794 MEM_WRITE_1(sc, 0x210000, 0x00); 1795 MEM_WRITE_1(sc, 0x210000, 0x00); 1796 MEM_WRITE_1(sc, 0x210000, 0x80); 1797 1798 MEM_WRITE_2(sc, 0x220000, 0x0703); 1799 MEM_WRITE_2(sc, 0x220000, 0x0707); 1800 1801 MEM_WRITE_1(sc, 0x210014, 0x72); 1802 MEM_WRITE_1(sc, 0x210014, 0x72); 1803 1804 MEM_WRITE_1(sc, 0x210000, 0x00); 1805 MEM_WRITE_1(sc, 0x210000, 0x80); 1806 1807 for (ntries = 0; ntries < 10; ntries++) { 1808 if (MEM_READ_1(sc, 0x210000) & 1) 1809 break; 1810 DELAY(10); 1811 } 1812 if (ntries == 10) { 1813 aprint_error_dev(&sc->sc_dev, "timeout waiting for ucode to initialize\n"); 1814 return EIO; 1815 } 1816 1817 MEM_WRITE_4(sc, 0x3000e0, 0); 1818 1819 return 0; 1820 } 1821 1822 /* set of macros to handle unaligned little endian data in firmware image */ 1823 #define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1824 #define GETLE16(p) ((p)[0] | (p)[1] << 8) 1825 static int 1826 ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size) 1827 { 1828 u_char *p, *end; 1829 uint32_t dst; 1830 uint16_t len; 1831 int error; 1832 1833 p = fw; 1834 end = fw + size; 1835 while (p < end) { 1836 dst = GETLE32(p); p += 4; 1837 len = GETLE16(p); p += 2; 1838 1839 ipw_write_mem_1(sc, dst, p, len); 1840 p += len; 1841 } 1842 1843 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1844 IPW_IO_LED_OFF); 1845 1846 /* enable interrupts */ 1847 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1848 1849 /* kick the firmware */ 1850 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1851 1852 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1853 IPW_CTL_ALLOW_STANDBY); 1854 1855 /* wait at most one second for firmware initialization to complete */ 1856 if ((error = tsleep(sc, 0, "ipwinit", hz)) != 0) { 1857 aprint_error_dev(&sc->sc_dev, "timeout waiting for firmware initialization " 1858 "to complete\n"); 1859 return error; 1860 } 1861 1862 CSR_WRITE_4(sc, IPW_CSR_IO, CSR_READ_4(sc, IPW_CSR_IO) | 1863 IPW_IO_GPIO1_MASK | IPW_IO_GPIO3_MASK); 1864 1865 return 0; 1866 } 1867 1868 /* 1869 * Store firmware into kernel memory so we can download it when we need to, 1870 * e.g when the adapter wakes up from suspend mode. 1871 */ 1872 static int 1873 ipw_cache_firmware(struct ipw_softc *sc) 1874 { 1875 struct ipw_firmware *fw = &sc->fw; 1876 struct ipw_firmware_hdr hdr; 1877 firmware_handle_t fwh; 1878 off_t fwsz, p; 1879 int error; 1880 1881 ipw_free_firmware(sc); 1882 1883 if (ipw_accept_eula == 0) { 1884 aprint_error_dev(&sc->sc_dev, 1885 "EULA not accepted, see hw.ipw.accept_eula\n"); 1886 return EPERM; 1887 } 1888 1889 if ((error = firmware_open("if_ipw", sc->sc_fwname, &fwh)) != 0) 1890 goto fail0; 1891 1892 fwsz = firmware_get_size(fwh); 1893 1894 if (fwsz < sizeof(hdr)) 1895 goto fail2; 1896 1897 if ((error = firmware_read(fwh, 0, &hdr, sizeof(hdr))) != 0) 1898 goto fail2; 1899 1900 fw->main_size = le32toh(hdr.main_size); 1901 fw->ucode_size = le32toh(hdr.ucode_size); 1902 1903 fw->main = firmware_malloc(fw->main_size); 1904 if (fw->main == NULL) { 1905 error = ENOMEM; 1906 goto fail1; 1907 } 1908 1909 fw->ucode = firmware_malloc(fw->ucode_size); 1910 if (fw->ucode == NULL) { 1911 error = ENOMEM; 1912 goto fail2; 1913 } 1914 1915 p = sizeof(hdr); 1916 if ((error = firmware_read(fwh, p, fw->main, fw->main_size)) != 0) 1917 goto fail3; 1918 1919 p += fw->main_size; 1920 if ((error = firmware_read(fwh, p, fw->ucode, fw->ucode_size)) != 0) 1921 goto fail3; 1922 1923 DPRINTF(("Firmware cached: main %u, ucode %u\n", fw->main_size, 1924 fw->ucode_size)); 1925 1926 sc->flags |= IPW_FLAG_FW_CACHED; 1927 1928 firmware_close(fwh); 1929 1930 return 0; 1931 1932 fail3: firmware_free(fw->ucode, 0); 1933 fail2: firmware_free(fw->main, 0); 1934 fail1: firmware_close(fwh); 1935 fail0: 1936 return error; 1937 } 1938 1939 static void 1940 ipw_free_firmware(struct ipw_softc *sc) 1941 { 1942 if (!(sc->flags & IPW_FLAG_FW_CACHED)) 1943 return; 1944 1945 firmware_free(sc->fw.main, 0); 1946 firmware_free(sc->fw.ucode, 0); 1947 1948 sc->flags &= ~IPW_FLAG_FW_CACHED; 1949 } 1950 1951 static int 1952 ipw_config(struct ipw_softc *sc) 1953 { 1954 struct ieee80211com *ic = &sc->sc_ic; 1955 struct ifnet *ifp = &sc->sc_if; 1956 struct ipw_security security; 1957 struct ieee80211_key *k; 1958 struct ipw_wep_key wepkey; 1959 struct ipw_scan_options options; 1960 struct ipw_configuration config; 1961 uint32_t data; 1962 int error, i; 1963 1964 switch (ic->ic_opmode) { 1965 case IEEE80211_M_STA: 1966 case IEEE80211_M_HOSTAP: 1967 data = htole32(IPW_MODE_BSS); 1968 break; 1969 1970 case IEEE80211_M_IBSS: 1971 case IEEE80211_M_AHDEMO: 1972 data = htole32(IPW_MODE_IBSS); 1973 break; 1974 1975 case IEEE80211_M_MONITOR: 1976 data = htole32(IPW_MODE_MONITOR); 1977 break; 1978 } 1979 DPRINTF(("Setting mode to %u\n", le32toh(data))); 1980 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 1981 if (error != 0) 1982 return error; 1983 1984 if (ic->ic_opmode == IEEE80211_M_IBSS || 1985 ic->ic_opmode == IEEE80211_M_MONITOR) { 1986 data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); 1987 DPRINTF(("Setting channel to %u\n", le32toh(data))); 1988 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 1989 if (error != 0) 1990 return error; 1991 } 1992 1993 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1994 DPRINTF(("Enabling adapter\n")); 1995 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1996 } 1997 1998 DPRINTF(("Setting MAC to %s\n", ether_sprintf(ic->ic_myaddr))); 1999 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 2000 IEEE80211_ADDR_LEN); 2001 if (error != 0) 2002 return error; 2003 2004 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 2005 IPW_CFG_PREAMBLE_AUTO | IPW_CFG_802_1x_ENABLE); 2006 2007 if (ic->ic_opmode == IEEE80211_M_IBSS) 2008 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 2009 if (ifp->if_flags & IFF_PROMISC) 2010 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 2011 config.bss_chan = htole32(0x3fff); /* channels 1-14 */ 2012 config.ibss_chan = htole32(0x7ff); /* channels 1-11 */ 2013 DPRINTF(("Setting adapter configuration 0x%08x\n", config.flags)); 2014 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 2015 if (error != 0) 2016 return error; 2017 2018 data = htole32(0x3); /* 1, 2 */ 2019 DPRINTF(("Setting basic tx rates to 0x%x\n", le32toh(data))); 2020 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 2021 if (error != 0) 2022 return error; 2023 2024 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 2025 DPRINTF(("Setting tx rates to 0x%x\n", le32toh(data))); 2026 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 2027 if (error != 0) 2028 return error; 2029 2030 data = htole32(IPW_POWER_MODE_CAM); 2031 DPRINTF(("Setting power mode to %u\n", le32toh(data))); 2032 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 2033 if (error != 0) 2034 return error; 2035 2036 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2037 data = htole32(32); /* default value */ 2038 DPRINTF(("Setting tx power index to %u\n", le32toh(data))); 2039 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 2040 sizeof data); 2041 if (error != 0) 2042 return error; 2043 } 2044 2045 data = htole32(ic->ic_rtsthreshold); 2046 DPRINTF(("Setting RTS threshold to %u\n", le32toh(data))); 2047 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 2048 if (error != 0) 2049 return error; 2050 2051 data = htole32(ic->ic_fragthreshold); 2052 DPRINTF(("Setting frag threshold to %u\n", le32toh(data))); 2053 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 2054 if (error != 0) 2055 return error; 2056 2057 #ifdef IPW_DEBUG 2058 if (ipw_debug > 0) { 2059 printf("Setting ESSID to "); 2060 ieee80211_print_essid(ic->ic_des_essid, ic->ic_des_esslen); 2061 printf("\n"); 2062 } 2063 #endif 2064 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ic->ic_des_essid, 2065 ic->ic_des_esslen); 2066 if (error != 0) 2067 return error; 2068 2069 /* no mandatory BSSID */ 2070 DPRINTF(("Setting mandatory BSSID to null\n")); 2071 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 2072 if (error != 0) 2073 return error; 2074 2075 if (ic->ic_flags & IEEE80211_F_DESBSSID) { 2076 DPRINTF(("Setting desired BSSID to %s\n", 2077 ether_sprintf(ic->ic_des_bssid))); 2078 error = ipw_cmd(sc, IPW_CMD_SET_DESIRED_BSSID, 2079 ic->ic_des_bssid, IEEE80211_ADDR_LEN); 2080 if (error != 0) 2081 return error; 2082 } 2083 2084 (void)memset(&security, 0, sizeof(security)); 2085 security.authmode = (ic->ic_bss->ni_authmode == IEEE80211_AUTH_SHARED) ? 2086 IPW_AUTH_SHARED : IPW_AUTH_OPEN; 2087 security.ciphers = htole32(IPW_CIPHER_NONE); 2088 DPRINTF(("Setting authmode to %u\n", security.authmode)); 2089 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 2090 sizeof security); 2091 if (error != 0) 2092 return error; 2093 2094 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 2095 k = ic->ic_crypto.cs_nw_keys; 2096 for (i = 0; i < IEEE80211_WEP_NKID; i++, k++) { 2097 if (k->wk_keylen == 0) 2098 continue; 2099 2100 wepkey.idx = i; 2101 wepkey.len = k->wk_keylen; 2102 memset(wepkey.key, 0, sizeof(wepkey.key)); 2103 memcpy(wepkey.key, k->wk_key, k->wk_keylen); 2104 DPRINTF(("Setting wep key index %u len %u\n", 2105 wepkey.idx, wepkey.len)); 2106 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY, &wepkey, 2107 sizeof wepkey); 2108 if (error != 0) 2109 return error; 2110 } 2111 2112 data = htole32(ic->ic_crypto.cs_def_txkey); 2113 DPRINTF(("Setting tx key index to %u\n", le32toh(data))); 2114 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY_INDEX, &data, 2115 sizeof data); 2116 if (error != 0) 2117 return error; 2118 } 2119 2120 data = htole32((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) ? IPW_WEPON : 0); 2121 DPRINTF(("Setting wep flags to 0x%x\n", le32toh(data))); 2122 error = ipw_cmd(sc, IPW_CMD_SET_WEP_FLAGS, &data, sizeof data); 2123 if (error != 0) 2124 return error; 2125 2126 #if 0 2127 struct ipw_wpa_ie ie; 2128 2129 memset(&ie, 0 sizeof(ie)); 2130 ie.len = htole32(sizeof (struct ieee80211_ie_wpa)); 2131 DPRINTF(("Setting wpa ie\n")); 2132 error = ipw_cmd(sc, IPW_CMD_SET_WPA_IE, &ie, sizeof ie); 2133 if (error != 0) 2134 return error; 2135 #endif 2136 2137 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2138 data = htole32(ic->ic_bintval); 2139 DPRINTF(("Setting beacon interval to %u\n", le32toh(data))); 2140 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 2141 sizeof data); 2142 if (error != 0) 2143 return error; 2144 } 2145 2146 options.flags = 0; 2147 options.channels = htole32(0x3fff); /* scan channels 1-14 */ 2148 DPRINTF(("Setting scan options to 0x%x\n", le32toh(options.flags))); 2149 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &options, sizeof options); 2150 if (error != 0) 2151 return error; 2152 2153 /* finally, enable adapter (start scanning for an access point) */ 2154 DPRINTF(("Enabling adapter\n")); 2155 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 2156 } 2157 2158 static int 2159 ipw_init(struct ifnet *ifp) 2160 { 2161 struct ipw_softc *sc = ifp->if_softc; 2162 struct ipw_firmware *fw = &sc->fw; 2163 2164 if (!(sc->flags & IPW_FLAG_FW_CACHED)) { 2165 if (ipw_cache_firmware(sc) != 0) { 2166 aprint_error_dev(&sc->sc_dev, "could not cache the firmware (%s)\n", 2167 sc->sc_fwname); 2168 goto fail; 2169 } 2170 } 2171 2172 ipw_stop(ifp, 0); 2173 2174 if (ipw_reset(sc) != 0) { 2175 aprint_error_dev(&sc->sc_dev, "could not reset adapter\n"); 2176 goto fail; 2177 } 2178 2179 if (ipw_load_ucode(sc, fw->ucode, fw->ucode_size) != 0) { 2180 aprint_error_dev(&sc->sc_dev, "could not load microcode\n"); 2181 goto fail; 2182 } 2183 2184 ipw_stop_master(sc); 2185 2186 /* 2187 * Setup tx, rx and status rings. 2188 */ 2189 sc->txold = IPW_NTBD - 1; 2190 sc->txcur = 0; 2191 sc->txfree = IPW_NTBD - 2; 2192 sc->rxcur = IPW_NRBD - 1; 2193 2194 CSR_WRITE_4(sc, IPW_CSR_TX_BASE, sc->tbd_map->dm_segs[0].ds_addr); 2195 CSR_WRITE_4(sc, IPW_CSR_TX_SIZE, IPW_NTBD); 2196 CSR_WRITE_4(sc, IPW_CSR_TX_READ, 0); 2197 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 2198 2199 CSR_WRITE_4(sc, IPW_CSR_RX_BASE, sc->rbd_map->dm_segs[0].ds_addr); 2200 CSR_WRITE_4(sc, IPW_CSR_RX_SIZE, IPW_NRBD); 2201 CSR_WRITE_4(sc, IPW_CSR_RX_READ, 0); 2202 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 2203 2204 CSR_WRITE_4(sc, IPW_CSR_STATUS_BASE, sc->status_map->dm_segs[0].ds_addr); 2205 2206 if (ipw_load_firmware(sc, fw->main, fw->main_size) != 0) { 2207 aprint_error_dev(&sc->sc_dev, "could not load firmware\n"); 2208 goto fail; 2209 } 2210 2211 sc->flags |= IPW_FLAG_FW_INITED; 2212 2213 /* retrieve information tables base addresses */ 2214 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 2215 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 2216 2217 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 2218 2219 if (ipw_config(sc) != 0) { 2220 aprint_error_dev(&sc->sc_dev, "device configuration failed\n"); 2221 goto fail; 2222 } 2223 2224 ifp->if_flags &= ~IFF_OACTIVE; 2225 ifp->if_flags |= IFF_RUNNING; 2226 2227 return 0; 2228 2229 fail: ifp->if_flags &= ~IFF_UP; 2230 ipw_stop(ifp, 0); 2231 2232 return EIO; 2233 } 2234 2235 static void 2236 ipw_stop(struct ifnet *ifp, int disable) 2237 { 2238 struct ipw_softc *sc = ifp->if_softc; 2239 struct ieee80211com *ic = &sc->sc_ic; 2240 int i; 2241 2242 ipw_stop_master(sc); 2243 2244 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 2245 2246 /* 2247 * Release tx buffers. 2248 */ 2249 for (i = 0; i < IPW_NTBD; i++) 2250 ipw_release_sbd(sc, &sc->stbd_list[i]); 2251 2252 sc->sc_tx_timer = 0; 2253 ifp->if_timer = 0; 2254 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2255 2256 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2257 } 2258 2259 static void 2260 ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2261 bus_size_t count) 2262 { 2263 for (; count > 0; offset++, datap++, count--) { 2264 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2265 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 2266 } 2267 } 2268 2269 static void 2270 ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2271 bus_size_t count) 2272 { 2273 for (; count > 0; offset++, datap++, count--) { 2274 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2275 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 2276 } 2277 } 2278 2279 SYSCTL_SETUP(sysctl_hw_ipw_accept_eula_setup, "sysctl hw.ipw.accept_eula") 2280 { 2281 const struct sysctlnode *rnode; 2282 const struct sysctlnode *cnode; 2283 2284 sysctl_createv(NULL, 0, NULL, &rnode, 2285 CTLFLAG_PERMANENT, 2286 CTLTYPE_NODE, "hw", 2287 NULL, 2288 NULL, 0, 2289 NULL, 0, 2290 CTL_HW, CTL_EOL); 2291 2292 sysctl_createv(NULL, 0, &rnode, &rnode, 2293 CTLFLAG_PERMANENT, 2294 CTLTYPE_NODE, "ipw", 2295 NULL, 2296 NULL, 0, 2297 NULL, 0, 2298 CTL_CREATE, CTL_EOL); 2299 2300 sysctl_createv(NULL, 0, &rnode, &cnode, 2301 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, 2302 CTLTYPE_INT, "accept_eula", 2303 SYSCTL_DESCR("Accept Intel EULA and permit use of ipw(4) firmware"), 2304 NULL, 0, 2305 &ipw_accept_eula, sizeof(ipw_accept_eula), 2306 CTL_CREATE, CTL_EOL); 2307 } 2308
Indexes created Mon Sep 29 21:09:56 GMT 2025