if_ipw.c revision 1.51
1 /* $NetBSD: if_ipw.c,v 1.51 2010/04/05 07:20:25 joerg Exp $ */ 2 /* FreeBSD: src/sys/dev/ipw/if_ipw.c,v 1.15 2005/11/13 17:17:40 damien Exp */ 3 4 /*- 5 * Copyright (c) 2004, 2005 6 * Damien Bergamini <damien.bergamini (at) free.fr>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: if_ipw.c,v 1.51 2010/04/05 07:20:25 joerg Exp $"); 33 34 /*- 35 * Intel(R) PRO/Wireless 2100 MiniPCI driver 36 * http://www.intel.com/network/connectivity/products/wireless/prowireless_mobile.htm 37 */ 38 39 40 #include <sys/param.h> 41 #include <sys/sockio.h> 42 #include <sys/sysctl.h> 43 #include <sys/mbuf.h> 44 #include <sys/kernel.h> 45 #include <sys/socket.h> 46 #include <sys/systm.h> 47 #include <sys/malloc.h> 48 #include <sys/conf.h> 49 50 #include <sys/bus.h> 51 #include <machine/endian.h> 52 #include <sys/intr.h> 53 54 #include <dev/pci/pcireg.h> 55 #include <dev/pci/pcivar.h> 56 #include <dev/pci/pcidevs.h> 57 58 #include <net/bpf.h> 59 #include <net/if.h> 60 #include <net/if_arp.h> 61 #include <net/if_dl.h> 62 #include <net/if_ether.h> 63 #include <net/if_media.h> 64 #include <net/if_types.h> 65 66 #include <net80211/ieee80211_var.h> 67 #include <net80211/ieee80211_radiotap.h> 68 69 #include <netinet/in.h> 70 #include <netinet/in_systm.h> 71 #include <netinet/in_var.h> 72 #include <netinet/ip.h> 73 74 #include <dev/firmload.h> 75 76 #include <dev/pci/if_ipwreg.h> 77 #include <dev/pci/if_ipwvar.h> 78 79 #ifdef IPW_DEBUG 80 #define DPRINTF(x) if (ipw_debug > 0) printf x 81 #define DPRINTFN(n, x) if (ipw_debug >= (n)) printf x 82 int ipw_debug = 0; 83 #else 84 #define DPRINTF(x) 85 #define DPRINTFN(n, x) 86 #endif 87 88 /* Permit loading the Intel firmware */ 89 static int ipw_accept_eula; 90 91 static int ipw_dma_alloc(struct ipw_softc *); 92 static void ipw_release(struct ipw_softc *); 93 static int ipw_match(device_t, cfdata_t, void *); 94 static void ipw_attach(device_t, device_t, void *); 95 static int ipw_detach(device_t, int); 96 97 static int ipw_media_change(struct ifnet *); 98 static void ipw_media_status(struct ifnet *, struct ifmediareq *); 99 static int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 100 static uint16_t ipw_read_prom_word(struct ipw_softc *, uint8_t); 101 static void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 102 static void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 103 static void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 104 struct ipw_soft_bd *, struct ipw_soft_buf *); 105 static void ipw_rx_intr(struct ipw_softc *); 106 static void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 107 static void ipw_tx_intr(struct ipw_softc *); 108 static int ipw_intr(void *); 109 static int ipw_cmd(struct ipw_softc *, uint32_t, void *, uint32_t); 110 static int ipw_tx_start(struct ifnet *, struct mbuf *, 111 struct ieee80211_node *); 112 static void ipw_start(struct ifnet *); 113 static void ipw_watchdog(struct ifnet *); 114 static int ipw_ioctl(struct ifnet *, u_long, void *); 115 static int ipw_get_table1(struct ipw_softc *, uint32_t *); 116 static int ipw_get_radio(struct ipw_softc *, int *); 117 static void ipw_stop_master(struct ipw_softc *); 118 static int ipw_reset(struct ipw_softc *); 119 static int ipw_load_ucode(struct ipw_softc *, u_char *, int); 120 static int ipw_load_firmware(struct ipw_softc *, u_char *, int); 121 static int ipw_cache_firmware(struct ipw_softc *); 122 static void ipw_free_firmware(struct ipw_softc *); 123 static int ipw_config(struct ipw_softc *); 124 static int ipw_init(struct ifnet *); 125 static void ipw_stop(struct ifnet *, int); 126 static uint32_t ipw_read_table1(struct ipw_softc *, uint32_t); 127 static void ipw_write_table1(struct ipw_softc *, uint32_t, uint32_t); 128 static int ipw_read_table2(struct ipw_softc *, uint32_t, void *, uint32_t *); 129 static void ipw_read_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 130 bus_size_t); 131 static void ipw_write_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 132 bus_size_t); 133 134 /* 135 * Supported rates for 802.11b mode (in 500Kbps unit). 136 */ 137 static const struct ieee80211_rateset ipw_rateset_11b = 138 { 4, { 2, 4, 11, 22 } }; 139 140 static inline uint8_t 141 MEM_READ_1(struct ipw_softc *sc, uint32_t addr) 142 { 143 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 144 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); 145 } 146 147 static inline uint32_t 148 MEM_READ_4(struct ipw_softc *sc, uint32_t addr) 149 { 150 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 151 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); 152 } 153 154 CFATTACH_DECL(ipw, sizeof (struct ipw_softc), ipw_match, ipw_attach, 155 ipw_detach, NULL); 156 157 static int 158 ipw_match(device_t parent, cfdata_t match, void *aux) 159 { 160 struct pci_attach_args *pa = aux; 161 162 if (PCI_VENDOR (pa->pa_id) == PCI_VENDOR_INTEL && 163 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_PRO_WL_2100) 164 return 1; 165 166 return 0; 167 } 168 169 /* Base Address Register */ 170 #define IPW_PCI_BAR0 0x10 171 172 static void 173 ipw_attach(device_t parent, device_t self, void *aux) 174 { 175 struct ipw_softc *sc = device_private(self); 176 struct ieee80211com *ic = &sc->sc_ic; 177 struct ifnet *ifp = &sc->sc_if; 178 struct pci_attach_args *pa = aux; 179 const char *intrstr; 180 char devinfo[256]; 181 bus_space_tag_t memt; 182 bus_space_handle_t memh; 183 bus_addr_t base; 184 pci_intr_handle_t ih; 185 uint32_t data; 186 uint16_t val; 187 int i, revision, error; 188 189 sc->sc_pct = pa->pa_pc; 190 sc->sc_pcitag = pa->pa_tag; 191 192 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof devinfo); 193 revision = PCI_REVISION(pa->pa_class); 194 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, revision); 195 196 /* enable bus-mastering */ 197 data = pci_conf_read(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG); 198 data |= PCI_COMMAND_MASTER_ENABLE; 199 pci_conf_write(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG, data); 200 201 /* map the register window */ 202 error = pci_mapreg_map(pa, IPW_PCI_BAR0, PCI_MAPREG_TYPE_MEM | 203 PCI_MAPREG_MEM_TYPE_32BIT, 0, &memt, &memh, &base, &sc->sc_sz); 204 if (error != 0) { 205 aprint_error_dev(&sc->sc_dev, "could not map memory space\n"); 206 return; 207 } 208 209 sc->sc_st = memt; 210 sc->sc_sh = memh; 211 sc->sc_dmat = pa->pa_dmat; 212 sc->sc_fwname = "ipw2100-1.2.fw"; 213 214 /* disable interrupts */ 215 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 216 217 if (pci_intr_map(pa, &ih) != 0) { 218 aprint_error_dev(&sc->sc_dev, "could not map interrupt\n"); 219 return; 220 } 221 222 intrstr = pci_intr_string(sc->sc_pct, ih); 223 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, ipw_intr, sc); 224 if (sc->sc_ih == NULL) { 225 aprint_error_dev(&sc->sc_dev, "could not establish interrupt"); 226 if (intrstr != NULL) 227 aprint_error(" at %s", intrstr); 228 aprint_error("\n"); 229 return; 230 } 231 aprint_normal_dev(&sc->sc_dev, "interrupting at %s\n", intrstr); 232 233 if (ipw_reset(sc) != 0) { 234 aprint_error_dev(&sc->sc_dev, "could not reset adapter\n"); 235 goto fail; 236 } 237 238 if (ipw_dma_alloc(sc) != 0) { 239 aprint_error_dev(&sc->sc_dev, "could not allocate DMA resources\n"); 240 goto fail; 241 } 242 243 ifp->if_softc = sc; 244 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 245 ifp->if_init = ipw_init; 246 ifp->if_stop = ipw_stop; 247 ifp->if_ioctl = ipw_ioctl; 248 ifp->if_start = ipw_start; 249 ifp->if_watchdog = ipw_watchdog; 250 IFQ_SET_READY(&ifp->if_snd); 251 strlcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 252 253 ic->ic_ifp = ifp; 254 ic->ic_phytype = IEEE80211_T_DS; 255 ic->ic_opmode = IEEE80211_M_STA; 256 ic->ic_state = IEEE80211_S_INIT; 257 258 /* set device capabilities */ 259 ic->ic_caps = 260 IEEE80211_C_SHPREAMBLE /* short preamble supported */ 261 | IEEE80211_C_TXPMGT /* tx power management */ 262 | IEEE80211_C_IBSS /* ibss mode */ 263 | IEEE80211_C_MONITOR /* monitor mode */ 264 ; 265 266 /* read MAC address from EEPROM */ 267 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0); 268 ic->ic_myaddr[0] = val >> 8; 269 ic->ic_myaddr[1] = val & 0xff; 270 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 1); 271 ic->ic_myaddr[2] = val >> 8; 272 ic->ic_myaddr[3] = val & 0xff; 273 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 2); 274 ic->ic_myaddr[4] = val >> 8; 275 ic->ic_myaddr[5] = val & 0xff; 276 277 /* set supported .11b rates */ 278 ic->ic_sup_rates[IEEE80211_MODE_11B] = ipw_rateset_11b; 279 280 /* set supported .11b channels (read from EEPROM) */ 281 if ((val = ipw_read_prom_word(sc, IPW_EEPROM_CHANNEL_LIST)) == 0) 282 val = 0x7ff; /* default to channels 1-11 */ 283 val <<= 1; 284 for (i = 1; i < 16; i++) { 285 if (val & (1 << i)) { 286 ic->ic_channels[i].ic_freq = 287 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 288 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 289 } 290 } 291 292 /* check support for radio transmitter switch in EEPROM */ 293 if (!(ipw_read_prom_word(sc, IPW_EEPROM_RADIO) & 8)) 294 sc->flags |= IPW_FLAG_HAS_RADIO_SWITCH; 295 296 aprint_normal_dev(&sc->sc_dev, "802.11 address %s\n", 297 ether_sprintf(ic->ic_myaddr)); 298 299 if_attach(ifp); 300 ieee80211_ifattach(ic); 301 302 /* override state transition machine */ 303 sc->sc_newstate = ic->ic_newstate; 304 ic->ic_newstate = ipw_newstate; 305 306 ieee80211_media_init(ic, ipw_media_change, ipw_media_status); 307 308 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 309 sizeof(struct ieee80211_frame) + 64, &sc->sc_drvbpf); 310 311 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 312 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 313 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 314 315 sc->sc_txtap_len = sizeof sc->sc_txtapu; 316 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 317 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 318 319 /* 320 * Add a few sysctl knobs. 321 * XXX: Not yet 322 */ 323 sc->dwelltime = 100; 324 325 if (pmf_device_register(self, NULL, NULL)) 326 pmf_class_network_register(self, ifp); 327 else 328 aprint_error_dev(self, "couldn't establish power handler\n"); 329 330 ieee80211_announce(ic); 331 332 return; 333 334 fail: ipw_detach(self, 0); 335 } 336 337 static int 338 ipw_detach(struct device* self, int flags) 339 { 340 struct ipw_softc *sc = device_private(self); 341 struct ifnet *ifp = &sc->sc_if; 342 343 if (ifp->if_softc) { 344 ipw_stop(ifp, 1); 345 ipw_free_firmware(sc); 346 347 bpf_detach(ifp); 348 ieee80211_ifdetach(&sc->sc_ic); 349 if_detach(ifp); 350 351 ipw_release(sc); 352 } 353 354 if (sc->sc_ih != NULL) { 355 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 356 sc->sc_ih = NULL; 357 } 358 359 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 360 361 return 0; 362 } 363 364 static int 365 ipw_dma_alloc(struct ipw_softc *sc) 366 { 367 struct ipw_soft_bd *sbd; 368 struct ipw_soft_hdr *shdr; 369 struct ipw_soft_buf *sbuf; 370 int error, i, nsegs; 371 372 /* 373 * Allocate and map tx ring. 374 */ 375 error = bus_dmamap_create(sc->sc_dmat, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, 376 BUS_DMA_NOWAIT, &sc->tbd_map); 377 if (error != 0) { 378 aprint_error_dev(&sc->sc_dev, "could not create tbd dma map\n"); 379 goto fail; 380 } 381 382 error = bus_dmamem_alloc(sc->sc_dmat, IPW_TBD_SZ, PAGE_SIZE, 0, 383 &sc->tbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 384 if (error != 0) { 385 aprint_error_dev(&sc->sc_dev, "could not allocate tbd dma memory\n"); 386 goto fail; 387 } 388 389 error = bus_dmamem_map(sc->sc_dmat, &sc->tbd_seg, nsegs, IPW_TBD_SZ, 390 (void **)&sc->tbd_list, BUS_DMA_NOWAIT); 391 if (error != 0) { 392 aprint_error_dev(&sc->sc_dev, "could not map tbd dma memory\n"); 393 goto fail; 394 } 395 396 error = bus_dmamap_load(sc->sc_dmat, sc->tbd_map, sc->tbd_list, 397 IPW_TBD_SZ, NULL, BUS_DMA_NOWAIT); 398 if (error != 0) { 399 aprint_error_dev(&sc->sc_dev, "could not load tbd dma memory\n"); 400 goto fail; 401 } 402 403 (void)memset(sc->tbd_list, 0, IPW_TBD_SZ); 404 405 /* 406 * Allocate and map rx ring. 407 */ 408 error = bus_dmamap_create(sc->sc_dmat, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, 409 BUS_DMA_NOWAIT, &sc->rbd_map); 410 if (error != 0) { 411 aprint_error_dev(&sc->sc_dev, "could not create rbd dma map\n"); 412 goto fail; 413 } 414 415 error = bus_dmamem_alloc(sc->sc_dmat, IPW_RBD_SZ, PAGE_SIZE, 0, 416 &sc->rbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 417 if (error != 0) { 418 aprint_error_dev(&sc->sc_dev, "could not allocate rbd dma memory\n"); 419 goto fail; 420 } 421 422 error = bus_dmamem_map(sc->sc_dmat, &sc->rbd_seg, nsegs, IPW_RBD_SZ, 423 (void **)&sc->rbd_list, BUS_DMA_NOWAIT); 424 if (error != 0) { 425 aprint_error_dev(&sc->sc_dev, "could not map rbd dma memory\n"); 426 goto fail; 427 } 428 429 error = bus_dmamap_load(sc->sc_dmat, sc->rbd_map, sc->rbd_list, 430 IPW_RBD_SZ, NULL, BUS_DMA_NOWAIT); 431 if (error != 0) { 432 aprint_error_dev(&sc->sc_dev, "could not load rbd dma memory\n"); 433 goto fail; 434 } 435 436 (void)memset(sc->rbd_list, 0, IPW_RBD_SZ); 437 438 /* 439 * Allocate and map status ring. 440 */ 441 error = bus_dmamap_create(sc->sc_dmat, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 442 0, BUS_DMA_NOWAIT, &sc->status_map); 443 if (error != 0) { 444 aprint_error_dev(&sc->sc_dev, "could not create status dma map\n"); 445 goto fail; 446 } 447 448 error = bus_dmamem_alloc(sc->sc_dmat, IPW_STATUS_SZ, PAGE_SIZE, 0, 449 &sc->status_seg, 1, &nsegs, BUS_DMA_NOWAIT); 450 if (error != 0) { 451 aprint_error_dev(&sc->sc_dev, "could not allocate status dma memory\n"); 452 goto fail; 453 } 454 455 error = bus_dmamem_map(sc->sc_dmat, &sc->status_seg, nsegs, 456 IPW_STATUS_SZ, (void **)&sc->status_list, BUS_DMA_NOWAIT); 457 if (error != 0) { 458 aprint_error_dev(&sc->sc_dev, "could not map status dma memory\n"); 459 goto fail; 460 } 461 462 error = bus_dmamap_load(sc->sc_dmat, sc->status_map, sc->status_list, 463 IPW_STATUS_SZ, NULL, BUS_DMA_NOWAIT); 464 if (error != 0) { 465 aprint_error_dev(&sc->sc_dev, "could not load status dma memory\n"); 466 goto fail; 467 } 468 469 (void)memset(sc->status_list, 0, IPW_STATUS_SZ); 470 471 /* 472 * Allocate command DMA map. 473 */ 474 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_cmd), 475 1, sizeof (struct ipw_cmd), 0, BUS_DMA_NOWAIT, &sc->cmd_map); 476 if (error != 0) { 477 aprint_error_dev(&sc->sc_dev, "could not create cmd dma map\n"); 478 goto fail; 479 } 480 481 error = bus_dmamem_alloc(sc->sc_dmat, sizeof (struct ipw_cmd), 482 PAGE_SIZE, 0, &sc->cmd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 483 if (error != 0) { 484 aprint_error_dev(&sc->sc_dev, "could not allocate cmd dma memory\n"); 485 goto fail; 486 } 487 488 error = bus_dmamem_map(sc->sc_dmat, &sc->cmd_seg, nsegs, 489 sizeof (struct ipw_cmd), (void **)&sc->cmd, BUS_DMA_NOWAIT); 490 if (error != 0) { 491 aprint_error_dev(&sc->sc_dev, "could not map cmd dma memory\n"); 492 goto fail; 493 } 494 495 error = bus_dmamap_load(sc->sc_dmat, sc->cmd_map, &sc->cmd, 496 sizeof (struct ipw_cmd), NULL, BUS_DMA_NOWAIT); 497 if (error != 0) { 498 aprint_error_dev(&sc->sc_dev, "could not map cmd dma memory\n"); 499 return error; 500 } 501 502 /* 503 * Allocate and map hdr list. 504 */ 505 506 error = bus_dmamap_create(sc->sc_dmat, 507 IPW_NDATA * sizeof(struct ipw_hdr), 1, 508 sizeof(struct ipw_hdr), 0, BUS_DMA_NOWAIT, 509 &sc->hdr_map); 510 if (error != 0) { 511 aprint_error_dev(&sc->sc_dev, "could not create hdr dma map\n"); 512 goto fail; 513 } 514 515 error = bus_dmamem_alloc(sc->sc_dmat, 516 IPW_NDATA * sizeof(struct ipw_hdr), PAGE_SIZE, 0, &sc->hdr_seg, 517 1, &nsegs, BUS_DMA_NOWAIT); 518 if (error != 0) { 519 aprint_error_dev(&sc->sc_dev, "could not allocate hdr memory\n"); 520 goto fail; 521 } 522 523 error = bus_dmamem_map(sc->sc_dmat, &sc->hdr_seg, nsegs, 524 IPW_NDATA * sizeof(struct ipw_hdr), (void **)&sc->hdr_list, 525 BUS_DMA_NOWAIT); 526 if (error != 0) { 527 aprint_error_dev(&sc->sc_dev, "could not map hdr memory\n"); 528 goto fail; 529 } 530 531 error = bus_dmamap_load(sc->sc_dmat, sc->hdr_map, sc->hdr_list, 532 IPW_NDATA * sizeof(struct ipw_hdr), NULL, BUS_DMA_NOWAIT); 533 if (error != 0) { 534 aprint_error_dev(&sc->sc_dev, "could not load hdr memory\n"); 535 goto fail; 536 } 537 538 (void)memset(sc->hdr_list, 0, IPW_HDR_SZ); 539 540 /* 541 * Create DMA hdrs tailq. 542 */ 543 TAILQ_INIT(&sc->sc_free_shdr); 544 for (i = 0; i < IPW_NDATA; i++) { 545 shdr = &sc->shdr_list[i]; 546 shdr->hdr = sc->hdr_list + i; 547 shdr->offset = sizeof(struct ipw_hdr) * i; 548 shdr->addr = sc->hdr_map->dm_segs[0].ds_addr + shdr->offset; 549 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 550 } 551 552 /* 553 * Allocate tx buffers DMA maps. 554 */ 555 TAILQ_INIT(&sc->sc_free_sbuf); 556 for (i = 0; i < IPW_NDATA; i++) { 557 sbuf = &sc->tx_sbuf_list[i]; 558 559 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 560 IPW_MAX_NSEG, MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 561 if (error != 0) { 562 aprint_error_dev(&sc->sc_dev, "could not create txbuf dma map\n"); 563 goto fail; 564 } 565 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 566 } 567 568 /* 569 * Initialize tx ring. 570 */ 571 for (i = 0; i < IPW_NTBD; i++) { 572 sbd = &sc->stbd_list[i]; 573 sbd->bd = &sc->tbd_list[i]; 574 sbd->type = IPW_SBD_TYPE_NOASSOC; 575 } 576 577 /* 578 * Pre-allocate rx buffers and DMA maps 579 */ 580 for (i = 0; i < IPW_NRBD; i++) { 581 sbd = &sc->srbd_list[i]; 582 sbuf = &sc->rx_sbuf_list[i]; 583 sbd->bd = &sc->rbd_list[i]; 584 585 MGETHDR(sbuf->m, M_DONTWAIT, MT_DATA); 586 if (sbuf->m == NULL) { 587 aprint_error_dev(&sc->sc_dev, "could not allocate rx mbuf\n"); 588 error = ENOMEM; 589 goto fail; 590 } 591 592 MCLGET(sbuf->m, M_DONTWAIT); 593 if (!(sbuf->m->m_flags & M_EXT)) { 594 m_freem(sbuf->m); 595 aprint_error_dev(&sc->sc_dev, "could not allocate rx mbuf cluster\n"); 596 error = ENOMEM; 597 goto fail; 598 } 599 600 sbuf->m->m_pkthdr.len = sbuf->m->m_len = sbuf->m->m_ext.ext_size; 601 602 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 603 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sbuf->map); 604 if (error != 0) { 605 aprint_error_dev(&sc->sc_dev, "could not create rxbuf dma map\n"); 606 m_freem(sbuf->m); 607 goto fail; 608 } 609 610 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, 611 sbuf->m, BUS_DMA_READ | BUS_DMA_NOWAIT); 612 if (error != 0) { 613 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 614 m_freem(sbuf->m); 615 aprint_error_dev(&sc->sc_dev, "could not map rxbuf dma memory\n"); 616 goto fail; 617 } 618 619 sbd->type = IPW_SBD_TYPE_DATA; 620 sbd->priv = sbuf; 621 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 622 sbd->bd->len = htole32(MCLBYTES); 623 624 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, 625 sbuf->map->dm_mapsize, BUS_DMASYNC_PREREAD); 626 627 } 628 629 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 0, IPW_RBD_SZ, 630 BUS_DMASYNC_PREREAD); 631 632 return 0; 633 634 fail: ipw_release(sc); 635 return error; 636 } 637 638 static void 639 ipw_release(struct ipw_softc *sc) 640 { 641 struct ipw_soft_buf *sbuf; 642 int i; 643 644 if (sc->tbd_map != NULL) { 645 if (sc->tbd_list != NULL) { 646 bus_dmamap_unload(sc->sc_dmat, sc->tbd_map); 647 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->tbd_list, 648 IPW_TBD_SZ); 649 bus_dmamem_free(sc->sc_dmat, &sc->tbd_seg, 1); 650 } 651 bus_dmamap_destroy(sc->sc_dmat, sc->tbd_map); 652 } 653 654 if (sc->rbd_map != NULL) { 655 if (sc->rbd_list != NULL) { 656 bus_dmamap_unload(sc->sc_dmat, sc->rbd_map); 657 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->rbd_list, 658 IPW_RBD_SZ); 659 bus_dmamem_free(sc->sc_dmat, &sc->rbd_seg, 1); 660 } 661 bus_dmamap_destroy(sc->sc_dmat, sc->rbd_map); 662 } 663 664 if (sc->status_map != NULL) { 665 if (sc->status_list != NULL) { 666 bus_dmamap_unload(sc->sc_dmat, sc->status_map); 667 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->status_list, 668 IPW_RBD_SZ); 669 bus_dmamem_free(sc->sc_dmat, &sc->status_seg, 1); 670 } 671 bus_dmamap_destroy(sc->sc_dmat, sc->status_map); 672 } 673 674 for (i = 0; i < IPW_NTBD; i++) 675 ipw_release_sbd(sc, &sc->stbd_list[i]); 676 677 if (sc->cmd_map != NULL) 678 bus_dmamap_destroy(sc->sc_dmat, sc->cmd_map); 679 680 if (sc->hdr_list != NULL) { 681 bus_dmamap_unload(sc->sc_dmat, sc->hdr_map); 682 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->hdr_list, 683 IPW_NDATA * sizeof(struct ipw_hdr)); 684 } 685 if (sc->hdr_map != NULL) { 686 bus_dmamem_free(sc->sc_dmat, &sc->hdr_seg, 1); 687 bus_dmamap_destroy(sc->sc_dmat, sc->hdr_map); 688 } 689 690 for (i = 0; i < IPW_NDATA; i++) 691 bus_dmamap_destroy(sc->sc_dmat, sc->tx_sbuf_list[i].map); 692 693 for (i = 0; i < IPW_NRBD; i++) { 694 sbuf = &sc->rx_sbuf_list[i]; 695 if (sbuf->map != NULL) { 696 if (sbuf->m != NULL) { 697 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 698 m_freem(sbuf->m); 699 } 700 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 701 } 702 } 703 704 } 705 706 static int 707 ipw_media_change(struct ifnet *ifp) 708 { 709 int error; 710 711 error = ieee80211_media_change(ifp); 712 if (error != ENETRESET) 713 return error; 714 715 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 716 ipw_init(ifp); 717 718 return 0; 719 } 720 721 /* 722 * The firmware automatically adapts the transmit speed. We report the current 723 * transmit speed here. 724 */ 725 static void 726 ipw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 727 { 728 #define N(a) (sizeof (a) / sizeof (a[0])) 729 struct ipw_softc *sc = ifp->if_softc; 730 struct ieee80211com *ic = &sc->sc_ic; 731 static const struct { 732 uint32_t val; 733 int rate; 734 } rates[] = { 735 { IPW_RATE_DS1, 2 }, 736 { IPW_RATE_DS2, 4 }, 737 { IPW_RATE_DS5, 11 }, 738 { IPW_RATE_DS11, 22 }, 739 }; 740 uint32_t val; 741 int rate, i; 742 743 imr->ifm_status = IFM_AVALID; 744 imr->ifm_active = IFM_IEEE80211; 745 if (ic->ic_state == IEEE80211_S_RUN) 746 imr->ifm_status |= IFM_ACTIVE; 747 748 /* read current transmission rate from adapter */ 749 val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE) & 0xf; 750 751 /* convert ipw rate to 802.11 rate */ 752 for (i = 0; i < N(rates) && rates[i].val != val; i++); 753 rate = (i < N(rates)) ? rates[i].rate : 0; 754 755 imr->ifm_active |= IFM_IEEE80211_11B; 756 imr->ifm_active |= ieee80211_rate2media(ic, rate, IEEE80211_MODE_11B); 757 switch (ic->ic_opmode) { 758 case IEEE80211_M_STA: 759 break; 760 761 case IEEE80211_M_IBSS: 762 imr->ifm_active |= IFM_IEEE80211_ADHOC; 763 break; 764 765 case IEEE80211_M_MONITOR: 766 imr->ifm_active |= IFM_IEEE80211_MONITOR; 767 break; 768 769 case IEEE80211_M_AHDEMO: 770 case IEEE80211_M_HOSTAP: 771 /* should not get there */ 772 break; 773 } 774 #undef N 775 } 776 777 static int 778 ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, 779 int arg) 780 { 781 struct ifnet *ifp = ic->ic_ifp; 782 struct ipw_softc *sc = ifp->if_softc; 783 struct ieee80211_node *ni; 784 uint8_t macaddr[IEEE80211_ADDR_LEN]; 785 uint32_t len; 786 struct ipw_rx_radiotap_header *wr = &sc->sc_rxtap; 787 struct ipw_tx_radiotap_header *wt = &sc->sc_txtap; 788 789 switch (nstate) { 790 case IEEE80211_S_INIT: 791 break; 792 default: 793 KASSERT(ic->ic_curchan != IEEE80211_CHAN_ANYC); 794 KASSERT(ic->ic_curchan != NULL); 795 wt->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 796 wt->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 797 wr->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 798 wr->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 799 break; 800 } 801 802 switch (nstate) { 803 case IEEE80211_S_RUN: 804 DELAY(200); /* firmware needs a short delay here */ 805 806 len = IEEE80211_ADDR_LEN; 807 ipw_read_table2(sc, IPW_INFO_CURRENT_BSSID, macaddr, &len); 808 809 ni = ieee80211_find_node(&ic->ic_scan, macaddr); 810 if (ni == NULL) 811 break; 812 813 ieee80211_ref_node(ni); 814 ieee80211_sta_join(ic, ni); 815 ieee80211_node_authorize(ni); 816 817 if (ic->ic_opmode == IEEE80211_M_STA) 818 ieee80211_notify_node_join(ic, ni, 1); 819 break; 820 821 case IEEE80211_S_INIT: 822 case IEEE80211_S_SCAN: 823 case IEEE80211_S_AUTH: 824 case IEEE80211_S_ASSOC: 825 break; 826 } 827 828 ic->ic_state = nstate; 829 return 0; 830 } 831 832 /* 833 * Read 16 bits at address 'addr' from the serial EEPROM. 834 */ 835 static uint16_t 836 ipw_read_prom_word(struct ipw_softc *sc, uint8_t addr) 837 { 838 uint32_t tmp; 839 uint16_t val; 840 int n; 841 842 /* clock C once before the first command */ 843 IPW_EEPROM_CTL(sc, 0); 844 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 845 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 846 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 847 848 /* write start bit (1) */ 849 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 850 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 851 852 /* write READ opcode (10) */ 853 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 854 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 855 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 856 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 857 858 /* write address A7-A0 */ 859 for (n = 7; n >= 0; n--) { 860 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 861 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D)); 862 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 863 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D) | IPW_EEPROM_C); 864 } 865 866 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 867 868 /* read data Q15-Q0 */ 869 val = 0; 870 for (n = 15; n >= 0; n--) { 871 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 872 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 873 tmp = MEM_READ_4(sc, IPW_MEM_EEPROM_CTL); 874 val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n; 875 } 876 877 IPW_EEPROM_CTL(sc, 0); 878 879 /* clear Chip Select and clock C */ 880 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 881 IPW_EEPROM_CTL(sc, 0); 882 IPW_EEPROM_CTL(sc, IPW_EEPROM_C); 883 884 return le16toh(val); 885 } 886 887 static void 888 ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 889 { 890 struct ipw_cmd *cmd; 891 892 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof (struct ipw_cmd), 893 BUS_DMASYNC_POSTREAD); 894 895 cmd = mtod(sbuf->m, struct ipw_cmd *); 896 897 DPRINTFN(2, ("cmd ack'ed (%u, %u, %u, %u, %u)\n", le32toh(cmd->type), 898 le32toh(cmd->subtype), le32toh(cmd->seq), le32toh(cmd->len), 899 le32toh(cmd->status))); 900 901 wakeup(&sc->cmd); 902 } 903 904 static void 905 ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 906 { 907 struct ieee80211com *ic = &sc->sc_ic; 908 struct ifnet *ifp = sc->sc_ic.ic_ifp; 909 uint32_t state; 910 911 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof state, 912 BUS_DMASYNC_POSTREAD); 913 914 state = le32toh(*mtod(sbuf->m, uint32_t *)); 915 916 DPRINTFN(2, ("entering state %u\n", state)); 917 918 switch (state) { 919 case IPW_STATE_ASSOCIATED: 920 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 921 break; 922 923 case IPW_STATE_SCANNING: 924 /* don't leave run state on background scan */ 925 if (ic->ic_state != IEEE80211_S_RUN) 926 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 927 928 ic->ic_flags |= IEEE80211_F_SCAN; 929 break; 930 931 case IPW_STATE_SCAN_COMPLETE: 932 ieee80211_notify_scan_done(ic); 933 ic->ic_flags &= ~IEEE80211_F_SCAN; 934 break; 935 936 case IPW_STATE_ASSOCIATION_LOST: 937 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 938 break; 939 940 case IPW_STATE_RADIO_DISABLED: 941 ic->ic_ifp->if_flags &= ~IFF_UP; 942 ipw_stop(ifp, 1); 943 break; 944 } 945 } 946 947 /* 948 * XXX: Hack to set the current channel to the value advertised in beacons or 949 * probe responses. Only used during AP detection. 950 */ 951 static void 952 ipw_fix_channel(struct ieee80211com *ic, struct mbuf *m) 953 { 954 struct ieee80211_frame *wh; 955 uint8_t subtype; 956 uint8_t *frm, *efrm; 957 958 wh = mtod(m, struct ieee80211_frame *); 959 960 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_MGT) 961 return; 962 963 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 964 965 if (subtype != IEEE80211_FC0_SUBTYPE_BEACON && 966 subtype != IEEE80211_FC0_SUBTYPE_PROBE_RESP) 967 return; 968 969 frm = (uint8_t *)(wh + 1); 970 efrm = mtod(m, uint8_t *) + m->m_len; 971 972 frm += 12; /* skip tstamp, bintval and capinfo fields */ 973 while (frm < efrm) { 974 if (*frm == IEEE80211_ELEMID_DSPARMS) 975 #if IEEE80211_CHAN_MAX < 255 976 if (frm[2] <= IEEE80211_CHAN_MAX) 977 #endif 978 ic->ic_curchan = &ic->ic_channels[frm[2]]; 979 980 frm += frm[1] + 2; 981 } 982 } 983 984 static void 985 ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 986 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 987 { 988 struct ieee80211com *ic = &sc->sc_ic; 989 struct ifnet *ifp = &sc->sc_if; 990 struct mbuf *mnew, *m; 991 struct ieee80211_frame *wh; 992 struct ieee80211_node *ni; 993 int error; 994 995 DPRINTFN(5, ("received frame len=%u, rssi=%u\n", le32toh(status->len), 996 status->rssi)); 997 998 if (le32toh(status->len) < sizeof (struct ieee80211_frame_min) || 999 le32toh(status->len) > MCLBYTES) 1000 return; 1001 1002 /* 1003 * Try to allocate a new mbuf for this ring element and load it before 1004 * processing the current mbuf. If the ring element cannot be loaded, 1005 * drop the received packet and reuse the old mbuf. In the unlikely 1006 * case that the old mbuf can't be reloaded either, explicitly panic. 1007 */ 1008 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1009 if (mnew == NULL) { 1010 aprint_error_dev(&sc->sc_dev, "could not allocate rx mbuf\n"); 1011 ifp->if_ierrors++; 1012 return; 1013 } 1014 1015 MCLGET(mnew, M_DONTWAIT); 1016 if (!(mnew->m_flags & M_EXT)) { 1017 aprint_error_dev(&sc->sc_dev, "could not allocate rx mbuf cluster\n"); 1018 m_freem(mnew); 1019 ifp->if_ierrors++; 1020 return; 1021 } 1022 1023 mnew->m_pkthdr.len = mnew->m_len = mnew->m_ext.ext_size; 1024 1025 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, le32toh(status->len), 1026 BUS_DMASYNC_POSTREAD); 1027 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1028 1029 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, mnew, 1030 BUS_DMA_READ | BUS_DMA_NOWAIT); 1031 if (error != 0) { 1032 aprint_error_dev(&sc->sc_dev, "could not load rx buf DMA map\n"); 1033 m_freem(mnew); 1034 1035 /* try to reload the old mbuf */ 1036 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, 1037 sbuf->m, BUS_DMA_READ | BUS_DMA_NOWAIT); 1038 if (error != 0) { 1039 /* very unlikely that it will fail... */ 1040 panic("%s: unable to remap rx buf", 1041 device_xname(&sc->sc_dev)); 1042 } 1043 ifp->if_ierrors++; 1044 return; 1045 } 1046 1047 /* 1048 * New mbuf successfully loaded, update Rx ring and continue 1049 * processing. 1050 */ 1051 m = sbuf->m; 1052 sbuf->m = mnew; 1053 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 1054 1055 /* finalize mbuf */ 1056 m->m_pkthdr.rcvif = ifp; 1057 m->m_pkthdr.len = m->m_len = le32toh(status->len); 1058 1059 if (sc->sc_drvbpf != NULL) { 1060 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 1061 1062 tap->wr_antsignal = status->rssi; 1063 1064 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 1065 } 1066 1067 if (ic->ic_state == IEEE80211_S_SCAN) 1068 ipw_fix_channel(ic, m); 1069 1070 wh = mtod(m, struct ieee80211_frame *); 1071 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 1072 1073 /* send the frame to the 802.11 layer */ 1074 ieee80211_input(ic, m, ni, status->rssi, 0); 1075 1076 /* node is no longer needed */ 1077 ieee80211_free_node(ni); 1078 1079 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, 1080 sbuf->map->dm_mapsize, BUS_DMASYNC_PREREAD); 1081 } 1082 1083 static void 1084 ipw_rx_intr(struct ipw_softc *sc) 1085 { 1086 struct ipw_status *status; 1087 struct ipw_soft_bd *sbd; 1088 struct ipw_soft_buf *sbuf; 1089 uint32_t r, i; 1090 1091 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1092 return; 1093 1094 r = CSR_READ_4(sc, IPW_CSR_RX_READ); 1095 1096 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 1097 1098 /* firmware was killed, stop processing received frames */ 1099 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1100 return; 1101 1102 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 1103 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1104 BUS_DMASYNC_POSTREAD); 1105 1106 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 1107 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 1108 BUS_DMASYNC_POSTREAD); 1109 1110 status = &sc->status_list[i]; 1111 sbd = &sc->srbd_list[i]; 1112 sbuf = sbd->priv; 1113 1114 switch (le16toh(status->code) & 0xf) { 1115 case IPW_STATUS_CODE_COMMAND: 1116 ipw_command_intr(sc, sbuf); 1117 break; 1118 1119 case IPW_STATUS_CODE_NEWSTATE: 1120 ipw_newstate_intr(sc, sbuf); 1121 break; 1122 1123 case IPW_STATUS_CODE_DATA_802_3: 1124 case IPW_STATUS_CODE_DATA_802_11: 1125 ipw_data_intr(sc, status, sbd, sbuf); 1126 break; 1127 1128 case IPW_STATUS_CODE_NOTIFICATION: 1129 DPRINTFN(2, ("received notification\n")); 1130 break; 1131 1132 default: 1133 aprint_error_dev(&sc->sc_dev, "unknown status code %u\n", 1134 le16toh(status->code)); 1135 } 1136 1137 sbd->bd->flags = 0; 1138 1139 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 1140 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1141 BUS_DMASYNC_PREREAD); 1142 1143 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 1144 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 1145 BUS_DMASYNC_PREREAD); 1146 } 1147 1148 /* Tell the firmware what we have processed */ 1149 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 1150 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 1151 } 1152 1153 static void 1154 ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 1155 { 1156 struct ieee80211com *ic; 1157 struct ipw_soft_hdr *shdr; 1158 struct ipw_soft_buf *sbuf; 1159 1160 switch (sbd->type) { 1161 case IPW_SBD_TYPE_COMMAND: 1162 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 1163 0, sizeof(struct ipw_cmd), BUS_DMASYNC_POSTWRITE); 1164 /* bus_dmamap_unload(sc->sc_dmat, sc->cmd_map); */ 1165 break; 1166 1167 case IPW_SBD_TYPE_HEADER: 1168 shdr = sbd->priv; 1169 bus_dmamap_sync(sc->sc_dmat, sc->hdr_map, 1170 shdr->offset, sizeof(struct ipw_hdr), BUS_DMASYNC_POSTWRITE); 1171 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 1172 break; 1173 1174 case IPW_SBD_TYPE_DATA: 1175 ic = &sc->sc_ic; 1176 sbuf = sbd->priv; 1177 1178 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 1179 0, MCLBYTES, BUS_DMASYNC_POSTWRITE); 1180 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1181 m_freem(sbuf->m); 1182 if (sbuf->ni != NULL) 1183 ieee80211_free_node(sbuf->ni); 1184 /* kill watchdog timer */ 1185 sc->sc_tx_timer = 0; 1186 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 1187 break; 1188 } 1189 sbd->type = IPW_SBD_TYPE_NOASSOC; 1190 } 1191 1192 static void 1193 ipw_tx_intr(struct ipw_softc *sc) 1194 { 1195 struct ifnet *ifp = &sc->sc_if; 1196 struct ipw_soft_bd *sbd; 1197 uint32_t r, i; 1198 1199 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1200 return; 1201 1202 r = CSR_READ_4(sc, IPW_CSR_TX_READ); 1203 1204 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) { 1205 sbd = &sc->stbd_list[i]; 1206 1207 if (sbd->type == IPW_SBD_TYPE_DATA) 1208 ifp->if_opackets++; 1209 1210 ipw_release_sbd(sc, sbd); 1211 sc->txfree++; 1212 } 1213 1214 /* remember what the firmware has processed */ 1215 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 1216 1217 /* Call start() since some buffer descriptors have been released */ 1218 ifp->if_flags &= ~IFF_OACTIVE; 1219 (*ifp->if_start)(ifp); 1220 } 1221 1222 static int 1223 ipw_intr(void *arg) 1224 { 1225 struct ipw_softc *sc = arg; 1226 uint32_t r; 1227 1228 r = CSR_READ_4(sc, IPW_CSR_INTR); 1229 if (r == 0 || r == 0xffffffff) 1230 return 0; 1231 1232 /* Disable interrupts */ 1233 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1234 1235 if (r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR)) { 1236 aprint_error_dev(&sc->sc_dev, "fatal error\n"); 1237 sc->sc_ic.ic_ifp->if_flags &= ~IFF_UP; 1238 ipw_stop(&sc->sc_if, 1); 1239 } 1240 1241 if (r & IPW_INTR_FW_INIT_DONE) { 1242 if (!(r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR))) 1243 wakeup(sc); 1244 } 1245 1246 if (r & IPW_INTR_RX_TRANSFER) 1247 ipw_rx_intr(sc); 1248 1249 if (r & IPW_INTR_TX_TRANSFER) 1250 ipw_tx_intr(sc); 1251 1252 /* Acknowledge all interrupts */ 1253 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 1254 1255 /* Re-enable interrupts */ 1256 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1257 1258 return 0; 1259 } 1260 1261 /* 1262 * Send a command to the firmware and wait for the acknowledgement. 1263 */ 1264 static int 1265 ipw_cmd(struct ipw_softc *sc, uint32_t type, void *data, uint32_t len) 1266 { 1267 struct ipw_soft_bd *sbd; 1268 1269 sbd = &sc->stbd_list[sc->txcur]; 1270 1271 sc->cmd.type = htole32(type); 1272 sc->cmd.subtype = 0; 1273 sc->cmd.len = htole32(len); 1274 sc->cmd.seq = 0; 1275 1276 (void)memcpy(sc->cmd.data, data, len); 1277 1278 sbd->type = IPW_SBD_TYPE_COMMAND; 1279 sbd->bd->physaddr = htole32(sc->cmd_map->dm_segs[0].ds_addr); 1280 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 1281 sbd->bd->nfrag = 1; 1282 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 1283 IPW_BD_FLAG_TX_LAST_FRAGMENT; 1284 1285 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 0, sizeof (struct ipw_cmd), 1286 BUS_DMASYNC_PREWRITE); 1287 1288 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1289 sc->txcur * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1290 BUS_DMASYNC_PREWRITE); 1291 1292 DPRINTFN(2, ("sending command (%u, %u, %u, %u)\n", type, 0, 0, len)); 1293 1294 /* kick firmware */ 1295 sc->txfree--; 1296 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1297 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1298 1299 /* Wait at most one second for command to complete */ 1300 return tsleep(&sc->cmd, 0, "ipwcmd", hz); 1301 } 1302 1303 static int 1304 ipw_tx_start(struct ifnet *ifp, struct mbuf *m0, struct ieee80211_node *ni) 1305 { 1306 struct ipw_softc *sc = ifp->if_softc; 1307 struct ieee80211com *ic = &sc->sc_ic; 1308 struct ieee80211_frame *wh; 1309 struct ipw_soft_bd *sbd; 1310 struct ipw_soft_hdr *shdr; 1311 struct ipw_soft_buf *sbuf; 1312 struct ieee80211_key *k; 1313 struct mbuf *mnew; 1314 int error, i; 1315 1316 wh = mtod(m0, struct ieee80211_frame *); 1317 1318 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1319 k = ieee80211_crypto_encap(ic, ni, m0); 1320 if (k == NULL) { 1321 m_freem(m0); 1322 return ENOBUFS; 1323 } 1324 1325 /* packet header may have moved, reset our local pointer */ 1326 wh = mtod(m0, struct ieee80211_frame *); 1327 } 1328 1329 if (sc->sc_drvbpf != NULL) { 1330 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 1331 1332 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 1333 } 1334 1335 shdr = TAILQ_FIRST(&sc->sc_free_shdr); 1336 sbuf = TAILQ_FIRST(&sc->sc_free_sbuf); 1337 KASSERT(shdr != NULL && sbuf != NULL); 1338 1339 shdr->hdr->type = htole32(IPW_HDR_TYPE_SEND); 1340 shdr->hdr->subtype = 0; 1341 shdr->hdr->encrypted = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0; 1342 shdr->hdr->encrypt = 0; 1343 shdr->hdr->keyidx = 0; 1344 shdr->hdr->keysz = 0; 1345 shdr->hdr->fragmentsz = 0; 1346 IEEE80211_ADDR_COPY(shdr->hdr->src_addr, wh->i_addr2); 1347 if (ic->ic_opmode == IEEE80211_M_STA) 1348 IEEE80211_ADDR_COPY(shdr->hdr->dst_addr, wh->i_addr3); 1349 else 1350 IEEE80211_ADDR_COPY(shdr->hdr->dst_addr, wh->i_addr1); 1351 1352 /* trim IEEE802.11 header */ 1353 m_adj(m0, sizeof (struct ieee80211_frame)); 1354 1355 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m0, BUS_DMA_NOWAIT); 1356 if (error != 0 && error != EFBIG) { 1357 aprint_error_dev(&sc->sc_dev, "could not map mbuf (error %d)\n", 1358 error); 1359 m_freem(m0); 1360 return error; 1361 } 1362 1363 if (error != 0) { 1364 /* too many fragments, linearize */ 1365 1366 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1367 if (mnew == NULL) { 1368 m_freem(m0); 1369 return ENOMEM; 1370 } 1371 1372 M_COPY_PKTHDR(mnew, m0); 1373 1374 /* If the data won't fit in the header, get a cluster */ 1375 if (m0->m_pkthdr.len > MHLEN) { 1376 MCLGET(mnew, M_DONTWAIT); 1377 if (!(mnew->m_flags & M_EXT)) { 1378 m_freem(m0); 1379 m_freem(mnew); 1380 return ENOMEM; 1381 } 1382 } 1383 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(mnew, void *)); 1384 m_freem(m0); 1385 mnew->m_len = mnew->m_pkthdr.len; 1386 m0 = mnew; 1387 1388 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m0, 1389 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1390 if (error != 0) { 1391 aprint_error_dev(&sc->sc_dev, "could not map mbuf (error %d)\n", error); 1392 m_freem(m0); 1393 return error; 1394 } 1395 } 1396 1397 TAILQ_REMOVE(&sc->sc_free_sbuf, sbuf, next); 1398 TAILQ_REMOVE(&sc->sc_free_shdr, shdr, next); 1399 1400 sbd = &sc->stbd_list[sc->txcur]; 1401 sbd->type = IPW_SBD_TYPE_HEADER; 1402 sbd->priv = shdr; 1403 sbd->bd->physaddr = htole32(shdr->addr); 1404 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 1405 sbd->bd->nfrag = 1 + sbuf->map->dm_nsegs; 1406 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 1407 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1408 1409 DPRINTFN(5, ("sending tx hdr (%u, %u, %u, %u, )\n", 1410 shdr->hdr->type, shdr->hdr->subtype, shdr->hdr->encrypted, 1411 shdr->hdr->encrypt)); 1412 DPRINTFN(5, ("%s->", ether_sprintf(shdr->hdr->src_addr))); 1413 DPRINTFN(5, ("%s\n", ether_sprintf(shdr->hdr->dst_addr))); 1414 1415 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1416 sc->txcur * sizeof (struct ipw_bd), 1417 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1418 1419 sc->txfree--; 1420 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1421 1422 sbuf->m = m0; 1423 sbuf->ni = ni; 1424 1425 for (i = 0; i < sbuf->map->dm_nsegs; i++) { 1426 sbd = &sc->stbd_list[sc->txcur]; 1427 1428 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[i].ds_addr); 1429 sbd->bd->len = htole32(sbuf->map->dm_segs[i].ds_len); 1430 sbd->bd->nfrag = 0; 1431 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 1432 if (i == sbuf->map->dm_nsegs - 1) { 1433 sbd->type = IPW_SBD_TYPE_DATA; 1434 sbd->priv = sbuf; 1435 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 1436 } else { 1437 sbd->type = IPW_SBD_TYPE_NOASSOC; 1438 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1439 } 1440 1441 DPRINTFN(5, ("sending fragment (%d, %d)\n", i, 1442 (int)sbuf->map->dm_segs[i].ds_len)); 1443 1444 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1445 sc->txcur * sizeof (struct ipw_bd), 1446 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1447 1448 sc->txfree--; 1449 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1450 } 1451 1452 bus_dmamap_sync(sc->sc_dmat, sc->hdr_map, shdr->offset, 1453 sizeof (struct ipw_hdr), BUS_DMASYNC_PREWRITE); 1454 1455 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, MCLBYTES, 1456 BUS_DMASYNC_PREWRITE); 1457 1458 /* Inform firmware about this new packet */ 1459 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1460 1461 return 0; 1462 } 1463 1464 static void 1465 ipw_start(struct ifnet *ifp) 1466 { 1467 struct ipw_softc *sc = ifp->if_softc; 1468 struct ieee80211com *ic = &sc->sc_ic; 1469 struct mbuf *m0; 1470 struct ether_header *eh; 1471 struct ieee80211_node *ni; 1472 1473 1474 if (ic->ic_state != IEEE80211_S_RUN) 1475 return; 1476 1477 for (;;) { 1478 IF_DEQUEUE(&ifp->if_snd, m0); 1479 if (m0 == NULL) 1480 break; 1481 1482 if (sc->txfree < 1 + IPW_MAX_NSEG) { 1483 IF_PREPEND(&ifp->if_snd, m0); 1484 ifp->if_flags |= IFF_OACTIVE; 1485 break; 1486 } 1487 1488 if (m0->m_len < sizeof (struct ether_header) && 1489 (m0 = m_pullup(m0, sizeof (struct ether_header))) == NULL) 1490 continue; 1491 1492 eh = mtod(m0, struct ether_header *); 1493 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1494 if (ni == NULL) { 1495 m_freem(m0); 1496 continue; 1497 } 1498 1499 bpf_mtap(ifp, m0); 1500 1501 m0 = ieee80211_encap(ic, m0, ni); 1502 if (m0 == NULL) { 1503 ieee80211_free_node(ni); 1504 continue; 1505 } 1506 1507 bpf_mtap3(ic->ic_rawbpf, m0); 1508 1509 if (ipw_tx_start(ifp, m0, ni) != 0) { 1510 ieee80211_free_node(ni); 1511 ifp->if_oerrors++; 1512 break; 1513 } 1514 1515 /* start watchdog timer */ 1516 sc->sc_tx_timer = 5; 1517 ifp->if_timer = 1; 1518 } 1519 } 1520 1521 static void 1522 ipw_watchdog(struct ifnet *ifp) 1523 { 1524 struct ipw_softc *sc = ifp->if_softc; 1525 1526 ifp->if_timer = 0; 1527 1528 if (sc->sc_tx_timer > 0) { 1529 if (--sc->sc_tx_timer == 0) { 1530 aprint_error_dev(&sc->sc_dev, "device timeout\n"); 1531 ifp->if_oerrors++; 1532 ifp->if_flags &= ~IFF_UP; 1533 ipw_stop(ifp, 1); 1534 return; 1535 } 1536 ifp->if_timer = 1; 1537 } 1538 1539 ieee80211_watchdog(&sc->sc_ic); 1540 } 1541 1542 static int 1543 ipw_get_table1(struct ipw_softc *sc, uint32_t *tbl) 1544 { 1545 uint32_t addr, size, i; 1546 1547 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1548 return ENOTTY; 1549 1550 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, sc->table1_base); 1551 1552 size = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 1553 if (suword(tbl, size) != 0) 1554 return EFAULT; 1555 1556 for (i = 1, ++tbl; i < size; i++, tbl++) { 1557 addr = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 1558 if (suword(tbl, MEM_READ_4(sc, addr)) != 0) 1559 return EFAULT; 1560 } 1561 return 0; 1562 } 1563 1564 static int 1565 ipw_get_radio(struct ipw_softc *sc, int *ret) 1566 { 1567 uint32_t addr; 1568 1569 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1570 return ENOTTY; 1571 1572 addr = ipw_read_table1(sc, IPW_INFO_EEPROM_ADDRESS); 1573 if ((MEM_READ_4(sc, addr + 32) >> 24) & 1) { 1574 suword(ret, -1); 1575 return 0; 1576 } 1577 1578 if (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED) 1579 suword(ret, 0); 1580 else 1581 suword(ret, 1); 1582 1583 return 0; 1584 } 1585 1586 static int 1587 ipw_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1588 { 1589 #define IS_RUNNING(ifp) \ 1590 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 1591 1592 struct ipw_softc *sc = ifp->if_softc; 1593 struct ieee80211com *ic = &sc->sc_ic; 1594 struct ifreq *ifr = (struct ifreq *)data; 1595 int s, error = 0; 1596 1597 s = splnet(); 1598 1599 switch (cmd) { 1600 case SIOCSIFFLAGS: 1601 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 1602 break; 1603 if (ifp->if_flags & IFF_UP) { 1604 if (!(ifp->if_flags & IFF_RUNNING)) 1605 ipw_init(ifp); 1606 } else { 1607 if (ifp->if_flags & IFF_RUNNING) 1608 ipw_stop(ifp, 1); 1609 } 1610 break; 1611 1612 case SIOCADDMULTI: 1613 case SIOCDELMULTI: 1614 /* XXX no h/w multicast filter? --dyoung */ 1615 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1616 /* setup multicast filter, etc */ 1617 error = 0; 1618 } 1619 break; 1620 1621 case SIOCGTABLE1: 1622 error = ipw_get_table1(sc, (uint32_t *)ifr->ifr_data); 1623 break; 1624 1625 case SIOCGRADIO: 1626 error = ipw_get_radio(sc, (int *)ifr->ifr_data); 1627 break; 1628 1629 case SIOCSIFMEDIA: 1630 if (ifr->ifr_media & IFM_IEEE80211_ADHOC) 1631 sc->sc_fwname = "ipw2100-1.2-i.fw"; 1632 else if (ifr->ifr_media & IFM_IEEE80211_MONITOR) 1633 sc->sc_fwname = "ipw2100-1.2-p.fw"; 1634 else 1635 sc->sc_fwname = "ipw2100-1.2.fw"; 1636 1637 ipw_free_firmware(sc); 1638 /* FALLTRHOUGH */ 1639 default: 1640 error = ieee80211_ioctl(&sc->sc_ic, cmd, data); 1641 if (error != ENETRESET) 1642 break; 1643 1644 if (error == ENETRESET) { 1645 if (IS_RUNNING(ifp) && 1646 (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)) 1647 ipw_init(ifp); 1648 error = 0; 1649 } 1650 1651 } 1652 1653 splx(s); 1654 return error; 1655 #undef IS_RUNNING 1656 } 1657 1658 static uint32_t 1659 ipw_read_table1(struct ipw_softc *sc, uint32_t off) 1660 { 1661 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 1662 } 1663 1664 static void 1665 ipw_write_table1(struct ipw_softc *sc, uint32_t off, uint32_t info) 1666 { 1667 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 1668 } 1669 1670 static int 1671 ipw_read_table2(struct ipw_softc *sc, uint32_t off, void *buf, uint32_t *len) 1672 { 1673 uint32_t addr, info; 1674 uint16_t count, size; 1675 uint32_t total; 1676 1677 /* addr[4] + count[2] + size[2] */ 1678 addr = MEM_READ_4(sc, sc->table2_base + off); 1679 info = MEM_READ_4(sc, sc->table2_base + off + 4); 1680 1681 count = info >> 16; 1682 size = info & 0xffff; 1683 total = count * size; 1684 1685 if (total > *len) { 1686 *len = total; 1687 return EINVAL; 1688 } 1689 1690 *len = total; 1691 ipw_read_mem_1(sc, addr, buf, total); 1692 1693 return 0; 1694 } 1695 1696 static void 1697 ipw_stop_master(struct ipw_softc *sc) 1698 { 1699 int ntries; 1700 1701 /* disable interrupts */ 1702 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1703 1704 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1705 for (ntries = 0; ntries < 50; ntries++) { 1706 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1707 break; 1708 DELAY(10); 1709 } 1710 if (ntries == 50) 1711 aprint_error_dev(&sc->sc_dev, "timeout waiting for master\n"); 1712 1713 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1714 IPW_RST_PRINCETON_RESET); 1715 1716 sc->flags &= ~IPW_FLAG_FW_INITED; 1717 } 1718 1719 static int 1720 ipw_reset(struct ipw_softc *sc) 1721 { 1722 int ntries; 1723 1724 ipw_stop_master(sc); 1725 1726 /* move adapter to D0 state */ 1727 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1728 IPW_CTL_INIT); 1729 1730 /* wait for clock stabilization */ 1731 for (ntries = 0; ntries < 1000; ntries++) { 1732 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY) 1733 break; 1734 DELAY(200); 1735 } 1736 if (ntries == 1000) 1737 return EIO; 1738 1739 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1740 IPW_RST_SW_RESET); 1741 1742 DELAY(10); 1743 1744 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1745 IPW_CTL_INIT); 1746 1747 return 0; 1748 } 1749 1750 /* 1751 * Upload the microcode to the device. 1752 */ 1753 static int 1754 ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size) 1755 { 1756 int ntries; 1757 1758 MEM_WRITE_4(sc, 0x3000e0, 0x80000000); 1759 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1760 1761 MEM_WRITE_2(sc, 0x220000, 0x0703); 1762 MEM_WRITE_2(sc, 0x220000, 0x0707); 1763 1764 MEM_WRITE_1(sc, 0x210014, 0x72); 1765 MEM_WRITE_1(sc, 0x210014, 0x72); 1766 1767 MEM_WRITE_1(sc, 0x210000, 0x40); 1768 MEM_WRITE_1(sc, 0x210000, 0x00); 1769 MEM_WRITE_1(sc, 0x210000, 0x40); 1770 1771 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1772 1773 MEM_WRITE_1(sc, 0x210000, 0x00); 1774 MEM_WRITE_1(sc, 0x210000, 0x00); 1775 MEM_WRITE_1(sc, 0x210000, 0x80); 1776 1777 MEM_WRITE_2(sc, 0x220000, 0x0703); 1778 MEM_WRITE_2(sc, 0x220000, 0x0707); 1779 1780 MEM_WRITE_1(sc, 0x210014, 0x72); 1781 MEM_WRITE_1(sc, 0x210014, 0x72); 1782 1783 MEM_WRITE_1(sc, 0x210000, 0x00); 1784 MEM_WRITE_1(sc, 0x210000, 0x80); 1785 1786 for (ntries = 0; ntries < 10; ntries++) { 1787 if (MEM_READ_1(sc, 0x210000) & 1) 1788 break; 1789 DELAY(10); 1790 } 1791 if (ntries == 10) { 1792 aprint_error_dev(&sc->sc_dev, "timeout waiting for ucode to initialize\n"); 1793 return EIO; 1794 } 1795 1796 MEM_WRITE_4(sc, 0x3000e0, 0); 1797 1798 return 0; 1799 } 1800 1801 /* set of macros to handle unaligned little endian data in firmware image */ 1802 #define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1803 #define GETLE16(p) ((p)[0] | (p)[1] << 8) 1804 static int 1805 ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size) 1806 { 1807 u_char *p, *end; 1808 uint32_t dst; 1809 uint16_t len; 1810 int error; 1811 1812 p = fw; 1813 end = fw + size; 1814 while (p < end) { 1815 dst = GETLE32(p); p += 4; 1816 len = GETLE16(p); p += 2; 1817 1818 ipw_write_mem_1(sc, dst, p, len); 1819 p += len; 1820 } 1821 1822 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1823 IPW_IO_LED_OFF); 1824 1825 /* enable interrupts */ 1826 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1827 1828 /* kick the firmware */ 1829 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1830 1831 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1832 IPW_CTL_ALLOW_STANDBY); 1833 1834 /* wait at most one second for firmware initialization to complete */ 1835 if ((error = tsleep(sc, 0, "ipwinit", hz)) != 0) { 1836 aprint_error_dev(&sc->sc_dev, "timeout waiting for firmware initialization " 1837 "to complete\n"); 1838 return error; 1839 } 1840 1841 CSR_WRITE_4(sc, IPW_CSR_IO, CSR_READ_4(sc, IPW_CSR_IO) | 1842 IPW_IO_GPIO1_MASK | IPW_IO_GPIO3_MASK); 1843 1844 return 0; 1845 } 1846 1847 /* 1848 * Store firmware into kernel memory so we can download it when we need to, 1849 * e.g when the adapter wakes up from suspend mode. 1850 */ 1851 static int 1852 ipw_cache_firmware(struct ipw_softc *sc) 1853 { 1854 struct ipw_firmware *fw = &sc->fw; 1855 struct ipw_firmware_hdr hdr; 1856 firmware_handle_t fwh; 1857 off_t fwsz, p; 1858 int error; 1859 1860 ipw_free_firmware(sc); 1861 1862 if (ipw_accept_eula == 0) { 1863 aprint_error_dev(&sc->sc_dev, 1864 "EULA not accepted; please see the ipw(4) man page.\n"); 1865 return EPERM; 1866 } 1867 1868 if ((error = firmware_open("if_ipw", sc->sc_fwname, &fwh)) != 0) 1869 goto fail0; 1870 1871 fwsz = firmware_get_size(fwh); 1872 1873 if (fwsz < sizeof(hdr)) 1874 goto fail2; 1875 1876 if ((error = firmware_read(fwh, 0, &hdr, sizeof(hdr))) != 0) 1877 goto fail2; 1878 1879 fw->main_size = le32toh(hdr.main_size); 1880 fw->ucode_size = le32toh(hdr.ucode_size); 1881 1882 fw->main = firmware_malloc(fw->main_size); 1883 if (fw->main == NULL) { 1884 error = ENOMEM; 1885 goto fail1; 1886 } 1887 1888 fw->ucode = firmware_malloc(fw->ucode_size); 1889 if (fw->ucode == NULL) { 1890 error = ENOMEM; 1891 goto fail2; 1892 } 1893 1894 p = sizeof(hdr); 1895 if ((error = firmware_read(fwh, p, fw->main, fw->main_size)) != 0) 1896 goto fail3; 1897 1898 p += fw->main_size; 1899 if ((error = firmware_read(fwh, p, fw->ucode, fw->ucode_size)) != 0) 1900 goto fail3; 1901 1902 DPRINTF(("Firmware cached: main %u, ucode %u\n", fw->main_size, 1903 fw->ucode_size)); 1904 1905 sc->flags |= IPW_FLAG_FW_CACHED; 1906 1907 firmware_close(fwh); 1908 1909 return 0; 1910 1911 fail3: firmware_free(fw->ucode, 0); 1912 fail2: firmware_free(fw->main, 0); 1913 fail1: firmware_close(fwh); 1914 fail0: 1915 return error; 1916 } 1917 1918 static void 1919 ipw_free_firmware(struct ipw_softc *sc) 1920 { 1921 if (!(sc->flags & IPW_FLAG_FW_CACHED)) 1922 return; 1923 1924 firmware_free(sc->fw.main, 0); 1925 firmware_free(sc->fw.ucode, 0); 1926 1927 sc->flags &= ~IPW_FLAG_FW_CACHED; 1928 } 1929 1930 static int 1931 ipw_config(struct ipw_softc *sc) 1932 { 1933 struct ieee80211com *ic = &sc->sc_ic; 1934 struct ifnet *ifp = &sc->sc_if; 1935 struct ipw_security security; 1936 struct ieee80211_key *k; 1937 struct ipw_wep_key wepkey; 1938 struct ipw_scan_options options; 1939 struct ipw_configuration config; 1940 uint32_t data; 1941 int error, i; 1942 1943 switch (ic->ic_opmode) { 1944 case IEEE80211_M_STA: 1945 case IEEE80211_M_HOSTAP: 1946 data = htole32(IPW_MODE_BSS); 1947 break; 1948 1949 case IEEE80211_M_IBSS: 1950 case IEEE80211_M_AHDEMO: 1951 data = htole32(IPW_MODE_IBSS); 1952 break; 1953 1954 case IEEE80211_M_MONITOR: 1955 data = htole32(IPW_MODE_MONITOR); 1956 break; 1957 } 1958 DPRINTF(("Setting mode to %u\n", le32toh(data))); 1959 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 1960 if (error != 0) 1961 return error; 1962 1963 if (ic->ic_opmode == IEEE80211_M_IBSS || 1964 ic->ic_opmode == IEEE80211_M_MONITOR) { 1965 data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); 1966 DPRINTF(("Setting channel to %u\n", le32toh(data))); 1967 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 1968 if (error != 0) 1969 return error; 1970 } 1971 1972 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1973 DPRINTF(("Enabling adapter\n")); 1974 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1975 } 1976 1977 DPRINTF(("Setting MAC to %s\n", ether_sprintf(ic->ic_myaddr))); 1978 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 1979 IEEE80211_ADDR_LEN); 1980 if (error != 0) 1981 return error; 1982 1983 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 1984 IPW_CFG_PREAMBLE_AUTO | IPW_CFG_802_1x_ENABLE); 1985 1986 if (ic->ic_opmode == IEEE80211_M_IBSS) 1987 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 1988 if (ifp->if_flags & IFF_PROMISC) 1989 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 1990 config.bss_chan = htole32(0x3fff); /* channels 1-14 */ 1991 config.ibss_chan = htole32(0x7ff); /* channels 1-11 */ 1992 DPRINTF(("Setting adapter configuration 0x%08x\n", config.flags)); 1993 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 1994 if (error != 0) 1995 return error; 1996 1997 data = htole32(0x3); /* 1, 2 */ 1998 DPRINTF(("Setting basic tx rates to 0x%x\n", le32toh(data))); 1999 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 2000 if (error != 0) 2001 return error; 2002 2003 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 2004 DPRINTF(("Setting tx rates to 0x%x\n", le32toh(data))); 2005 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 2006 if (error != 0) 2007 return error; 2008 2009 data = htole32(IPW_POWER_MODE_CAM); 2010 DPRINTF(("Setting power mode to %u\n", le32toh(data))); 2011 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 2012 if (error != 0) 2013 return error; 2014 2015 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2016 data = htole32(32); /* default value */ 2017 DPRINTF(("Setting tx power index to %u\n", le32toh(data))); 2018 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 2019 sizeof data); 2020 if (error != 0) 2021 return error; 2022 } 2023 2024 data = htole32(ic->ic_rtsthreshold); 2025 DPRINTF(("Setting RTS threshold to %u\n", le32toh(data))); 2026 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 2027 if (error != 0) 2028 return error; 2029 2030 data = htole32(ic->ic_fragthreshold); 2031 DPRINTF(("Setting frag threshold to %u\n", le32toh(data))); 2032 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 2033 if (error != 0) 2034 return error; 2035 2036 #ifdef IPW_DEBUG 2037 if (ipw_debug > 0) { 2038 printf("Setting ESSID to "); 2039 ieee80211_print_essid(ic->ic_des_essid, ic->ic_des_esslen); 2040 printf("\n"); 2041 } 2042 #endif 2043 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ic->ic_des_essid, 2044 ic->ic_des_esslen); 2045 if (error != 0) 2046 return error; 2047 2048 /* no mandatory BSSID */ 2049 DPRINTF(("Setting mandatory BSSID to null\n")); 2050 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 2051 if (error != 0) 2052 return error; 2053 2054 if (ic->ic_flags & IEEE80211_F_DESBSSID) { 2055 DPRINTF(("Setting desired BSSID to %s\n", 2056 ether_sprintf(ic->ic_des_bssid))); 2057 error = ipw_cmd(sc, IPW_CMD_SET_DESIRED_BSSID, 2058 ic->ic_des_bssid, IEEE80211_ADDR_LEN); 2059 if (error != 0) 2060 return error; 2061 } 2062 2063 (void)memset(&security, 0, sizeof(security)); 2064 security.authmode = (ic->ic_bss->ni_authmode == IEEE80211_AUTH_SHARED) ? 2065 IPW_AUTH_SHARED : IPW_AUTH_OPEN; 2066 security.ciphers = htole32(IPW_CIPHER_NONE); 2067 DPRINTF(("Setting authmode to %u\n", security.authmode)); 2068 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 2069 sizeof security); 2070 if (error != 0) 2071 return error; 2072 2073 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 2074 k = ic->ic_crypto.cs_nw_keys; 2075 for (i = 0; i < IEEE80211_WEP_NKID; i++, k++) { 2076 if (k->wk_keylen == 0) 2077 continue; 2078 2079 wepkey.idx = i; 2080 wepkey.len = k->wk_keylen; 2081 memset(wepkey.key, 0, sizeof(wepkey.key)); 2082 memcpy(wepkey.key, k->wk_key, k->wk_keylen); 2083 DPRINTF(("Setting wep key index %u len %u\n", 2084 wepkey.idx, wepkey.len)); 2085 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY, &wepkey, 2086 sizeof wepkey); 2087 if (error != 0) 2088 return error; 2089 } 2090 2091 data = htole32(ic->ic_crypto.cs_def_txkey); 2092 DPRINTF(("Setting tx key index to %u\n", le32toh(data))); 2093 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY_INDEX, &data, 2094 sizeof data); 2095 if (error != 0) 2096 return error; 2097 } 2098 2099 data = htole32((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) ? IPW_WEPON : 0); 2100 DPRINTF(("Setting wep flags to 0x%x\n", le32toh(data))); 2101 error = ipw_cmd(sc, IPW_CMD_SET_WEP_FLAGS, &data, sizeof data); 2102 if (error != 0) 2103 return error; 2104 2105 #if 0 2106 struct ipw_wpa_ie ie; 2107 2108 memset(&ie, 0 sizeof(ie)); 2109 ie.len = htole32(sizeof (struct ieee80211_ie_wpa)); 2110 DPRINTF(("Setting wpa ie\n")); 2111 error = ipw_cmd(sc, IPW_CMD_SET_WPA_IE, &ie, sizeof ie); 2112 if (error != 0) 2113 return error; 2114 #endif 2115 2116 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2117 data = htole32(ic->ic_bintval); 2118 DPRINTF(("Setting beacon interval to %u\n", le32toh(data))); 2119 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 2120 sizeof data); 2121 if (error != 0) 2122 return error; 2123 } 2124 2125 options.flags = 0; 2126 options.channels = htole32(0x3fff); /* scan channels 1-14 */ 2127 DPRINTF(("Setting scan options to 0x%x\n", le32toh(options.flags))); 2128 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &options, sizeof options); 2129 if (error != 0) 2130 return error; 2131 2132 /* finally, enable adapter (start scanning for an access point) */ 2133 DPRINTF(("Enabling adapter\n")); 2134 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 2135 } 2136 2137 static int 2138 ipw_init(struct ifnet *ifp) 2139 { 2140 struct ipw_softc *sc = ifp->if_softc; 2141 struct ipw_firmware *fw = &sc->fw; 2142 2143 if (!(sc->flags & IPW_FLAG_FW_CACHED)) { 2144 if (ipw_cache_firmware(sc) != 0) { 2145 aprint_error_dev(&sc->sc_dev, "could not cache the firmware (%s)\n", 2146 sc->sc_fwname); 2147 goto fail; 2148 } 2149 } 2150 2151 ipw_stop(ifp, 0); 2152 2153 if (ipw_reset(sc) != 0) { 2154 aprint_error_dev(&sc->sc_dev, "could not reset adapter\n"); 2155 goto fail; 2156 } 2157 2158 if (ipw_load_ucode(sc, fw->ucode, fw->ucode_size) != 0) { 2159 aprint_error_dev(&sc->sc_dev, "could not load microcode\n"); 2160 goto fail; 2161 } 2162 2163 ipw_stop_master(sc); 2164 2165 /* 2166 * Setup tx, rx and status rings. 2167 */ 2168 sc->txold = IPW_NTBD - 1; 2169 sc->txcur = 0; 2170 sc->txfree = IPW_NTBD - 2; 2171 sc->rxcur = IPW_NRBD - 1; 2172 2173 CSR_WRITE_4(sc, IPW_CSR_TX_BASE, sc->tbd_map->dm_segs[0].ds_addr); 2174 CSR_WRITE_4(sc, IPW_CSR_TX_SIZE, IPW_NTBD); 2175 CSR_WRITE_4(sc, IPW_CSR_TX_READ, 0); 2176 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 2177 2178 CSR_WRITE_4(sc, IPW_CSR_RX_BASE, sc->rbd_map->dm_segs[0].ds_addr); 2179 CSR_WRITE_4(sc, IPW_CSR_RX_SIZE, IPW_NRBD); 2180 CSR_WRITE_4(sc, IPW_CSR_RX_READ, 0); 2181 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 2182 2183 CSR_WRITE_4(sc, IPW_CSR_STATUS_BASE, sc->status_map->dm_segs[0].ds_addr); 2184 2185 if (ipw_load_firmware(sc, fw->main, fw->main_size) != 0) { 2186 aprint_error_dev(&sc->sc_dev, "could not load firmware\n"); 2187 goto fail; 2188 } 2189 2190 sc->flags |= IPW_FLAG_FW_INITED; 2191 2192 /* retrieve information tables base addresses */ 2193 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 2194 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 2195 2196 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 2197 2198 if (ipw_config(sc) != 0) { 2199 aprint_error_dev(&sc->sc_dev, "device configuration failed\n"); 2200 goto fail; 2201 } 2202 2203 ifp->if_flags &= ~IFF_OACTIVE; 2204 ifp->if_flags |= IFF_RUNNING; 2205 2206 return 0; 2207 2208 fail: ifp->if_flags &= ~IFF_UP; 2209 ipw_stop(ifp, 0); 2210 2211 return EIO; 2212 } 2213 2214 static void 2215 ipw_stop(struct ifnet *ifp, int disable) 2216 { 2217 struct ipw_softc *sc = ifp->if_softc; 2218 struct ieee80211com *ic = &sc->sc_ic; 2219 int i; 2220 2221 ipw_stop_master(sc); 2222 2223 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 2224 2225 /* 2226 * Release tx buffers. 2227 */ 2228 for (i = 0; i < IPW_NTBD; i++) 2229 ipw_release_sbd(sc, &sc->stbd_list[i]); 2230 2231 sc->sc_tx_timer = 0; 2232 ifp->if_timer = 0; 2233 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2234 2235 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2236 } 2237 2238 static void 2239 ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2240 bus_size_t count) 2241 { 2242 for (; count > 0; offset++, datap++, count--) { 2243 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2244 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 2245 } 2246 } 2247 2248 static void 2249 ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2250 bus_size_t count) 2251 { 2252 for (; count > 0; offset++, datap++, count--) { 2253 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2254 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 2255 } 2256 } 2257 2258 SYSCTL_SETUP(sysctl_hw_ipw_accept_eula_setup, "sysctl hw.ipw.accept_eula") 2259 { 2260 const struct sysctlnode *rnode; 2261 const struct sysctlnode *cnode; 2262 2263 sysctl_createv(NULL, 0, NULL, &rnode, 2264 CTLFLAG_PERMANENT, 2265 CTLTYPE_NODE, "hw", 2266 NULL, 2267 NULL, 0, 2268 NULL, 0, 2269 CTL_HW, CTL_EOL); 2270 2271 sysctl_createv(NULL, 0, &rnode, &rnode, 2272 CTLFLAG_PERMANENT, 2273 CTLTYPE_NODE, "ipw", 2274 NULL, 2275 NULL, 0, 2276 NULL, 0, 2277 CTL_CREATE, CTL_EOL); 2278 2279 sysctl_createv(NULL, 0, &rnode, &cnode, 2280 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, 2281 CTLTYPE_INT, "accept_eula", 2282 SYSCTL_DESCR("Accept Intel EULA and permit use of ipw(4) firmware"), 2283 NULL, 0, 2284 &ipw_accept_eula, sizeof(ipw_accept_eula), 2285 CTL_CREATE, CTL_EOL); 2286 } 2287
Indexes created Tue Sep 30 11:09:46 GMT 2025