if_ipw.c revision 1.52.8.1
1 /* $NetBSD: if_ipw.c,v 1.52.8.1 2012/04/17 00:07:47 yamt Exp $ */ 2 /* FreeBSD: src/sys/dev/ipw/if_ipw.c,v 1.15 2005/11/13 17:17:40 damien Exp */ 3 4 /*- 5 * Copyright (c) 2004, 2005 6 * Damien Bergamini <damien.bergamini (at) free.fr>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: if_ipw.c,v 1.52.8.1 2012/04/17 00:07:47 yamt Exp $"); 33 34 /*- 35 * Intel(R) PRO/Wireless 2100 MiniPCI driver 36 * http://www.intel.com/network/connectivity/products/wireless/prowireless_mobile.htm 37 */ 38 39 40 #include <sys/param.h> 41 #include <sys/sockio.h> 42 #include <sys/sysctl.h> 43 #include <sys/mbuf.h> 44 #include <sys/kernel.h> 45 #include <sys/socket.h> 46 #include <sys/systm.h> 47 #include <sys/malloc.h> 48 #include <sys/conf.h> 49 #include <sys/proc.h> 50 51 #include <sys/bus.h> 52 #include <machine/endian.h> 53 #include <sys/intr.h> 54 55 #include <dev/pci/pcireg.h> 56 #include <dev/pci/pcivar.h> 57 #include <dev/pci/pcidevs.h> 58 59 #include <net/bpf.h> 60 #include <net/if.h> 61 #include <net/if_arp.h> 62 #include <net/if_dl.h> 63 #include <net/if_ether.h> 64 #include <net/if_media.h> 65 #include <net/if_types.h> 66 67 #include <net80211/ieee80211_var.h> 68 #include <net80211/ieee80211_radiotap.h> 69 70 #include <netinet/in.h> 71 #include <netinet/in_systm.h> 72 #include <netinet/in_var.h> 73 #include <netinet/ip.h> 74 75 #include <dev/firmload.h> 76 77 #include <dev/pci/if_ipwreg.h> 78 #include <dev/pci/if_ipwvar.h> 79 80 #ifdef IPW_DEBUG 81 #define DPRINTF(x) if (ipw_debug > 0) printf x 82 #define DPRINTFN(n, x) if (ipw_debug >= (n)) printf x 83 int ipw_debug = 0; 84 #else 85 #define DPRINTF(x) 86 #define DPRINTFN(n, x) 87 #endif 88 89 /* Permit loading the Intel firmware */ 90 static int ipw_accept_eula; 91 92 static int ipw_dma_alloc(struct ipw_softc *); 93 static void ipw_release(struct ipw_softc *); 94 static int ipw_match(device_t, cfdata_t, void *); 95 static void ipw_attach(device_t, device_t, void *); 96 static int ipw_detach(device_t, int); 97 98 static int ipw_media_change(struct ifnet *); 99 static void ipw_media_status(struct ifnet *, struct ifmediareq *); 100 static int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 101 static uint16_t ipw_read_prom_word(struct ipw_softc *, uint8_t); 102 static void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 103 static void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 104 static void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 105 struct ipw_soft_bd *, struct ipw_soft_buf *); 106 static void ipw_rx_intr(struct ipw_softc *); 107 static void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 108 static void ipw_tx_intr(struct ipw_softc *); 109 static int ipw_intr(void *); 110 static int ipw_cmd(struct ipw_softc *, uint32_t, void *, uint32_t); 111 static int ipw_tx_start(struct ifnet *, struct mbuf *, 112 struct ieee80211_node *); 113 static void ipw_start(struct ifnet *); 114 static void ipw_watchdog(struct ifnet *); 115 static int ipw_ioctl(struct ifnet *, u_long, void *); 116 static int ipw_get_table1(struct ipw_softc *, uint32_t *); 117 static int ipw_get_radio(struct ipw_softc *, int *); 118 static void ipw_stop_master(struct ipw_softc *); 119 static int ipw_reset(struct ipw_softc *); 120 static int ipw_load_ucode(struct ipw_softc *, u_char *, int); 121 static int ipw_load_firmware(struct ipw_softc *, u_char *, int); 122 static int ipw_cache_firmware(struct ipw_softc *); 123 static void ipw_free_firmware(struct ipw_softc *); 124 static int ipw_config(struct ipw_softc *); 125 static int ipw_init(struct ifnet *); 126 static void ipw_stop(struct ifnet *, int); 127 static uint32_t ipw_read_table1(struct ipw_softc *, uint32_t); 128 static void ipw_write_table1(struct ipw_softc *, uint32_t, uint32_t); 129 static int ipw_read_table2(struct ipw_softc *, uint32_t, void *, uint32_t *); 130 static void ipw_read_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 131 bus_size_t); 132 static void ipw_write_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 133 bus_size_t); 134 135 /* 136 * Supported rates for 802.11b mode (in 500Kbps unit). 137 */ 138 static const struct ieee80211_rateset ipw_rateset_11b = 139 { 4, { 2, 4, 11, 22 } }; 140 141 static inline uint8_t 142 MEM_READ_1(struct ipw_softc *sc, uint32_t addr) 143 { 144 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 145 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); 146 } 147 148 static inline uint32_t 149 MEM_READ_4(struct ipw_softc *sc, uint32_t addr) 150 { 151 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 152 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); 153 } 154 155 CFATTACH_DECL(ipw, sizeof (struct ipw_softc), ipw_match, ipw_attach, 156 ipw_detach, NULL); 157 158 static int 159 ipw_match(device_t parent, cfdata_t match, void *aux) 160 { 161 struct pci_attach_args *pa = aux; 162 163 if (PCI_VENDOR (pa->pa_id) == PCI_VENDOR_INTEL && 164 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_PRO_WL_2100) 165 return 1; 166 167 return 0; 168 } 169 170 /* Base Address Register */ 171 #define IPW_PCI_BAR0 0x10 172 173 static void 174 ipw_attach(device_t parent, device_t self, void *aux) 175 { 176 struct ipw_softc *sc = device_private(self); 177 struct ieee80211com *ic = &sc->sc_ic; 178 struct ifnet *ifp = &sc->sc_if; 179 struct pci_attach_args *pa = aux; 180 const char *intrstr; 181 bus_space_tag_t memt; 182 bus_space_handle_t memh; 183 bus_addr_t base; 184 pci_intr_handle_t ih; 185 uint32_t data; 186 uint16_t val; 187 int i, error; 188 189 sc->sc_pct = pa->pa_pc; 190 sc->sc_pcitag = pa->pa_tag; 191 192 pci_aprint_devinfo(pa, NULL); 193 194 /* enable bus-mastering */ 195 data = pci_conf_read(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG); 196 data |= PCI_COMMAND_MASTER_ENABLE; 197 pci_conf_write(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG, data); 198 199 /* map the register window */ 200 error = pci_mapreg_map(pa, IPW_PCI_BAR0, PCI_MAPREG_TYPE_MEM | 201 PCI_MAPREG_MEM_TYPE_32BIT, 0, &memt, &memh, &base, &sc->sc_sz); 202 if (error != 0) { 203 aprint_error_dev(&sc->sc_dev, "could not map memory space\n"); 204 return; 205 } 206 207 sc->sc_st = memt; 208 sc->sc_sh = memh; 209 sc->sc_dmat = pa->pa_dmat; 210 sc->sc_fwname = "ipw2100-1.2.fw"; 211 212 /* disable interrupts */ 213 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 214 215 if (pci_intr_map(pa, &ih) != 0) { 216 aprint_error_dev(&sc->sc_dev, "could not map interrupt\n"); 217 return; 218 } 219 220 intrstr = pci_intr_string(sc->sc_pct, ih); 221 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, ipw_intr, sc); 222 if (sc->sc_ih == NULL) { 223 aprint_error_dev(&sc->sc_dev, "could not establish interrupt"); 224 if (intrstr != NULL) 225 aprint_error(" at %s", intrstr); 226 aprint_error("\n"); 227 return; 228 } 229 aprint_normal_dev(&sc->sc_dev, "interrupting at %s\n", intrstr); 230 231 if (ipw_reset(sc) != 0) { 232 aprint_error_dev(&sc->sc_dev, "could not reset adapter\n"); 233 goto fail; 234 } 235 236 if (ipw_dma_alloc(sc) != 0) { 237 aprint_error_dev(&sc->sc_dev, "could not allocate DMA resources\n"); 238 goto fail; 239 } 240 241 ifp->if_softc = sc; 242 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 243 ifp->if_init = ipw_init; 244 ifp->if_stop = ipw_stop; 245 ifp->if_ioctl = ipw_ioctl; 246 ifp->if_start = ipw_start; 247 ifp->if_watchdog = ipw_watchdog; 248 IFQ_SET_READY(&ifp->if_snd); 249 strlcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 250 251 ic->ic_ifp = ifp; 252 ic->ic_phytype = IEEE80211_T_DS; 253 ic->ic_opmode = IEEE80211_M_STA; 254 ic->ic_state = IEEE80211_S_INIT; 255 256 /* set device capabilities */ 257 ic->ic_caps = 258 IEEE80211_C_SHPREAMBLE /* short preamble supported */ 259 | IEEE80211_C_TXPMGT /* tx power management */ 260 | IEEE80211_C_IBSS /* ibss mode */ 261 | IEEE80211_C_MONITOR /* monitor mode */ 262 ; 263 264 /* read MAC address from EEPROM */ 265 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0); 266 ic->ic_myaddr[0] = val >> 8; 267 ic->ic_myaddr[1] = val & 0xff; 268 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 1); 269 ic->ic_myaddr[2] = val >> 8; 270 ic->ic_myaddr[3] = val & 0xff; 271 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 2); 272 ic->ic_myaddr[4] = val >> 8; 273 ic->ic_myaddr[5] = val & 0xff; 274 275 /* set supported .11b rates */ 276 ic->ic_sup_rates[IEEE80211_MODE_11B] = ipw_rateset_11b; 277 278 /* set supported .11b channels (read from EEPROM) */ 279 if ((val = ipw_read_prom_word(sc, IPW_EEPROM_CHANNEL_LIST)) == 0) 280 val = 0x7ff; /* default to channels 1-11 */ 281 val <<= 1; 282 for (i = 1; i < 16; i++) { 283 if (val & (1 << i)) { 284 ic->ic_channels[i].ic_freq = 285 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 286 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 287 } 288 } 289 290 /* check support for radio transmitter switch in EEPROM */ 291 if (!(ipw_read_prom_word(sc, IPW_EEPROM_RADIO) & 8)) 292 sc->flags |= IPW_FLAG_HAS_RADIO_SWITCH; 293 294 aprint_normal_dev(&sc->sc_dev, "802.11 address %s\n", 295 ether_sprintf(ic->ic_myaddr)); 296 297 if_attach(ifp); 298 ieee80211_ifattach(ic); 299 300 /* override state transition machine */ 301 sc->sc_newstate = ic->ic_newstate; 302 ic->ic_newstate = ipw_newstate; 303 304 ieee80211_media_init(ic, ipw_media_change, ipw_media_status); 305 306 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 307 sizeof(struct ieee80211_frame) + 64, &sc->sc_drvbpf); 308 309 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 310 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 311 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 312 313 sc->sc_txtap_len = sizeof sc->sc_txtapu; 314 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 315 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 316 317 /* 318 * Add a few sysctl knobs. 319 * XXX: Not yet 320 */ 321 sc->dwelltime = 100; 322 323 if (pmf_device_register(self, NULL, NULL)) 324 pmf_class_network_register(self, ifp); 325 else 326 aprint_error_dev(self, "couldn't establish power handler\n"); 327 328 ieee80211_announce(ic); 329 330 return; 331 332 fail: ipw_detach(self, 0); 333 } 334 335 static int 336 ipw_detach(struct device* self, int flags) 337 { 338 struct ipw_softc *sc = device_private(self); 339 struct ifnet *ifp = &sc->sc_if; 340 341 if (ifp->if_softc) { 342 ipw_stop(ifp, 1); 343 ipw_free_firmware(sc); 344 345 bpf_detach(ifp); 346 ieee80211_ifdetach(&sc->sc_ic); 347 if_detach(ifp); 348 349 ipw_release(sc); 350 } 351 352 if (sc->sc_ih != NULL) { 353 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 354 sc->sc_ih = NULL; 355 } 356 357 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 358 359 return 0; 360 } 361 362 static int 363 ipw_dma_alloc(struct ipw_softc *sc) 364 { 365 struct ipw_soft_bd *sbd; 366 struct ipw_soft_hdr *shdr; 367 struct ipw_soft_buf *sbuf; 368 int error, i, nsegs; 369 370 /* 371 * Allocate and map tx ring. 372 */ 373 error = bus_dmamap_create(sc->sc_dmat, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, 374 BUS_DMA_NOWAIT, &sc->tbd_map); 375 if (error != 0) { 376 aprint_error_dev(&sc->sc_dev, "could not create tbd dma map\n"); 377 goto fail; 378 } 379 380 error = bus_dmamem_alloc(sc->sc_dmat, IPW_TBD_SZ, PAGE_SIZE, 0, 381 &sc->tbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 382 if (error != 0) { 383 aprint_error_dev(&sc->sc_dev, "could not allocate tbd dma memory\n"); 384 goto fail; 385 } 386 387 error = bus_dmamem_map(sc->sc_dmat, &sc->tbd_seg, nsegs, IPW_TBD_SZ, 388 (void **)&sc->tbd_list, BUS_DMA_NOWAIT); 389 if (error != 0) { 390 aprint_error_dev(&sc->sc_dev, "could not map tbd dma memory\n"); 391 goto fail; 392 } 393 394 error = bus_dmamap_load(sc->sc_dmat, sc->tbd_map, sc->tbd_list, 395 IPW_TBD_SZ, NULL, BUS_DMA_NOWAIT); 396 if (error != 0) { 397 aprint_error_dev(&sc->sc_dev, "could not load tbd dma memory\n"); 398 goto fail; 399 } 400 401 (void)memset(sc->tbd_list, 0, IPW_TBD_SZ); 402 403 /* 404 * Allocate and map rx ring. 405 */ 406 error = bus_dmamap_create(sc->sc_dmat, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, 407 BUS_DMA_NOWAIT, &sc->rbd_map); 408 if (error != 0) { 409 aprint_error_dev(&sc->sc_dev, "could not create rbd dma map\n"); 410 goto fail; 411 } 412 413 error = bus_dmamem_alloc(sc->sc_dmat, IPW_RBD_SZ, PAGE_SIZE, 0, 414 &sc->rbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 415 if (error != 0) { 416 aprint_error_dev(&sc->sc_dev, "could not allocate rbd dma memory\n"); 417 goto fail; 418 } 419 420 error = bus_dmamem_map(sc->sc_dmat, &sc->rbd_seg, nsegs, IPW_RBD_SZ, 421 (void **)&sc->rbd_list, BUS_DMA_NOWAIT); 422 if (error != 0) { 423 aprint_error_dev(&sc->sc_dev, "could not map rbd dma memory\n"); 424 goto fail; 425 } 426 427 error = bus_dmamap_load(sc->sc_dmat, sc->rbd_map, sc->rbd_list, 428 IPW_RBD_SZ, NULL, BUS_DMA_NOWAIT); 429 if (error != 0) { 430 aprint_error_dev(&sc->sc_dev, "could not load rbd dma memory\n"); 431 goto fail; 432 } 433 434 (void)memset(sc->rbd_list, 0, IPW_RBD_SZ); 435 436 /* 437 * Allocate and map status ring. 438 */ 439 error = bus_dmamap_create(sc->sc_dmat, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 440 0, BUS_DMA_NOWAIT, &sc->status_map); 441 if (error != 0) { 442 aprint_error_dev(&sc->sc_dev, "could not create status dma map\n"); 443 goto fail; 444 } 445 446 error = bus_dmamem_alloc(sc->sc_dmat, IPW_STATUS_SZ, PAGE_SIZE, 0, 447 &sc->status_seg, 1, &nsegs, BUS_DMA_NOWAIT); 448 if (error != 0) { 449 aprint_error_dev(&sc->sc_dev, "could not allocate status dma memory\n"); 450 goto fail; 451 } 452 453 error = bus_dmamem_map(sc->sc_dmat, &sc->status_seg, nsegs, 454 IPW_STATUS_SZ, (void **)&sc->status_list, BUS_DMA_NOWAIT); 455 if (error != 0) { 456 aprint_error_dev(&sc->sc_dev, "could not map status dma memory\n"); 457 goto fail; 458 } 459 460 error = bus_dmamap_load(sc->sc_dmat, sc->status_map, sc->status_list, 461 IPW_STATUS_SZ, NULL, BUS_DMA_NOWAIT); 462 if (error != 0) { 463 aprint_error_dev(&sc->sc_dev, "could not load status dma memory\n"); 464 goto fail; 465 } 466 467 (void)memset(sc->status_list, 0, IPW_STATUS_SZ); 468 469 /* 470 * Allocate command DMA map. 471 */ 472 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_cmd), 473 1, sizeof (struct ipw_cmd), 0, BUS_DMA_NOWAIT, &sc->cmd_map); 474 if (error != 0) { 475 aprint_error_dev(&sc->sc_dev, "could not create cmd dma map\n"); 476 goto fail; 477 } 478 479 error = bus_dmamem_alloc(sc->sc_dmat, sizeof (struct ipw_cmd), 480 PAGE_SIZE, 0, &sc->cmd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 481 if (error != 0) { 482 aprint_error_dev(&sc->sc_dev, "could not allocate cmd dma memory\n"); 483 goto fail; 484 } 485 486 error = bus_dmamem_map(sc->sc_dmat, &sc->cmd_seg, nsegs, 487 sizeof (struct ipw_cmd), (void **)&sc->cmd, BUS_DMA_NOWAIT); 488 if (error != 0) { 489 aprint_error_dev(&sc->sc_dev, "could not map cmd dma memory\n"); 490 goto fail; 491 } 492 493 error = bus_dmamap_load(sc->sc_dmat, sc->cmd_map, &sc->cmd, 494 sizeof (struct ipw_cmd), NULL, BUS_DMA_NOWAIT); 495 if (error != 0) { 496 aprint_error_dev(&sc->sc_dev, "could not map cmd dma memory\n"); 497 return error; 498 } 499 500 /* 501 * Allocate and map hdr list. 502 */ 503 504 error = bus_dmamap_create(sc->sc_dmat, 505 IPW_NDATA * sizeof(struct ipw_hdr), 1, 506 sizeof(struct ipw_hdr), 0, BUS_DMA_NOWAIT, 507 &sc->hdr_map); 508 if (error != 0) { 509 aprint_error_dev(&sc->sc_dev, "could not create hdr dma map\n"); 510 goto fail; 511 } 512 513 error = bus_dmamem_alloc(sc->sc_dmat, 514 IPW_NDATA * sizeof(struct ipw_hdr), PAGE_SIZE, 0, &sc->hdr_seg, 515 1, &nsegs, BUS_DMA_NOWAIT); 516 if (error != 0) { 517 aprint_error_dev(&sc->sc_dev, "could not allocate hdr memory\n"); 518 goto fail; 519 } 520 521 error = bus_dmamem_map(sc->sc_dmat, &sc->hdr_seg, nsegs, 522 IPW_NDATA * sizeof(struct ipw_hdr), (void **)&sc->hdr_list, 523 BUS_DMA_NOWAIT); 524 if (error != 0) { 525 aprint_error_dev(&sc->sc_dev, "could not map hdr memory\n"); 526 goto fail; 527 } 528 529 error = bus_dmamap_load(sc->sc_dmat, sc->hdr_map, sc->hdr_list, 530 IPW_NDATA * sizeof(struct ipw_hdr), NULL, BUS_DMA_NOWAIT); 531 if (error != 0) { 532 aprint_error_dev(&sc->sc_dev, "could not load hdr memory\n"); 533 goto fail; 534 } 535 536 (void)memset(sc->hdr_list, 0, IPW_HDR_SZ); 537 538 /* 539 * Create DMA hdrs tailq. 540 */ 541 TAILQ_INIT(&sc->sc_free_shdr); 542 for (i = 0; i < IPW_NDATA; i++) { 543 shdr = &sc->shdr_list[i]; 544 shdr->hdr = sc->hdr_list + i; 545 shdr->offset = sizeof(struct ipw_hdr) * i; 546 shdr->addr = sc->hdr_map->dm_segs[0].ds_addr + shdr->offset; 547 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 548 } 549 550 /* 551 * Allocate tx buffers DMA maps. 552 */ 553 TAILQ_INIT(&sc->sc_free_sbuf); 554 for (i = 0; i < IPW_NDATA; i++) { 555 sbuf = &sc->tx_sbuf_list[i]; 556 557 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 558 IPW_MAX_NSEG, MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 559 if (error != 0) { 560 aprint_error_dev(&sc->sc_dev, "could not create txbuf dma map\n"); 561 goto fail; 562 } 563 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 564 } 565 566 /* 567 * Initialize tx ring. 568 */ 569 for (i = 0; i < IPW_NTBD; i++) { 570 sbd = &sc->stbd_list[i]; 571 sbd->bd = &sc->tbd_list[i]; 572 sbd->type = IPW_SBD_TYPE_NOASSOC; 573 } 574 575 /* 576 * Pre-allocate rx buffers and DMA maps 577 */ 578 for (i = 0; i < IPW_NRBD; i++) { 579 sbd = &sc->srbd_list[i]; 580 sbuf = &sc->rx_sbuf_list[i]; 581 sbd->bd = &sc->rbd_list[i]; 582 583 MGETHDR(sbuf->m, M_DONTWAIT, MT_DATA); 584 if (sbuf->m == NULL) { 585 aprint_error_dev(&sc->sc_dev, "could not allocate rx mbuf\n"); 586 error = ENOMEM; 587 goto fail; 588 } 589 590 MCLGET(sbuf->m, M_DONTWAIT); 591 if (!(sbuf->m->m_flags & M_EXT)) { 592 m_freem(sbuf->m); 593 aprint_error_dev(&sc->sc_dev, "could not allocate rx mbuf cluster\n"); 594 error = ENOMEM; 595 goto fail; 596 } 597 598 sbuf->m->m_pkthdr.len = sbuf->m->m_len = sbuf->m->m_ext.ext_size; 599 600 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 601 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sbuf->map); 602 if (error != 0) { 603 aprint_error_dev(&sc->sc_dev, "could not create rxbuf dma map\n"); 604 m_freem(sbuf->m); 605 goto fail; 606 } 607 608 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, 609 sbuf->m, BUS_DMA_READ | BUS_DMA_NOWAIT); 610 if (error != 0) { 611 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 612 m_freem(sbuf->m); 613 aprint_error_dev(&sc->sc_dev, "could not map rxbuf dma memory\n"); 614 goto fail; 615 } 616 617 sbd->type = IPW_SBD_TYPE_DATA; 618 sbd->priv = sbuf; 619 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 620 sbd->bd->len = htole32(MCLBYTES); 621 622 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, 623 sbuf->map->dm_mapsize, BUS_DMASYNC_PREREAD); 624 625 } 626 627 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 0, IPW_RBD_SZ, 628 BUS_DMASYNC_PREREAD); 629 630 return 0; 631 632 fail: ipw_release(sc); 633 return error; 634 } 635 636 static void 637 ipw_release(struct ipw_softc *sc) 638 { 639 struct ipw_soft_buf *sbuf; 640 int i; 641 642 if (sc->tbd_map != NULL) { 643 if (sc->tbd_list != NULL) { 644 bus_dmamap_unload(sc->sc_dmat, sc->tbd_map); 645 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->tbd_list, 646 IPW_TBD_SZ); 647 bus_dmamem_free(sc->sc_dmat, &sc->tbd_seg, 1); 648 } 649 bus_dmamap_destroy(sc->sc_dmat, sc->tbd_map); 650 } 651 652 if (sc->rbd_map != NULL) { 653 if (sc->rbd_list != NULL) { 654 bus_dmamap_unload(sc->sc_dmat, sc->rbd_map); 655 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->rbd_list, 656 IPW_RBD_SZ); 657 bus_dmamem_free(sc->sc_dmat, &sc->rbd_seg, 1); 658 } 659 bus_dmamap_destroy(sc->sc_dmat, sc->rbd_map); 660 } 661 662 if (sc->status_map != NULL) { 663 if (sc->status_list != NULL) { 664 bus_dmamap_unload(sc->sc_dmat, sc->status_map); 665 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->status_list, 666 IPW_RBD_SZ); 667 bus_dmamem_free(sc->sc_dmat, &sc->status_seg, 1); 668 } 669 bus_dmamap_destroy(sc->sc_dmat, sc->status_map); 670 } 671 672 for (i = 0; i < IPW_NTBD; i++) 673 ipw_release_sbd(sc, &sc->stbd_list[i]); 674 675 if (sc->cmd_map != NULL) 676 bus_dmamap_destroy(sc->sc_dmat, sc->cmd_map); 677 678 if (sc->hdr_list != NULL) { 679 bus_dmamap_unload(sc->sc_dmat, sc->hdr_map); 680 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->hdr_list, 681 IPW_NDATA * sizeof(struct ipw_hdr)); 682 } 683 if (sc->hdr_map != NULL) { 684 bus_dmamem_free(sc->sc_dmat, &sc->hdr_seg, 1); 685 bus_dmamap_destroy(sc->sc_dmat, sc->hdr_map); 686 } 687 688 for (i = 0; i < IPW_NDATA; i++) 689 bus_dmamap_destroy(sc->sc_dmat, sc->tx_sbuf_list[i].map); 690 691 for (i = 0; i < IPW_NRBD; i++) { 692 sbuf = &sc->rx_sbuf_list[i]; 693 if (sbuf->map != NULL) { 694 if (sbuf->m != NULL) { 695 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 696 m_freem(sbuf->m); 697 } 698 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 699 } 700 } 701 702 } 703 704 static int 705 ipw_media_change(struct ifnet *ifp) 706 { 707 int error; 708 709 error = ieee80211_media_change(ifp); 710 if (error != ENETRESET) 711 return error; 712 713 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 714 ipw_init(ifp); 715 716 return 0; 717 } 718 719 /* 720 * The firmware automatically adapts the transmit speed. We report the current 721 * transmit speed here. 722 */ 723 static void 724 ipw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 725 { 726 #define N(a) (sizeof (a) / sizeof (a[0])) 727 struct ipw_softc *sc = ifp->if_softc; 728 struct ieee80211com *ic = &sc->sc_ic; 729 static const struct { 730 uint32_t val; 731 int rate; 732 } rates[] = { 733 { IPW_RATE_DS1, 2 }, 734 { IPW_RATE_DS2, 4 }, 735 { IPW_RATE_DS5, 11 }, 736 { IPW_RATE_DS11, 22 }, 737 }; 738 uint32_t val; 739 int rate, i; 740 741 imr->ifm_status = IFM_AVALID; 742 imr->ifm_active = IFM_IEEE80211; 743 if (ic->ic_state == IEEE80211_S_RUN) 744 imr->ifm_status |= IFM_ACTIVE; 745 746 /* read current transmission rate from adapter */ 747 val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE) & 0xf; 748 749 /* convert ipw rate to 802.11 rate */ 750 for (i = 0; i < N(rates) && rates[i].val != val; i++); 751 rate = (i < N(rates)) ? rates[i].rate : 0; 752 753 imr->ifm_active |= IFM_IEEE80211_11B; 754 imr->ifm_active |= ieee80211_rate2media(ic, rate, IEEE80211_MODE_11B); 755 switch (ic->ic_opmode) { 756 case IEEE80211_M_STA: 757 break; 758 759 case IEEE80211_M_IBSS: 760 imr->ifm_active |= IFM_IEEE80211_ADHOC; 761 break; 762 763 case IEEE80211_M_MONITOR: 764 imr->ifm_active |= IFM_IEEE80211_MONITOR; 765 break; 766 767 case IEEE80211_M_AHDEMO: 768 case IEEE80211_M_HOSTAP: 769 /* should not get there */ 770 break; 771 } 772 #undef N 773 } 774 775 static int 776 ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, 777 int arg) 778 { 779 struct ifnet *ifp = ic->ic_ifp; 780 struct ipw_softc *sc = ifp->if_softc; 781 struct ieee80211_node *ni; 782 uint8_t macaddr[IEEE80211_ADDR_LEN]; 783 uint32_t len; 784 struct ipw_rx_radiotap_header *wr = &sc->sc_rxtap; 785 struct ipw_tx_radiotap_header *wt = &sc->sc_txtap; 786 787 switch (nstate) { 788 case IEEE80211_S_INIT: 789 break; 790 default: 791 KASSERT(ic->ic_curchan != IEEE80211_CHAN_ANYC); 792 KASSERT(ic->ic_curchan != NULL); 793 wt->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 794 wt->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 795 wr->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 796 wr->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 797 break; 798 } 799 800 switch (nstate) { 801 case IEEE80211_S_RUN: 802 DELAY(200); /* firmware needs a short delay here */ 803 804 len = IEEE80211_ADDR_LEN; 805 ipw_read_table2(sc, IPW_INFO_CURRENT_BSSID, macaddr, &len); 806 807 ni = ieee80211_find_node(&ic->ic_scan, macaddr); 808 if (ni == NULL) 809 break; 810 811 ieee80211_ref_node(ni); 812 ieee80211_sta_join(ic, ni); 813 ieee80211_node_authorize(ni); 814 815 if (ic->ic_opmode == IEEE80211_M_STA) 816 ieee80211_notify_node_join(ic, ni, 1); 817 break; 818 819 case IEEE80211_S_INIT: 820 case IEEE80211_S_SCAN: 821 case IEEE80211_S_AUTH: 822 case IEEE80211_S_ASSOC: 823 break; 824 } 825 826 ic->ic_state = nstate; 827 return 0; 828 } 829 830 /* 831 * Read 16 bits at address 'addr' from the serial EEPROM. 832 */ 833 static uint16_t 834 ipw_read_prom_word(struct ipw_softc *sc, uint8_t addr) 835 { 836 uint32_t tmp; 837 uint16_t val; 838 int n; 839 840 /* clock C once before the first command */ 841 IPW_EEPROM_CTL(sc, 0); 842 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 843 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 844 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 845 846 /* write start bit (1) */ 847 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 848 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 849 850 /* write READ opcode (10) */ 851 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 852 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 853 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 854 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 855 856 /* write address A7-A0 */ 857 for (n = 7; n >= 0; n--) { 858 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 859 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D)); 860 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 861 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D) | IPW_EEPROM_C); 862 } 863 864 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 865 866 /* read data Q15-Q0 */ 867 val = 0; 868 for (n = 15; n >= 0; n--) { 869 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 870 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 871 tmp = MEM_READ_4(sc, IPW_MEM_EEPROM_CTL); 872 val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n; 873 } 874 875 IPW_EEPROM_CTL(sc, 0); 876 877 /* clear Chip Select and clock C */ 878 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 879 IPW_EEPROM_CTL(sc, 0); 880 IPW_EEPROM_CTL(sc, IPW_EEPROM_C); 881 882 return le16toh(val); 883 } 884 885 static void 886 ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 887 { 888 struct ipw_cmd *cmd; 889 890 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof (struct ipw_cmd), 891 BUS_DMASYNC_POSTREAD); 892 893 cmd = mtod(sbuf->m, struct ipw_cmd *); 894 895 DPRINTFN(2, ("cmd ack'ed (%u, %u, %u, %u, %u)\n", le32toh(cmd->type), 896 le32toh(cmd->subtype), le32toh(cmd->seq), le32toh(cmd->len), 897 le32toh(cmd->status))); 898 899 wakeup(&sc->cmd); 900 } 901 902 static void 903 ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 904 { 905 struct ieee80211com *ic = &sc->sc_ic; 906 struct ifnet *ifp = sc->sc_ic.ic_ifp; 907 uint32_t state; 908 909 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof state, 910 BUS_DMASYNC_POSTREAD); 911 912 state = le32toh(*mtod(sbuf->m, uint32_t *)); 913 914 DPRINTFN(2, ("entering state %u\n", state)); 915 916 switch (state) { 917 case IPW_STATE_ASSOCIATED: 918 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 919 break; 920 921 case IPW_STATE_SCANNING: 922 /* don't leave run state on background scan */ 923 if (ic->ic_state != IEEE80211_S_RUN) 924 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 925 926 ic->ic_flags |= IEEE80211_F_SCAN; 927 break; 928 929 case IPW_STATE_SCAN_COMPLETE: 930 ieee80211_notify_scan_done(ic); 931 ic->ic_flags &= ~IEEE80211_F_SCAN; 932 break; 933 934 case IPW_STATE_ASSOCIATION_LOST: 935 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 936 break; 937 938 case IPW_STATE_RADIO_DISABLED: 939 ic->ic_ifp->if_flags &= ~IFF_UP; 940 ipw_stop(ifp, 1); 941 break; 942 } 943 } 944 945 /* 946 * XXX: Hack to set the current channel to the value advertised in beacons or 947 * probe responses. Only used during AP detection. 948 */ 949 static void 950 ipw_fix_channel(struct ieee80211com *ic, struct mbuf *m) 951 { 952 struct ieee80211_frame *wh; 953 uint8_t subtype; 954 uint8_t *frm, *efrm; 955 956 wh = mtod(m, struct ieee80211_frame *); 957 958 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_MGT) 959 return; 960 961 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 962 963 if (subtype != IEEE80211_FC0_SUBTYPE_BEACON && 964 subtype != IEEE80211_FC0_SUBTYPE_PROBE_RESP) 965 return; 966 967 frm = (uint8_t *)(wh + 1); 968 efrm = mtod(m, uint8_t *) + m->m_len; 969 970 frm += 12; /* skip tstamp, bintval and capinfo fields */ 971 while (frm < efrm) { 972 if (*frm == IEEE80211_ELEMID_DSPARMS) 973 #if IEEE80211_CHAN_MAX < 255 974 if (frm[2] <= IEEE80211_CHAN_MAX) 975 #endif 976 ic->ic_curchan = &ic->ic_channels[frm[2]]; 977 978 frm += frm[1] + 2; 979 } 980 } 981 982 static void 983 ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 984 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 985 { 986 struct ieee80211com *ic = &sc->sc_ic; 987 struct ifnet *ifp = &sc->sc_if; 988 struct mbuf *mnew, *m; 989 struct ieee80211_frame *wh; 990 struct ieee80211_node *ni; 991 int error; 992 993 DPRINTFN(5, ("received frame len=%u, rssi=%u\n", le32toh(status->len), 994 status->rssi)); 995 996 if (le32toh(status->len) < sizeof (struct ieee80211_frame_min) || 997 le32toh(status->len) > MCLBYTES) 998 return; 999 1000 /* 1001 * Try to allocate a new mbuf for this ring element and load it before 1002 * processing the current mbuf. If the ring element cannot be loaded, 1003 * drop the received packet and reuse the old mbuf. In the unlikely 1004 * case that the old mbuf can't be reloaded either, explicitly panic. 1005 */ 1006 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1007 if (mnew == NULL) { 1008 aprint_error_dev(&sc->sc_dev, "could not allocate rx mbuf\n"); 1009 ifp->if_ierrors++; 1010 return; 1011 } 1012 1013 MCLGET(mnew, M_DONTWAIT); 1014 if (!(mnew->m_flags & M_EXT)) { 1015 aprint_error_dev(&sc->sc_dev, "could not allocate rx mbuf cluster\n"); 1016 m_freem(mnew); 1017 ifp->if_ierrors++; 1018 return; 1019 } 1020 1021 mnew->m_pkthdr.len = mnew->m_len = mnew->m_ext.ext_size; 1022 1023 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, le32toh(status->len), 1024 BUS_DMASYNC_POSTREAD); 1025 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1026 1027 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, mnew, 1028 BUS_DMA_READ | BUS_DMA_NOWAIT); 1029 if (error != 0) { 1030 aprint_error_dev(&sc->sc_dev, "could not load rx buf DMA map\n"); 1031 m_freem(mnew); 1032 1033 /* try to reload the old mbuf */ 1034 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, 1035 sbuf->m, BUS_DMA_READ | BUS_DMA_NOWAIT); 1036 if (error != 0) { 1037 /* very unlikely that it will fail... */ 1038 panic("%s: unable to remap rx buf", 1039 device_xname(&sc->sc_dev)); 1040 } 1041 ifp->if_ierrors++; 1042 return; 1043 } 1044 1045 /* 1046 * New mbuf successfully loaded, update Rx ring and continue 1047 * processing. 1048 */ 1049 m = sbuf->m; 1050 sbuf->m = mnew; 1051 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 1052 1053 /* finalize mbuf */ 1054 m->m_pkthdr.rcvif = ifp; 1055 m->m_pkthdr.len = m->m_len = le32toh(status->len); 1056 1057 if (sc->sc_drvbpf != NULL) { 1058 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 1059 1060 tap->wr_antsignal = status->rssi; 1061 1062 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 1063 } 1064 1065 if (ic->ic_state == IEEE80211_S_SCAN) 1066 ipw_fix_channel(ic, m); 1067 1068 wh = mtod(m, struct ieee80211_frame *); 1069 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 1070 1071 /* send the frame to the 802.11 layer */ 1072 ieee80211_input(ic, m, ni, status->rssi, 0); 1073 1074 /* node is no longer needed */ 1075 ieee80211_free_node(ni); 1076 1077 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, 1078 sbuf->map->dm_mapsize, BUS_DMASYNC_PREREAD); 1079 } 1080 1081 static void 1082 ipw_rx_intr(struct ipw_softc *sc) 1083 { 1084 struct ipw_status *status; 1085 struct ipw_soft_bd *sbd; 1086 struct ipw_soft_buf *sbuf; 1087 uint32_t r, i; 1088 1089 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1090 return; 1091 1092 r = CSR_READ_4(sc, IPW_CSR_RX_READ); 1093 1094 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 1095 1096 /* firmware was killed, stop processing received frames */ 1097 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1098 return; 1099 1100 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 1101 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1102 BUS_DMASYNC_POSTREAD); 1103 1104 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 1105 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 1106 BUS_DMASYNC_POSTREAD); 1107 1108 status = &sc->status_list[i]; 1109 sbd = &sc->srbd_list[i]; 1110 sbuf = sbd->priv; 1111 1112 switch (le16toh(status->code) & 0xf) { 1113 case IPW_STATUS_CODE_COMMAND: 1114 ipw_command_intr(sc, sbuf); 1115 break; 1116 1117 case IPW_STATUS_CODE_NEWSTATE: 1118 ipw_newstate_intr(sc, sbuf); 1119 break; 1120 1121 case IPW_STATUS_CODE_DATA_802_3: 1122 case IPW_STATUS_CODE_DATA_802_11: 1123 ipw_data_intr(sc, status, sbd, sbuf); 1124 break; 1125 1126 case IPW_STATUS_CODE_NOTIFICATION: 1127 DPRINTFN(2, ("received notification\n")); 1128 break; 1129 1130 default: 1131 aprint_error_dev(&sc->sc_dev, "unknown status code %u\n", 1132 le16toh(status->code)); 1133 } 1134 1135 sbd->bd->flags = 0; 1136 1137 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 1138 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1139 BUS_DMASYNC_PREREAD); 1140 1141 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 1142 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 1143 BUS_DMASYNC_PREREAD); 1144 } 1145 1146 /* Tell the firmware what we have processed */ 1147 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 1148 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 1149 } 1150 1151 static void 1152 ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 1153 { 1154 struct ieee80211com *ic; 1155 struct ipw_soft_hdr *shdr; 1156 struct ipw_soft_buf *sbuf; 1157 1158 switch (sbd->type) { 1159 case IPW_SBD_TYPE_COMMAND: 1160 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 1161 0, sizeof(struct ipw_cmd), BUS_DMASYNC_POSTWRITE); 1162 /* bus_dmamap_unload(sc->sc_dmat, sc->cmd_map); */ 1163 break; 1164 1165 case IPW_SBD_TYPE_HEADER: 1166 shdr = sbd->priv; 1167 bus_dmamap_sync(sc->sc_dmat, sc->hdr_map, 1168 shdr->offset, sizeof(struct ipw_hdr), BUS_DMASYNC_POSTWRITE); 1169 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 1170 break; 1171 1172 case IPW_SBD_TYPE_DATA: 1173 ic = &sc->sc_ic; 1174 sbuf = sbd->priv; 1175 1176 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 1177 0, MCLBYTES, BUS_DMASYNC_POSTWRITE); 1178 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1179 m_freem(sbuf->m); 1180 if (sbuf->ni != NULL) 1181 ieee80211_free_node(sbuf->ni); 1182 /* kill watchdog timer */ 1183 sc->sc_tx_timer = 0; 1184 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 1185 break; 1186 } 1187 sbd->type = IPW_SBD_TYPE_NOASSOC; 1188 } 1189 1190 static void 1191 ipw_tx_intr(struct ipw_softc *sc) 1192 { 1193 struct ifnet *ifp = &sc->sc_if; 1194 struct ipw_soft_bd *sbd; 1195 uint32_t r, i; 1196 1197 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1198 return; 1199 1200 r = CSR_READ_4(sc, IPW_CSR_TX_READ); 1201 1202 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) { 1203 sbd = &sc->stbd_list[i]; 1204 1205 if (sbd->type == IPW_SBD_TYPE_DATA) 1206 ifp->if_opackets++; 1207 1208 ipw_release_sbd(sc, sbd); 1209 sc->txfree++; 1210 } 1211 1212 /* remember what the firmware has processed */ 1213 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 1214 1215 /* Call start() since some buffer descriptors have been released */ 1216 ifp->if_flags &= ~IFF_OACTIVE; 1217 (*ifp->if_start)(ifp); 1218 } 1219 1220 static int 1221 ipw_intr(void *arg) 1222 { 1223 struct ipw_softc *sc = arg; 1224 uint32_t r; 1225 1226 r = CSR_READ_4(sc, IPW_CSR_INTR); 1227 if (r == 0 || r == 0xffffffff) 1228 return 0; 1229 1230 /* Disable interrupts */ 1231 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1232 1233 if (r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR)) { 1234 aprint_error_dev(&sc->sc_dev, "fatal error\n"); 1235 sc->sc_ic.ic_ifp->if_flags &= ~IFF_UP; 1236 ipw_stop(&sc->sc_if, 1); 1237 } 1238 1239 if (r & IPW_INTR_FW_INIT_DONE) { 1240 if (!(r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR))) 1241 wakeup(sc); 1242 } 1243 1244 if (r & IPW_INTR_RX_TRANSFER) 1245 ipw_rx_intr(sc); 1246 1247 if (r & IPW_INTR_TX_TRANSFER) 1248 ipw_tx_intr(sc); 1249 1250 /* Acknowledge all interrupts */ 1251 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 1252 1253 /* Re-enable interrupts */ 1254 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1255 1256 return 0; 1257 } 1258 1259 /* 1260 * Send a command to the firmware and wait for the acknowledgement. 1261 */ 1262 static int 1263 ipw_cmd(struct ipw_softc *sc, uint32_t type, void *data, uint32_t len) 1264 { 1265 struct ipw_soft_bd *sbd; 1266 1267 sbd = &sc->stbd_list[sc->txcur]; 1268 1269 sc->cmd.type = htole32(type); 1270 sc->cmd.subtype = 0; 1271 sc->cmd.len = htole32(len); 1272 sc->cmd.seq = 0; 1273 1274 (void)memcpy(sc->cmd.data, data, len); 1275 1276 sbd->type = IPW_SBD_TYPE_COMMAND; 1277 sbd->bd->physaddr = htole32(sc->cmd_map->dm_segs[0].ds_addr); 1278 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 1279 sbd->bd->nfrag = 1; 1280 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 1281 IPW_BD_FLAG_TX_LAST_FRAGMENT; 1282 1283 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 0, sizeof (struct ipw_cmd), 1284 BUS_DMASYNC_PREWRITE); 1285 1286 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1287 sc->txcur * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1288 BUS_DMASYNC_PREWRITE); 1289 1290 DPRINTFN(2, ("sending command (%u, %u, %u, %u)\n", type, 0, 0, len)); 1291 1292 /* kick firmware */ 1293 sc->txfree--; 1294 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1295 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1296 1297 /* Wait at most one second for command to complete */ 1298 return tsleep(&sc->cmd, 0, "ipwcmd", hz); 1299 } 1300 1301 static int 1302 ipw_tx_start(struct ifnet *ifp, struct mbuf *m0, struct ieee80211_node *ni) 1303 { 1304 struct ipw_softc *sc = ifp->if_softc; 1305 struct ieee80211com *ic = &sc->sc_ic; 1306 struct ieee80211_frame *wh; 1307 struct ipw_soft_bd *sbd; 1308 struct ipw_soft_hdr *shdr; 1309 struct ipw_soft_buf *sbuf; 1310 struct ieee80211_key *k; 1311 struct mbuf *mnew; 1312 int error, i; 1313 1314 wh = mtod(m0, struct ieee80211_frame *); 1315 1316 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1317 k = ieee80211_crypto_encap(ic, ni, m0); 1318 if (k == NULL) { 1319 m_freem(m0); 1320 return ENOBUFS; 1321 } 1322 1323 /* packet header may have moved, reset our local pointer */ 1324 wh = mtod(m0, struct ieee80211_frame *); 1325 } 1326 1327 if (sc->sc_drvbpf != NULL) { 1328 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 1329 1330 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 1331 } 1332 1333 shdr = TAILQ_FIRST(&sc->sc_free_shdr); 1334 sbuf = TAILQ_FIRST(&sc->sc_free_sbuf); 1335 KASSERT(shdr != NULL && sbuf != NULL); 1336 1337 shdr->hdr->type = htole32(IPW_HDR_TYPE_SEND); 1338 shdr->hdr->subtype = 0; 1339 shdr->hdr->encrypted = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0; 1340 shdr->hdr->encrypt = 0; 1341 shdr->hdr->keyidx = 0; 1342 shdr->hdr->keysz = 0; 1343 shdr->hdr->fragmentsz = 0; 1344 IEEE80211_ADDR_COPY(shdr->hdr->src_addr, wh->i_addr2); 1345 if (ic->ic_opmode == IEEE80211_M_STA) 1346 IEEE80211_ADDR_COPY(shdr->hdr->dst_addr, wh->i_addr3); 1347 else 1348 IEEE80211_ADDR_COPY(shdr->hdr->dst_addr, wh->i_addr1); 1349 1350 /* trim IEEE802.11 header */ 1351 m_adj(m0, sizeof (struct ieee80211_frame)); 1352 1353 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m0, BUS_DMA_NOWAIT); 1354 if (error != 0 && error != EFBIG) { 1355 aprint_error_dev(&sc->sc_dev, "could not map mbuf (error %d)\n", 1356 error); 1357 m_freem(m0); 1358 return error; 1359 } 1360 1361 if (error != 0) { 1362 /* too many fragments, linearize */ 1363 1364 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1365 if (mnew == NULL) { 1366 m_freem(m0); 1367 return ENOMEM; 1368 } 1369 1370 M_COPY_PKTHDR(mnew, m0); 1371 1372 /* If the data won't fit in the header, get a cluster */ 1373 if (m0->m_pkthdr.len > MHLEN) { 1374 MCLGET(mnew, M_DONTWAIT); 1375 if (!(mnew->m_flags & M_EXT)) { 1376 m_freem(m0); 1377 m_freem(mnew); 1378 return ENOMEM; 1379 } 1380 } 1381 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(mnew, void *)); 1382 m_freem(m0); 1383 mnew->m_len = mnew->m_pkthdr.len; 1384 m0 = mnew; 1385 1386 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m0, 1387 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1388 if (error != 0) { 1389 aprint_error_dev(&sc->sc_dev, "could not map mbuf (error %d)\n", error); 1390 m_freem(m0); 1391 return error; 1392 } 1393 } 1394 1395 TAILQ_REMOVE(&sc->sc_free_sbuf, sbuf, next); 1396 TAILQ_REMOVE(&sc->sc_free_shdr, shdr, next); 1397 1398 sbd = &sc->stbd_list[sc->txcur]; 1399 sbd->type = IPW_SBD_TYPE_HEADER; 1400 sbd->priv = shdr; 1401 sbd->bd->physaddr = htole32(shdr->addr); 1402 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 1403 sbd->bd->nfrag = 1 + sbuf->map->dm_nsegs; 1404 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 1405 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1406 1407 DPRINTFN(5, ("sending tx hdr (%u, %u, %u, %u, )\n", 1408 shdr->hdr->type, shdr->hdr->subtype, shdr->hdr->encrypted, 1409 shdr->hdr->encrypt)); 1410 DPRINTFN(5, ("%s->", ether_sprintf(shdr->hdr->src_addr))); 1411 DPRINTFN(5, ("%s\n", ether_sprintf(shdr->hdr->dst_addr))); 1412 1413 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1414 sc->txcur * sizeof (struct ipw_bd), 1415 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1416 1417 sc->txfree--; 1418 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1419 1420 sbuf->m = m0; 1421 sbuf->ni = ni; 1422 1423 for (i = 0; i < sbuf->map->dm_nsegs; i++) { 1424 sbd = &sc->stbd_list[sc->txcur]; 1425 1426 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[i].ds_addr); 1427 sbd->bd->len = htole32(sbuf->map->dm_segs[i].ds_len); 1428 sbd->bd->nfrag = 0; 1429 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 1430 if (i == sbuf->map->dm_nsegs - 1) { 1431 sbd->type = IPW_SBD_TYPE_DATA; 1432 sbd->priv = sbuf; 1433 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 1434 } else { 1435 sbd->type = IPW_SBD_TYPE_NOASSOC; 1436 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1437 } 1438 1439 DPRINTFN(5, ("sending fragment (%d, %d)\n", i, 1440 (int)sbuf->map->dm_segs[i].ds_len)); 1441 1442 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1443 sc->txcur * sizeof (struct ipw_bd), 1444 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1445 1446 sc->txfree--; 1447 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1448 } 1449 1450 bus_dmamap_sync(sc->sc_dmat, sc->hdr_map, shdr->offset, 1451 sizeof (struct ipw_hdr), BUS_DMASYNC_PREWRITE); 1452 1453 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, MCLBYTES, 1454 BUS_DMASYNC_PREWRITE); 1455 1456 /* Inform firmware about this new packet */ 1457 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1458 1459 return 0; 1460 } 1461 1462 static void 1463 ipw_start(struct ifnet *ifp) 1464 { 1465 struct ipw_softc *sc = ifp->if_softc; 1466 struct ieee80211com *ic = &sc->sc_ic; 1467 struct mbuf *m0; 1468 struct ether_header *eh; 1469 struct ieee80211_node *ni; 1470 1471 1472 if (ic->ic_state != IEEE80211_S_RUN) 1473 return; 1474 1475 for (;;) { 1476 IF_DEQUEUE(&ifp->if_snd, m0); 1477 if (m0 == NULL) 1478 break; 1479 1480 if (sc->txfree < 1 + IPW_MAX_NSEG) { 1481 IF_PREPEND(&ifp->if_snd, m0); 1482 ifp->if_flags |= IFF_OACTIVE; 1483 break; 1484 } 1485 1486 if (m0->m_len < sizeof (struct ether_header) && 1487 (m0 = m_pullup(m0, sizeof (struct ether_header))) == NULL) 1488 continue; 1489 1490 eh = mtod(m0, struct ether_header *); 1491 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1492 if (ni == NULL) { 1493 m_freem(m0); 1494 continue; 1495 } 1496 1497 bpf_mtap(ifp, m0); 1498 1499 m0 = ieee80211_encap(ic, m0, ni); 1500 if (m0 == NULL) { 1501 ieee80211_free_node(ni); 1502 continue; 1503 } 1504 1505 bpf_mtap3(ic->ic_rawbpf, m0); 1506 1507 if (ipw_tx_start(ifp, m0, ni) != 0) { 1508 ieee80211_free_node(ni); 1509 ifp->if_oerrors++; 1510 break; 1511 } 1512 1513 /* start watchdog timer */ 1514 sc->sc_tx_timer = 5; 1515 ifp->if_timer = 1; 1516 } 1517 } 1518 1519 static void 1520 ipw_watchdog(struct ifnet *ifp) 1521 { 1522 struct ipw_softc *sc = ifp->if_softc; 1523 1524 ifp->if_timer = 0; 1525 1526 if (sc->sc_tx_timer > 0) { 1527 if (--sc->sc_tx_timer == 0) { 1528 aprint_error_dev(&sc->sc_dev, "device timeout\n"); 1529 ifp->if_oerrors++; 1530 ifp->if_flags &= ~IFF_UP; 1531 ipw_stop(ifp, 1); 1532 return; 1533 } 1534 ifp->if_timer = 1; 1535 } 1536 1537 ieee80211_watchdog(&sc->sc_ic); 1538 } 1539 1540 static int 1541 ipw_get_table1(struct ipw_softc *sc, uint32_t *tbl) 1542 { 1543 uint32_t addr, size, i; 1544 1545 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1546 return ENOTTY; 1547 1548 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, sc->table1_base); 1549 1550 size = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 1551 if (suword(tbl, size) != 0) 1552 return EFAULT; 1553 1554 for (i = 1, ++tbl; i < size; i++, tbl++) { 1555 addr = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 1556 if (suword(tbl, MEM_READ_4(sc, addr)) != 0) 1557 return EFAULT; 1558 } 1559 return 0; 1560 } 1561 1562 static int 1563 ipw_get_radio(struct ipw_softc *sc, int *ret) 1564 { 1565 uint32_t addr; 1566 1567 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1568 return ENOTTY; 1569 1570 addr = ipw_read_table1(sc, IPW_INFO_EEPROM_ADDRESS); 1571 if ((MEM_READ_4(sc, addr + 32) >> 24) & 1) { 1572 suword(ret, -1); 1573 return 0; 1574 } 1575 1576 if (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED) 1577 suword(ret, 0); 1578 else 1579 suword(ret, 1); 1580 1581 return 0; 1582 } 1583 1584 static int 1585 ipw_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1586 { 1587 #define IS_RUNNING(ifp) \ 1588 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 1589 1590 struct ipw_softc *sc = ifp->if_softc; 1591 struct ieee80211com *ic = &sc->sc_ic; 1592 struct ifreq *ifr = (struct ifreq *)data; 1593 int s, error = 0; 1594 1595 s = splnet(); 1596 1597 switch (cmd) { 1598 case SIOCSIFFLAGS: 1599 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 1600 break; 1601 if (ifp->if_flags & IFF_UP) { 1602 if (!(ifp->if_flags & IFF_RUNNING)) 1603 ipw_init(ifp); 1604 } else { 1605 if (ifp->if_flags & IFF_RUNNING) 1606 ipw_stop(ifp, 1); 1607 } 1608 break; 1609 1610 case SIOCADDMULTI: 1611 case SIOCDELMULTI: 1612 /* XXX no h/w multicast filter? --dyoung */ 1613 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1614 /* setup multicast filter, etc */ 1615 error = 0; 1616 } 1617 break; 1618 1619 case SIOCGTABLE1: 1620 error = ipw_get_table1(sc, (uint32_t *)ifr->ifr_data); 1621 break; 1622 1623 case SIOCGRADIO: 1624 error = ipw_get_radio(sc, (int *)ifr->ifr_data); 1625 break; 1626 1627 case SIOCSIFMEDIA: 1628 if (ifr->ifr_media & IFM_IEEE80211_ADHOC) 1629 sc->sc_fwname = "ipw2100-1.2-i.fw"; 1630 else if (ifr->ifr_media & IFM_IEEE80211_MONITOR) 1631 sc->sc_fwname = "ipw2100-1.2-p.fw"; 1632 else 1633 sc->sc_fwname = "ipw2100-1.2.fw"; 1634 1635 ipw_free_firmware(sc); 1636 /* FALLTRHOUGH */ 1637 default: 1638 error = ieee80211_ioctl(&sc->sc_ic, cmd, data); 1639 if (error != ENETRESET) 1640 break; 1641 1642 if (error == ENETRESET) { 1643 if (IS_RUNNING(ifp) && 1644 (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)) 1645 ipw_init(ifp); 1646 error = 0; 1647 } 1648 1649 } 1650 1651 splx(s); 1652 return error; 1653 #undef IS_RUNNING 1654 } 1655 1656 static uint32_t 1657 ipw_read_table1(struct ipw_softc *sc, uint32_t off) 1658 { 1659 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 1660 } 1661 1662 static void 1663 ipw_write_table1(struct ipw_softc *sc, uint32_t off, uint32_t info) 1664 { 1665 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 1666 } 1667 1668 static int 1669 ipw_read_table2(struct ipw_softc *sc, uint32_t off, void *buf, uint32_t *len) 1670 { 1671 uint32_t addr, info; 1672 uint16_t count, size; 1673 uint32_t total; 1674 1675 /* addr[4] + count[2] + size[2] */ 1676 addr = MEM_READ_4(sc, sc->table2_base + off); 1677 info = MEM_READ_4(sc, sc->table2_base + off + 4); 1678 1679 count = info >> 16; 1680 size = info & 0xffff; 1681 total = count * size; 1682 1683 if (total > *len) { 1684 *len = total; 1685 return EINVAL; 1686 } 1687 1688 *len = total; 1689 ipw_read_mem_1(sc, addr, buf, total); 1690 1691 return 0; 1692 } 1693 1694 static void 1695 ipw_stop_master(struct ipw_softc *sc) 1696 { 1697 int ntries; 1698 1699 /* disable interrupts */ 1700 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1701 1702 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1703 for (ntries = 0; ntries < 50; ntries++) { 1704 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1705 break; 1706 DELAY(10); 1707 } 1708 if (ntries == 50) 1709 aprint_error_dev(&sc->sc_dev, "timeout waiting for master\n"); 1710 1711 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1712 IPW_RST_PRINCETON_RESET); 1713 1714 sc->flags &= ~IPW_FLAG_FW_INITED; 1715 } 1716 1717 static int 1718 ipw_reset(struct ipw_softc *sc) 1719 { 1720 int ntries; 1721 1722 ipw_stop_master(sc); 1723 1724 /* move adapter to D0 state */ 1725 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1726 IPW_CTL_INIT); 1727 1728 /* wait for clock stabilization */ 1729 for (ntries = 0; ntries < 1000; ntries++) { 1730 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY) 1731 break; 1732 DELAY(200); 1733 } 1734 if (ntries == 1000) 1735 return EIO; 1736 1737 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1738 IPW_RST_SW_RESET); 1739 1740 DELAY(10); 1741 1742 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1743 IPW_CTL_INIT); 1744 1745 return 0; 1746 } 1747 1748 /* 1749 * Upload the microcode to the device. 1750 */ 1751 static int 1752 ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size) 1753 { 1754 int ntries; 1755 1756 MEM_WRITE_4(sc, 0x3000e0, 0x80000000); 1757 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1758 1759 MEM_WRITE_2(sc, 0x220000, 0x0703); 1760 MEM_WRITE_2(sc, 0x220000, 0x0707); 1761 1762 MEM_WRITE_1(sc, 0x210014, 0x72); 1763 MEM_WRITE_1(sc, 0x210014, 0x72); 1764 1765 MEM_WRITE_1(sc, 0x210000, 0x40); 1766 MEM_WRITE_1(sc, 0x210000, 0x00); 1767 MEM_WRITE_1(sc, 0x210000, 0x40); 1768 1769 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1770 1771 MEM_WRITE_1(sc, 0x210000, 0x00); 1772 MEM_WRITE_1(sc, 0x210000, 0x00); 1773 MEM_WRITE_1(sc, 0x210000, 0x80); 1774 1775 MEM_WRITE_2(sc, 0x220000, 0x0703); 1776 MEM_WRITE_2(sc, 0x220000, 0x0707); 1777 1778 MEM_WRITE_1(sc, 0x210014, 0x72); 1779 MEM_WRITE_1(sc, 0x210014, 0x72); 1780 1781 MEM_WRITE_1(sc, 0x210000, 0x00); 1782 MEM_WRITE_1(sc, 0x210000, 0x80); 1783 1784 for (ntries = 0; ntries < 10; ntries++) { 1785 if (MEM_READ_1(sc, 0x210000) & 1) 1786 break; 1787 DELAY(10); 1788 } 1789 if (ntries == 10) { 1790 aprint_error_dev(&sc->sc_dev, "timeout waiting for ucode to initialize\n"); 1791 return EIO; 1792 } 1793 1794 MEM_WRITE_4(sc, 0x3000e0, 0); 1795 1796 return 0; 1797 } 1798 1799 /* set of macros to handle unaligned little endian data in firmware image */ 1800 #define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1801 #define GETLE16(p) ((p)[0] | (p)[1] << 8) 1802 static int 1803 ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size) 1804 { 1805 u_char *p, *end; 1806 uint32_t dst; 1807 uint16_t len; 1808 int error; 1809 1810 p = fw; 1811 end = fw + size; 1812 while (p < end) { 1813 dst = GETLE32(p); p += 4; 1814 len = GETLE16(p); p += 2; 1815 1816 ipw_write_mem_1(sc, dst, p, len); 1817 p += len; 1818 } 1819 1820 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1821 IPW_IO_LED_OFF); 1822 1823 /* enable interrupts */ 1824 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1825 1826 /* kick the firmware */ 1827 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1828 1829 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1830 IPW_CTL_ALLOW_STANDBY); 1831 1832 /* wait at most one second for firmware initialization to complete */ 1833 if ((error = tsleep(sc, 0, "ipwinit", hz)) != 0) { 1834 aprint_error_dev(&sc->sc_dev, "timeout waiting for firmware initialization " 1835 "to complete\n"); 1836 return error; 1837 } 1838 1839 CSR_WRITE_4(sc, IPW_CSR_IO, CSR_READ_4(sc, IPW_CSR_IO) | 1840 IPW_IO_GPIO1_MASK | IPW_IO_GPIO3_MASK); 1841 1842 return 0; 1843 } 1844 1845 /* 1846 * Store firmware into kernel memory so we can download it when we need to, 1847 * e.g when the adapter wakes up from suspend mode. 1848 */ 1849 static int 1850 ipw_cache_firmware(struct ipw_softc *sc) 1851 { 1852 struct ipw_firmware *fw = &sc->fw; 1853 struct ipw_firmware_hdr hdr; 1854 firmware_handle_t fwh; 1855 off_t fwsz, p; 1856 int error; 1857 1858 ipw_free_firmware(sc); 1859 1860 if (ipw_accept_eula == 0) { 1861 aprint_error_dev(&sc->sc_dev, 1862 "EULA not accepted; please see the ipw(4) man page.\n"); 1863 return EPERM; 1864 } 1865 1866 if ((error = firmware_open("if_ipw", sc->sc_fwname, &fwh)) != 0) 1867 goto fail0; 1868 1869 fwsz = firmware_get_size(fwh); 1870 1871 if (fwsz < sizeof(hdr)) 1872 goto fail2; 1873 1874 if ((error = firmware_read(fwh, 0, &hdr, sizeof(hdr))) != 0) 1875 goto fail2; 1876 1877 fw->main_size = le32toh(hdr.main_size); 1878 fw->ucode_size = le32toh(hdr.ucode_size); 1879 1880 fw->main = firmware_malloc(fw->main_size); 1881 if (fw->main == NULL) { 1882 error = ENOMEM; 1883 goto fail1; 1884 } 1885 1886 fw->ucode = firmware_malloc(fw->ucode_size); 1887 if (fw->ucode == NULL) { 1888 error = ENOMEM; 1889 goto fail2; 1890 } 1891 1892 p = sizeof(hdr); 1893 if ((error = firmware_read(fwh, p, fw->main, fw->main_size)) != 0) 1894 goto fail3; 1895 1896 p += fw->main_size; 1897 if ((error = firmware_read(fwh, p, fw->ucode, fw->ucode_size)) != 0) 1898 goto fail3; 1899 1900 DPRINTF(("Firmware cached: main %u, ucode %u\n", fw->main_size, 1901 fw->ucode_size)); 1902 1903 sc->flags |= IPW_FLAG_FW_CACHED; 1904 1905 firmware_close(fwh); 1906 1907 return 0; 1908 1909 fail3: firmware_free(fw->ucode, 0); 1910 fail2: firmware_free(fw->main, 0); 1911 fail1: firmware_close(fwh); 1912 fail0: 1913 return error; 1914 } 1915 1916 static void 1917 ipw_free_firmware(struct ipw_softc *sc) 1918 { 1919 if (!(sc->flags & IPW_FLAG_FW_CACHED)) 1920 return; 1921 1922 firmware_free(sc->fw.main, 0); 1923 firmware_free(sc->fw.ucode, 0); 1924 1925 sc->flags &= ~IPW_FLAG_FW_CACHED; 1926 } 1927 1928 static int 1929 ipw_config(struct ipw_softc *sc) 1930 { 1931 struct ieee80211com *ic = &sc->sc_ic; 1932 struct ifnet *ifp = &sc->sc_if; 1933 struct ipw_security security; 1934 struct ieee80211_key *k; 1935 struct ipw_wep_key wepkey; 1936 struct ipw_scan_options options; 1937 struct ipw_configuration config; 1938 uint32_t data; 1939 int error, i; 1940 1941 switch (ic->ic_opmode) { 1942 case IEEE80211_M_STA: 1943 case IEEE80211_M_HOSTAP: 1944 data = htole32(IPW_MODE_BSS); 1945 break; 1946 1947 case IEEE80211_M_IBSS: 1948 case IEEE80211_M_AHDEMO: 1949 data = htole32(IPW_MODE_IBSS); 1950 break; 1951 1952 case IEEE80211_M_MONITOR: 1953 data = htole32(IPW_MODE_MONITOR); 1954 break; 1955 } 1956 DPRINTF(("Setting mode to %u\n", le32toh(data))); 1957 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 1958 if (error != 0) 1959 return error; 1960 1961 if (ic->ic_opmode == IEEE80211_M_IBSS || 1962 ic->ic_opmode == IEEE80211_M_MONITOR) { 1963 data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); 1964 DPRINTF(("Setting channel to %u\n", le32toh(data))); 1965 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 1966 if (error != 0) 1967 return error; 1968 } 1969 1970 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1971 DPRINTF(("Enabling adapter\n")); 1972 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1973 } 1974 1975 DPRINTF(("Setting MAC to %s\n", ether_sprintf(ic->ic_myaddr))); 1976 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 1977 IEEE80211_ADDR_LEN); 1978 if (error != 0) 1979 return error; 1980 1981 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 1982 IPW_CFG_PREAMBLE_AUTO | IPW_CFG_802_1x_ENABLE); 1983 1984 if (ic->ic_opmode == IEEE80211_M_IBSS) 1985 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 1986 if (ifp->if_flags & IFF_PROMISC) 1987 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 1988 config.bss_chan = htole32(0x3fff); /* channels 1-14 */ 1989 config.ibss_chan = htole32(0x7ff); /* channels 1-11 */ 1990 DPRINTF(("Setting adapter configuration 0x%08x\n", config.flags)); 1991 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 1992 if (error != 0) 1993 return error; 1994 1995 data = htole32(0x3); /* 1, 2 */ 1996 DPRINTF(("Setting basic tx rates to 0x%x\n", le32toh(data))); 1997 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 1998 if (error != 0) 1999 return error; 2000 2001 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 2002 DPRINTF(("Setting tx rates to 0x%x\n", le32toh(data))); 2003 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 2004 if (error != 0) 2005 return error; 2006 2007 data = htole32(IPW_POWER_MODE_CAM); 2008 DPRINTF(("Setting power mode to %u\n", le32toh(data))); 2009 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 2010 if (error != 0) 2011 return error; 2012 2013 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2014 data = htole32(32); /* default value */ 2015 DPRINTF(("Setting tx power index to %u\n", le32toh(data))); 2016 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 2017 sizeof data); 2018 if (error != 0) 2019 return error; 2020 } 2021 2022 data = htole32(ic->ic_rtsthreshold); 2023 DPRINTF(("Setting RTS threshold to %u\n", le32toh(data))); 2024 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 2025 if (error != 0) 2026 return error; 2027 2028 data = htole32(ic->ic_fragthreshold); 2029 DPRINTF(("Setting frag threshold to %u\n", le32toh(data))); 2030 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 2031 if (error != 0) 2032 return error; 2033 2034 #ifdef IPW_DEBUG 2035 if (ipw_debug > 0) { 2036 printf("Setting ESSID to "); 2037 ieee80211_print_essid(ic->ic_des_essid, ic->ic_des_esslen); 2038 printf("\n"); 2039 } 2040 #endif 2041 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ic->ic_des_essid, 2042 ic->ic_des_esslen); 2043 if (error != 0) 2044 return error; 2045 2046 /* no mandatory BSSID */ 2047 DPRINTF(("Setting mandatory BSSID to null\n")); 2048 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 2049 if (error != 0) 2050 return error; 2051 2052 if (ic->ic_flags & IEEE80211_F_DESBSSID) { 2053 DPRINTF(("Setting desired BSSID to %s\n", 2054 ether_sprintf(ic->ic_des_bssid))); 2055 error = ipw_cmd(sc, IPW_CMD_SET_DESIRED_BSSID, 2056 ic->ic_des_bssid, IEEE80211_ADDR_LEN); 2057 if (error != 0) 2058 return error; 2059 } 2060 2061 (void)memset(&security, 0, sizeof(security)); 2062 security.authmode = (ic->ic_bss->ni_authmode == IEEE80211_AUTH_SHARED) ? 2063 IPW_AUTH_SHARED : IPW_AUTH_OPEN; 2064 security.ciphers = htole32(IPW_CIPHER_NONE); 2065 DPRINTF(("Setting authmode to %u\n", security.authmode)); 2066 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 2067 sizeof security); 2068 if (error != 0) 2069 return error; 2070 2071 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 2072 k = ic->ic_crypto.cs_nw_keys; 2073 for (i = 0; i < IEEE80211_WEP_NKID; i++, k++) { 2074 if (k->wk_keylen == 0) 2075 continue; 2076 2077 wepkey.idx = i; 2078 wepkey.len = k->wk_keylen; 2079 memset(wepkey.key, 0, sizeof(wepkey.key)); 2080 memcpy(wepkey.key, k->wk_key, k->wk_keylen); 2081 DPRINTF(("Setting wep key index %u len %u\n", 2082 wepkey.idx, wepkey.len)); 2083 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY, &wepkey, 2084 sizeof wepkey); 2085 if (error != 0) 2086 return error; 2087 } 2088 2089 data = htole32(ic->ic_crypto.cs_def_txkey); 2090 DPRINTF(("Setting tx key index to %u\n", le32toh(data))); 2091 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY_INDEX, &data, 2092 sizeof data); 2093 if (error != 0) 2094 return error; 2095 } 2096 2097 data = htole32((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) ? IPW_WEPON : 0); 2098 DPRINTF(("Setting wep flags to 0x%x\n", le32toh(data))); 2099 error = ipw_cmd(sc, IPW_CMD_SET_WEP_FLAGS, &data, sizeof data); 2100 if (error != 0) 2101 return error; 2102 2103 #if 0 2104 struct ipw_wpa_ie ie; 2105 2106 memset(&ie, 0 sizeof(ie)); 2107 ie.len = htole32(sizeof (struct ieee80211_ie_wpa)); 2108 DPRINTF(("Setting wpa ie\n")); 2109 error = ipw_cmd(sc, IPW_CMD_SET_WPA_IE, &ie, sizeof ie); 2110 if (error != 0) 2111 return error; 2112 #endif 2113 2114 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2115 data = htole32(ic->ic_bintval); 2116 DPRINTF(("Setting beacon interval to %u\n", le32toh(data))); 2117 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 2118 sizeof data); 2119 if (error != 0) 2120 return error; 2121 } 2122 2123 options.flags = 0; 2124 options.channels = htole32(0x3fff); /* scan channels 1-14 */ 2125 DPRINTF(("Setting scan options to 0x%x\n", le32toh(options.flags))); 2126 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &options, sizeof options); 2127 if (error != 0) 2128 return error; 2129 2130 /* finally, enable adapter (start scanning for an access point) */ 2131 DPRINTF(("Enabling adapter\n")); 2132 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 2133 } 2134 2135 static int 2136 ipw_init(struct ifnet *ifp) 2137 { 2138 struct ipw_softc *sc = ifp->if_softc; 2139 struct ipw_firmware *fw = &sc->fw; 2140 2141 if (!(sc->flags & IPW_FLAG_FW_CACHED)) { 2142 if (ipw_cache_firmware(sc) != 0) { 2143 aprint_error_dev(&sc->sc_dev, "could not cache the firmware (%s)\n", 2144 sc->sc_fwname); 2145 goto fail; 2146 } 2147 } 2148 2149 ipw_stop(ifp, 0); 2150 2151 if (ipw_reset(sc) != 0) { 2152 aprint_error_dev(&sc->sc_dev, "could not reset adapter\n"); 2153 goto fail; 2154 } 2155 2156 if (ipw_load_ucode(sc, fw->ucode, fw->ucode_size) != 0) { 2157 aprint_error_dev(&sc->sc_dev, "could not load microcode\n"); 2158 goto fail; 2159 } 2160 2161 ipw_stop_master(sc); 2162 2163 /* 2164 * Setup tx, rx and status rings. 2165 */ 2166 sc->txold = IPW_NTBD - 1; 2167 sc->txcur = 0; 2168 sc->txfree = IPW_NTBD - 2; 2169 sc->rxcur = IPW_NRBD - 1; 2170 2171 CSR_WRITE_4(sc, IPW_CSR_TX_BASE, sc->tbd_map->dm_segs[0].ds_addr); 2172 CSR_WRITE_4(sc, IPW_CSR_TX_SIZE, IPW_NTBD); 2173 CSR_WRITE_4(sc, IPW_CSR_TX_READ, 0); 2174 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 2175 2176 CSR_WRITE_4(sc, IPW_CSR_RX_BASE, sc->rbd_map->dm_segs[0].ds_addr); 2177 CSR_WRITE_4(sc, IPW_CSR_RX_SIZE, IPW_NRBD); 2178 CSR_WRITE_4(sc, IPW_CSR_RX_READ, 0); 2179 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 2180 2181 CSR_WRITE_4(sc, IPW_CSR_STATUS_BASE, sc->status_map->dm_segs[0].ds_addr); 2182 2183 if (ipw_load_firmware(sc, fw->main, fw->main_size) != 0) { 2184 aprint_error_dev(&sc->sc_dev, "could not load firmware\n"); 2185 goto fail; 2186 } 2187 2188 sc->flags |= IPW_FLAG_FW_INITED; 2189 2190 /* retrieve information tables base addresses */ 2191 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 2192 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 2193 2194 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 2195 2196 if (ipw_config(sc) != 0) { 2197 aprint_error_dev(&sc->sc_dev, "device configuration failed\n"); 2198 goto fail; 2199 } 2200 2201 ifp->if_flags &= ~IFF_OACTIVE; 2202 ifp->if_flags |= IFF_RUNNING; 2203 2204 return 0; 2205 2206 fail: ifp->if_flags &= ~IFF_UP; 2207 ipw_stop(ifp, 0); 2208 2209 return EIO; 2210 } 2211 2212 static void 2213 ipw_stop(struct ifnet *ifp, int disable) 2214 { 2215 struct ipw_softc *sc = ifp->if_softc; 2216 struct ieee80211com *ic = &sc->sc_ic; 2217 int i; 2218 2219 ipw_stop_master(sc); 2220 2221 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 2222 2223 /* 2224 * Release tx buffers. 2225 */ 2226 for (i = 0; i < IPW_NTBD; i++) 2227 ipw_release_sbd(sc, &sc->stbd_list[i]); 2228 2229 sc->sc_tx_timer = 0; 2230 ifp->if_timer = 0; 2231 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2232 2233 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2234 } 2235 2236 static void 2237 ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2238 bus_size_t count) 2239 { 2240 for (; count > 0; offset++, datap++, count--) { 2241 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2242 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 2243 } 2244 } 2245 2246 static void 2247 ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2248 bus_size_t count) 2249 { 2250 for (; count > 0; offset++, datap++, count--) { 2251 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2252 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 2253 } 2254 } 2255 2256 SYSCTL_SETUP(sysctl_hw_ipw_accept_eula_setup, "sysctl hw.ipw.accept_eula") 2257 { 2258 const struct sysctlnode *rnode; 2259 const struct sysctlnode *cnode; 2260 2261 sysctl_createv(NULL, 0, NULL, &rnode, 2262 CTLFLAG_PERMANENT, 2263 CTLTYPE_NODE, "hw", 2264 NULL, 2265 NULL, 0, 2266 NULL, 0, 2267 CTL_HW, CTL_EOL); 2268 2269 sysctl_createv(NULL, 0, &rnode, &rnode, 2270 CTLFLAG_PERMANENT, 2271 CTLTYPE_NODE, "ipw", 2272 NULL, 2273 NULL, 0, 2274 NULL, 0, 2275 CTL_CREATE, CTL_EOL); 2276 2277 sysctl_createv(NULL, 0, &rnode, &cnode, 2278 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, 2279 CTLTYPE_INT, "accept_eula", 2280 SYSCTL_DESCR("Accept Intel EULA and permit use of ipw(4) firmware"), 2281 NULL, 0, 2282 &ipw_accept_eula, sizeof(ipw_accept_eula), 2283 CTL_CREATE, CTL_EOL); 2284 } 2285
Indexes created Tue Sep 30 17:09:57 GMT 2025