if_ipw.c revision 1.53.6.1
1 /* $NetBSD: if_ipw.c,v 1.53.6.1 2012/11/20 03:02:16 tls Exp $ */ 2 /* FreeBSD: src/sys/dev/ipw/if_ipw.c,v 1.15 2005/11/13 17:17:40 damien Exp */ 3 4 /*- 5 * Copyright (c) 2004, 2005 6 * Damien Bergamini <damien.bergamini (at) free.fr>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: if_ipw.c,v 1.53.6.1 2012/11/20 03:02:16 tls Exp $"); 33 34 /*- 35 * Intel(R) PRO/Wireless 2100 MiniPCI driver 36 * http://www.intel.com/network/connectivity/products/wireless/prowireless_mobile.htm 37 */ 38 39 40 #include <sys/param.h> 41 #include <sys/sockio.h> 42 #include <sys/sysctl.h> 43 #include <sys/mbuf.h> 44 #include <sys/kernel.h> 45 #include <sys/socket.h> 46 #include <sys/systm.h> 47 #include <sys/malloc.h> 48 #include <sys/conf.h> 49 #include <sys/proc.h> 50 51 #include <sys/bus.h> 52 #include <machine/endian.h> 53 #include <sys/intr.h> 54 55 #include <dev/pci/pcireg.h> 56 #include <dev/pci/pcivar.h> 57 #include <dev/pci/pcidevs.h> 58 59 #include <net/bpf.h> 60 #include <net/if.h> 61 #include <net/if_arp.h> 62 #include <net/if_dl.h> 63 #include <net/if_ether.h> 64 #include <net/if_media.h> 65 #include <net/if_types.h> 66 67 #include <net80211/ieee80211_var.h> 68 #include <net80211/ieee80211_radiotap.h> 69 70 #include <netinet/in.h> 71 #include <netinet/in_systm.h> 72 #include <netinet/in_var.h> 73 #include <netinet/ip.h> 74 75 #include <dev/firmload.h> 76 77 #include <dev/pci/if_ipwreg.h> 78 #include <dev/pci/if_ipwvar.h> 79 80 #ifdef IPW_DEBUG 81 #define DPRINTF(x) if (ipw_debug > 0) printf x 82 #define DPRINTFN(n, x) if (ipw_debug >= (n)) printf x 83 int ipw_debug = 0; 84 #else 85 #define DPRINTF(x) 86 #define DPRINTFN(n, x) 87 #endif 88 89 /* Permit loading the Intel firmware */ 90 static int ipw_accept_eula; 91 92 static int ipw_dma_alloc(struct ipw_softc *); 93 static void ipw_release(struct ipw_softc *); 94 static int ipw_match(device_t, cfdata_t, void *); 95 static void ipw_attach(device_t, device_t, void *); 96 static int ipw_detach(device_t, int); 97 98 static int ipw_media_change(struct ifnet *); 99 static void ipw_media_status(struct ifnet *, struct ifmediareq *); 100 static int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 101 static uint16_t ipw_read_prom_word(struct ipw_softc *, uint8_t); 102 static void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 103 static void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 104 static void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 105 struct ipw_soft_bd *, struct ipw_soft_buf *); 106 static void ipw_rx_intr(struct ipw_softc *); 107 static void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 108 static void ipw_tx_intr(struct ipw_softc *); 109 static int ipw_intr(void *); 110 static int ipw_cmd(struct ipw_softc *, uint32_t, void *, uint32_t); 111 static int ipw_tx_start(struct ifnet *, struct mbuf *, 112 struct ieee80211_node *); 113 static void ipw_start(struct ifnet *); 114 static void ipw_watchdog(struct ifnet *); 115 static int ipw_ioctl(struct ifnet *, u_long, void *); 116 static int ipw_get_table1(struct ipw_softc *, uint32_t *); 117 static int ipw_get_radio(struct ipw_softc *, int *); 118 static void ipw_stop_master(struct ipw_softc *); 119 static int ipw_reset(struct ipw_softc *); 120 static int ipw_load_ucode(struct ipw_softc *, u_char *, int); 121 static int ipw_load_firmware(struct ipw_softc *, u_char *, int); 122 static int ipw_cache_firmware(struct ipw_softc *); 123 static void ipw_free_firmware(struct ipw_softc *); 124 static int ipw_config(struct ipw_softc *); 125 static int ipw_init(struct ifnet *); 126 static void ipw_stop(struct ifnet *, int); 127 static uint32_t ipw_read_table1(struct ipw_softc *, uint32_t); 128 static void ipw_write_table1(struct ipw_softc *, uint32_t, uint32_t); 129 static int ipw_read_table2(struct ipw_softc *, uint32_t, void *, uint32_t *); 130 static void ipw_read_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 131 bus_size_t); 132 static void ipw_write_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 133 bus_size_t); 134 135 /* 136 * Supported rates for 802.11b mode (in 500Kbps unit). 137 */ 138 static const struct ieee80211_rateset ipw_rateset_11b = 139 { 4, { 2, 4, 11, 22 } }; 140 141 static inline uint8_t 142 MEM_READ_1(struct ipw_softc *sc, uint32_t addr) 143 { 144 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 145 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); 146 } 147 148 static inline uint32_t 149 MEM_READ_4(struct ipw_softc *sc, uint32_t addr) 150 { 151 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 152 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); 153 } 154 155 CFATTACH_DECL_NEW(ipw, sizeof (struct ipw_softc), ipw_match, ipw_attach, 156 ipw_detach, NULL); 157 158 static int 159 ipw_match(device_t parent, cfdata_t match, void *aux) 160 { 161 struct pci_attach_args *pa = aux; 162 163 if (PCI_VENDOR (pa->pa_id) == PCI_VENDOR_INTEL && 164 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_PRO_WL_2100) 165 return 1; 166 167 return 0; 168 } 169 170 /* Base Address Register */ 171 #define IPW_PCI_BAR0 0x10 172 173 static void 174 ipw_attach(device_t parent, device_t self, void *aux) 175 { 176 struct ipw_softc *sc = device_private(self); 177 struct ieee80211com *ic = &sc->sc_ic; 178 struct ifnet *ifp = &sc->sc_if; 179 struct pci_attach_args *pa = aux; 180 const char *intrstr; 181 bus_space_tag_t memt; 182 bus_space_handle_t memh; 183 bus_addr_t base; 184 pci_intr_handle_t ih; 185 uint32_t data; 186 uint16_t val; 187 int i, error; 188 189 sc->sc_dev = self; 190 sc->sc_pct = pa->pa_pc; 191 sc->sc_pcitag = pa->pa_tag; 192 193 pci_aprint_devinfo(pa, NULL); 194 195 /* enable bus-mastering */ 196 data = pci_conf_read(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG); 197 data |= PCI_COMMAND_MASTER_ENABLE; 198 pci_conf_write(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG, data); 199 200 /* map the register window */ 201 error = pci_mapreg_map(pa, IPW_PCI_BAR0, PCI_MAPREG_TYPE_MEM | 202 PCI_MAPREG_MEM_TYPE_32BIT, 0, &memt, &memh, &base, &sc->sc_sz); 203 if (error != 0) { 204 aprint_error_dev(sc->sc_dev, "could not map memory space\n"); 205 return; 206 } 207 208 sc->sc_st = memt; 209 sc->sc_sh = memh; 210 sc->sc_dmat = pa->pa_dmat; 211 sc->sc_fwname = "ipw2100-1.2.fw"; 212 213 /* disable interrupts */ 214 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 215 216 if (pci_intr_map(pa, &ih) != 0) { 217 aprint_error_dev(sc->sc_dev, "could not map interrupt\n"); 218 return; 219 } 220 221 intrstr = pci_intr_string(sc->sc_pct, ih); 222 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, ipw_intr, sc); 223 if (sc->sc_ih == NULL) { 224 aprint_error_dev(sc->sc_dev, "could not establish interrupt"); 225 if (intrstr != NULL) 226 aprint_error(" at %s", intrstr); 227 aprint_error("\n"); 228 return; 229 } 230 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 231 232 if (ipw_reset(sc) != 0) { 233 aprint_error_dev(sc->sc_dev, "could not reset adapter\n"); 234 goto fail; 235 } 236 237 if (ipw_dma_alloc(sc) != 0) { 238 aprint_error_dev(sc->sc_dev, "could not allocate DMA resources\n"); 239 goto fail; 240 } 241 242 ifp->if_softc = sc; 243 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 244 ifp->if_init = ipw_init; 245 ifp->if_stop = ipw_stop; 246 ifp->if_ioctl = ipw_ioctl; 247 ifp->if_start = ipw_start; 248 ifp->if_watchdog = ipw_watchdog; 249 IFQ_SET_READY(&ifp->if_snd); 250 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 251 252 ic->ic_ifp = ifp; 253 ic->ic_phytype = IEEE80211_T_DS; 254 ic->ic_opmode = IEEE80211_M_STA; 255 ic->ic_state = IEEE80211_S_INIT; 256 257 /* set device capabilities */ 258 ic->ic_caps = 259 IEEE80211_C_SHPREAMBLE /* short preamble supported */ 260 | IEEE80211_C_TXPMGT /* tx power management */ 261 | IEEE80211_C_IBSS /* ibss mode */ 262 | IEEE80211_C_MONITOR /* monitor mode */ 263 ; 264 265 /* read MAC address from EEPROM */ 266 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0); 267 ic->ic_myaddr[0] = val >> 8; 268 ic->ic_myaddr[1] = val & 0xff; 269 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 1); 270 ic->ic_myaddr[2] = val >> 8; 271 ic->ic_myaddr[3] = val & 0xff; 272 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 2); 273 ic->ic_myaddr[4] = val >> 8; 274 ic->ic_myaddr[5] = val & 0xff; 275 276 /* set supported .11b rates */ 277 ic->ic_sup_rates[IEEE80211_MODE_11B] = ipw_rateset_11b; 278 279 /* set supported .11b channels (read from EEPROM) */ 280 if ((val = ipw_read_prom_word(sc, IPW_EEPROM_CHANNEL_LIST)) == 0) 281 val = 0x7ff; /* default to channels 1-11 */ 282 val <<= 1; 283 for (i = 1; i < 16; i++) { 284 if (val & (1 << i)) { 285 ic->ic_channels[i].ic_freq = 286 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 287 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 288 } 289 } 290 291 /* check support for radio transmitter switch in EEPROM */ 292 if (!(ipw_read_prom_word(sc, IPW_EEPROM_RADIO) & 8)) 293 sc->flags |= IPW_FLAG_HAS_RADIO_SWITCH; 294 295 aprint_normal_dev(sc->sc_dev, "802.11 address %s\n", 296 ether_sprintf(ic->ic_myaddr)); 297 298 if_attach(ifp); 299 ieee80211_ifattach(ic); 300 301 /* override state transition machine */ 302 sc->sc_newstate = ic->ic_newstate; 303 ic->ic_newstate = ipw_newstate; 304 305 ieee80211_media_init(ic, ipw_media_change, ipw_media_status); 306 307 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 308 sizeof(struct ieee80211_frame) + 64, &sc->sc_drvbpf); 309 310 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 311 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 312 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 313 314 sc->sc_txtap_len = sizeof sc->sc_txtapu; 315 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 316 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 317 318 /* 319 * Add a few sysctl knobs. 320 * XXX: Not yet 321 */ 322 sc->dwelltime = 100; 323 324 if (pmf_device_register(self, NULL, NULL)) 325 pmf_class_network_register(self, ifp); 326 else 327 aprint_error_dev(self, "couldn't establish power handler\n"); 328 329 ieee80211_announce(ic); 330 331 return; 332 333 fail: ipw_detach(self, 0); 334 } 335 336 static int 337 ipw_detach(device_t self, int flags) 338 { 339 struct ipw_softc *sc = device_private(self); 340 struct ifnet *ifp = &sc->sc_if; 341 342 if (ifp->if_softc) { 343 ipw_stop(ifp, 1); 344 ipw_free_firmware(sc); 345 346 bpf_detach(ifp); 347 ieee80211_ifdetach(&sc->sc_ic); 348 if_detach(ifp); 349 350 ipw_release(sc); 351 } 352 353 if (sc->sc_ih != NULL) { 354 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 355 sc->sc_ih = NULL; 356 } 357 358 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 359 360 return 0; 361 } 362 363 static int 364 ipw_dma_alloc(struct ipw_softc *sc) 365 { 366 struct ipw_soft_bd *sbd; 367 struct ipw_soft_hdr *shdr; 368 struct ipw_soft_buf *sbuf; 369 int error, i, nsegs; 370 371 /* 372 * Allocate and map tx ring. 373 */ 374 error = bus_dmamap_create(sc->sc_dmat, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, 375 BUS_DMA_NOWAIT, &sc->tbd_map); 376 if (error != 0) { 377 aprint_error_dev(sc->sc_dev, "could not create tbd dma map\n"); 378 goto fail; 379 } 380 381 error = bus_dmamem_alloc(sc->sc_dmat, IPW_TBD_SZ, PAGE_SIZE, 0, 382 &sc->tbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 383 if (error != 0) { 384 aprint_error_dev(sc->sc_dev, "could not allocate tbd dma memory\n"); 385 goto fail; 386 } 387 388 error = bus_dmamem_map(sc->sc_dmat, &sc->tbd_seg, nsegs, IPW_TBD_SZ, 389 (void **)&sc->tbd_list, BUS_DMA_NOWAIT); 390 if (error != 0) { 391 aprint_error_dev(sc->sc_dev, "could not map tbd dma memory\n"); 392 goto fail; 393 } 394 395 error = bus_dmamap_load(sc->sc_dmat, sc->tbd_map, sc->tbd_list, 396 IPW_TBD_SZ, NULL, BUS_DMA_NOWAIT); 397 if (error != 0) { 398 aprint_error_dev(sc->sc_dev, "could not load tbd dma memory\n"); 399 goto fail; 400 } 401 402 (void)memset(sc->tbd_list, 0, IPW_TBD_SZ); 403 404 /* 405 * Allocate and map rx ring. 406 */ 407 error = bus_dmamap_create(sc->sc_dmat, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, 408 BUS_DMA_NOWAIT, &sc->rbd_map); 409 if (error != 0) { 410 aprint_error_dev(sc->sc_dev, "could not create rbd dma map\n"); 411 goto fail; 412 } 413 414 error = bus_dmamem_alloc(sc->sc_dmat, IPW_RBD_SZ, PAGE_SIZE, 0, 415 &sc->rbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 416 if (error != 0) { 417 aprint_error_dev(sc->sc_dev, "could not allocate rbd dma memory\n"); 418 goto fail; 419 } 420 421 error = bus_dmamem_map(sc->sc_dmat, &sc->rbd_seg, nsegs, IPW_RBD_SZ, 422 (void **)&sc->rbd_list, BUS_DMA_NOWAIT); 423 if (error != 0) { 424 aprint_error_dev(sc->sc_dev, "could not map rbd dma memory\n"); 425 goto fail; 426 } 427 428 error = bus_dmamap_load(sc->sc_dmat, sc->rbd_map, sc->rbd_list, 429 IPW_RBD_SZ, NULL, BUS_DMA_NOWAIT); 430 if (error != 0) { 431 aprint_error_dev(sc->sc_dev, "could not load rbd dma memory\n"); 432 goto fail; 433 } 434 435 (void)memset(sc->rbd_list, 0, IPW_RBD_SZ); 436 437 /* 438 * Allocate and map status ring. 439 */ 440 error = bus_dmamap_create(sc->sc_dmat, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 441 0, BUS_DMA_NOWAIT, &sc->status_map); 442 if (error != 0) { 443 aprint_error_dev(sc->sc_dev, "could not create status dma map\n"); 444 goto fail; 445 } 446 447 error = bus_dmamem_alloc(sc->sc_dmat, IPW_STATUS_SZ, PAGE_SIZE, 0, 448 &sc->status_seg, 1, &nsegs, BUS_DMA_NOWAIT); 449 if (error != 0) { 450 aprint_error_dev(sc->sc_dev, "could not allocate status dma memory\n"); 451 goto fail; 452 } 453 454 error = bus_dmamem_map(sc->sc_dmat, &sc->status_seg, nsegs, 455 IPW_STATUS_SZ, (void **)&sc->status_list, BUS_DMA_NOWAIT); 456 if (error != 0) { 457 aprint_error_dev(sc->sc_dev, "could not map status dma memory\n"); 458 goto fail; 459 } 460 461 error = bus_dmamap_load(sc->sc_dmat, sc->status_map, sc->status_list, 462 IPW_STATUS_SZ, NULL, BUS_DMA_NOWAIT); 463 if (error != 0) { 464 aprint_error_dev(sc->sc_dev, "could not load status dma memory\n"); 465 goto fail; 466 } 467 468 (void)memset(sc->status_list, 0, IPW_STATUS_SZ); 469 470 /* 471 * Allocate command DMA map. 472 */ 473 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_cmd), 474 1, sizeof (struct ipw_cmd), 0, BUS_DMA_NOWAIT, &sc->cmd_map); 475 if (error != 0) { 476 aprint_error_dev(sc->sc_dev, "could not create cmd dma map\n"); 477 goto fail; 478 } 479 480 error = bus_dmamem_alloc(sc->sc_dmat, sizeof (struct ipw_cmd), 481 PAGE_SIZE, 0, &sc->cmd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 482 if (error != 0) { 483 aprint_error_dev(sc->sc_dev, "could not allocate cmd dma memory\n"); 484 goto fail; 485 } 486 487 error = bus_dmamem_map(sc->sc_dmat, &sc->cmd_seg, nsegs, 488 sizeof (struct ipw_cmd), (void **)&sc->cmd, BUS_DMA_NOWAIT); 489 if (error != 0) { 490 aprint_error_dev(sc->sc_dev, "could not map cmd dma memory\n"); 491 goto fail; 492 } 493 494 error = bus_dmamap_load(sc->sc_dmat, sc->cmd_map, &sc->cmd, 495 sizeof (struct ipw_cmd), NULL, BUS_DMA_NOWAIT); 496 if (error != 0) { 497 aprint_error_dev(sc->sc_dev, "could not map cmd dma memory\n"); 498 return error; 499 } 500 501 /* 502 * Allocate and map hdr list. 503 */ 504 505 error = bus_dmamap_create(sc->sc_dmat, 506 IPW_NDATA * sizeof(struct ipw_hdr), 1, 507 sizeof(struct ipw_hdr), 0, BUS_DMA_NOWAIT, 508 &sc->hdr_map); 509 if (error != 0) { 510 aprint_error_dev(sc->sc_dev, "could not create hdr dma map\n"); 511 goto fail; 512 } 513 514 error = bus_dmamem_alloc(sc->sc_dmat, 515 IPW_NDATA * sizeof(struct ipw_hdr), PAGE_SIZE, 0, &sc->hdr_seg, 516 1, &nsegs, BUS_DMA_NOWAIT); 517 if (error != 0) { 518 aprint_error_dev(sc->sc_dev, "could not allocate hdr memory\n"); 519 goto fail; 520 } 521 522 error = bus_dmamem_map(sc->sc_dmat, &sc->hdr_seg, nsegs, 523 IPW_NDATA * sizeof(struct ipw_hdr), (void **)&sc->hdr_list, 524 BUS_DMA_NOWAIT); 525 if (error != 0) { 526 aprint_error_dev(sc->sc_dev, "could not map hdr memory\n"); 527 goto fail; 528 } 529 530 error = bus_dmamap_load(sc->sc_dmat, sc->hdr_map, sc->hdr_list, 531 IPW_NDATA * sizeof(struct ipw_hdr), NULL, BUS_DMA_NOWAIT); 532 if (error != 0) { 533 aprint_error_dev(sc->sc_dev, "could not load hdr memory\n"); 534 goto fail; 535 } 536 537 (void)memset(sc->hdr_list, 0, IPW_HDR_SZ); 538 539 /* 540 * Create DMA hdrs tailq. 541 */ 542 TAILQ_INIT(&sc->sc_free_shdr); 543 for (i = 0; i < IPW_NDATA; i++) { 544 shdr = &sc->shdr_list[i]; 545 shdr->hdr = sc->hdr_list + i; 546 shdr->offset = sizeof(struct ipw_hdr) * i; 547 shdr->addr = sc->hdr_map->dm_segs[0].ds_addr + shdr->offset; 548 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 549 } 550 551 /* 552 * Allocate tx buffers DMA maps. 553 */ 554 TAILQ_INIT(&sc->sc_free_sbuf); 555 for (i = 0; i < IPW_NDATA; i++) { 556 sbuf = &sc->tx_sbuf_list[i]; 557 558 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 559 IPW_MAX_NSEG, MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 560 if (error != 0) { 561 aprint_error_dev(sc->sc_dev, "could not create txbuf dma map\n"); 562 goto fail; 563 } 564 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 565 } 566 567 /* 568 * Initialize tx ring. 569 */ 570 for (i = 0; i < IPW_NTBD; i++) { 571 sbd = &sc->stbd_list[i]; 572 sbd->bd = &sc->tbd_list[i]; 573 sbd->type = IPW_SBD_TYPE_NOASSOC; 574 } 575 576 /* 577 * Pre-allocate rx buffers and DMA maps 578 */ 579 for (i = 0; i < IPW_NRBD; i++) { 580 sbd = &sc->srbd_list[i]; 581 sbuf = &sc->rx_sbuf_list[i]; 582 sbd->bd = &sc->rbd_list[i]; 583 584 MGETHDR(sbuf->m, M_DONTWAIT, MT_DATA); 585 if (sbuf->m == NULL) { 586 aprint_error_dev(sc->sc_dev, "could not allocate rx mbuf\n"); 587 error = ENOMEM; 588 goto fail; 589 } 590 591 MCLGET(sbuf->m, M_DONTWAIT); 592 if (!(sbuf->m->m_flags & M_EXT)) { 593 m_freem(sbuf->m); 594 aprint_error_dev(sc->sc_dev, "could not allocate rx mbuf cluster\n"); 595 error = ENOMEM; 596 goto fail; 597 } 598 599 sbuf->m->m_pkthdr.len = sbuf->m->m_len = sbuf->m->m_ext.ext_size; 600 601 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 602 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sbuf->map); 603 if (error != 0) { 604 aprint_error_dev(sc->sc_dev, "could not create rxbuf dma map\n"); 605 m_freem(sbuf->m); 606 goto fail; 607 } 608 609 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, 610 sbuf->m, BUS_DMA_READ | BUS_DMA_NOWAIT); 611 if (error != 0) { 612 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 613 m_freem(sbuf->m); 614 aprint_error_dev(sc->sc_dev, "could not map rxbuf dma memory\n"); 615 goto fail; 616 } 617 618 sbd->type = IPW_SBD_TYPE_DATA; 619 sbd->priv = sbuf; 620 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 621 sbd->bd->len = htole32(MCLBYTES); 622 623 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, 624 sbuf->map->dm_mapsize, BUS_DMASYNC_PREREAD); 625 626 } 627 628 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 0, IPW_RBD_SZ, 629 BUS_DMASYNC_PREREAD); 630 631 return 0; 632 633 fail: ipw_release(sc); 634 return error; 635 } 636 637 static void 638 ipw_release(struct ipw_softc *sc) 639 { 640 struct ipw_soft_buf *sbuf; 641 int i; 642 643 if (sc->tbd_map != NULL) { 644 if (sc->tbd_list != NULL) { 645 bus_dmamap_unload(sc->sc_dmat, sc->tbd_map); 646 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->tbd_list, 647 IPW_TBD_SZ); 648 bus_dmamem_free(sc->sc_dmat, &sc->tbd_seg, 1); 649 } 650 bus_dmamap_destroy(sc->sc_dmat, sc->tbd_map); 651 } 652 653 if (sc->rbd_map != NULL) { 654 if (sc->rbd_list != NULL) { 655 bus_dmamap_unload(sc->sc_dmat, sc->rbd_map); 656 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->rbd_list, 657 IPW_RBD_SZ); 658 bus_dmamem_free(sc->sc_dmat, &sc->rbd_seg, 1); 659 } 660 bus_dmamap_destroy(sc->sc_dmat, sc->rbd_map); 661 } 662 663 if (sc->status_map != NULL) { 664 if (sc->status_list != NULL) { 665 bus_dmamap_unload(sc->sc_dmat, sc->status_map); 666 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->status_list, 667 IPW_RBD_SZ); 668 bus_dmamem_free(sc->sc_dmat, &sc->status_seg, 1); 669 } 670 bus_dmamap_destroy(sc->sc_dmat, sc->status_map); 671 } 672 673 for (i = 0; i < IPW_NTBD; i++) 674 ipw_release_sbd(sc, &sc->stbd_list[i]); 675 676 if (sc->cmd_map != NULL) 677 bus_dmamap_destroy(sc->sc_dmat, sc->cmd_map); 678 679 if (sc->hdr_list != NULL) { 680 bus_dmamap_unload(sc->sc_dmat, sc->hdr_map); 681 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->hdr_list, 682 IPW_NDATA * sizeof(struct ipw_hdr)); 683 } 684 if (sc->hdr_map != NULL) { 685 bus_dmamem_free(sc->sc_dmat, &sc->hdr_seg, 1); 686 bus_dmamap_destroy(sc->sc_dmat, sc->hdr_map); 687 } 688 689 for (i = 0; i < IPW_NDATA; i++) 690 bus_dmamap_destroy(sc->sc_dmat, sc->tx_sbuf_list[i].map); 691 692 for (i = 0; i < IPW_NRBD; i++) { 693 sbuf = &sc->rx_sbuf_list[i]; 694 if (sbuf->map != NULL) { 695 if (sbuf->m != NULL) { 696 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 697 m_freem(sbuf->m); 698 } 699 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 700 } 701 } 702 703 } 704 705 static int 706 ipw_media_change(struct ifnet *ifp) 707 { 708 int error; 709 710 error = ieee80211_media_change(ifp); 711 if (error != ENETRESET) 712 return error; 713 714 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 715 ipw_init(ifp); 716 717 return 0; 718 } 719 720 /* 721 * The firmware automatically adapts the transmit speed. We report the current 722 * transmit speed here. 723 */ 724 static void 725 ipw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 726 { 727 #define N(a) (sizeof (a) / sizeof (a[0])) 728 struct ipw_softc *sc = ifp->if_softc; 729 struct ieee80211com *ic = &sc->sc_ic; 730 static const struct { 731 uint32_t val; 732 int rate; 733 } rates[] = { 734 { IPW_RATE_DS1, 2 }, 735 { IPW_RATE_DS2, 4 }, 736 { IPW_RATE_DS5, 11 }, 737 { IPW_RATE_DS11, 22 }, 738 }; 739 uint32_t val; 740 int rate, i; 741 742 imr->ifm_status = IFM_AVALID; 743 imr->ifm_active = IFM_IEEE80211; 744 if (ic->ic_state == IEEE80211_S_RUN) 745 imr->ifm_status |= IFM_ACTIVE; 746 747 /* read current transmission rate from adapter */ 748 val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE) & 0xf; 749 750 /* convert ipw rate to 802.11 rate */ 751 for (i = 0; i < N(rates) && rates[i].val != val; i++); 752 rate = (i < N(rates)) ? rates[i].rate : 0; 753 754 imr->ifm_active |= IFM_IEEE80211_11B; 755 imr->ifm_active |= ieee80211_rate2media(ic, rate, IEEE80211_MODE_11B); 756 switch (ic->ic_opmode) { 757 case IEEE80211_M_STA: 758 break; 759 760 case IEEE80211_M_IBSS: 761 imr->ifm_active |= IFM_IEEE80211_ADHOC; 762 break; 763 764 case IEEE80211_M_MONITOR: 765 imr->ifm_active |= IFM_IEEE80211_MONITOR; 766 break; 767 768 case IEEE80211_M_AHDEMO: 769 case IEEE80211_M_HOSTAP: 770 /* should not get there */ 771 break; 772 } 773 #undef N 774 } 775 776 static int 777 ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, 778 int arg) 779 { 780 struct ifnet *ifp = ic->ic_ifp; 781 struct ipw_softc *sc = ifp->if_softc; 782 struct ieee80211_node *ni; 783 uint8_t macaddr[IEEE80211_ADDR_LEN]; 784 uint32_t len; 785 struct ipw_rx_radiotap_header *wr = &sc->sc_rxtap; 786 struct ipw_tx_radiotap_header *wt = &sc->sc_txtap; 787 788 switch (nstate) { 789 case IEEE80211_S_INIT: 790 break; 791 default: 792 KASSERT(ic->ic_curchan != IEEE80211_CHAN_ANYC); 793 KASSERT(ic->ic_curchan != NULL); 794 wt->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 795 wt->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 796 wr->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 797 wr->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 798 break; 799 } 800 801 switch (nstate) { 802 case IEEE80211_S_RUN: 803 DELAY(200); /* firmware needs a short delay here */ 804 805 len = IEEE80211_ADDR_LEN; 806 ipw_read_table2(sc, IPW_INFO_CURRENT_BSSID, macaddr, &len); 807 808 ni = ieee80211_find_node(&ic->ic_scan, macaddr); 809 if (ni == NULL) 810 break; 811 812 ieee80211_ref_node(ni); 813 ieee80211_sta_join(ic, ni); 814 ieee80211_node_authorize(ni); 815 816 if (ic->ic_opmode == IEEE80211_M_STA) 817 ieee80211_notify_node_join(ic, ni, 1); 818 break; 819 820 case IEEE80211_S_INIT: 821 case IEEE80211_S_SCAN: 822 case IEEE80211_S_AUTH: 823 case IEEE80211_S_ASSOC: 824 break; 825 } 826 827 ic->ic_state = nstate; 828 return 0; 829 } 830 831 /* 832 * Read 16 bits at address 'addr' from the serial EEPROM. 833 */ 834 static uint16_t 835 ipw_read_prom_word(struct ipw_softc *sc, uint8_t addr) 836 { 837 uint32_t tmp; 838 uint16_t val; 839 int n; 840 841 /* clock C once before the first command */ 842 IPW_EEPROM_CTL(sc, 0); 843 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 844 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 845 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 846 847 /* write start bit (1) */ 848 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 849 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 850 851 /* write READ opcode (10) */ 852 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 853 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 854 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 855 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 856 857 /* write address A7-A0 */ 858 for (n = 7; n >= 0; n--) { 859 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 860 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D)); 861 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 862 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D) | IPW_EEPROM_C); 863 } 864 865 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 866 867 /* read data Q15-Q0 */ 868 val = 0; 869 for (n = 15; n >= 0; n--) { 870 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 871 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 872 tmp = MEM_READ_4(sc, IPW_MEM_EEPROM_CTL); 873 val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n; 874 } 875 876 IPW_EEPROM_CTL(sc, 0); 877 878 /* clear Chip Select and clock C */ 879 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 880 IPW_EEPROM_CTL(sc, 0); 881 IPW_EEPROM_CTL(sc, IPW_EEPROM_C); 882 883 return le16toh(val); 884 } 885 886 static void 887 ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 888 { 889 struct ipw_cmd *cmd; 890 891 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof (struct ipw_cmd), 892 BUS_DMASYNC_POSTREAD); 893 894 cmd = mtod(sbuf->m, struct ipw_cmd *); 895 896 DPRINTFN(2, ("cmd ack'ed (%u, %u, %u, %u, %u)\n", le32toh(cmd->type), 897 le32toh(cmd->subtype), le32toh(cmd->seq), le32toh(cmd->len), 898 le32toh(cmd->status))); 899 900 wakeup(&sc->cmd); 901 } 902 903 static void 904 ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 905 { 906 struct ieee80211com *ic = &sc->sc_ic; 907 struct ifnet *ifp = sc->sc_ic.ic_ifp; 908 uint32_t state; 909 910 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof state, 911 BUS_DMASYNC_POSTREAD); 912 913 state = le32toh(*mtod(sbuf->m, uint32_t *)); 914 915 DPRINTFN(2, ("entering state %u\n", state)); 916 917 switch (state) { 918 case IPW_STATE_ASSOCIATED: 919 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 920 break; 921 922 case IPW_STATE_SCANNING: 923 /* don't leave run state on background scan */ 924 if (ic->ic_state != IEEE80211_S_RUN) 925 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 926 927 ic->ic_flags |= IEEE80211_F_SCAN; 928 break; 929 930 case IPW_STATE_SCAN_COMPLETE: 931 ieee80211_notify_scan_done(ic); 932 ic->ic_flags &= ~IEEE80211_F_SCAN; 933 break; 934 935 case IPW_STATE_ASSOCIATION_LOST: 936 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 937 break; 938 939 case IPW_STATE_RADIO_DISABLED: 940 ic->ic_ifp->if_flags &= ~IFF_UP; 941 ipw_stop(ifp, 1); 942 break; 943 } 944 } 945 946 /* 947 * XXX: Hack to set the current channel to the value advertised in beacons or 948 * probe responses. Only used during AP detection. 949 */ 950 static void 951 ipw_fix_channel(struct ieee80211com *ic, struct mbuf *m) 952 { 953 struct ieee80211_frame *wh; 954 uint8_t subtype; 955 uint8_t *frm, *efrm; 956 957 wh = mtod(m, struct ieee80211_frame *); 958 959 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_MGT) 960 return; 961 962 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 963 964 if (subtype != IEEE80211_FC0_SUBTYPE_BEACON && 965 subtype != IEEE80211_FC0_SUBTYPE_PROBE_RESP) 966 return; 967 968 frm = (uint8_t *)(wh + 1); 969 efrm = mtod(m, uint8_t *) + m->m_len; 970 971 frm += 12; /* skip tstamp, bintval and capinfo fields */ 972 while (frm < efrm) { 973 if (*frm == IEEE80211_ELEMID_DSPARMS) 974 #if IEEE80211_CHAN_MAX < 255 975 if (frm[2] <= IEEE80211_CHAN_MAX) 976 #endif 977 ic->ic_curchan = &ic->ic_channels[frm[2]]; 978 979 frm += frm[1] + 2; 980 } 981 } 982 983 static void 984 ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 985 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 986 { 987 struct ieee80211com *ic = &sc->sc_ic; 988 struct ifnet *ifp = &sc->sc_if; 989 struct mbuf *mnew, *m; 990 struct ieee80211_frame *wh; 991 struct ieee80211_node *ni; 992 int error; 993 994 DPRINTFN(5, ("received frame len=%u, rssi=%u\n", le32toh(status->len), 995 status->rssi)); 996 997 if (le32toh(status->len) < sizeof (struct ieee80211_frame_min) || 998 le32toh(status->len) > MCLBYTES) 999 return; 1000 1001 /* 1002 * Try to allocate a new mbuf for this ring element and load it before 1003 * processing the current mbuf. If the ring element cannot be loaded, 1004 * drop the received packet and reuse the old mbuf. In the unlikely 1005 * case that the old mbuf can't be reloaded either, explicitly panic. 1006 */ 1007 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1008 if (mnew == NULL) { 1009 aprint_error_dev(sc->sc_dev, "could not allocate rx mbuf\n"); 1010 ifp->if_ierrors++; 1011 return; 1012 } 1013 1014 MCLGET(mnew, M_DONTWAIT); 1015 if (!(mnew->m_flags & M_EXT)) { 1016 aprint_error_dev(sc->sc_dev, "could not allocate rx mbuf cluster\n"); 1017 m_freem(mnew); 1018 ifp->if_ierrors++; 1019 return; 1020 } 1021 1022 mnew->m_pkthdr.len = mnew->m_len = mnew->m_ext.ext_size; 1023 1024 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, le32toh(status->len), 1025 BUS_DMASYNC_POSTREAD); 1026 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1027 1028 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, mnew, 1029 BUS_DMA_READ | BUS_DMA_NOWAIT); 1030 if (error != 0) { 1031 aprint_error_dev(sc->sc_dev, "could not load rx buf DMA map\n"); 1032 m_freem(mnew); 1033 1034 /* try to reload the old mbuf */ 1035 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, 1036 sbuf->m, BUS_DMA_READ | BUS_DMA_NOWAIT); 1037 if (error != 0) { 1038 /* very unlikely that it will fail... */ 1039 panic("%s: unable to remap rx buf", 1040 device_xname(sc->sc_dev)); 1041 } 1042 ifp->if_ierrors++; 1043 return; 1044 } 1045 1046 /* 1047 * New mbuf successfully loaded, update Rx ring and continue 1048 * processing. 1049 */ 1050 m = sbuf->m; 1051 sbuf->m = mnew; 1052 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 1053 1054 /* finalize mbuf */ 1055 m->m_pkthdr.rcvif = ifp; 1056 m->m_pkthdr.len = m->m_len = le32toh(status->len); 1057 1058 if (sc->sc_drvbpf != NULL) { 1059 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 1060 1061 tap->wr_antsignal = status->rssi; 1062 1063 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 1064 } 1065 1066 if (ic->ic_state == IEEE80211_S_SCAN) 1067 ipw_fix_channel(ic, m); 1068 1069 wh = mtod(m, struct ieee80211_frame *); 1070 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 1071 1072 /* send the frame to the 802.11 layer */ 1073 ieee80211_input(ic, m, ni, status->rssi, 0); 1074 1075 /* node is no longer needed */ 1076 ieee80211_free_node(ni); 1077 1078 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, 1079 sbuf->map->dm_mapsize, BUS_DMASYNC_PREREAD); 1080 } 1081 1082 static void 1083 ipw_rx_intr(struct ipw_softc *sc) 1084 { 1085 struct ipw_status *status; 1086 struct ipw_soft_bd *sbd; 1087 struct ipw_soft_buf *sbuf; 1088 uint32_t r, i; 1089 1090 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1091 return; 1092 1093 r = CSR_READ_4(sc, IPW_CSR_RX_READ); 1094 1095 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 1096 1097 /* firmware was killed, stop processing received frames */ 1098 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1099 return; 1100 1101 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 1102 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1103 BUS_DMASYNC_POSTREAD); 1104 1105 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 1106 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 1107 BUS_DMASYNC_POSTREAD); 1108 1109 status = &sc->status_list[i]; 1110 sbd = &sc->srbd_list[i]; 1111 sbuf = sbd->priv; 1112 1113 switch (le16toh(status->code) & 0xf) { 1114 case IPW_STATUS_CODE_COMMAND: 1115 ipw_command_intr(sc, sbuf); 1116 break; 1117 1118 case IPW_STATUS_CODE_NEWSTATE: 1119 ipw_newstate_intr(sc, sbuf); 1120 break; 1121 1122 case IPW_STATUS_CODE_DATA_802_3: 1123 case IPW_STATUS_CODE_DATA_802_11: 1124 ipw_data_intr(sc, status, sbd, sbuf); 1125 break; 1126 1127 case IPW_STATUS_CODE_NOTIFICATION: 1128 DPRINTFN(2, ("received notification\n")); 1129 break; 1130 1131 default: 1132 aprint_error_dev(sc->sc_dev, "unknown status code %u\n", 1133 le16toh(status->code)); 1134 } 1135 1136 sbd->bd->flags = 0; 1137 1138 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 1139 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1140 BUS_DMASYNC_PREREAD); 1141 1142 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 1143 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 1144 BUS_DMASYNC_PREREAD); 1145 } 1146 1147 /* Tell the firmware what we have processed */ 1148 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 1149 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 1150 } 1151 1152 static void 1153 ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 1154 { 1155 struct ieee80211com *ic; 1156 struct ipw_soft_hdr *shdr; 1157 struct ipw_soft_buf *sbuf; 1158 1159 switch (sbd->type) { 1160 case IPW_SBD_TYPE_COMMAND: 1161 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 1162 0, sizeof(struct ipw_cmd), BUS_DMASYNC_POSTWRITE); 1163 /* bus_dmamap_unload(sc->sc_dmat, sc->cmd_map); */ 1164 break; 1165 1166 case IPW_SBD_TYPE_HEADER: 1167 shdr = sbd->priv; 1168 bus_dmamap_sync(sc->sc_dmat, sc->hdr_map, 1169 shdr->offset, sizeof(struct ipw_hdr), BUS_DMASYNC_POSTWRITE); 1170 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 1171 break; 1172 1173 case IPW_SBD_TYPE_DATA: 1174 ic = &sc->sc_ic; 1175 sbuf = sbd->priv; 1176 1177 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 1178 0, MCLBYTES, BUS_DMASYNC_POSTWRITE); 1179 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1180 m_freem(sbuf->m); 1181 if (sbuf->ni != NULL) 1182 ieee80211_free_node(sbuf->ni); 1183 /* kill watchdog timer */ 1184 sc->sc_tx_timer = 0; 1185 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 1186 break; 1187 } 1188 sbd->type = IPW_SBD_TYPE_NOASSOC; 1189 } 1190 1191 static void 1192 ipw_tx_intr(struct ipw_softc *sc) 1193 { 1194 struct ifnet *ifp = &sc->sc_if; 1195 struct ipw_soft_bd *sbd; 1196 uint32_t r, i; 1197 1198 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1199 return; 1200 1201 r = CSR_READ_4(sc, IPW_CSR_TX_READ); 1202 1203 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) { 1204 sbd = &sc->stbd_list[i]; 1205 1206 if (sbd->type == IPW_SBD_TYPE_DATA) 1207 ifp->if_opackets++; 1208 1209 ipw_release_sbd(sc, sbd); 1210 sc->txfree++; 1211 } 1212 1213 /* remember what the firmware has processed */ 1214 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 1215 1216 /* Call start() since some buffer descriptors have been released */ 1217 ifp->if_flags &= ~IFF_OACTIVE; 1218 (*ifp->if_start)(ifp); 1219 } 1220 1221 static int 1222 ipw_intr(void *arg) 1223 { 1224 struct ipw_softc *sc = arg; 1225 uint32_t r; 1226 1227 r = CSR_READ_4(sc, IPW_CSR_INTR); 1228 if (r == 0 || r == 0xffffffff) 1229 return 0; 1230 1231 /* Disable interrupts */ 1232 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1233 1234 if (r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR)) { 1235 aprint_error_dev(sc->sc_dev, "fatal error\n"); 1236 sc->sc_ic.ic_ifp->if_flags &= ~IFF_UP; 1237 ipw_stop(&sc->sc_if, 1); 1238 } 1239 1240 if (r & IPW_INTR_FW_INIT_DONE) { 1241 if (!(r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR))) 1242 wakeup(sc); 1243 } 1244 1245 if (r & IPW_INTR_RX_TRANSFER) 1246 ipw_rx_intr(sc); 1247 1248 if (r & IPW_INTR_TX_TRANSFER) 1249 ipw_tx_intr(sc); 1250 1251 /* Acknowledge all interrupts */ 1252 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 1253 1254 /* Re-enable interrupts */ 1255 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1256 1257 return 0; 1258 } 1259 1260 /* 1261 * Send a command to the firmware and wait for the acknowledgement. 1262 */ 1263 static int 1264 ipw_cmd(struct ipw_softc *sc, uint32_t type, void *data, uint32_t len) 1265 { 1266 struct ipw_soft_bd *sbd; 1267 1268 sbd = &sc->stbd_list[sc->txcur]; 1269 1270 sc->cmd.type = htole32(type); 1271 sc->cmd.subtype = 0; 1272 sc->cmd.len = htole32(len); 1273 sc->cmd.seq = 0; 1274 1275 (void)memcpy(sc->cmd.data, data, len); 1276 1277 sbd->type = IPW_SBD_TYPE_COMMAND; 1278 sbd->bd->physaddr = htole32(sc->cmd_map->dm_segs[0].ds_addr); 1279 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 1280 sbd->bd->nfrag = 1; 1281 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 1282 IPW_BD_FLAG_TX_LAST_FRAGMENT; 1283 1284 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 0, sizeof (struct ipw_cmd), 1285 BUS_DMASYNC_PREWRITE); 1286 1287 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1288 sc->txcur * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1289 BUS_DMASYNC_PREWRITE); 1290 1291 DPRINTFN(2, ("sending command (%u, %u, %u, %u)\n", type, 0, 0, len)); 1292 1293 /* kick firmware */ 1294 sc->txfree--; 1295 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1296 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1297 1298 /* Wait at most one second for command to complete */ 1299 return tsleep(&sc->cmd, 0, "ipwcmd", hz); 1300 } 1301 1302 static int 1303 ipw_tx_start(struct ifnet *ifp, struct mbuf *m0, struct ieee80211_node *ni) 1304 { 1305 struct ipw_softc *sc = ifp->if_softc; 1306 struct ieee80211com *ic = &sc->sc_ic; 1307 struct ieee80211_frame *wh; 1308 struct ipw_soft_bd *sbd; 1309 struct ipw_soft_hdr *shdr; 1310 struct ipw_soft_buf *sbuf; 1311 struct ieee80211_key *k; 1312 struct mbuf *mnew; 1313 int error, i; 1314 1315 wh = mtod(m0, struct ieee80211_frame *); 1316 1317 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1318 k = ieee80211_crypto_encap(ic, ni, m0); 1319 if (k == NULL) { 1320 m_freem(m0); 1321 return ENOBUFS; 1322 } 1323 1324 /* packet header may have moved, reset our local pointer */ 1325 wh = mtod(m0, struct ieee80211_frame *); 1326 } 1327 1328 if (sc->sc_drvbpf != NULL) { 1329 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 1330 1331 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 1332 } 1333 1334 shdr = TAILQ_FIRST(&sc->sc_free_shdr); 1335 sbuf = TAILQ_FIRST(&sc->sc_free_sbuf); 1336 KASSERT(shdr != NULL && sbuf != NULL); 1337 1338 shdr->hdr->type = htole32(IPW_HDR_TYPE_SEND); 1339 shdr->hdr->subtype = 0; 1340 shdr->hdr->encrypted = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0; 1341 shdr->hdr->encrypt = 0; 1342 shdr->hdr->keyidx = 0; 1343 shdr->hdr->keysz = 0; 1344 shdr->hdr->fragmentsz = 0; 1345 IEEE80211_ADDR_COPY(shdr->hdr->src_addr, wh->i_addr2); 1346 if (ic->ic_opmode == IEEE80211_M_STA) 1347 IEEE80211_ADDR_COPY(shdr->hdr->dst_addr, wh->i_addr3); 1348 else 1349 IEEE80211_ADDR_COPY(shdr->hdr->dst_addr, wh->i_addr1); 1350 1351 /* trim IEEE802.11 header */ 1352 m_adj(m0, sizeof (struct ieee80211_frame)); 1353 1354 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m0, BUS_DMA_NOWAIT); 1355 if (error != 0 && error != EFBIG) { 1356 aprint_error_dev(sc->sc_dev, "could not map mbuf (error %d)\n", 1357 error); 1358 m_freem(m0); 1359 return error; 1360 } 1361 1362 if (error != 0) { 1363 /* too many fragments, linearize */ 1364 1365 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1366 if (mnew == NULL) { 1367 m_freem(m0); 1368 return ENOMEM; 1369 } 1370 1371 M_COPY_PKTHDR(mnew, m0); 1372 1373 /* If the data won't fit in the header, get a cluster */ 1374 if (m0->m_pkthdr.len > MHLEN) { 1375 MCLGET(mnew, M_DONTWAIT); 1376 if (!(mnew->m_flags & M_EXT)) { 1377 m_freem(m0); 1378 m_freem(mnew); 1379 return ENOMEM; 1380 } 1381 } 1382 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(mnew, void *)); 1383 m_freem(m0); 1384 mnew->m_len = mnew->m_pkthdr.len; 1385 m0 = mnew; 1386 1387 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m0, 1388 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1389 if (error != 0) { 1390 aprint_error_dev(sc->sc_dev, "could not map mbuf (error %d)\n", error); 1391 m_freem(m0); 1392 return error; 1393 } 1394 } 1395 1396 TAILQ_REMOVE(&sc->sc_free_sbuf, sbuf, next); 1397 TAILQ_REMOVE(&sc->sc_free_shdr, shdr, next); 1398 1399 sbd = &sc->stbd_list[sc->txcur]; 1400 sbd->type = IPW_SBD_TYPE_HEADER; 1401 sbd->priv = shdr; 1402 sbd->bd->physaddr = htole32(shdr->addr); 1403 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 1404 sbd->bd->nfrag = 1 + sbuf->map->dm_nsegs; 1405 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 1406 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1407 1408 DPRINTFN(5, ("sending tx hdr (%u, %u, %u, %u, )\n", 1409 shdr->hdr->type, shdr->hdr->subtype, shdr->hdr->encrypted, 1410 shdr->hdr->encrypt)); 1411 DPRINTFN(5, ("%s->", ether_sprintf(shdr->hdr->src_addr))); 1412 DPRINTFN(5, ("%s\n", ether_sprintf(shdr->hdr->dst_addr))); 1413 1414 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1415 sc->txcur * sizeof (struct ipw_bd), 1416 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1417 1418 sc->txfree--; 1419 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1420 1421 sbuf->m = m0; 1422 sbuf->ni = ni; 1423 1424 for (i = 0; i < sbuf->map->dm_nsegs; i++) { 1425 sbd = &sc->stbd_list[sc->txcur]; 1426 1427 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[i].ds_addr); 1428 sbd->bd->len = htole32(sbuf->map->dm_segs[i].ds_len); 1429 sbd->bd->nfrag = 0; 1430 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 1431 if (i == sbuf->map->dm_nsegs - 1) { 1432 sbd->type = IPW_SBD_TYPE_DATA; 1433 sbd->priv = sbuf; 1434 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 1435 } else { 1436 sbd->type = IPW_SBD_TYPE_NOASSOC; 1437 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1438 } 1439 1440 DPRINTFN(5, ("sending fragment (%d, %d)\n", i, 1441 (int)sbuf->map->dm_segs[i].ds_len)); 1442 1443 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1444 sc->txcur * sizeof (struct ipw_bd), 1445 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1446 1447 sc->txfree--; 1448 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1449 } 1450 1451 bus_dmamap_sync(sc->sc_dmat, sc->hdr_map, shdr->offset, 1452 sizeof (struct ipw_hdr), BUS_DMASYNC_PREWRITE); 1453 1454 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, MCLBYTES, 1455 BUS_DMASYNC_PREWRITE); 1456 1457 /* Inform firmware about this new packet */ 1458 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1459 1460 return 0; 1461 } 1462 1463 static void 1464 ipw_start(struct ifnet *ifp) 1465 { 1466 struct ipw_softc *sc = ifp->if_softc; 1467 struct ieee80211com *ic = &sc->sc_ic; 1468 struct mbuf *m0; 1469 struct ether_header *eh; 1470 struct ieee80211_node *ni; 1471 1472 1473 if (ic->ic_state != IEEE80211_S_RUN) 1474 return; 1475 1476 for (;;) { 1477 IF_DEQUEUE(&ifp->if_snd, m0); 1478 if (m0 == NULL) 1479 break; 1480 1481 if (sc->txfree < 1 + IPW_MAX_NSEG) { 1482 IF_PREPEND(&ifp->if_snd, m0); 1483 ifp->if_flags |= IFF_OACTIVE; 1484 break; 1485 } 1486 1487 if (m0->m_len < sizeof (struct ether_header) && 1488 (m0 = m_pullup(m0, sizeof (struct ether_header))) == NULL) 1489 continue; 1490 1491 eh = mtod(m0, struct ether_header *); 1492 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1493 if (ni == NULL) { 1494 m_freem(m0); 1495 continue; 1496 } 1497 1498 bpf_mtap(ifp, m0); 1499 1500 m0 = ieee80211_encap(ic, m0, ni); 1501 if (m0 == NULL) { 1502 ieee80211_free_node(ni); 1503 continue; 1504 } 1505 1506 bpf_mtap3(ic->ic_rawbpf, m0); 1507 1508 if (ipw_tx_start(ifp, m0, ni) != 0) { 1509 ieee80211_free_node(ni); 1510 ifp->if_oerrors++; 1511 break; 1512 } 1513 1514 /* start watchdog timer */ 1515 sc->sc_tx_timer = 5; 1516 ifp->if_timer = 1; 1517 } 1518 } 1519 1520 static void 1521 ipw_watchdog(struct ifnet *ifp) 1522 { 1523 struct ipw_softc *sc = ifp->if_softc; 1524 1525 ifp->if_timer = 0; 1526 1527 if (sc->sc_tx_timer > 0) { 1528 if (--sc->sc_tx_timer == 0) { 1529 aprint_error_dev(sc->sc_dev, "device timeout\n"); 1530 ifp->if_oerrors++; 1531 ifp->if_flags &= ~IFF_UP; 1532 ipw_stop(ifp, 1); 1533 return; 1534 } 1535 ifp->if_timer = 1; 1536 } 1537 1538 ieee80211_watchdog(&sc->sc_ic); 1539 } 1540 1541 static int 1542 ipw_get_table1(struct ipw_softc *sc, uint32_t *tbl) 1543 { 1544 uint32_t addr, size, i; 1545 1546 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1547 return ENOTTY; 1548 1549 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, sc->table1_base); 1550 1551 size = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 1552 if (suword(tbl, size) != 0) 1553 return EFAULT; 1554 1555 for (i = 1, ++tbl; i < size; i++, tbl++) { 1556 addr = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 1557 if (suword(tbl, MEM_READ_4(sc, addr)) != 0) 1558 return EFAULT; 1559 } 1560 return 0; 1561 } 1562 1563 static int 1564 ipw_get_radio(struct ipw_softc *sc, int *ret) 1565 { 1566 uint32_t addr; 1567 1568 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1569 return ENOTTY; 1570 1571 addr = ipw_read_table1(sc, IPW_INFO_EEPROM_ADDRESS); 1572 if ((MEM_READ_4(sc, addr + 32) >> 24) & 1) { 1573 suword(ret, -1); 1574 return 0; 1575 } 1576 1577 if (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED) 1578 suword(ret, 0); 1579 else 1580 suword(ret, 1); 1581 1582 return 0; 1583 } 1584 1585 static int 1586 ipw_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1587 { 1588 #define IS_RUNNING(ifp) \ 1589 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 1590 1591 struct ipw_softc *sc = ifp->if_softc; 1592 struct ieee80211com *ic = &sc->sc_ic; 1593 struct ifreq *ifr = (struct ifreq *)data; 1594 int s, error = 0; 1595 1596 s = splnet(); 1597 1598 switch (cmd) { 1599 case SIOCSIFFLAGS: 1600 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 1601 break; 1602 if (ifp->if_flags & IFF_UP) { 1603 if (!(ifp->if_flags & IFF_RUNNING)) 1604 ipw_init(ifp); 1605 } else { 1606 if (ifp->if_flags & IFF_RUNNING) 1607 ipw_stop(ifp, 1); 1608 } 1609 break; 1610 1611 case SIOCADDMULTI: 1612 case SIOCDELMULTI: 1613 /* XXX no h/w multicast filter? --dyoung */ 1614 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1615 /* setup multicast filter, etc */ 1616 error = 0; 1617 } 1618 break; 1619 1620 case SIOCGTABLE1: 1621 error = ipw_get_table1(sc, (uint32_t *)ifr->ifr_data); 1622 break; 1623 1624 case SIOCGRADIO: 1625 error = ipw_get_radio(sc, (int *)ifr->ifr_data); 1626 break; 1627 1628 case SIOCSIFMEDIA: 1629 if (ifr->ifr_media & IFM_IEEE80211_ADHOC) 1630 sc->sc_fwname = "ipw2100-1.2-i.fw"; 1631 else if (ifr->ifr_media & IFM_IEEE80211_MONITOR) 1632 sc->sc_fwname = "ipw2100-1.2-p.fw"; 1633 else 1634 sc->sc_fwname = "ipw2100-1.2.fw"; 1635 1636 ipw_free_firmware(sc); 1637 /* FALLTRHOUGH */ 1638 default: 1639 error = ieee80211_ioctl(&sc->sc_ic, cmd, data); 1640 if (error != ENETRESET) 1641 break; 1642 1643 if (error == ENETRESET) { 1644 if (IS_RUNNING(ifp) && 1645 (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)) 1646 ipw_init(ifp); 1647 error = 0; 1648 } 1649 1650 } 1651 1652 splx(s); 1653 return error; 1654 #undef IS_RUNNING 1655 } 1656 1657 static uint32_t 1658 ipw_read_table1(struct ipw_softc *sc, uint32_t off) 1659 { 1660 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 1661 } 1662 1663 static void 1664 ipw_write_table1(struct ipw_softc *sc, uint32_t off, uint32_t info) 1665 { 1666 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 1667 } 1668 1669 static int 1670 ipw_read_table2(struct ipw_softc *sc, uint32_t off, void *buf, uint32_t *len) 1671 { 1672 uint32_t addr, info; 1673 uint16_t count, size; 1674 uint32_t total; 1675 1676 /* addr[4] + count[2] + size[2] */ 1677 addr = MEM_READ_4(sc, sc->table2_base + off); 1678 info = MEM_READ_4(sc, sc->table2_base + off + 4); 1679 1680 count = info >> 16; 1681 size = info & 0xffff; 1682 total = count * size; 1683 1684 if (total > *len) { 1685 *len = total; 1686 return EINVAL; 1687 } 1688 1689 *len = total; 1690 ipw_read_mem_1(sc, addr, buf, total); 1691 1692 return 0; 1693 } 1694 1695 static void 1696 ipw_stop_master(struct ipw_softc *sc) 1697 { 1698 int ntries; 1699 1700 /* disable interrupts */ 1701 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1702 1703 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1704 for (ntries = 0; ntries < 50; ntries++) { 1705 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1706 break; 1707 DELAY(10); 1708 } 1709 if (ntries == 50) 1710 aprint_error_dev(sc->sc_dev, "timeout waiting for master\n"); 1711 1712 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1713 IPW_RST_PRINCETON_RESET); 1714 1715 sc->flags &= ~IPW_FLAG_FW_INITED; 1716 } 1717 1718 static int 1719 ipw_reset(struct ipw_softc *sc) 1720 { 1721 int ntries; 1722 1723 ipw_stop_master(sc); 1724 1725 /* move adapter to D0 state */ 1726 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1727 IPW_CTL_INIT); 1728 1729 /* wait for clock stabilization */ 1730 for (ntries = 0; ntries < 1000; ntries++) { 1731 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY) 1732 break; 1733 DELAY(200); 1734 } 1735 if (ntries == 1000) 1736 return EIO; 1737 1738 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1739 IPW_RST_SW_RESET); 1740 1741 DELAY(10); 1742 1743 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1744 IPW_CTL_INIT); 1745 1746 return 0; 1747 } 1748 1749 /* 1750 * Upload the microcode to the device. 1751 */ 1752 static int 1753 ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size) 1754 { 1755 int ntries; 1756 1757 MEM_WRITE_4(sc, 0x3000e0, 0x80000000); 1758 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1759 1760 MEM_WRITE_2(sc, 0x220000, 0x0703); 1761 MEM_WRITE_2(sc, 0x220000, 0x0707); 1762 1763 MEM_WRITE_1(sc, 0x210014, 0x72); 1764 MEM_WRITE_1(sc, 0x210014, 0x72); 1765 1766 MEM_WRITE_1(sc, 0x210000, 0x40); 1767 MEM_WRITE_1(sc, 0x210000, 0x00); 1768 MEM_WRITE_1(sc, 0x210000, 0x40); 1769 1770 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1771 1772 MEM_WRITE_1(sc, 0x210000, 0x00); 1773 MEM_WRITE_1(sc, 0x210000, 0x00); 1774 MEM_WRITE_1(sc, 0x210000, 0x80); 1775 1776 MEM_WRITE_2(sc, 0x220000, 0x0703); 1777 MEM_WRITE_2(sc, 0x220000, 0x0707); 1778 1779 MEM_WRITE_1(sc, 0x210014, 0x72); 1780 MEM_WRITE_1(sc, 0x210014, 0x72); 1781 1782 MEM_WRITE_1(sc, 0x210000, 0x00); 1783 MEM_WRITE_1(sc, 0x210000, 0x80); 1784 1785 for (ntries = 0; ntries < 10; ntries++) { 1786 if (MEM_READ_1(sc, 0x210000) & 1) 1787 break; 1788 DELAY(10); 1789 } 1790 if (ntries == 10) { 1791 aprint_error_dev(sc->sc_dev, "timeout waiting for ucode to initialize\n"); 1792 return EIO; 1793 } 1794 1795 MEM_WRITE_4(sc, 0x3000e0, 0); 1796 1797 return 0; 1798 } 1799 1800 /* set of macros to handle unaligned little endian data in firmware image */ 1801 #define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1802 #define GETLE16(p) ((p)[0] | (p)[1] << 8) 1803 static int 1804 ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size) 1805 { 1806 u_char *p, *end; 1807 uint32_t dst; 1808 uint16_t len; 1809 int error; 1810 1811 p = fw; 1812 end = fw + size; 1813 while (p < end) { 1814 dst = GETLE32(p); p += 4; 1815 len = GETLE16(p); p += 2; 1816 1817 ipw_write_mem_1(sc, dst, p, len); 1818 p += len; 1819 } 1820 1821 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1822 IPW_IO_LED_OFF); 1823 1824 /* enable interrupts */ 1825 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1826 1827 /* kick the firmware */ 1828 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1829 1830 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1831 IPW_CTL_ALLOW_STANDBY); 1832 1833 /* wait at most one second for firmware initialization to complete */ 1834 if ((error = tsleep(sc, 0, "ipwinit", hz)) != 0) { 1835 aprint_error_dev(sc->sc_dev, "timeout waiting for firmware initialization " 1836 "to complete\n"); 1837 return error; 1838 } 1839 1840 CSR_WRITE_4(sc, IPW_CSR_IO, CSR_READ_4(sc, IPW_CSR_IO) | 1841 IPW_IO_GPIO1_MASK | IPW_IO_GPIO3_MASK); 1842 1843 return 0; 1844 } 1845 1846 /* 1847 * Store firmware into kernel memory so we can download it when we need to, 1848 * e.g when the adapter wakes up from suspend mode. 1849 */ 1850 static int 1851 ipw_cache_firmware(struct ipw_softc *sc) 1852 { 1853 struct ipw_firmware *fw = &sc->fw; 1854 struct ipw_firmware_hdr hdr; 1855 firmware_handle_t fwh; 1856 off_t fwsz, p; 1857 int error; 1858 1859 ipw_free_firmware(sc); 1860 1861 if (ipw_accept_eula == 0) { 1862 aprint_error_dev(sc->sc_dev, 1863 "EULA not accepted; please see the ipw(4) man page.\n"); 1864 return EPERM; 1865 } 1866 1867 if ((error = firmware_open("if_ipw", sc->sc_fwname, &fwh)) != 0) 1868 goto fail0; 1869 1870 fwsz = firmware_get_size(fwh); 1871 1872 if (fwsz < sizeof(hdr)) 1873 goto fail2; 1874 1875 if ((error = firmware_read(fwh, 0, &hdr, sizeof(hdr))) != 0) 1876 goto fail2; 1877 1878 fw->main_size = le32toh(hdr.main_size); 1879 fw->ucode_size = le32toh(hdr.ucode_size); 1880 1881 fw->main = firmware_malloc(fw->main_size); 1882 if (fw->main == NULL) { 1883 error = ENOMEM; 1884 goto fail1; 1885 } 1886 1887 fw->ucode = firmware_malloc(fw->ucode_size); 1888 if (fw->ucode == NULL) { 1889 error = ENOMEM; 1890 goto fail2; 1891 } 1892 1893 p = sizeof(hdr); 1894 if ((error = firmware_read(fwh, p, fw->main, fw->main_size)) != 0) 1895 goto fail3; 1896 1897 p += fw->main_size; 1898 if ((error = firmware_read(fwh, p, fw->ucode, fw->ucode_size)) != 0) 1899 goto fail3; 1900 1901 DPRINTF(("Firmware cached: main %u, ucode %u\n", fw->main_size, 1902 fw->ucode_size)); 1903 1904 sc->flags |= IPW_FLAG_FW_CACHED; 1905 1906 firmware_close(fwh); 1907 1908 return 0; 1909 1910 fail3: firmware_free(fw->ucode, 0); 1911 fail2: firmware_free(fw->main, 0); 1912 fail1: firmware_close(fwh); 1913 fail0: 1914 return error; 1915 } 1916 1917 static void 1918 ipw_free_firmware(struct ipw_softc *sc) 1919 { 1920 if (!(sc->flags & IPW_FLAG_FW_CACHED)) 1921 return; 1922 1923 firmware_free(sc->fw.main, 0); 1924 firmware_free(sc->fw.ucode, 0); 1925 1926 sc->flags &= ~IPW_FLAG_FW_CACHED; 1927 } 1928 1929 static int 1930 ipw_config(struct ipw_softc *sc) 1931 { 1932 struct ieee80211com *ic = &sc->sc_ic; 1933 struct ifnet *ifp = &sc->sc_if; 1934 struct ipw_security security; 1935 struct ieee80211_key *k; 1936 struct ipw_wep_key wepkey; 1937 struct ipw_scan_options options; 1938 struct ipw_configuration config; 1939 uint32_t data; 1940 int error, i; 1941 1942 switch (ic->ic_opmode) { 1943 case IEEE80211_M_STA: 1944 case IEEE80211_M_HOSTAP: 1945 data = htole32(IPW_MODE_BSS); 1946 break; 1947 1948 case IEEE80211_M_IBSS: 1949 case IEEE80211_M_AHDEMO: 1950 data = htole32(IPW_MODE_IBSS); 1951 break; 1952 1953 case IEEE80211_M_MONITOR: 1954 data = htole32(IPW_MODE_MONITOR); 1955 break; 1956 } 1957 DPRINTF(("Setting mode to %u\n", le32toh(data))); 1958 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 1959 if (error != 0) 1960 return error; 1961 1962 if (ic->ic_opmode == IEEE80211_M_IBSS || 1963 ic->ic_opmode == IEEE80211_M_MONITOR) { 1964 data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); 1965 DPRINTF(("Setting channel to %u\n", le32toh(data))); 1966 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 1967 if (error != 0) 1968 return error; 1969 } 1970 1971 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1972 DPRINTF(("Enabling adapter\n")); 1973 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1974 } 1975 1976 DPRINTF(("Setting MAC to %s\n", ether_sprintf(ic->ic_myaddr))); 1977 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 1978 IEEE80211_ADDR_LEN); 1979 if (error != 0) 1980 return error; 1981 1982 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 1983 IPW_CFG_PREAMBLE_AUTO | IPW_CFG_802_1x_ENABLE); 1984 1985 if (ic->ic_opmode == IEEE80211_M_IBSS) 1986 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 1987 if (ifp->if_flags & IFF_PROMISC) 1988 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 1989 config.bss_chan = htole32(0x3fff); /* channels 1-14 */ 1990 config.ibss_chan = htole32(0x7ff); /* channels 1-11 */ 1991 DPRINTF(("Setting adapter configuration 0x%08x\n", config.flags)); 1992 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 1993 if (error != 0) 1994 return error; 1995 1996 data = htole32(0x3); /* 1, 2 */ 1997 DPRINTF(("Setting basic tx rates to 0x%x\n", le32toh(data))); 1998 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 1999 if (error != 0) 2000 return error; 2001 2002 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 2003 DPRINTF(("Setting tx rates to 0x%x\n", le32toh(data))); 2004 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 2005 if (error != 0) 2006 return error; 2007 2008 data = htole32(IPW_POWER_MODE_CAM); 2009 DPRINTF(("Setting power mode to %u\n", le32toh(data))); 2010 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 2011 if (error != 0) 2012 return error; 2013 2014 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2015 data = htole32(32); /* default value */ 2016 DPRINTF(("Setting tx power index to %u\n", le32toh(data))); 2017 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 2018 sizeof data); 2019 if (error != 0) 2020 return error; 2021 } 2022 2023 data = htole32(ic->ic_rtsthreshold); 2024 DPRINTF(("Setting RTS threshold to %u\n", le32toh(data))); 2025 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 2026 if (error != 0) 2027 return error; 2028 2029 data = htole32(ic->ic_fragthreshold); 2030 DPRINTF(("Setting frag threshold to %u\n", le32toh(data))); 2031 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 2032 if (error != 0) 2033 return error; 2034 2035 #ifdef IPW_DEBUG 2036 if (ipw_debug > 0) { 2037 printf("Setting ESSID to "); 2038 ieee80211_print_essid(ic->ic_des_essid, ic->ic_des_esslen); 2039 printf("\n"); 2040 } 2041 #endif 2042 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ic->ic_des_essid, 2043 ic->ic_des_esslen); 2044 if (error != 0) 2045 return error; 2046 2047 /* no mandatory BSSID */ 2048 DPRINTF(("Setting mandatory BSSID to null\n")); 2049 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 2050 if (error != 0) 2051 return error; 2052 2053 if (ic->ic_flags & IEEE80211_F_DESBSSID) { 2054 DPRINTF(("Setting desired BSSID to %s\n", 2055 ether_sprintf(ic->ic_des_bssid))); 2056 error = ipw_cmd(sc, IPW_CMD_SET_DESIRED_BSSID, 2057 ic->ic_des_bssid, IEEE80211_ADDR_LEN); 2058 if (error != 0) 2059 return error; 2060 } 2061 2062 (void)memset(&security, 0, sizeof(security)); 2063 security.authmode = (ic->ic_bss->ni_authmode == IEEE80211_AUTH_SHARED) ? 2064 IPW_AUTH_SHARED : IPW_AUTH_OPEN; 2065 security.ciphers = htole32(IPW_CIPHER_NONE); 2066 DPRINTF(("Setting authmode to %u\n", security.authmode)); 2067 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 2068 sizeof security); 2069 if (error != 0) 2070 return error; 2071 2072 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 2073 k = ic->ic_crypto.cs_nw_keys; 2074 for (i = 0; i < IEEE80211_WEP_NKID; i++, k++) { 2075 if (k->wk_keylen == 0) 2076 continue; 2077 2078 wepkey.idx = i; 2079 wepkey.len = k->wk_keylen; 2080 memset(wepkey.key, 0, sizeof(wepkey.key)); 2081 memcpy(wepkey.key, k->wk_key, k->wk_keylen); 2082 DPRINTF(("Setting wep key index %u len %u\n", 2083 wepkey.idx, wepkey.len)); 2084 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY, &wepkey, 2085 sizeof wepkey); 2086 if (error != 0) 2087 return error; 2088 } 2089 2090 data = htole32(ic->ic_crypto.cs_def_txkey); 2091 DPRINTF(("Setting tx key index to %u\n", le32toh(data))); 2092 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY_INDEX, &data, 2093 sizeof data); 2094 if (error != 0) 2095 return error; 2096 } 2097 2098 data = htole32((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) ? IPW_WEPON : 0); 2099 DPRINTF(("Setting wep flags to 0x%x\n", le32toh(data))); 2100 error = ipw_cmd(sc, IPW_CMD_SET_WEP_FLAGS, &data, sizeof data); 2101 if (error != 0) 2102 return error; 2103 2104 #if 0 2105 struct ipw_wpa_ie ie; 2106 2107 memset(&ie, 0 sizeof(ie)); 2108 ie.len = htole32(sizeof (struct ieee80211_ie_wpa)); 2109 DPRINTF(("Setting wpa ie\n")); 2110 error = ipw_cmd(sc, IPW_CMD_SET_WPA_IE, &ie, sizeof ie); 2111 if (error != 0) 2112 return error; 2113 #endif 2114 2115 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2116 data = htole32(ic->ic_bintval); 2117 DPRINTF(("Setting beacon interval to %u\n", le32toh(data))); 2118 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 2119 sizeof data); 2120 if (error != 0) 2121 return error; 2122 } 2123 2124 options.flags = 0; 2125 options.channels = htole32(0x3fff); /* scan channels 1-14 */ 2126 DPRINTF(("Setting scan options to 0x%x\n", le32toh(options.flags))); 2127 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &options, sizeof options); 2128 if (error != 0) 2129 return error; 2130 2131 /* finally, enable adapter (start scanning for an access point) */ 2132 DPRINTF(("Enabling adapter\n")); 2133 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 2134 } 2135 2136 static int 2137 ipw_init(struct ifnet *ifp) 2138 { 2139 struct ipw_softc *sc = ifp->if_softc; 2140 struct ipw_firmware *fw = &sc->fw; 2141 2142 if (!(sc->flags & IPW_FLAG_FW_CACHED)) { 2143 if (ipw_cache_firmware(sc) != 0) { 2144 aprint_error_dev(sc->sc_dev, "could not cache the firmware (%s)\n", 2145 sc->sc_fwname); 2146 goto fail; 2147 } 2148 } 2149 2150 ipw_stop(ifp, 0); 2151 2152 if (ipw_reset(sc) != 0) { 2153 aprint_error_dev(sc->sc_dev, "could not reset adapter\n"); 2154 goto fail; 2155 } 2156 2157 if (ipw_load_ucode(sc, fw->ucode, fw->ucode_size) != 0) { 2158 aprint_error_dev(sc->sc_dev, "could not load microcode\n"); 2159 goto fail; 2160 } 2161 2162 ipw_stop_master(sc); 2163 2164 /* 2165 * Setup tx, rx and status rings. 2166 */ 2167 sc->txold = IPW_NTBD - 1; 2168 sc->txcur = 0; 2169 sc->txfree = IPW_NTBD - 2; 2170 sc->rxcur = IPW_NRBD - 1; 2171 2172 CSR_WRITE_4(sc, IPW_CSR_TX_BASE, sc->tbd_map->dm_segs[0].ds_addr); 2173 CSR_WRITE_4(sc, IPW_CSR_TX_SIZE, IPW_NTBD); 2174 CSR_WRITE_4(sc, IPW_CSR_TX_READ, 0); 2175 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 2176 2177 CSR_WRITE_4(sc, IPW_CSR_RX_BASE, sc->rbd_map->dm_segs[0].ds_addr); 2178 CSR_WRITE_4(sc, IPW_CSR_RX_SIZE, IPW_NRBD); 2179 CSR_WRITE_4(sc, IPW_CSR_RX_READ, 0); 2180 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 2181 2182 CSR_WRITE_4(sc, IPW_CSR_STATUS_BASE, sc->status_map->dm_segs[0].ds_addr); 2183 2184 if (ipw_load_firmware(sc, fw->main, fw->main_size) != 0) { 2185 aprint_error_dev(sc->sc_dev, "could not load firmware\n"); 2186 goto fail; 2187 } 2188 2189 sc->flags |= IPW_FLAG_FW_INITED; 2190 2191 /* retrieve information tables base addresses */ 2192 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 2193 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 2194 2195 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 2196 2197 if (ipw_config(sc) != 0) { 2198 aprint_error_dev(sc->sc_dev, "device configuration failed\n"); 2199 goto fail; 2200 } 2201 2202 ifp->if_flags &= ~IFF_OACTIVE; 2203 ifp->if_flags |= IFF_RUNNING; 2204 2205 return 0; 2206 2207 fail: ifp->if_flags &= ~IFF_UP; 2208 ipw_stop(ifp, 0); 2209 2210 return EIO; 2211 } 2212 2213 static void 2214 ipw_stop(struct ifnet *ifp, int disable) 2215 { 2216 struct ipw_softc *sc = ifp->if_softc; 2217 struct ieee80211com *ic = &sc->sc_ic; 2218 int i; 2219 2220 ipw_stop_master(sc); 2221 2222 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 2223 2224 /* 2225 * Release tx buffers. 2226 */ 2227 for (i = 0; i < IPW_NTBD; i++) 2228 ipw_release_sbd(sc, &sc->stbd_list[i]); 2229 2230 sc->sc_tx_timer = 0; 2231 ifp->if_timer = 0; 2232 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2233 2234 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2235 } 2236 2237 static void 2238 ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2239 bus_size_t count) 2240 { 2241 for (; count > 0; offset++, datap++, count--) { 2242 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2243 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 2244 } 2245 } 2246 2247 static void 2248 ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2249 bus_size_t count) 2250 { 2251 for (; count > 0; offset++, datap++, count--) { 2252 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2253 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 2254 } 2255 } 2256 2257 SYSCTL_SETUP(sysctl_hw_ipw_accept_eula_setup, "sysctl hw.ipw.accept_eula") 2258 { 2259 const struct sysctlnode *rnode; 2260 const struct sysctlnode *cnode; 2261 2262 sysctl_createv(NULL, 0, NULL, &rnode, 2263 CTLFLAG_PERMANENT, 2264 CTLTYPE_NODE, "hw", 2265 NULL, 2266 NULL, 0, 2267 NULL, 0, 2268 CTL_HW, CTL_EOL); 2269 2270 sysctl_createv(NULL, 0, &rnode, &rnode, 2271 CTLFLAG_PERMANENT, 2272 CTLTYPE_NODE, "ipw", 2273 NULL, 2274 NULL, 0, 2275 NULL, 0, 2276 CTL_CREATE, CTL_EOL); 2277 2278 sysctl_createv(NULL, 0, &rnode, &cnode, 2279 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, 2280 CTLTYPE_INT, "accept_eula", 2281 SYSCTL_DESCR("Accept Intel EULA and permit use of ipw(4) firmware"), 2282 NULL, 0, 2283 &ipw_accept_eula, sizeof(ipw_accept_eula), 2284 CTL_CREATE, CTL_EOL); 2285 } 2286
Indexes created Tue Sep 30 17:09:57 GMT 2025