if_ipw.c revision 1.57.8.1
1 /* $NetBSD: if_ipw.c,v 1.57.8.1 2017/08/12 03:23:03 snj Exp $ */ 2 /* FreeBSD: src/sys/dev/ipw/if_ipw.c,v 1.15 2005/11/13 17:17:40 damien Exp */ 3 4 /*- 5 * Copyright (c) 2004, 2005 6 * Damien Bergamini <damien.bergamini (at) free.fr>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: if_ipw.c,v 1.57.8.1 2017/08/12 03:23:03 snj Exp $"); 33 34 /*- 35 * Intel(R) PRO/Wireless 2100 MiniPCI driver 36 * http://www.intel.com/network/connectivity/products/wireless/prowireless_mobile.htm 37 */ 38 39 40 #include <sys/param.h> 41 #include <sys/sockio.h> 42 #include <sys/sysctl.h> 43 #include <sys/mbuf.h> 44 #include <sys/kernel.h> 45 #include <sys/socket.h> 46 #include <sys/systm.h> 47 #include <sys/malloc.h> 48 #include <sys/conf.h> 49 #include <sys/proc.h> 50 51 #include <sys/bus.h> 52 #include <machine/endian.h> 53 #include <sys/intr.h> 54 55 #include <dev/pci/pcireg.h> 56 #include <dev/pci/pcivar.h> 57 #include <dev/pci/pcidevs.h> 58 59 #include <net/bpf.h> 60 #include <net/if.h> 61 #include <net/if_arp.h> 62 #include <net/if_dl.h> 63 #include <net/if_ether.h> 64 #include <net/if_media.h> 65 #include <net/if_types.h> 66 67 #include <net80211/ieee80211_var.h> 68 #include <net80211/ieee80211_radiotap.h> 69 70 #include <netinet/in.h> 71 #include <netinet/in_systm.h> 72 #include <netinet/in_var.h> 73 #include <netinet/ip.h> 74 75 #include <dev/firmload.h> 76 77 #include <dev/pci/if_ipwreg.h> 78 #include <dev/pci/if_ipwvar.h> 79 80 #ifdef IPW_DEBUG 81 #define DPRINTF(x) if (ipw_debug > 0) printf x 82 #define DPRINTFN(n, x) if (ipw_debug >= (n)) printf x 83 int ipw_debug = 0; 84 #else 85 #define DPRINTF(x) 86 #define DPRINTFN(n, x) 87 #endif 88 89 /* Permit loading the Intel firmware */ 90 static int ipw_accept_eula; 91 92 static int ipw_dma_alloc(struct ipw_softc *); 93 static void ipw_release(struct ipw_softc *); 94 static int ipw_match(device_t, cfdata_t, void *); 95 static void ipw_attach(device_t, device_t, void *); 96 static int ipw_detach(device_t, int); 97 98 static int ipw_media_change(struct ifnet *); 99 static void ipw_media_status(struct ifnet *, struct ifmediareq *); 100 static int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 101 static uint16_t ipw_read_prom_word(struct ipw_softc *, uint8_t); 102 static void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 103 static void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 104 static void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 105 struct ipw_soft_bd *, struct ipw_soft_buf *); 106 static void ipw_rx_intr(struct ipw_softc *); 107 static void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 108 static void ipw_tx_intr(struct ipw_softc *); 109 static int ipw_intr(void *); 110 static int ipw_cmd(struct ipw_softc *, uint32_t, void *, uint32_t); 111 static int ipw_tx_start(struct ifnet *, struct mbuf *, 112 struct ieee80211_node *); 113 static void ipw_start(struct ifnet *); 114 static void ipw_watchdog(struct ifnet *); 115 static int ipw_ioctl(struct ifnet *, u_long, void *); 116 static int ipw_get_table1(struct ipw_softc *, uint32_t *); 117 static int ipw_get_radio(struct ipw_softc *, int *); 118 static void ipw_stop_master(struct ipw_softc *); 119 static int ipw_reset(struct ipw_softc *); 120 static int ipw_load_ucode(struct ipw_softc *, u_char *, int); 121 static int ipw_load_firmware(struct ipw_softc *, u_char *, int); 122 static int ipw_cache_firmware(struct ipw_softc *); 123 static void ipw_free_firmware(struct ipw_softc *); 124 static int ipw_config(struct ipw_softc *); 125 static int ipw_init(struct ifnet *); 126 static void ipw_stop(struct ifnet *, int); 127 static uint32_t ipw_read_table1(struct ipw_softc *, uint32_t); 128 static void ipw_write_table1(struct ipw_softc *, uint32_t, uint32_t); 129 static int ipw_read_table2(struct ipw_softc *, uint32_t, void *, uint32_t *); 130 static void ipw_read_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 131 bus_size_t); 132 static void ipw_write_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 133 bus_size_t); 134 135 /* 136 * Supported rates for 802.11b mode (in 500Kbps unit). 137 */ 138 static const struct ieee80211_rateset ipw_rateset_11b = 139 { 4, { 2, 4, 11, 22 } }; 140 141 static inline uint8_t 142 MEM_READ_1(struct ipw_softc *sc, uint32_t addr) 143 { 144 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 145 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); 146 } 147 148 static inline uint32_t 149 MEM_READ_4(struct ipw_softc *sc, uint32_t addr) 150 { 151 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 152 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); 153 } 154 155 CFATTACH_DECL_NEW(ipw, sizeof (struct ipw_softc), ipw_match, ipw_attach, 156 ipw_detach, NULL); 157 158 static int 159 ipw_match(device_t parent, cfdata_t match, void *aux) 160 { 161 struct pci_attach_args *pa = aux; 162 163 if (PCI_VENDOR (pa->pa_id) == PCI_VENDOR_INTEL && 164 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_PRO_WL_2100) 165 return 1; 166 167 return 0; 168 } 169 170 /* Base Address Register */ 171 #define IPW_PCI_BAR0 0x10 172 173 static void 174 ipw_attach(device_t parent, device_t self, void *aux) 175 { 176 struct ipw_softc *sc = device_private(self); 177 struct ieee80211com *ic = &sc->sc_ic; 178 struct ifnet *ifp = &sc->sc_if; 179 struct pci_attach_args *pa = aux; 180 const char *intrstr; 181 bus_space_tag_t memt; 182 bus_space_handle_t memh; 183 bus_addr_t base; 184 pci_intr_handle_t ih; 185 uint32_t data; 186 uint16_t val; 187 int i, error; 188 char intrbuf[PCI_INTRSTR_LEN]; 189 190 sc->sc_dev = self; 191 sc->sc_pct = pa->pa_pc; 192 sc->sc_pcitag = pa->pa_tag; 193 194 pci_aprint_devinfo(pa, NULL); 195 196 /* enable bus-mastering */ 197 data = pci_conf_read(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG); 198 data |= PCI_COMMAND_MASTER_ENABLE; 199 pci_conf_write(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG, data); 200 201 /* map the register window */ 202 error = pci_mapreg_map(pa, IPW_PCI_BAR0, PCI_MAPREG_TYPE_MEM | 203 PCI_MAPREG_MEM_TYPE_32BIT, 0, &memt, &memh, &base, &sc->sc_sz); 204 if (error != 0) { 205 aprint_error_dev(sc->sc_dev, "could not map memory space\n"); 206 return; 207 } 208 209 sc->sc_st = memt; 210 sc->sc_sh = memh; 211 sc->sc_dmat = pa->pa_dmat; 212 sc->sc_fwname = "ipw2100-1.2.fw"; 213 214 /* disable interrupts */ 215 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 216 217 if (pci_intr_map(pa, &ih) != 0) { 218 aprint_error_dev(sc->sc_dev, "could not map interrupt\n"); 219 return; 220 } 221 222 intrstr = pci_intr_string(sc->sc_pct, ih, intrbuf, sizeof(intrbuf)); 223 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, ipw_intr, sc); 224 if (sc->sc_ih == NULL) { 225 aprint_error_dev(sc->sc_dev, "could not establish interrupt"); 226 if (intrstr != NULL) 227 aprint_error(" at %s", intrstr); 228 aprint_error("\n"); 229 return; 230 } 231 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 232 233 if (ipw_reset(sc) != 0) { 234 aprint_error_dev(sc->sc_dev, "could not reset adapter\n"); 235 goto fail; 236 } 237 238 if (ipw_dma_alloc(sc) != 0) { 239 aprint_error_dev(sc->sc_dev, "could not allocate DMA resources\n"); 240 goto fail; 241 } 242 243 ifp->if_softc = sc; 244 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 245 ifp->if_init = ipw_init; 246 ifp->if_stop = ipw_stop; 247 ifp->if_ioctl = ipw_ioctl; 248 ifp->if_start = ipw_start; 249 ifp->if_watchdog = ipw_watchdog; 250 IFQ_SET_READY(&ifp->if_snd); 251 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 252 253 ic->ic_ifp = ifp; 254 ic->ic_phytype = IEEE80211_T_DS; 255 ic->ic_opmode = IEEE80211_M_STA; 256 ic->ic_state = IEEE80211_S_INIT; 257 258 /* set device capabilities */ 259 ic->ic_caps = 260 IEEE80211_C_SHPREAMBLE /* short preamble supported */ 261 | IEEE80211_C_TXPMGT /* tx power management */ 262 | IEEE80211_C_IBSS /* ibss mode */ 263 | IEEE80211_C_MONITOR /* monitor mode */ 264 ; 265 266 /* read MAC address from EEPROM */ 267 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0); 268 ic->ic_myaddr[0] = val >> 8; 269 ic->ic_myaddr[1] = val & 0xff; 270 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 1); 271 ic->ic_myaddr[2] = val >> 8; 272 ic->ic_myaddr[3] = val & 0xff; 273 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 2); 274 ic->ic_myaddr[4] = val >> 8; 275 ic->ic_myaddr[5] = val & 0xff; 276 277 /* set supported .11b rates */ 278 ic->ic_sup_rates[IEEE80211_MODE_11B] = ipw_rateset_11b; 279 280 /* set supported .11b channels (read from EEPROM) */ 281 if ((val = ipw_read_prom_word(sc, IPW_EEPROM_CHANNEL_LIST)) == 0) 282 val = 0x7ff; /* default to channels 1-11 */ 283 val <<= 1; 284 for (i = 1; i < 16; i++) { 285 if (val & (1 << i)) { 286 ic->ic_channels[i].ic_freq = 287 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 288 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 289 } 290 } 291 292 /* check support for radio transmitter switch in EEPROM */ 293 if (!(ipw_read_prom_word(sc, IPW_EEPROM_RADIO) & 8)) 294 sc->flags |= IPW_FLAG_HAS_RADIO_SWITCH; 295 296 aprint_normal_dev(sc->sc_dev, "802.11 address %s\n", 297 ether_sprintf(ic->ic_myaddr)); 298 299 if_attach(ifp); 300 ieee80211_ifattach(ic); 301 302 /* override state transition machine */ 303 sc->sc_newstate = ic->ic_newstate; 304 ic->ic_newstate = ipw_newstate; 305 306 ieee80211_media_init(ic, ipw_media_change, ipw_media_status); 307 308 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 309 sizeof(struct ieee80211_frame) + 64, &sc->sc_drvbpf); 310 311 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 312 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 313 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 314 315 sc->sc_txtap_len = sizeof sc->sc_txtapu; 316 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 317 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 318 319 /* 320 * Add a few sysctl knobs. 321 * XXX: Not yet 322 */ 323 sc->dwelltime = 100; 324 325 if (pmf_device_register(self, NULL, NULL)) 326 pmf_class_network_register(self, ifp); 327 else 328 aprint_error_dev(self, "couldn't establish power handler\n"); 329 330 ieee80211_announce(ic); 331 332 return; 333 334 fail: ipw_detach(self, 0); 335 } 336 337 static int 338 ipw_detach(device_t self, int flags) 339 { 340 struct ipw_softc *sc = device_private(self); 341 struct ifnet *ifp = &sc->sc_if; 342 343 if (ifp->if_softc) { 344 ipw_stop(ifp, 1); 345 ipw_free_firmware(sc); 346 347 bpf_detach(ifp); 348 ieee80211_ifdetach(&sc->sc_ic); 349 if_detach(ifp); 350 351 ipw_release(sc); 352 } 353 354 if (sc->sc_ih != NULL) { 355 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 356 sc->sc_ih = NULL; 357 } 358 359 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 360 361 return 0; 362 } 363 364 static int 365 ipw_dma_alloc(struct ipw_softc *sc) 366 { 367 struct ipw_soft_bd *sbd; 368 struct ipw_soft_hdr *shdr; 369 struct ipw_soft_buf *sbuf; 370 int error, i, nsegs; 371 372 /* 373 * Allocate and map tx ring. 374 */ 375 error = bus_dmamap_create(sc->sc_dmat, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, 376 BUS_DMA_NOWAIT, &sc->tbd_map); 377 if (error != 0) { 378 aprint_error_dev(sc->sc_dev, "could not create tbd dma map\n"); 379 goto fail; 380 } 381 382 error = bus_dmamem_alloc(sc->sc_dmat, IPW_TBD_SZ, PAGE_SIZE, 0, 383 &sc->tbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 384 if (error != 0) { 385 aprint_error_dev(sc->sc_dev, "could not allocate tbd dma memory\n"); 386 goto fail; 387 } 388 389 error = bus_dmamem_map(sc->sc_dmat, &sc->tbd_seg, nsegs, IPW_TBD_SZ, 390 (void **)&sc->tbd_list, BUS_DMA_NOWAIT); 391 if (error != 0) { 392 aprint_error_dev(sc->sc_dev, "could not map tbd dma memory\n"); 393 goto fail; 394 } 395 396 error = bus_dmamap_load(sc->sc_dmat, sc->tbd_map, sc->tbd_list, 397 IPW_TBD_SZ, NULL, BUS_DMA_NOWAIT); 398 if (error != 0) { 399 aprint_error_dev(sc->sc_dev, "could not load tbd dma memory\n"); 400 goto fail; 401 } 402 403 (void)memset(sc->tbd_list, 0, IPW_TBD_SZ); 404 405 /* 406 * Allocate and map rx ring. 407 */ 408 error = bus_dmamap_create(sc->sc_dmat, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, 409 BUS_DMA_NOWAIT, &sc->rbd_map); 410 if (error != 0) { 411 aprint_error_dev(sc->sc_dev, "could not create rbd dma map\n"); 412 goto fail; 413 } 414 415 error = bus_dmamem_alloc(sc->sc_dmat, IPW_RBD_SZ, PAGE_SIZE, 0, 416 &sc->rbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 417 if (error != 0) { 418 aprint_error_dev(sc->sc_dev, "could not allocate rbd dma memory\n"); 419 goto fail; 420 } 421 422 error = bus_dmamem_map(sc->sc_dmat, &sc->rbd_seg, nsegs, IPW_RBD_SZ, 423 (void **)&sc->rbd_list, BUS_DMA_NOWAIT); 424 if (error != 0) { 425 aprint_error_dev(sc->sc_dev, "could not map rbd dma memory\n"); 426 goto fail; 427 } 428 429 error = bus_dmamap_load(sc->sc_dmat, sc->rbd_map, sc->rbd_list, 430 IPW_RBD_SZ, NULL, BUS_DMA_NOWAIT); 431 if (error != 0) { 432 aprint_error_dev(sc->sc_dev, "could not load rbd dma memory\n"); 433 goto fail; 434 } 435 436 (void)memset(sc->rbd_list, 0, IPW_RBD_SZ); 437 438 /* 439 * Allocate and map status ring. 440 */ 441 error = bus_dmamap_create(sc->sc_dmat, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 442 0, BUS_DMA_NOWAIT, &sc->status_map); 443 if (error != 0) { 444 aprint_error_dev(sc->sc_dev, "could not create status dma map\n"); 445 goto fail; 446 } 447 448 error = bus_dmamem_alloc(sc->sc_dmat, IPW_STATUS_SZ, PAGE_SIZE, 0, 449 &sc->status_seg, 1, &nsegs, BUS_DMA_NOWAIT); 450 if (error != 0) { 451 aprint_error_dev(sc->sc_dev, "could not allocate status dma memory\n"); 452 goto fail; 453 } 454 455 error = bus_dmamem_map(sc->sc_dmat, &sc->status_seg, nsegs, 456 IPW_STATUS_SZ, (void **)&sc->status_list, BUS_DMA_NOWAIT); 457 if (error != 0) { 458 aprint_error_dev(sc->sc_dev, "could not map status dma memory\n"); 459 goto fail; 460 } 461 462 error = bus_dmamap_load(sc->sc_dmat, sc->status_map, sc->status_list, 463 IPW_STATUS_SZ, NULL, BUS_DMA_NOWAIT); 464 if (error != 0) { 465 aprint_error_dev(sc->sc_dev, "could not load status dma memory\n"); 466 goto fail; 467 } 468 469 (void)memset(sc->status_list, 0, IPW_STATUS_SZ); 470 471 /* 472 * Allocate command DMA map. 473 */ 474 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_cmd), 475 1, sizeof (struct ipw_cmd), 0, BUS_DMA_NOWAIT, &sc->cmd_map); 476 if (error != 0) { 477 aprint_error_dev(sc->sc_dev, "could not create cmd dma map\n"); 478 goto fail; 479 } 480 481 error = bus_dmamem_alloc(sc->sc_dmat, sizeof (struct ipw_cmd), 482 PAGE_SIZE, 0, &sc->cmd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 483 if (error != 0) { 484 aprint_error_dev(sc->sc_dev, "could not allocate cmd dma memory\n"); 485 goto fail; 486 } 487 488 error = bus_dmamem_map(sc->sc_dmat, &sc->cmd_seg, nsegs, 489 sizeof (struct ipw_cmd), (void **)&sc->cmd, BUS_DMA_NOWAIT); 490 if (error != 0) { 491 aprint_error_dev(sc->sc_dev, "could not map cmd dma memory\n"); 492 goto fail; 493 } 494 495 error = bus_dmamap_load(sc->sc_dmat, sc->cmd_map, &sc->cmd, 496 sizeof (struct ipw_cmd), NULL, BUS_DMA_NOWAIT); 497 if (error != 0) { 498 aprint_error_dev(sc->sc_dev, "could not map cmd dma memory\n"); 499 return error; 500 } 501 502 /* 503 * Allocate and map hdr list. 504 */ 505 506 error = bus_dmamap_create(sc->sc_dmat, 507 IPW_NDATA * sizeof(struct ipw_hdr), 1, 508 sizeof(struct ipw_hdr), 0, BUS_DMA_NOWAIT, 509 &sc->hdr_map); 510 if (error != 0) { 511 aprint_error_dev(sc->sc_dev, "could not create hdr dma map\n"); 512 goto fail; 513 } 514 515 error = bus_dmamem_alloc(sc->sc_dmat, 516 IPW_NDATA * sizeof(struct ipw_hdr), PAGE_SIZE, 0, &sc->hdr_seg, 517 1, &nsegs, BUS_DMA_NOWAIT); 518 if (error != 0) { 519 aprint_error_dev(sc->sc_dev, "could not allocate hdr memory\n"); 520 goto fail; 521 } 522 523 error = bus_dmamem_map(sc->sc_dmat, &sc->hdr_seg, nsegs, 524 IPW_NDATA * sizeof(struct ipw_hdr), (void **)&sc->hdr_list, 525 BUS_DMA_NOWAIT); 526 if (error != 0) { 527 aprint_error_dev(sc->sc_dev, "could not map hdr memory\n"); 528 goto fail; 529 } 530 531 error = bus_dmamap_load(sc->sc_dmat, sc->hdr_map, sc->hdr_list, 532 IPW_NDATA * sizeof(struct ipw_hdr), NULL, BUS_DMA_NOWAIT); 533 if (error != 0) { 534 aprint_error_dev(sc->sc_dev, "could not load hdr memory\n"); 535 goto fail; 536 } 537 538 (void)memset(sc->hdr_list, 0, IPW_HDR_SZ); 539 540 /* 541 * Create DMA hdrs tailq. 542 */ 543 TAILQ_INIT(&sc->sc_free_shdr); 544 for (i = 0; i < IPW_NDATA; i++) { 545 shdr = &sc->shdr_list[i]; 546 shdr->hdr = sc->hdr_list + i; 547 shdr->offset = sizeof(struct ipw_hdr) * i; 548 shdr->addr = sc->hdr_map->dm_segs[0].ds_addr + shdr->offset; 549 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 550 } 551 552 /* 553 * Allocate tx buffers DMA maps. 554 */ 555 TAILQ_INIT(&sc->sc_free_sbuf); 556 for (i = 0; i < IPW_NDATA; i++) { 557 sbuf = &sc->tx_sbuf_list[i]; 558 559 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 560 IPW_MAX_NSEG, MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 561 if (error != 0) { 562 aprint_error_dev(sc->sc_dev, "could not create txbuf dma map\n"); 563 goto fail; 564 } 565 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 566 } 567 568 /* 569 * Initialize tx ring. 570 */ 571 for (i = 0; i < IPW_NTBD; i++) { 572 sbd = &sc->stbd_list[i]; 573 sbd->bd = &sc->tbd_list[i]; 574 sbd->type = IPW_SBD_TYPE_NOASSOC; 575 } 576 577 /* 578 * Pre-allocate rx buffers and DMA maps 579 */ 580 for (i = 0; i < IPW_NRBD; i++) { 581 sbd = &sc->srbd_list[i]; 582 sbuf = &sc->rx_sbuf_list[i]; 583 sbd->bd = &sc->rbd_list[i]; 584 585 MGETHDR(sbuf->m, M_DONTWAIT, MT_DATA); 586 if (sbuf->m == NULL) { 587 aprint_error_dev(sc->sc_dev, "could not allocate rx mbuf\n"); 588 error = ENOMEM; 589 goto fail; 590 } 591 592 MCLGET(sbuf->m, M_DONTWAIT); 593 if (!(sbuf->m->m_flags & M_EXT)) { 594 m_freem(sbuf->m); 595 sbuf->m = NULL; 596 aprint_error_dev(sc->sc_dev, "could not allocate rx mbuf cluster\n"); 597 error = ENOMEM; 598 goto fail; 599 } 600 601 sbuf->m->m_pkthdr.len = sbuf->m->m_len = sbuf->m->m_ext.ext_size; 602 603 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 604 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sbuf->map); 605 if (error != 0) { 606 aprint_error_dev(sc->sc_dev, "could not create rxbuf dma map\n"); 607 m_freem(sbuf->m); 608 sbuf->m = NULL; 609 goto fail; 610 } 611 612 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, 613 sbuf->m, BUS_DMA_READ | BUS_DMA_NOWAIT); 614 if (error != 0) { 615 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 616 sbuf->map = NULL; 617 m_freem(sbuf->m); 618 sbuf->m = NULL; 619 aprint_error_dev(sc->sc_dev, "could not map rxbuf dma memory\n"); 620 goto fail; 621 } 622 623 sbd->type = IPW_SBD_TYPE_DATA; 624 sbd->priv = sbuf; 625 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 626 sbd->bd->len = htole32(MCLBYTES); 627 628 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, 629 sbuf->map->dm_mapsize, BUS_DMASYNC_PREREAD); 630 631 } 632 633 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 0, IPW_RBD_SZ, 634 BUS_DMASYNC_PREREAD); 635 636 return 0; 637 638 fail: ipw_release(sc); 639 return error; 640 } 641 642 static void 643 ipw_release(struct ipw_softc *sc) 644 { 645 struct ipw_soft_buf *sbuf; 646 int i; 647 648 if (sc->tbd_map != NULL) { 649 if (sc->tbd_list != NULL) { 650 bus_dmamap_unload(sc->sc_dmat, sc->tbd_map); 651 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->tbd_list, 652 IPW_TBD_SZ); 653 bus_dmamem_free(sc->sc_dmat, &sc->tbd_seg, 1); 654 } 655 bus_dmamap_destroy(sc->sc_dmat, sc->tbd_map); 656 } 657 658 if (sc->rbd_map != NULL) { 659 if (sc->rbd_list != NULL) { 660 bus_dmamap_unload(sc->sc_dmat, sc->rbd_map); 661 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->rbd_list, 662 IPW_RBD_SZ); 663 bus_dmamem_free(sc->sc_dmat, &sc->rbd_seg, 1); 664 } 665 bus_dmamap_destroy(sc->sc_dmat, sc->rbd_map); 666 } 667 668 if (sc->status_map != NULL) { 669 if (sc->status_list != NULL) { 670 bus_dmamap_unload(sc->sc_dmat, sc->status_map); 671 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->status_list, 672 IPW_RBD_SZ); 673 bus_dmamem_free(sc->sc_dmat, &sc->status_seg, 1); 674 } 675 bus_dmamap_destroy(sc->sc_dmat, sc->status_map); 676 } 677 678 for (i = 0; i < IPW_NTBD; i++) 679 ipw_release_sbd(sc, &sc->stbd_list[i]); 680 681 if (sc->cmd_map != NULL) 682 bus_dmamap_destroy(sc->sc_dmat, sc->cmd_map); 683 684 if (sc->hdr_list != NULL) { 685 bus_dmamap_unload(sc->sc_dmat, sc->hdr_map); 686 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->hdr_list, 687 IPW_NDATA * sizeof(struct ipw_hdr)); 688 } 689 if (sc->hdr_map != NULL) { 690 bus_dmamem_free(sc->sc_dmat, &sc->hdr_seg, 1); 691 bus_dmamap_destroy(sc->sc_dmat, sc->hdr_map); 692 } 693 694 for (i = 0; i < IPW_NDATA; i++) 695 bus_dmamap_destroy(sc->sc_dmat, sc->tx_sbuf_list[i].map); 696 697 for (i = 0; i < IPW_NRBD; i++) { 698 sbuf = &sc->rx_sbuf_list[i]; 699 if (sbuf->map != NULL) { 700 if (sbuf->m != NULL) { 701 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 702 m_freem(sbuf->m); 703 } 704 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 705 } 706 } 707 708 } 709 710 static int 711 ipw_media_change(struct ifnet *ifp) 712 { 713 int error; 714 715 error = ieee80211_media_change(ifp); 716 if (error != ENETRESET) 717 return error; 718 719 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 720 ipw_init(ifp); 721 722 return 0; 723 } 724 725 /* 726 * The firmware automatically adapts the transmit speed. We report the current 727 * transmit speed here. 728 */ 729 static void 730 ipw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 731 { 732 #define N(a) (sizeof (a) / sizeof (a[0])) 733 struct ipw_softc *sc = ifp->if_softc; 734 struct ieee80211com *ic = &sc->sc_ic; 735 static const struct { 736 uint32_t val; 737 int rate; 738 } rates[] = { 739 { IPW_RATE_DS1, 2 }, 740 { IPW_RATE_DS2, 4 }, 741 { IPW_RATE_DS5, 11 }, 742 { IPW_RATE_DS11, 22 }, 743 }; 744 uint32_t val; 745 int rate, i; 746 747 imr->ifm_status = IFM_AVALID; 748 imr->ifm_active = IFM_IEEE80211; 749 if (ic->ic_state == IEEE80211_S_RUN) 750 imr->ifm_status |= IFM_ACTIVE; 751 752 /* read current transmission rate from adapter */ 753 val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE) & 0xf; 754 755 /* convert ipw rate to 802.11 rate */ 756 for (i = 0; i < N(rates) && rates[i].val != val; i++); 757 rate = (i < N(rates)) ? rates[i].rate : 0; 758 759 imr->ifm_active |= IFM_IEEE80211_11B; 760 imr->ifm_active |= ieee80211_rate2media(ic, rate, IEEE80211_MODE_11B); 761 switch (ic->ic_opmode) { 762 case IEEE80211_M_STA: 763 break; 764 765 case IEEE80211_M_IBSS: 766 imr->ifm_active |= IFM_IEEE80211_ADHOC; 767 break; 768 769 case IEEE80211_M_MONITOR: 770 imr->ifm_active |= IFM_IEEE80211_MONITOR; 771 break; 772 773 case IEEE80211_M_AHDEMO: 774 case IEEE80211_M_HOSTAP: 775 /* should not get there */ 776 break; 777 } 778 #undef N 779 } 780 781 static int 782 ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, 783 int arg) 784 { 785 struct ifnet *ifp = ic->ic_ifp; 786 struct ipw_softc *sc = ifp->if_softc; 787 struct ieee80211_node *ni; 788 uint8_t macaddr[IEEE80211_ADDR_LEN]; 789 uint32_t len; 790 struct ipw_rx_radiotap_header *wr = &sc->sc_rxtap; 791 struct ipw_tx_radiotap_header *wt = &sc->sc_txtap; 792 793 switch (nstate) { 794 case IEEE80211_S_INIT: 795 break; 796 default: 797 KASSERT(ic->ic_curchan != IEEE80211_CHAN_ANYC); 798 KASSERT(ic->ic_curchan != NULL); 799 wt->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 800 wt->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 801 wr->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 802 wr->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 803 break; 804 } 805 806 switch (nstate) { 807 case IEEE80211_S_RUN: 808 DELAY(200); /* firmware needs a short delay here */ 809 810 len = IEEE80211_ADDR_LEN; 811 ipw_read_table2(sc, IPW_INFO_CURRENT_BSSID, macaddr, &len); 812 813 ni = ieee80211_find_node(&ic->ic_scan, macaddr); 814 if (ni == NULL) 815 break; 816 817 ieee80211_ref_node(ni); 818 ieee80211_sta_join(ic, ni); 819 ieee80211_node_authorize(ni); 820 821 if (ic->ic_opmode == IEEE80211_M_STA) 822 ieee80211_notify_node_join(ic, ni, 1); 823 break; 824 825 case IEEE80211_S_INIT: 826 case IEEE80211_S_SCAN: 827 case IEEE80211_S_AUTH: 828 case IEEE80211_S_ASSOC: 829 break; 830 } 831 832 ic->ic_state = nstate; 833 return 0; 834 } 835 836 /* 837 * Read 16 bits at address 'addr' from the serial EEPROM. 838 */ 839 static uint16_t 840 ipw_read_prom_word(struct ipw_softc *sc, uint8_t addr) 841 { 842 uint32_t tmp; 843 uint16_t val; 844 int n; 845 846 /* clock C once before the first command */ 847 IPW_EEPROM_CTL(sc, 0); 848 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 849 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 850 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 851 852 /* write start bit (1) */ 853 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 854 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 855 856 /* write READ opcode (10) */ 857 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 858 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 859 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 860 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 861 862 /* write address A7-A0 */ 863 for (n = 7; n >= 0; n--) { 864 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 865 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D)); 866 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 867 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D) | IPW_EEPROM_C); 868 } 869 870 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 871 872 /* read data Q15-Q0 */ 873 val = 0; 874 for (n = 15; n >= 0; n--) { 875 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 876 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 877 tmp = MEM_READ_4(sc, IPW_MEM_EEPROM_CTL); 878 val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n; 879 } 880 881 IPW_EEPROM_CTL(sc, 0); 882 883 /* clear Chip Select and clock C */ 884 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 885 IPW_EEPROM_CTL(sc, 0); 886 IPW_EEPROM_CTL(sc, IPW_EEPROM_C); 887 888 return le16toh(val); 889 } 890 891 static void 892 ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 893 { 894 895 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof (struct ipw_cmd), 896 BUS_DMASYNC_POSTREAD); 897 898 #ifdef IPW_DEBUG 899 struct ipw_cmd *cmd = mtod(sbuf->m, struct ipw_cmd *); 900 901 DPRINTFN(2, ("cmd ack'ed (%u, %u, %u, %u, %u)\n", le32toh(cmd->type), 902 le32toh(cmd->subtype), le32toh(cmd->seq), le32toh(cmd->len), 903 le32toh(cmd->status))); 904 #endif 905 906 wakeup(&sc->cmd); 907 } 908 909 static void 910 ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 911 { 912 struct ieee80211com *ic = &sc->sc_ic; 913 struct ifnet *ifp = sc->sc_ic.ic_ifp; 914 uint32_t state; 915 916 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof state, 917 BUS_DMASYNC_POSTREAD); 918 919 state = le32toh(*mtod(sbuf->m, uint32_t *)); 920 921 DPRINTFN(2, ("entering state %u\n", state)); 922 923 switch (state) { 924 case IPW_STATE_ASSOCIATED: 925 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 926 break; 927 928 case IPW_STATE_SCANNING: 929 /* don't leave run state on background scan */ 930 if (ic->ic_state != IEEE80211_S_RUN) 931 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 932 933 ic->ic_flags |= IEEE80211_F_SCAN; 934 break; 935 936 case IPW_STATE_SCAN_COMPLETE: 937 ieee80211_notify_scan_done(ic); 938 ic->ic_flags &= ~IEEE80211_F_SCAN; 939 break; 940 941 case IPW_STATE_ASSOCIATION_LOST: 942 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 943 break; 944 945 case IPW_STATE_RADIO_DISABLED: 946 ic->ic_ifp->if_flags &= ~IFF_UP; 947 ipw_stop(ifp, 1); 948 break; 949 } 950 } 951 952 /* 953 * XXX: Hack to set the current channel to the value advertised in beacons or 954 * probe responses. Only used during AP detection. 955 */ 956 static void 957 ipw_fix_channel(struct ieee80211com *ic, struct mbuf *m) 958 { 959 struct ieee80211_frame *wh; 960 uint8_t subtype; 961 uint8_t *frm, *efrm; 962 963 wh = mtod(m, struct ieee80211_frame *); 964 965 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_MGT) 966 return; 967 968 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 969 970 if (subtype != IEEE80211_FC0_SUBTYPE_BEACON && 971 subtype != IEEE80211_FC0_SUBTYPE_PROBE_RESP) 972 return; 973 974 frm = (uint8_t *)(wh + 1); 975 efrm = mtod(m, uint8_t *) + m->m_len; 976 977 frm += 12; /* skip tstamp, bintval and capinfo fields */ 978 while (frm < efrm) { 979 if (*frm == IEEE80211_ELEMID_DSPARMS) 980 #if IEEE80211_CHAN_MAX < 255 981 if (frm[2] <= IEEE80211_CHAN_MAX) 982 #endif 983 ic->ic_curchan = &ic->ic_channels[frm[2]]; 984 985 frm += frm[1] + 2; 986 } 987 } 988 989 static void 990 ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 991 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 992 { 993 struct ieee80211com *ic = &sc->sc_ic; 994 struct ifnet *ifp = &sc->sc_if; 995 struct mbuf *mnew, *m; 996 struct ieee80211_frame *wh; 997 struct ieee80211_node *ni; 998 int error; 999 1000 DPRINTFN(5, ("received frame len=%u, rssi=%u\n", le32toh(status->len), 1001 status->rssi)); 1002 1003 if (le32toh(status->len) < sizeof (struct ieee80211_frame_min) || 1004 le32toh(status->len) > MCLBYTES) 1005 return; 1006 1007 /* 1008 * Try to allocate a new mbuf for this ring element and load it before 1009 * processing the current mbuf. If the ring element cannot be loaded, 1010 * drop the received packet and reuse the old mbuf. In the unlikely 1011 * case that the old mbuf can't be reloaded either, explicitly panic. 1012 */ 1013 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1014 if (mnew == NULL) { 1015 aprint_error_dev(sc->sc_dev, "could not allocate rx mbuf\n"); 1016 ifp->if_ierrors++; 1017 return; 1018 } 1019 1020 MCLGET(mnew, M_DONTWAIT); 1021 if (!(mnew->m_flags & M_EXT)) { 1022 aprint_error_dev(sc->sc_dev, "could not allocate rx mbuf cluster\n"); 1023 m_freem(mnew); 1024 ifp->if_ierrors++; 1025 return; 1026 } 1027 1028 mnew->m_pkthdr.len = mnew->m_len = mnew->m_ext.ext_size; 1029 1030 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, le32toh(status->len), 1031 BUS_DMASYNC_POSTREAD); 1032 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1033 1034 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, mnew, 1035 BUS_DMA_READ | BUS_DMA_NOWAIT); 1036 if (error != 0) { 1037 aprint_error_dev(sc->sc_dev, "could not load rx buf DMA map\n"); 1038 m_freem(mnew); 1039 1040 /* try to reload the old mbuf */ 1041 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, 1042 sbuf->m, BUS_DMA_READ | BUS_DMA_NOWAIT); 1043 if (error != 0) { 1044 /* very unlikely that it will fail... */ 1045 panic("%s: unable to remap rx buf", 1046 device_xname(sc->sc_dev)); 1047 } 1048 ifp->if_ierrors++; 1049 return; 1050 } 1051 1052 /* 1053 * New mbuf successfully loaded, update Rx ring and continue 1054 * processing. 1055 */ 1056 m = sbuf->m; 1057 sbuf->m = mnew; 1058 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 1059 1060 /* finalize mbuf */ 1061 m->m_pkthdr.rcvif = ifp; 1062 m->m_pkthdr.len = m->m_len = le32toh(status->len); 1063 1064 if (sc->sc_drvbpf != NULL) { 1065 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 1066 1067 tap->wr_antsignal = status->rssi; 1068 1069 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 1070 } 1071 1072 if (ic->ic_state == IEEE80211_S_SCAN) 1073 ipw_fix_channel(ic, m); 1074 1075 wh = mtod(m, struct ieee80211_frame *); 1076 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 1077 1078 /* send the frame to the 802.11 layer */ 1079 ieee80211_input(ic, m, ni, status->rssi, 0); 1080 1081 /* node is no longer needed */ 1082 ieee80211_free_node(ni); 1083 1084 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, 1085 sbuf->map->dm_mapsize, BUS_DMASYNC_PREREAD); 1086 } 1087 1088 static void 1089 ipw_rx_intr(struct ipw_softc *sc) 1090 { 1091 struct ipw_status *status; 1092 struct ipw_soft_bd *sbd; 1093 struct ipw_soft_buf *sbuf; 1094 uint32_t r, i; 1095 1096 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1097 return; 1098 1099 r = CSR_READ_4(sc, IPW_CSR_RX_READ); 1100 1101 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 1102 1103 /* firmware was killed, stop processing received frames */ 1104 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1105 return; 1106 1107 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 1108 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1109 BUS_DMASYNC_POSTREAD); 1110 1111 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 1112 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 1113 BUS_DMASYNC_POSTREAD); 1114 1115 status = &sc->status_list[i]; 1116 sbd = &sc->srbd_list[i]; 1117 sbuf = sbd->priv; 1118 1119 switch (le16toh(status->code) & 0xf) { 1120 case IPW_STATUS_CODE_COMMAND: 1121 ipw_command_intr(sc, sbuf); 1122 break; 1123 1124 case IPW_STATUS_CODE_NEWSTATE: 1125 ipw_newstate_intr(sc, sbuf); 1126 break; 1127 1128 case IPW_STATUS_CODE_DATA_802_3: 1129 case IPW_STATUS_CODE_DATA_802_11: 1130 ipw_data_intr(sc, status, sbd, sbuf); 1131 break; 1132 1133 case IPW_STATUS_CODE_NOTIFICATION: 1134 DPRINTFN(2, ("received notification\n")); 1135 break; 1136 1137 default: 1138 aprint_error_dev(sc->sc_dev, "unknown status code %u\n", 1139 le16toh(status->code)); 1140 } 1141 1142 sbd->bd->flags = 0; 1143 1144 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 1145 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1146 BUS_DMASYNC_PREREAD); 1147 1148 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 1149 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 1150 BUS_DMASYNC_PREREAD); 1151 } 1152 1153 /* Tell the firmware what we have processed */ 1154 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 1155 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 1156 } 1157 1158 static void 1159 ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 1160 { 1161 struct ipw_soft_hdr *shdr; 1162 struct ipw_soft_buf *sbuf; 1163 1164 switch (sbd->type) { 1165 case IPW_SBD_TYPE_COMMAND: 1166 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 1167 0, sizeof(struct ipw_cmd), BUS_DMASYNC_POSTWRITE); 1168 /* bus_dmamap_unload(sc->sc_dmat, sc->cmd_map); */ 1169 break; 1170 1171 case IPW_SBD_TYPE_HEADER: 1172 shdr = sbd->priv; 1173 bus_dmamap_sync(sc->sc_dmat, sc->hdr_map, 1174 shdr->offset, sizeof(struct ipw_hdr), BUS_DMASYNC_POSTWRITE); 1175 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 1176 break; 1177 1178 case IPW_SBD_TYPE_DATA: 1179 sbuf = sbd->priv; 1180 1181 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 1182 0, MCLBYTES, BUS_DMASYNC_POSTWRITE); 1183 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1184 m_freem(sbuf->m); 1185 if (sbuf->ni != NULL) 1186 ieee80211_free_node(sbuf->ni); 1187 /* kill watchdog timer */ 1188 sc->sc_tx_timer = 0; 1189 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 1190 break; 1191 } 1192 sbd->type = IPW_SBD_TYPE_NOASSOC; 1193 } 1194 1195 static void 1196 ipw_tx_intr(struct ipw_softc *sc) 1197 { 1198 struct ifnet *ifp = &sc->sc_if; 1199 struct ipw_soft_bd *sbd; 1200 uint32_t r, i; 1201 1202 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1203 return; 1204 1205 r = CSR_READ_4(sc, IPW_CSR_TX_READ); 1206 1207 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) { 1208 sbd = &sc->stbd_list[i]; 1209 1210 if (sbd->type == IPW_SBD_TYPE_DATA) 1211 ifp->if_opackets++; 1212 1213 ipw_release_sbd(sc, sbd); 1214 sc->txfree++; 1215 } 1216 1217 /* remember what the firmware has processed */ 1218 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 1219 1220 /* Call start() since some buffer descriptors have been released */ 1221 ifp->if_flags &= ~IFF_OACTIVE; 1222 (*ifp->if_start)(ifp); 1223 } 1224 1225 static int 1226 ipw_intr(void *arg) 1227 { 1228 struct ipw_softc *sc = arg; 1229 uint32_t r; 1230 1231 r = CSR_READ_4(sc, IPW_CSR_INTR); 1232 if (r == 0 || r == 0xffffffff) 1233 return 0; 1234 1235 /* Disable interrupts */ 1236 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1237 1238 if (r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR)) { 1239 aprint_error_dev(sc->sc_dev, "fatal error\n"); 1240 sc->sc_ic.ic_ifp->if_flags &= ~IFF_UP; 1241 ipw_stop(&sc->sc_if, 1); 1242 } 1243 1244 if (r & IPW_INTR_FW_INIT_DONE) { 1245 if (!(r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR))) 1246 wakeup(sc); 1247 } 1248 1249 if (r & IPW_INTR_RX_TRANSFER) 1250 ipw_rx_intr(sc); 1251 1252 if (r & IPW_INTR_TX_TRANSFER) 1253 ipw_tx_intr(sc); 1254 1255 /* Acknowledge all interrupts */ 1256 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 1257 1258 /* Re-enable interrupts */ 1259 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1260 1261 return 0; 1262 } 1263 1264 /* 1265 * Send a command to the firmware and wait for the acknowledgement. 1266 */ 1267 static int 1268 ipw_cmd(struct ipw_softc *sc, uint32_t type, void *data, uint32_t len) 1269 { 1270 struct ipw_soft_bd *sbd; 1271 1272 sbd = &sc->stbd_list[sc->txcur]; 1273 1274 sc->cmd.type = htole32(type); 1275 sc->cmd.subtype = 0; 1276 sc->cmd.len = htole32(len); 1277 sc->cmd.seq = 0; 1278 1279 (void)memcpy(sc->cmd.data, data, len); 1280 1281 sbd->type = IPW_SBD_TYPE_COMMAND; 1282 sbd->bd->physaddr = htole32(sc->cmd_map->dm_segs[0].ds_addr); 1283 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 1284 sbd->bd->nfrag = 1; 1285 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 1286 IPW_BD_FLAG_TX_LAST_FRAGMENT; 1287 1288 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 0, sizeof (struct ipw_cmd), 1289 BUS_DMASYNC_PREWRITE); 1290 1291 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1292 sc->txcur * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1293 BUS_DMASYNC_PREWRITE); 1294 1295 DPRINTFN(2, ("sending command (%u, %u, %u, %u)\n", type, 0, 0, len)); 1296 1297 /* kick firmware */ 1298 sc->txfree--; 1299 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1300 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1301 1302 /* Wait at most one second for command to complete */ 1303 return tsleep(&sc->cmd, 0, "ipwcmd", hz); 1304 } 1305 1306 static int 1307 ipw_tx_start(struct ifnet *ifp, struct mbuf *m0, struct ieee80211_node *ni) 1308 { 1309 struct ipw_softc *sc = ifp->if_softc; 1310 struct ieee80211com *ic = &sc->sc_ic; 1311 struct ieee80211_frame *wh; 1312 struct ipw_soft_bd *sbd; 1313 struct ipw_soft_hdr *shdr; 1314 struct ipw_soft_buf *sbuf; 1315 struct ieee80211_key *k; 1316 struct mbuf *mnew; 1317 int error, i; 1318 1319 wh = mtod(m0, struct ieee80211_frame *); 1320 1321 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1322 k = ieee80211_crypto_encap(ic, ni, m0); 1323 if (k == NULL) { 1324 m_freem(m0); 1325 return ENOBUFS; 1326 } 1327 1328 /* packet header may have moved, reset our local pointer */ 1329 wh = mtod(m0, struct ieee80211_frame *); 1330 } 1331 1332 if (sc->sc_drvbpf != NULL) { 1333 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 1334 1335 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 1336 } 1337 1338 shdr = TAILQ_FIRST(&sc->sc_free_shdr); 1339 sbuf = TAILQ_FIRST(&sc->sc_free_sbuf); 1340 KASSERT(shdr != NULL && sbuf != NULL); 1341 1342 shdr->hdr->type = htole32(IPW_HDR_TYPE_SEND); 1343 shdr->hdr->subtype = 0; 1344 shdr->hdr->encrypted = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0; 1345 shdr->hdr->encrypt = 0; 1346 shdr->hdr->keyidx = 0; 1347 shdr->hdr->keysz = 0; 1348 shdr->hdr->fragmentsz = 0; 1349 IEEE80211_ADDR_COPY(shdr->hdr->src_addr, wh->i_addr2); 1350 if (ic->ic_opmode == IEEE80211_M_STA) 1351 IEEE80211_ADDR_COPY(shdr->hdr->dst_addr, wh->i_addr3); 1352 else 1353 IEEE80211_ADDR_COPY(shdr->hdr->dst_addr, wh->i_addr1); 1354 1355 /* trim IEEE802.11 header */ 1356 m_adj(m0, sizeof (struct ieee80211_frame)); 1357 1358 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m0, BUS_DMA_NOWAIT); 1359 if (error != 0 && error != EFBIG) { 1360 aprint_error_dev(sc->sc_dev, "could not map mbuf (error %d)\n", 1361 error); 1362 m_freem(m0); 1363 return error; 1364 } 1365 1366 if (error != 0) { 1367 /* too many fragments, linearize */ 1368 1369 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1370 if (mnew == NULL) { 1371 m_freem(m0); 1372 return ENOMEM; 1373 } 1374 1375 M_COPY_PKTHDR(mnew, m0); 1376 1377 /* If the data won't fit in the header, get a cluster */ 1378 if (m0->m_pkthdr.len > MHLEN) { 1379 MCLGET(mnew, M_DONTWAIT); 1380 if (!(mnew->m_flags & M_EXT)) { 1381 m_freem(m0); 1382 m_freem(mnew); 1383 return ENOMEM; 1384 } 1385 } 1386 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(mnew, void *)); 1387 m_freem(m0); 1388 mnew->m_len = mnew->m_pkthdr.len; 1389 m0 = mnew; 1390 1391 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m0, 1392 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1393 if (error != 0) { 1394 aprint_error_dev(sc->sc_dev, "could not map mbuf (error %d)\n", error); 1395 m_freem(m0); 1396 return error; 1397 } 1398 } 1399 1400 TAILQ_REMOVE(&sc->sc_free_sbuf, sbuf, next); 1401 TAILQ_REMOVE(&sc->sc_free_shdr, shdr, next); 1402 1403 sbd = &sc->stbd_list[sc->txcur]; 1404 sbd->type = IPW_SBD_TYPE_HEADER; 1405 sbd->priv = shdr; 1406 sbd->bd->physaddr = htole32(shdr->addr); 1407 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 1408 sbd->bd->nfrag = 1 + sbuf->map->dm_nsegs; 1409 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 1410 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1411 1412 DPRINTFN(5, ("sending tx hdr (%u, %u, %u, %u, )\n", 1413 shdr->hdr->type, shdr->hdr->subtype, shdr->hdr->encrypted, 1414 shdr->hdr->encrypt)); 1415 DPRINTFN(5, ("%s->", ether_sprintf(shdr->hdr->src_addr))); 1416 DPRINTFN(5, ("%s\n", ether_sprintf(shdr->hdr->dst_addr))); 1417 1418 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1419 sc->txcur * sizeof (struct ipw_bd), 1420 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1421 1422 sc->txfree--; 1423 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1424 1425 sbuf->m = m0; 1426 sbuf->ni = ni; 1427 1428 for (i = 0; i < sbuf->map->dm_nsegs; i++) { 1429 sbd = &sc->stbd_list[sc->txcur]; 1430 1431 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[i].ds_addr); 1432 sbd->bd->len = htole32(sbuf->map->dm_segs[i].ds_len); 1433 sbd->bd->nfrag = 0; 1434 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 1435 if (i == sbuf->map->dm_nsegs - 1) { 1436 sbd->type = IPW_SBD_TYPE_DATA; 1437 sbd->priv = sbuf; 1438 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 1439 } else { 1440 sbd->type = IPW_SBD_TYPE_NOASSOC; 1441 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1442 } 1443 1444 DPRINTFN(5, ("sending fragment (%d, %d)\n", i, 1445 (int)sbuf->map->dm_segs[i].ds_len)); 1446 1447 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1448 sc->txcur * sizeof (struct ipw_bd), 1449 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1450 1451 sc->txfree--; 1452 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1453 } 1454 1455 bus_dmamap_sync(sc->sc_dmat, sc->hdr_map, shdr->offset, 1456 sizeof (struct ipw_hdr), BUS_DMASYNC_PREWRITE); 1457 1458 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, MCLBYTES, 1459 BUS_DMASYNC_PREWRITE); 1460 1461 /* Inform firmware about this new packet */ 1462 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1463 1464 return 0; 1465 } 1466 1467 static void 1468 ipw_start(struct ifnet *ifp) 1469 { 1470 struct ipw_softc *sc = ifp->if_softc; 1471 struct ieee80211com *ic = &sc->sc_ic; 1472 struct mbuf *m0; 1473 struct ether_header *eh; 1474 struct ieee80211_node *ni; 1475 1476 1477 if (ic->ic_state != IEEE80211_S_RUN) 1478 return; 1479 1480 for (;;) { 1481 IF_DEQUEUE(&ifp->if_snd, m0); 1482 if (m0 == NULL) 1483 break; 1484 1485 if (sc->txfree < 1 + IPW_MAX_NSEG) { 1486 IF_PREPEND(&ifp->if_snd, m0); 1487 ifp->if_flags |= IFF_OACTIVE; 1488 break; 1489 } 1490 1491 if (m0->m_len < sizeof (struct ether_header) && 1492 (m0 = m_pullup(m0, sizeof (struct ether_header))) == NULL) 1493 continue; 1494 1495 eh = mtod(m0, struct ether_header *); 1496 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1497 if (ni == NULL) { 1498 m_freem(m0); 1499 continue; 1500 } 1501 1502 bpf_mtap(ifp, m0); 1503 1504 m0 = ieee80211_encap(ic, m0, ni); 1505 if (m0 == NULL) { 1506 ieee80211_free_node(ni); 1507 continue; 1508 } 1509 1510 bpf_mtap3(ic->ic_rawbpf, m0); 1511 1512 if (ipw_tx_start(ifp, m0, ni) != 0) { 1513 ieee80211_free_node(ni); 1514 ifp->if_oerrors++; 1515 break; 1516 } 1517 1518 /* start watchdog timer */ 1519 sc->sc_tx_timer = 5; 1520 ifp->if_timer = 1; 1521 } 1522 } 1523 1524 static void 1525 ipw_watchdog(struct ifnet *ifp) 1526 { 1527 struct ipw_softc *sc = ifp->if_softc; 1528 1529 ifp->if_timer = 0; 1530 1531 if (sc->sc_tx_timer > 0) { 1532 if (--sc->sc_tx_timer == 0) { 1533 aprint_error_dev(sc->sc_dev, "device timeout\n"); 1534 ifp->if_oerrors++; 1535 ifp->if_flags &= ~IFF_UP; 1536 ipw_stop(ifp, 1); 1537 return; 1538 } 1539 ifp->if_timer = 1; 1540 } 1541 1542 ieee80211_watchdog(&sc->sc_ic); 1543 } 1544 1545 static int 1546 ipw_get_table1(struct ipw_softc *sc, uint32_t *tbl) 1547 { 1548 uint32_t addr, size, i; 1549 1550 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1551 return ENOTTY; 1552 1553 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, sc->table1_base); 1554 1555 size = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 1556 if (suword(tbl, size) != 0) 1557 return EFAULT; 1558 1559 for (i = 1, ++tbl; i < size; i++, tbl++) { 1560 addr = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 1561 if (suword(tbl, MEM_READ_4(sc, addr)) != 0) 1562 return EFAULT; 1563 } 1564 return 0; 1565 } 1566 1567 static int 1568 ipw_get_radio(struct ipw_softc *sc, int *ret) 1569 { 1570 uint32_t addr; 1571 1572 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1573 return ENOTTY; 1574 1575 addr = ipw_read_table1(sc, IPW_INFO_EEPROM_ADDRESS); 1576 if ((MEM_READ_4(sc, addr + 32) >> 24) & 1) { 1577 suword(ret, -1); 1578 return 0; 1579 } 1580 1581 if (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED) 1582 suword(ret, 0); 1583 else 1584 suword(ret, 1); 1585 1586 return 0; 1587 } 1588 1589 static int 1590 ipw_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1591 { 1592 #define IS_RUNNING(ifp) \ 1593 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 1594 1595 struct ipw_softc *sc = ifp->if_softc; 1596 struct ieee80211com *ic = &sc->sc_ic; 1597 struct ifreq *ifr = (struct ifreq *)data; 1598 int s, error = 0; 1599 1600 s = splnet(); 1601 1602 switch (cmd) { 1603 case SIOCSIFFLAGS: 1604 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 1605 break; 1606 if (ifp->if_flags & IFF_UP) { 1607 if (!(ifp->if_flags & IFF_RUNNING)) 1608 ipw_init(ifp); 1609 } else { 1610 if (ifp->if_flags & IFF_RUNNING) 1611 ipw_stop(ifp, 1); 1612 } 1613 break; 1614 1615 case SIOCADDMULTI: 1616 case SIOCDELMULTI: 1617 /* XXX no h/w multicast filter? --dyoung */ 1618 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1619 /* setup multicast filter, etc */ 1620 error = 0; 1621 } 1622 break; 1623 1624 case SIOCGTABLE1: 1625 error = ipw_get_table1(sc, (uint32_t *)ifr->ifr_data); 1626 break; 1627 1628 case SIOCGRADIO: 1629 error = ipw_get_radio(sc, (int *)ifr->ifr_data); 1630 break; 1631 1632 case SIOCSIFMEDIA: 1633 if (ifr->ifr_media & IFM_IEEE80211_ADHOC) 1634 sc->sc_fwname = "ipw2100-1.2-i.fw"; 1635 else if (ifr->ifr_media & IFM_IEEE80211_MONITOR) 1636 sc->sc_fwname = "ipw2100-1.2-p.fw"; 1637 else 1638 sc->sc_fwname = "ipw2100-1.2.fw"; 1639 1640 ipw_free_firmware(sc); 1641 /* FALLTRHOUGH */ 1642 default: 1643 error = ieee80211_ioctl(&sc->sc_ic, cmd, data); 1644 if (error != ENETRESET) 1645 break; 1646 1647 if (error == ENETRESET) { 1648 if (IS_RUNNING(ifp) && 1649 (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)) 1650 ipw_init(ifp); 1651 error = 0; 1652 } 1653 1654 } 1655 1656 splx(s); 1657 return error; 1658 #undef IS_RUNNING 1659 } 1660 1661 static uint32_t 1662 ipw_read_table1(struct ipw_softc *sc, uint32_t off) 1663 { 1664 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 1665 } 1666 1667 static void 1668 ipw_write_table1(struct ipw_softc *sc, uint32_t off, uint32_t info) 1669 { 1670 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 1671 } 1672 1673 static int 1674 ipw_read_table2(struct ipw_softc *sc, uint32_t off, void *buf, uint32_t *len) 1675 { 1676 uint32_t addr, info; 1677 uint16_t count, size; 1678 uint32_t total; 1679 1680 /* addr[4] + count[2] + size[2] */ 1681 addr = MEM_READ_4(sc, sc->table2_base + off); 1682 info = MEM_READ_4(sc, sc->table2_base + off + 4); 1683 1684 count = info >> 16; 1685 size = info & 0xffff; 1686 total = count * size; 1687 1688 if (total > *len) { 1689 *len = total; 1690 return EINVAL; 1691 } 1692 1693 *len = total; 1694 ipw_read_mem_1(sc, addr, buf, total); 1695 1696 return 0; 1697 } 1698 1699 static void 1700 ipw_stop_master(struct ipw_softc *sc) 1701 { 1702 int ntries; 1703 1704 /* disable interrupts */ 1705 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1706 1707 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1708 for (ntries = 0; ntries < 50; ntries++) { 1709 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1710 break; 1711 DELAY(10); 1712 } 1713 if (ntries == 50) 1714 aprint_error_dev(sc->sc_dev, "timeout waiting for master\n"); 1715 1716 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1717 IPW_RST_PRINCETON_RESET); 1718 1719 sc->flags &= ~IPW_FLAG_FW_INITED; 1720 } 1721 1722 static int 1723 ipw_reset(struct ipw_softc *sc) 1724 { 1725 int ntries; 1726 1727 ipw_stop_master(sc); 1728 1729 /* move adapter to D0 state */ 1730 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1731 IPW_CTL_INIT); 1732 1733 /* wait for clock stabilization */ 1734 for (ntries = 0; ntries < 1000; ntries++) { 1735 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY) 1736 break; 1737 DELAY(200); 1738 } 1739 if (ntries == 1000) 1740 return EIO; 1741 1742 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1743 IPW_RST_SW_RESET); 1744 1745 DELAY(10); 1746 1747 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1748 IPW_CTL_INIT); 1749 1750 return 0; 1751 } 1752 1753 /* 1754 * Upload the microcode to the device. 1755 */ 1756 static int 1757 ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size) 1758 { 1759 int ntries; 1760 1761 MEM_WRITE_4(sc, 0x3000e0, 0x80000000); 1762 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1763 1764 MEM_WRITE_2(sc, 0x220000, 0x0703); 1765 MEM_WRITE_2(sc, 0x220000, 0x0707); 1766 1767 MEM_WRITE_1(sc, 0x210014, 0x72); 1768 MEM_WRITE_1(sc, 0x210014, 0x72); 1769 1770 MEM_WRITE_1(sc, 0x210000, 0x40); 1771 MEM_WRITE_1(sc, 0x210000, 0x00); 1772 MEM_WRITE_1(sc, 0x210000, 0x40); 1773 1774 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1775 1776 MEM_WRITE_1(sc, 0x210000, 0x00); 1777 MEM_WRITE_1(sc, 0x210000, 0x00); 1778 MEM_WRITE_1(sc, 0x210000, 0x80); 1779 1780 MEM_WRITE_2(sc, 0x220000, 0x0703); 1781 MEM_WRITE_2(sc, 0x220000, 0x0707); 1782 1783 MEM_WRITE_1(sc, 0x210014, 0x72); 1784 MEM_WRITE_1(sc, 0x210014, 0x72); 1785 1786 MEM_WRITE_1(sc, 0x210000, 0x00); 1787 MEM_WRITE_1(sc, 0x210000, 0x80); 1788 1789 for (ntries = 0; ntries < 10; ntries++) { 1790 if (MEM_READ_1(sc, 0x210000) & 1) 1791 break; 1792 DELAY(10); 1793 } 1794 if (ntries == 10) { 1795 aprint_error_dev(sc->sc_dev, "timeout waiting for ucode to initialize\n"); 1796 return EIO; 1797 } 1798 1799 MEM_WRITE_4(sc, 0x3000e0, 0); 1800 1801 return 0; 1802 } 1803 1804 /* set of macros to handle unaligned little endian data in firmware image */ 1805 #define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1806 #define GETLE16(p) ((p)[0] | (p)[1] << 8) 1807 static int 1808 ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size) 1809 { 1810 u_char *p, *end; 1811 uint32_t dst; 1812 uint16_t len; 1813 int error; 1814 1815 p = fw; 1816 end = fw + size; 1817 while (p < end) { 1818 dst = GETLE32(p); p += 4; 1819 len = GETLE16(p); p += 2; 1820 1821 ipw_write_mem_1(sc, dst, p, len); 1822 p += len; 1823 } 1824 1825 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1826 IPW_IO_LED_OFF); 1827 1828 /* enable interrupts */ 1829 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1830 1831 /* kick the firmware */ 1832 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1833 1834 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1835 IPW_CTL_ALLOW_STANDBY); 1836 1837 /* wait at most one second for firmware initialization to complete */ 1838 if ((error = tsleep(sc, 0, "ipwinit", hz)) != 0) { 1839 aprint_error_dev(sc->sc_dev, "timeout waiting for firmware initialization " 1840 "to complete\n"); 1841 return error; 1842 } 1843 1844 CSR_WRITE_4(sc, IPW_CSR_IO, CSR_READ_4(sc, IPW_CSR_IO) | 1845 IPW_IO_GPIO1_MASK | IPW_IO_GPIO3_MASK); 1846 1847 return 0; 1848 } 1849 1850 /* 1851 * Store firmware into kernel memory so we can download it when we need to, 1852 * e.g when the adapter wakes up from suspend mode. 1853 */ 1854 static int 1855 ipw_cache_firmware(struct ipw_softc *sc) 1856 { 1857 struct ipw_firmware *fw = &sc->fw; 1858 struct ipw_firmware_hdr hdr; 1859 firmware_handle_t fwh; 1860 off_t fwsz, p; 1861 int error; 1862 1863 ipw_free_firmware(sc); 1864 1865 if (ipw_accept_eula == 0) { 1866 aprint_error_dev(sc->sc_dev, 1867 "EULA not accepted; please see the ipw(4) man page.\n"); 1868 return EPERM; 1869 } 1870 1871 if ((error = firmware_open("if_ipw", sc->sc_fwname, &fwh)) != 0) 1872 goto fail0; 1873 1874 fwsz = firmware_get_size(fwh); 1875 1876 if (fwsz < sizeof(hdr)) 1877 goto fail2; 1878 1879 if ((error = firmware_read(fwh, 0, &hdr, sizeof(hdr))) != 0) 1880 goto fail2; 1881 1882 fw->main_size = le32toh(hdr.main_size); 1883 fw->ucode_size = le32toh(hdr.ucode_size); 1884 1885 fw->main = firmware_malloc(fw->main_size); 1886 if (fw->main == NULL) { 1887 error = ENOMEM; 1888 goto fail1; 1889 } 1890 1891 fw->ucode = firmware_malloc(fw->ucode_size); 1892 if (fw->ucode == NULL) { 1893 error = ENOMEM; 1894 goto fail2; 1895 } 1896 1897 p = sizeof(hdr); 1898 if ((error = firmware_read(fwh, p, fw->main, fw->main_size)) != 0) 1899 goto fail3; 1900 1901 p += fw->main_size; 1902 if ((error = firmware_read(fwh, p, fw->ucode, fw->ucode_size)) != 0) 1903 goto fail3; 1904 1905 DPRINTF(("Firmware cached: main %u, ucode %u\n", fw->main_size, 1906 fw->ucode_size)); 1907 1908 sc->flags |= IPW_FLAG_FW_CACHED; 1909 1910 firmware_close(fwh); 1911 1912 return 0; 1913 1914 fail3: firmware_free(fw->ucode, 0); 1915 fail2: firmware_free(fw->main, 0); 1916 fail1: firmware_close(fwh); 1917 fail0: 1918 return error; 1919 } 1920 1921 static void 1922 ipw_free_firmware(struct ipw_softc *sc) 1923 { 1924 if (!(sc->flags & IPW_FLAG_FW_CACHED)) 1925 return; 1926 1927 firmware_free(sc->fw.main, 0); 1928 firmware_free(sc->fw.ucode, 0); 1929 1930 sc->flags &= ~IPW_FLAG_FW_CACHED; 1931 } 1932 1933 static int 1934 ipw_config(struct ipw_softc *sc) 1935 { 1936 struct ieee80211com *ic = &sc->sc_ic; 1937 struct ifnet *ifp = &sc->sc_if; 1938 struct ipw_security security; 1939 struct ieee80211_key *k; 1940 struct ipw_wep_key wepkey; 1941 struct ipw_scan_options options; 1942 struct ipw_configuration config; 1943 uint32_t data; 1944 int error, i; 1945 1946 switch (ic->ic_opmode) { 1947 case IEEE80211_M_STA: 1948 case IEEE80211_M_HOSTAP: 1949 data = htole32(IPW_MODE_BSS); 1950 break; 1951 1952 case IEEE80211_M_IBSS: 1953 case IEEE80211_M_AHDEMO: 1954 data = htole32(IPW_MODE_IBSS); 1955 break; 1956 1957 case IEEE80211_M_MONITOR: 1958 data = htole32(IPW_MODE_MONITOR); 1959 break; 1960 } 1961 DPRINTF(("Setting mode to %u\n", le32toh(data))); 1962 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 1963 if (error != 0) 1964 return error; 1965 1966 if (ic->ic_opmode == IEEE80211_M_IBSS || 1967 ic->ic_opmode == IEEE80211_M_MONITOR) { 1968 data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); 1969 DPRINTF(("Setting channel to %u\n", le32toh(data))); 1970 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 1971 if (error != 0) 1972 return error; 1973 } 1974 1975 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1976 DPRINTF(("Enabling adapter\n")); 1977 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1978 } 1979 1980 DPRINTF(("Setting MAC to %s\n", ether_sprintf(ic->ic_myaddr))); 1981 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 1982 IEEE80211_ADDR_LEN); 1983 if (error != 0) 1984 return error; 1985 1986 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 1987 IPW_CFG_PREAMBLE_AUTO | IPW_CFG_802_1x_ENABLE); 1988 1989 if (ic->ic_opmode == IEEE80211_M_IBSS) 1990 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 1991 if (ifp->if_flags & IFF_PROMISC) 1992 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 1993 config.bss_chan = htole32(0x3fff); /* channels 1-14 */ 1994 config.ibss_chan = htole32(0x7ff); /* channels 1-11 */ 1995 DPRINTF(("Setting adapter configuration 0x%08x\n", config.flags)); 1996 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 1997 if (error != 0) 1998 return error; 1999 2000 data = htole32(0x3); /* 1, 2 */ 2001 DPRINTF(("Setting basic tx rates to 0x%x\n", le32toh(data))); 2002 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 2003 if (error != 0) 2004 return error; 2005 2006 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 2007 DPRINTF(("Setting tx rates to 0x%x\n", le32toh(data))); 2008 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 2009 if (error != 0) 2010 return error; 2011 2012 data = htole32(IPW_POWER_MODE_CAM); 2013 DPRINTF(("Setting power mode to %u\n", le32toh(data))); 2014 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 2015 if (error != 0) 2016 return error; 2017 2018 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2019 data = htole32(32); /* default value */ 2020 DPRINTF(("Setting tx power index to %u\n", le32toh(data))); 2021 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 2022 sizeof data); 2023 if (error != 0) 2024 return error; 2025 } 2026 2027 data = htole32(ic->ic_rtsthreshold); 2028 DPRINTF(("Setting RTS threshold to %u\n", le32toh(data))); 2029 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 2030 if (error != 0) 2031 return error; 2032 2033 data = htole32(ic->ic_fragthreshold); 2034 DPRINTF(("Setting frag threshold to %u\n", le32toh(data))); 2035 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 2036 if (error != 0) 2037 return error; 2038 2039 #ifdef IPW_DEBUG 2040 if (ipw_debug > 0) { 2041 printf("Setting ESSID to "); 2042 ieee80211_print_essid(ic->ic_des_essid, ic->ic_des_esslen); 2043 printf("\n"); 2044 } 2045 #endif 2046 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ic->ic_des_essid, 2047 ic->ic_des_esslen); 2048 if (error != 0) 2049 return error; 2050 2051 /* no mandatory BSSID */ 2052 DPRINTF(("Setting mandatory BSSID to null\n")); 2053 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 2054 if (error != 0) 2055 return error; 2056 2057 if (ic->ic_flags & IEEE80211_F_DESBSSID) { 2058 DPRINTF(("Setting desired BSSID to %s\n", 2059 ether_sprintf(ic->ic_des_bssid))); 2060 error = ipw_cmd(sc, IPW_CMD_SET_DESIRED_BSSID, 2061 ic->ic_des_bssid, IEEE80211_ADDR_LEN); 2062 if (error != 0) 2063 return error; 2064 } 2065 2066 (void)memset(&security, 0, sizeof(security)); 2067 security.authmode = (ic->ic_bss->ni_authmode == IEEE80211_AUTH_SHARED) ? 2068 IPW_AUTH_SHARED : IPW_AUTH_OPEN; 2069 security.ciphers = htole32(IPW_CIPHER_NONE); 2070 DPRINTF(("Setting authmode to %u\n", security.authmode)); 2071 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 2072 sizeof security); 2073 if (error != 0) 2074 return error; 2075 2076 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 2077 k = ic->ic_crypto.cs_nw_keys; 2078 for (i = 0; i < IEEE80211_WEP_NKID; i++, k++) { 2079 if (k->wk_keylen == 0) 2080 continue; 2081 2082 wepkey.idx = i; 2083 wepkey.len = k->wk_keylen; 2084 memset(wepkey.key, 0, sizeof(wepkey.key)); 2085 memcpy(wepkey.key, k->wk_key, k->wk_keylen); 2086 DPRINTF(("Setting wep key index %u len %u\n", 2087 wepkey.idx, wepkey.len)); 2088 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY, &wepkey, 2089 sizeof wepkey); 2090 if (error != 0) 2091 return error; 2092 } 2093 2094 data = htole32(ic->ic_crypto.cs_def_txkey); 2095 DPRINTF(("Setting tx key index to %u\n", le32toh(data))); 2096 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY_INDEX, &data, 2097 sizeof data); 2098 if (error != 0) 2099 return error; 2100 } 2101 2102 data = htole32((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) ? IPW_WEPON : 0); 2103 DPRINTF(("Setting wep flags to 0x%x\n", le32toh(data))); 2104 error = ipw_cmd(sc, IPW_CMD_SET_WEP_FLAGS, &data, sizeof data); 2105 if (error != 0) 2106 return error; 2107 2108 #if 0 2109 struct ipw_wpa_ie ie; 2110 2111 memset(&ie, 0 sizeof(ie)); 2112 ie.len = htole32(sizeof (struct ieee80211_ie_wpa)); 2113 DPRINTF(("Setting wpa ie\n")); 2114 error = ipw_cmd(sc, IPW_CMD_SET_WPA_IE, &ie, sizeof ie); 2115 if (error != 0) 2116 return error; 2117 #endif 2118 2119 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2120 data = htole32(ic->ic_bintval); 2121 DPRINTF(("Setting beacon interval to %u\n", le32toh(data))); 2122 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 2123 sizeof data); 2124 if (error != 0) 2125 return error; 2126 } 2127 2128 options.flags = 0; 2129 options.channels = htole32(0x3fff); /* scan channels 1-14 */ 2130 DPRINTF(("Setting scan options to 0x%x\n", le32toh(options.flags))); 2131 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &options, sizeof options); 2132 if (error != 0) 2133 return error; 2134 2135 /* finally, enable adapter (start scanning for an access point) */ 2136 DPRINTF(("Enabling adapter\n")); 2137 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 2138 } 2139 2140 static int 2141 ipw_init(struct ifnet *ifp) 2142 { 2143 struct ipw_softc *sc = ifp->if_softc; 2144 struct ipw_firmware *fw = &sc->fw; 2145 2146 if (!(sc->flags & IPW_FLAG_FW_CACHED)) { 2147 if (ipw_cache_firmware(sc) != 0) { 2148 aprint_error_dev(sc->sc_dev, "could not cache the firmware (%s)\n", 2149 sc->sc_fwname); 2150 goto fail; 2151 } 2152 } 2153 2154 ipw_stop(ifp, 0); 2155 2156 if (ipw_reset(sc) != 0) { 2157 aprint_error_dev(sc->sc_dev, "could not reset adapter\n"); 2158 goto fail; 2159 } 2160 2161 if (ipw_load_ucode(sc, fw->ucode, fw->ucode_size) != 0) { 2162 aprint_error_dev(sc->sc_dev, "could not load microcode\n"); 2163 goto fail; 2164 } 2165 2166 ipw_stop_master(sc); 2167 2168 /* 2169 * Setup tx, rx and status rings. 2170 */ 2171 sc->txold = IPW_NTBD - 1; 2172 sc->txcur = 0; 2173 sc->txfree = IPW_NTBD - 2; 2174 sc->rxcur = IPW_NRBD - 1; 2175 2176 CSR_WRITE_4(sc, IPW_CSR_TX_BASE, sc->tbd_map->dm_segs[0].ds_addr); 2177 CSR_WRITE_4(sc, IPW_CSR_TX_SIZE, IPW_NTBD); 2178 CSR_WRITE_4(sc, IPW_CSR_TX_READ, 0); 2179 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 2180 2181 CSR_WRITE_4(sc, IPW_CSR_RX_BASE, sc->rbd_map->dm_segs[0].ds_addr); 2182 CSR_WRITE_4(sc, IPW_CSR_RX_SIZE, IPW_NRBD); 2183 CSR_WRITE_4(sc, IPW_CSR_RX_READ, 0); 2184 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 2185 2186 CSR_WRITE_4(sc, IPW_CSR_STATUS_BASE, sc->status_map->dm_segs[0].ds_addr); 2187 2188 if (ipw_load_firmware(sc, fw->main, fw->main_size) != 0) { 2189 aprint_error_dev(sc->sc_dev, "could not load firmware\n"); 2190 goto fail; 2191 } 2192 2193 sc->flags |= IPW_FLAG_FW_INITED; 2194 2195 /* retrieve information tables base addresses */ 2196 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 2197 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 2198 2199 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 2200 2201 if (ipw_config(sc) != 0) { 2202 aprint_error_dev(sc->sc_dev, "device configuration failed\n"); 2203 goto fail; 2204 } 2205 2206 ifp->if_flags &= ~IFF_OACTIVE; 2207 ifp->if_flags |= IFF_RUNNING; 2208 2209 return 0; 2210 2211 fail: ifp->if_flags &= ~IFF_UP; 2212 ipw_stop(ifp, 0); 2213 2214 return EIO; 2215 } 2216 2217 static void 2218 ipw_stop(struct ifnet *ifp, int disable) 2219 { 2220 struct ipw_softc *sc = ifp->if_softc; 2221 struct ieee80211com *ic = &sc->sc_ic; 2222 int i; 2223 2224 ipw_stop_master(sc); 2225 2226 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 2227 2228 /* 2229 * Release tx buffers. 2230 */ 2231 for (i = 0; i < IPW_NTBD; i++) 2232 ipw_release_sbd(sc, &sc->stbd_list[i]); 2233 2234 sc->sc_tx_timer = 0; 2235 ifp->if_timer = 0; 2236 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2237 2238 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2239 } 2240 2241 static void 2242 ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2243 bus_size_t count) 2244 { 2245 for (; count > 0; offset++, datap++, count--) { 2246 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2247 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 2248 } 2249 } 2250 2251 static void 2252 ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2253 bus_size_t count) 2254 { 2255 for (; count > 0; offset++, datap++, count--) { 2256 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2257 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 2258 } 2259 } 2260 2261 SYSCTL_SETUP(sysctl_hw_ipw_accept_eula_setup, "sysctl hw.ipw.accept_eula") 2262 { 2263 const struct sysctlnode *rnode; 2264 const struct sysctlnode *cnode; 2265 2266 sysctl_createv(NULL, 0, NULL, &rnode, 2267 CTLFLAG_PERMANENT, 2268 CTLTYPE_NODE, "ipw", 2269 NULL, 2270 NULL, 0, 2271 NULL, 0, 2272 CTL_HW, CTL_CREATE, CTL_EOL); 2273 2274 sysctl_createv(NULL, 0, &rnode, &cnode, 2275 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, 2276 CTLTYPE_INT, "accept_eula", 2277 SYSCTL_DESCR("Accept Intel EULA and permit use of ipw(4) firmware"), 2278 NULL, 0, 2279 &ipw_accept_eula, sizeof(ipw_accept_eula), 2280 CTL_CREATE, CTL_EOL); 2281 } 2282
Indexes created Tue Sep 30 17:09:57 GMT 2025