if_ipw.c revision 1.6
1 /* $NetBSD: if_ipw.c,v 1.6 2004/09/14 00:34:19 lukem Exp $ */ 2 /* Id: if_ipw.c,v 1.1.2.7 2004/08/20 11:20:11 damien Exp */ 3 4 /*- 5 * Copyright (c) 2004 6 * Damien Bergamini <damien.bergamini (at) free.fr>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: if_ipw.c,v 1.6 2004/09/14 00:34:19 lukem Exp $"); 33 34 /*- 35 * Intel(R) PRO/Wireless 2100 MiniPCI driver 36 * http://www.intel.com/products/mobiletechnology/prowireless.htm 37 */ 38 39 #include "bpfilter.h" 40 41 #include <sys/param.h> 42 #include <sys/sockio.h> 43 #include <sys/sysctl.h> 44 #include <sys/mbuf.h> 45 #include <sys/kernel.h> 46 #include <sys/socket.h> 47 #include <sys/systm.h> 48 #include <sys/malloc.h> 49 #include <sys/conf.h> 50 51 #include <machine/bus.h> 52 #include <machine/endian.h> 53 #include <machine/intr.h> 54 55 #include <dev/pci/pcireg.h> 56 #include <dev/pci/pcivar.h> 57 #include <dev/pci/pcidevs.h> 58 59 #if NBPFILTER > 0 60 #include <net/bpf.h> 61 #endif 62 #include <net/if.h> 63 #include <net/if_arp.h> 64 #include <net/if_dl.h> 65 #include <net/if_ether.h> 66 #include <net/if_media.h> 67 #include <net/if_types.h> 68 69 #include <net80211/ieee80211_var.h> 70 #include <net80211/ieee80211_radiotap.h> 71 72 #include <netinet/in.h> 73 #include <netinet/in_systm.h> 74 #include <netinet/in_var.h> 75 #include <netinet/ip.h> 76 77 #include <dev/pci/if_ipwreg.h> 78 #include <dev/pci/if_ipwvar.h> 79 80 static int ipw_match(struct device *, struct cfdata *, void *); 81 static void ipw_attach(struct device *, struct device *, void *); 82 static int ipw_detach(struct device *, int); 83 static int ipw_media_change(struct ifnet *); 84 static int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 85 static void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 86 static void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 87 static void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 88 struct ipw_soft_bd *, struct ipw_soft_buf *); 89 static void ipw_notification_intr(struct ipw_softc *, struct ipw_soft_buf *); 90 static void ipw_rx_intr(struct ipw_softc *); 91 static void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 92 static void ipw_tx_intr(struct ipw_softc *); 93 static int ipw_intr(void *); 94 static int ipw_cmd(struct ipw_softc *, u_int32_t, void *, u_int32_t); 95 static int ipw_tx_start(struct ifnet *, struct mbuf *, struct ieee80211_node *); 96 static void ipw_start(struct ifnet *); 97 static void ipw_watchdog(struct ifnet *); 98 static int ipw_get_table1(struct ipw_softc *, u_int32_t *); 99 static int ipw_get_radio(struct ipw_softc *, int *); 100 static int ipw_ioctl(struct ifnet *, u_long, caddr_t); 101 static u_int32_t ipw_read_table1(struct ipw_softc *, u_int32_t); 102 static void ipw_write_table1(struct ipw_softc *, u_int32_t, u_int32_t); 103 static int ipw_read_table2(struct ipw_softc *, u_int32_t, void *, u_int32_t *); 104 static int ipw_tx_init(struct ipw_softc *); 105 static void ipw_tx_stop(struct ipw_softc *); 106 static int ipw_rx_init(struct ipw_softc *); 107 static void ipw_rx_stop(struct ipw_softc *); 108 static void ipw_reset(struct ipw_softc *); 109 static int ipw_clock_sync(struct ipw_softc *); 110 static int ipw_load_ucode(struct ipw_softc *, u_char *, int); 111 static int ipw_load_firmware(struct ipw_softc *, u_char *, int); 112 static int ipw_firmware_init(struct ipw_softc *, u_char *); 113 static int ipw_config(struct ipw_softc *); 114 static int ipw_init(struct ifnet *); 115 static void ipw_stop(struct ifnet *, int); 116 static void ipw_read_mem_1(struct ipw_softc *, bus_size_t, u_int8_t *, 117 bus_size_t); 118 static void ipw_write_mem_1(struct ipw_softc *, bus_size_t, u_int8_t *, 119 bus_size_t); 120 static void ipw_zero_mem_4(struct ipw_softc *, bus_size_t, bus_size_t); 121 122 static inline u_int8_t MEM_READ_1(struct ipw_softc *sc, u_int32_t addr) 123 { 124 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 125 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); 126 } 127 128 static inline u_int16_t MEM_READ_2(struct ipw_softc *sc, u_int32_t addr) 129 { 130 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 131 return CSR_READ_2(sc, IPW_CSR_INDIRECT_DATA); 132 } 133 134 static inline u_int32_t MEM_READ_4(struct ipw_softc *sc, u_int32_t addr) 135 { 136 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 137 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); 138 } 139 140 #ifdef IPW_DEBUG 141 #define DPRINTF(x) if (ipw_debug > 0) printf x 142 #define DPRINTFN(n, x) if (ipw_debug >= (n)) printf x 143 int ipw_debug = 0; 144 #else 145 #define DPRINTF(x) 146 #define DPRINTFN(n, x) 147 #endif 148 149 CFATTACH_DECL(ipw, sizeof (struct ipw_softc), ipw_match, ipw_attach, 150 ipw_detach, NULL); 151 152 static int 153 ipw_match(struct device *parent, struct cfdata *match, void *aux) 154 { 155 struct pci_attach_args *pa = aux; 156 157 if (PCI_VENDOR (pa->pa_id) == PCI_VENDOR_INTEL && 158 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_PRO_WL_2100) 159 return 1; 160 161 return 0; 162 } 163 164 /* Base Address Register */ 165 #define IPW_PCI_BAR0 0x10 166 167 static void 168 ipw_attach(struct device *parent, struct device *self, void *aux) 169 { 170 struct ipw_softc *sc = (struct ipw_softc *)self; 171 struct ieee80211com *ic = &sc->sc_ic; 172 struct ifnet *ifp = &ic->ic_if; 173 struct ieee80211_rateset *rs; 174 struct pci_attach_args *pa = aux; 175 const char *intrstr; 176 char devinfo[256]; 177 bus_space_tag_t memt; 178 bus_space_handle_t memh; 179 bus_addr_t base; 180 pci_intr_handle_t ih; 181 u_int32_t data; 182 int i, revision, error; 183 184 sc->sc_pct = pa->pa_pc; 185 186 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof devinfo); 187 revision = PCI_REVISION(pa->pa_class); 188 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, revision); 189 190 /* enable bus-mastering */ 191 data = pci_conf_read(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG); 192 data |= PCI_COMMAND_MASTER_ENABLE; 193 pci_conf_write(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG, data); 194 195 /* map the register window */ 196 error = pci_mapreg_map(pa, IPW_PCI_BAR0, PCI_MAPREG_TYPE_MEM | 197 PCI_MAPREG_MEM_TYPE_32BIT, 0, &memt, &memh, &base, &sc->sc_sz); 198 if (error != 0) { 199 aprint_error("%s: could not map memory space\n", 200 sc->sc_dev.dv_xname); 201 return; 202 } 203 204 sc->sc_st = memt; 205 sc->sc_sh = memh; 206 sc->sc_dmat = pa->pa_dmat; 207 208 /* disable interrupts */ 209 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 210 211 if (pci_intr_map(pa, &ih) != 0) { 212 aprint_error("%s: could not map interrupt\n", 213 sc->sc_dev.dv_xname); 214 return; 215 } 216 217 intrstr = pci_intr_string(sc->sc_pct, ih); 218 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, ipw_intr, sc); 219 if (sc->sc_ih == NULL) { 220 aprint_error("%s: could not establish interrupt", 221 sc->sc_dev.dv_xname); 222 if (intrstr != NULL) 223 aprint_error(" at %s", intrstr); 224 aprint_error("\n"); 225 return; 226 } 227 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 228 229 ic->ic_phytype = IEEE80211_T_DS; 230 ic->ic_opmode = IEEE80211_M_STA; 231 ic->ic_state = IEEE80211_S_INIT; 232 233 /* set device capabilities */ 234 ic->ic_caps = IEEE80211_C_IBSS | IEEE80211_C_MONITOR | 235 IEEE80211_C_PMGT | IEEE80211_C_TXPMGT | IEEE80211_C_WEP; 236 237 /* set supported 11.b rates */ 238 rs = &ic->ic_sup_rates[IEEE80211_MODE_11B]; 239 rs->rs_nrates = 4; 240 rs->rs_rates[0] = 2; /* 1Mbps */ 241 rs->rs_rates[1] = 4; /* 2Mbps */ 242 rs->rs_rates[2] = 11; /* 5.5Mbps */ 243 rs->rs_rates[3] = 22; /* 11Mbps */ 244 245 /* set supported 11.b channels (1 through 14) */ 246 for (i = 1; i <= 14; i++) { 247 ic->ic_channels[i].ic_freq = 248 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 249 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 250 } 251 252 ic->ic_ibss_chan = &ic->ic_channels[0]; 253 254 ifp->if_softc = sc; 255 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 256 ifp->if_init = ipw_init; 257 ifp->if_stop = ipw_stop; 258 ifp->if_ioctl = ipw_ioctl; 259 ifp->if_start = ipw_start; 260 ifp->if_watchdog = ipw_watchdog; 261 IFQ_SET_READY(&ifp->if_snd); 262 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 263 264 if_attach(ifp); 265 ieee80211_ifattach(ifp); 266 /* override state transition machine */ 267 sc->sc_newstate = ic->ic_newstate; 268 ic->ic_newstate = ipw_newstate; 269 270 ieee80211_media_init(ifp, ipw_media_change, ieee80211_media_status); 271 272 #if NBPFILTER > 0 273 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 274 sizeof (struct ieee80211_frame) + 64, &sc->sc_drvbpf); 275 276 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 277 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 278 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 279 280 sc->sc_txtap_len = sizeof sc->sc_txtapu; 281 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 282 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 283 #endif 284 } 285 286 static int 287 ipw_detach(struct device* self, int flags) 288 { 289 struct ipw_softc *sc = (struct ipw_softc *)self; 290 struct ifnet *ifp = &sc->sc_ic.ic_if; 291 292 ipw_reset(sc); 293 294 #if NBPFILTER > 0 295 bpfdetach(ifp); 296 #endif 297 ieee80211_ifdetach(ifp); 298 if_detach(ifp); 299 300 if (sc->sc_ih != NULL) { 301 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 302 sc->sc_ih = NULL; 303 } 304 305 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 306 307 return 0; 308 } 309 310 static int 311 ipw_media_change(struct ifnet *ifp) 312 { 313 int error; 314 315 error = ieee80211_media_change(ifp); 316 if (error != ENETRESET) 317 return error; 318 319 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 320 ipw_init(ifp); 321 322 return 0; 323 } 324 325 static int 326 ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 327 { 328 struct ifnet *ifp = &ic->ic_if; 329 struct ipw_softc *sc = ifp->if_softc; 330 struct ieee80211_node *ni = ic->ic_bss; 331 u_int32_t val, len; 332 333 switch (nstate) { 334 case IEEE80211_S_INIT: 335 break; 336 337 case IEEE80211_S_RUN: 338 len = IEEE80211_NWID_LEN; 339 ipw_read_table2(sc, IPW_INFO_CURRENT_SSID, ni->ni_essid, &len); 340 ni->ni_esslen = len; 341 342 val = ipw_read_table1(sc, IPW_INFO_CURRENT_CHANNEL); 343 ni->ni_chan = &ic->ic_channels[val]; 344 345 DELAY(100); /* firmware needs a short delay here */ 346 347 len = IEEE80211_ADDR_LEN; 348 ipw_read_table2(sc, IPW_INFO_CURRENT_BSSID, ni->ni_bssid, &len); 349 break; 350 351 case IEEE80211_S_SCAN: 352 case IEEE80211_S_AUTH: 353 case IEEE80211_S_ASSOC: 354 break; 355 } 356 357 ic->ic_state = nstate; 358 return 0; 359 } 360 361 static void 362 ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 363 { 364 struct ipw_cmd *cmd; 365 366 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof (struct ipw_cmd), 367 BUS_DMASYNC_POSTREAD); 368 369 cmd = mtod(sbuf->m, struct ipw_cmd *); 370 371 DPRINTFN(2, ("RX!CMD!%u!%u!%u!%u!%u\n", 372 le32toh(cmd->type), le32toh(cmd->subtype), le32toh(cmd->seq), 373 le32toh(cmd->len), le32toh(cmd->status))); 374 375 /* 376 * Wake up processes waiting for command ack. In the case of the 377 * IPW_CMD_DISABLE command, wake up the process only when the adapter 378 * enters the IPW_STATE_DISABLED state. This is notified in 379 * ipw_newstate_intr(). 380 */ 381 if (le32toh(cmd->type) != IPW_CMD_DISABLE) 382 wakeup(sc->cmd); 383 } 384 385 static void 386 ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 387 { 388 struct ieee80211com *ic = &sc->sc_ic; 389 u_int32_t state; 390 391 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof state, 392 BUS_DMASYNC_POSTREAD); 393 394 state = le32toh(*mtod(sbuf->m, u_int32_t *)); 395 396 DPRINTFN(2, ("RX!NEWSTATE!%u\n", state)); 397 398 switch (state) { 399 case IPW_STATE_ASSOCIATED: 400 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 401 break; 402 403 case IPW_STATE_SCANNING: 404 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 405 break; 406 407 case IPW_STATE_ASSOCIATION_LOST: 408 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 409 break; 410 411 case IPW_STATE_DISABLED: 412 wakeup(sc->cmd); 413 break; 414 415 case IPW_STATE_RADIO_DISABLED: 416 /* XXX should turn the interface down */ 417 break; 418 } 419 } 420 421 static void 422 ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 423 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 424 { 425 struct ieee80211com *ic = &sc->sc_ic; 426 struct ifnet *ifp = &ic->ic_if; 427 struct mbuf *m; 428 struct ieee80211_frame *wh; 429 struct ieee80211_node *ni; 430 int error; 431 432 DPRINTFN(5, ("RX!DATA!%u!%u\n", le32toh(status->len), status->rssi)); 433 434 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, le32toh(status->len), 435 BUS_DMASYNC_POSTREAD); 436 437 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 438 439 /* Finalize mbuf */ 440 m = sbuf->m; 441 m->m_pkthdr.rcvif = ifp; 442 m->m_pkthdr.len = m->m_len = le32toh(status->len); 443 444 #if NBPFILTER > 0 445 if (sc->sc_drvbpf != NULL) { 446 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 447 448 tap->wr_flags = 0; 449 tap->wr_antsignal = status->rssi; 450 tap->wr_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 451 tap->wr_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 452 453 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 454 } 455 #endif 456 457 wh = mtod(m, struct ieee80211_frame *); 458 459 if (ic->ic_opmode != IEEE80211_M_STA) { 460 ni = ieee80211_find_node(ic, wh->i_addr2); 461 if (ni == NULL) 462 ni = ieee80211_ref_node(ic->ic_bss); 463 } else 464 ni = ieee80211_ref_node(ic->ic_bss); 465 466 /* Send it up to the upper layer */ 467 ieee80211_input(ifp, m, ni, status->rssi, 0/*rstamp*/); 468 469 ieee80211_release_node(ic, ni); 470 471 MGETHDR(m, M_DONTWAIT, MT_DATA); 472 if (m == NULL) { 473 aprint_error("%s: could not allocate rx mbuf\n", 474 sc->sc_dev.dv_xname); 475 return; 476 } 477 MCLGET(m, M_DONTWAIT); 478 if (!(m->m_flags & M_EXT)) { 479 m_freem(m); 480 aprint_error("%s: could not allocate rx mbuf cluster\n", 481 sc->sc_dev.dv_xname); 482 return; 483 } 484 485 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, mtod(m, void *), 486 MCLBYTES, NULL, BUS_DMA_NOWAIT); 487 if (error != 0) { 488 aprint_error("%s: could not map rxbuf dma memory\n", 489 sc->sc_dev.dv_xname); 490 m_freem(m); 491 return; 492 } 493 494 sbuf->m = m; 495 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 496 } 497 498 static void 499 ipw_notification_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 500 { 501 DPRINTFN(2, ("RX!NOTIFICATION\n")); 502 } 503 504 static void 505 ipw_rx_intr(struct ipw_softc *sc) 506 { 507 struct ipw_status *status; 508 struct ipw_soft_bd *sbd; 509 struct ipw_soft_buf *sbuf; 510 u_int32_t r, i; 511 512 r = CSR_READ_4(sc, IPW_CSR_RX_READ_INDEX); 513 514 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 515 516 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 517 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 518 BUS_DMASYNC_POSTREAD); 519 520 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 521 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 522 BUS_DMASYNC_POSTREAD); 523 524 status = &sc->status_list[i]; 525 sbd = &sc->srbd_list[i]; 526 sbuf = sbd->priv; 527 528 switch (le16toh(status->code) & 0xf) { 529 case IPW_STATUS_CODE_COMMAND: 530 ipw_command_intr(sc, sbuf); 531 break; 532 533 case IPW_STATUS_CODE_NEWSTATE: 534 ipw_newstate_intr(sc, sbuf); 535 break; 536 537 case IPW_STATUS_CODE_DATA_802_3: 538 case IPW_STATUS_CODE_DATA_802_11: 539 ipw_data_intr(sc, status, sbd, sbuf); 540 break; 541 542 case IPW_STATUS_CODE_NOTIFICATION: 543 ipw_notification_intr(sc, sbuf); 544 break; 545 546 default: 547 aprint_debug("%s: unknown status code %u\n", 548 sc->sc_dev.dv_xname, le16toh(status->code)); 549 } 550 sbd->bd->flags = 0; 551 552 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 553 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 554 BUS_DMASYNC_PREWRITE); 555 } 556 557 /* Tell the firmware what we have processed */ 558 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 559 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE_INDEX, sc->rxcur); 560 } 561 562 static void 563 ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 564 { 565 struct ieee80211com *ic; 566 struct ipw_soft_hdr *shdr; 567 struct ipw_soft_buf *sbuf; 568 569 switch (sbd->type) { 570 case IPW_SBD_TYPE_COMMAND: 571 bus_dmamap_unload(sc->sc_dmat, sc->cmd_map); 572 break; 573 574 case IPW_SBD_TYPE_HEADER: 575 shdr = sbd->priv; 576 bus_dmamap_unload(sc->sc_dmat, shdr->map); 577 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 578 break; 579 580 case IPW_SBD_TYPE_DATA: 581 ic = &sc->sc_ic; 582 sbuf = sbd->priv; 583 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 584 m_freem(sbuf->m); 585 if (sbuf->ni != NULL) 586 ieee80211_release_node(ic, sbuf->ni); 587 /* kill watchdog timer */ 588 sc->sc_tx_timer = 0; 589 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 590 break; 591 } 592 sbd->type = IPW_SBD_TYPE_NOASSOC; 593 } 594 595 static void 596 ipw_tx_intr(struct ipw_softc *sc) 597 { 598 struct ifnet *ifp = &sc->sc_ic.ic_if; 599 u_int32_t r, i; 600 601 r = CSR_READ_4(sc, IPW_CSR_TX_READ_INDEX); 602 603 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) 604 ipw_release_sbd(sc, &sc->stbd_list[i]); 605 606 /* Remember what the firmware has processed */ 607 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 608 609 /* Call start() since some buffer descriptors have been released */ 610 ifp->if_flags &= ~IFF_OACTIVE; 611 (*ifp->if_start)(ifp); 612 } 613 614 static int 615 ipw_intr(void *arg) 616 { 617 struct ipw_softc *sc = arg; 618 u_int32_t r; 619 620 if ((r = CSR_READ_4(sc, IPW_CSR_INTR)) == 0) 621 return 0; 622 623 /* Disable interrupts */ 624 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 625 626 DPRINTFN(8, ("INTR!0x%08x\n", r)); 627 628 if (r & IPW_INTR_RX_TRANSFER) 629 ipw_rx_intr(sc); 630 631 if (r & IPW_INTR_TX_TRANSFER) 632 ipw_tx_intr(sc); 633 634 if (r & IPW_INTR_FW_INIT_DONE) { 635 if (!(r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR))) 636 wakeup(sc); 637 } 638 639 /* Acknowledge interrupts */ 640 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 641 642 /* Re-enable interrupts */ 643 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 644 645 return 0; 646 } 647 648 static int 649 ipw_cmd(struct ipw_softc *sc, u_int32_t type, void *data, u_int32_t len) 650 { 651 struct ipw_soft_bd *sbd; 652 int error; 653 654 sbd = &sc->stbd_list[sc->txcur]; 655 656 error = bus_dmamap_load(sc->sc_dmat, sc->cmd_map, sc->cmd, 657 sizeof (struct ipw_cmd), NULL, BUS_DMA_NOWAIT); 658 if (error != 0) { 659 aprint_error("%s: could not map cmd dma memory\n", 660 sc->sc_dev.dv_xname); 661 return error; 662 } 663 664 sc->cmd->type = htole32(type); 665 sc->cmd->subtype = htole32(0); 666 sc->cmd->len = htole32(len); 667 sc->cmd->seq = htole32(0); 668 if (data != NULL) 669 bcopy(data, sc->cmd->data, len); 670 671 sbd->type = IPW_SBD_TYPE_COMMAND; 672 sbd->bd->physaddr = htole32(sc->cmd_map->dm_segs[0].ds_addr); 673 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 674 sbd->bd->nfrag = 1; 675 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 676 IPW_BD_FLAG_TX_LAST_FRAGMENT; 677 678 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 0, sizeof (struct ipw_cmd), 679 BUS_DMASYNC_PREWRITE); 680 681 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 682 sc->txcur * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 683 BUS_DMASYNC_PREWRITE); 684 685 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 686 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, sc->txcur); 687 688 DPRINTFN(2, ("TX!CMD!%u!%u!%u!%u\n", type, 0, 0, len)); 689 690 /* Wait at most two seconds for command to complete */ 691 return tsleep(sc->cmd, 0, "ipwcmd", 2 * hz); 692 } 693 694 static int 695 ipw_tx_start(struct ifnet *ifp, struct mbuf *m, struct ieee80211_node *ni) 696 { 697 struct ipw_softc *sc = ifp->if_softc; 698 struct ieee80211com *ic = &sc->sc_ic; 699 struct ieee80211_frame *wh; 700 struct ipw_soft_bd *sbd; 701 struct ipw_soft_hdr *shdr; 702 struct ipw_soft_buf *sbuf; 703 int error, i; 704 705 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 706 m = ieee80211_wep_crypt(ifp, m, 1); 707 if (m == NULL) 708 return ENOBUFS; 709 } 710 711 #if NBPFILTER > 0 712 if (sc->sc_drvbpf != NULL) { 713 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 714 715 tap->wt_flags = 0; 716 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 717 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 718 719 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m); 720 } 721 #endif 722 723 wh = mtod(m, struct ieee80211_frame *); 724 725 shdr = TAILQ_FIRST(&sc->sc_free_shdr); 726 sbuf = TAILQ_FIRST(&sc->sc_free_sbuf); 727 728 shdr->hdr.type = htole32(IPW_HDR_TYPE_SEND); 729 shdr->hdr.subtype = htole32(0); 730 shdr->hdr.encrypted = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0; 731 shdr->hdr.encrypt = 0; 732 shdr->hdr.keyidx = 0; 733 shdr->hdr.keysz = 0; 734 shdr->hdr.fragmentsz = htole16(0); 735 IEEE80211_ADDR_COPY(shdr->hdr.src_addr, wh->i_addr2); 736 if (ic->ic_opmode == IEEE80211_M_STA) 737 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr3); 738 else 739 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr1); 740 741 /* trim IEEE802.11 header */ 742 m_adj(m, sizeof (struct ieee80211_frame)); 743 744 /* 745 * We need to map the mbuf first to know how many buffer descriptors 746 * are needed for this transfer. 747 */ 748 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m, BUS_DMA_NOWAIT); 749 if (error != 0) { 750 aprint_error("%s: could not map mbuf (error %d)\n", 751 sc->sc_dev.dv_xname, error); 752 m_freem(m); 753 return error; 754 } 755 756 error = bus_dmamap_load(sc->sc_dmat, shdr->map, &shdr->hdr, 757 sizeof (struct ipw_hdr), NULL, BUS_DMA_NOWAIT); 758 if (error != 0) { 759 aprint_error("%s: could not map hdr (error %d)\n", 760 sc->sc_dev.dv_xname, error); 761 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 762 m_freem(m); 763 return error; 764 } 765 766 TAILQ_REMOVE(&sc->sc_free_sbuf, sbuf, next); 767 TAILQ_REMOVE(&sc->sc_free_shdr, shdr, next); 768 769 sbd = &sc->stbd_list[sc->txcur]; 770 sbd->type = IPW_SBD_TYPE_HEADER; 771 sbd->priv = shdr; 772 sbd->bd->physaddr = htole32(shdr->map->dm_segs[0].ds_addr); 773 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 774 sbd->bd->nfrag = 1 + sbuf->map->dm_nsegs; 775 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 776 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 777 778 DPRINTFN(5, ("TX!HDR!%u!%u!%u!%u\n", shdr->hdr.type, shdr->hdr.subtype, 779 shdr->hdr.encrypted, shdr->hdr.encrypt)); 780 DPRINTFN(5, ("!%s", ether_sprintf(shdr->hdr.src_addr))); 781 DPRINTFN(5, ("!%s\n", ether_sprintf(shdr->hdr.dst_addr))); 782 783 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 784 sc->txcur * sizeof (struct ipw_bd), 785 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 786 787 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 788 789 sbuf->m = m; 790 sbuf->ni = ni; 791 792 for (i = 0; i < sbuf->map->dm_nsegs; i++) { 793 sbd = &sc->stbd_list[sc->txcur]; 794 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[i].ds_addr); 795 sbd->bd->len = htole32(sbuf->map->dm_segs[i].ds_len); 796 sbd->bd->nfrag = 0; /* used only in first bd */ 797 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 798 if (i == sbuf->map->dm_nsegs - 1) { 799 sbd->type = IPW_SBD_TYPE_DATA; 800 sbd->priv = sbuf; 801 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 802 } else { 803 sbd->type = IPW_SBD_TYPE_NOASSOC; 804 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 805 } 806 807 DPRINTFN(5, ("TX!FRAG!%d!%ld\n", i, 808 sbuf->map->dm_segs[i].ds_len)); 809 810 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 811 sc->txcur * sizeof (struct ipw_bd), 812 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 813 814 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 815 } 816 817 bus_dmamap_sync(sc->sc_dmat, shdr->map, 0, sizeof (struct ipw_hdr), 818 BUS_DMASYNC_PREWRITE); 819 820 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, MCLBYTES, 821 BUS_DMASYNC_PREWRITE); 822 823 /* Inform firmware about this new packet */ 824 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, sc->txcur); 825 826 return 0; 827 } 828 829 static void 830 ipw_start(struct ifnet *ifp) 831 { 832 struct ipw_softc *sc = ifp->if_softc; 833 struct ieee80211com *ic = &sc->sc_ic; 834 struct mbuf *m; 835 struct ieee80211_node *ni; 836 837 for (;;) { 838 IF_DEQUEUE(&ifp->if_snd, m); 839 if (m == NULL) 840 break; 841 842 #if NBPFILTER > 0 843 if (ifp->if_bpf != NULL) 844 bpf_mtap(ifp->if_bpf, m); 845 #endif 846 847 m = ieee80211_encap(ifp, m, &ni); 848 if (m == NULL) 849 continue; 850 851 #if NBPFILTER > 0 852 if (ic->ic_rawbpf != NULL) 853 bpf_mtap(ic->ic_rawbpf, m); 854 #endif 855 856 if (ipw_tx_start(ifp, m, ni) != 0) { 857 if (ni != NULL) 858 ieee80211_release_node(ic, ni); 859 break; 860 } 861 862 /* start watchdog timer */ 863 sc->sc_tx_timer = 5; 864 ifp->if_timer = 1; 865 } 866 } 867 868 static void 869 ipw_watchdog(struct ifnet *ifp) 870 { 871 struct ipw_softc *sc = ifp->if_softc; 872 873 ifp->if_timer = 0; 874 875 if (sc->sc_tx_timer > 0) { 876 if (--sc->sc_tx_timer == 0) { 877 aprint_error("%s: device timeout\n", 878 sc->sc_dev.dv_xname); 879 #ifdef notyet 880 ipw_init(ifp); 881 #endif 882 return; 883 } 884 ifp->if_timer = 1; 885 } 886 887 ieee80211_watchdog(ifp); 888 } 889 890 static int 891 ipw_get_table1(struct ipw_softc *sc, u_int32_t *tbl) 892 { 893 u_int32_t addr, size, i; 894 895 if (!(sc->flags & IPW_FLAG_FW_INITED)) 896 return ENOTTY; 897 898 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, sc->table1_base); 899 900 size = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 901 if (suword(tbl, size) != 0) 902 return EFAULT; 903 904 for (i = 1, ++tbl; i < size; i++, tbl++) { 905 addr = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 906 if (suword(tbl, MEM_READ_4(sc, addr)) != 0) 907 return EFAULT; 908 } 909 return 0; 910 } 911 912 static int 913 ipw_get_radio(struct ipw_softc *sc, int *ret) 914 { 915 u_int32_t addr; 916 917 if (!(sc->flags & IPW_FLAG_FW_INITED)) 918 return ENOTTY; 919 920 addr = ipw_read_table1(sc, IPW_INFO_EEPROM_ADDRESS); 921 if ((MEM_READ_4(sc, addr + 32) >> 24) & 1) { 922 suword(ret, -1); 923 return 0; 924 } 925 926 if (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED) 927 suword(ret, 0); 928 else 929 suword(ret, 1); 930 931 return 0; 932 } 933 934 static int 935 ipw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 936 { 937 struct ipw_softc *sc = ifp->if_softc; 938 struct ifreq *ifr; 939 int s, error = 0; 940 941 s = splnet(); 942 943 switch (cmd) { 944 case SIOCSIFFLAGS: 945 if (ifp->if_flags & IFF_UP) { 946 if (!(ifp->if_flags & IFF_RUNNING)) 947 ipw_init(ifp); 948 } else { 949 if (ifp->if_flags & IFF_RUNNING) 950 ipw_stop(ifp, 1); 951 } 952 break; 953 954 case SIOCGTABLE1: 955 ifr = (struct ifreq *)data; 956 error = ipw_get_table1(sc, (u_int32_t *)ifr->ifr_data); 957 break; 958 959 case SIOCGRADIO: 960 ifr = (struct ifreq *)data; 961 error = ipw_get_radio(sc, (int *)ifr->ifr_data); 962 break; 963 964 case SIOCSLOADFW: 965 /* only super-user can do that! */ 966 if ((error = suser(curproc->p_ucred, &curproc->p_acflag)) != 0) 967 break; 968 969 ifr = (struct ifreq *)data; 970 error = ipw_firmware_init(sc, (u_char *)ifr->ifr_data); 971 break; 972 973 case SIOCSKILLFW: 974 /* only super-user can do that! */ 975 if ((error = suser(curproc->p_ucred, &curproc->p_acflag)) != 0) 976 break; 977 978 ipw_reset(sc); 979 break; 980 981 default: 982 error = ieee80211_ioctl(ifp, cmd, data); 983 if (error != ENETRESET) 984 break; 985 986 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 987 (IFF_UP | IFF_RUNNING)) 988 ipw_init(ifp); 989 error = 0; 990 } 991 992 splx(s); 993 return error; 994 } 995 996 static u_int32_t 997 ipw_read_table1(struct ipw_softc *sc, u_int32_t off) 998 { 999 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 1000 } 1001 1002 static void 1003 ipw_write_table1(struct ipw_softc *sc, u_int32_t off, u_int32_t info) 1004 { 1005 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 1006 } 1007 1008 static int 1009 ipw_read_table2(struct ipw_softc *sc, u_int32_t off, void *buf, u_int32_t *len) 1010 { 1011 u_int32_t addr, info; 1012 u_int16_t count, size; 1013 u_int32_t total; 1014 1015 /* addr[4] + count[2] + size[2] */ 1016 addr = MEM_READ_4(sc, sc->table2_base + off); 1017 info = MEM_READ_4(sc, sc->table2_base + off + 4); 1018 1019 count = info >> 16; 1020 size = info & 0xffff; 1021 total = count * size; 1022 1023 if (total > *len) { 1024 *len = total; 1025 return EINVAL; 1026 } 1027 1028 *len = total; 1029 ipw_read_mem_1(sc, addr, buf, total); 1030 1031 return 0; 1032 } 1033 1034 static int 1035 ipw_tx_init(struct ipw_softc *sc) 1036 { 1037 char *errmsg; 1038 struct ipw_bd *bd; 1039 struct ipw_soft_bd *sbd; 1040 struct ipw_soft_hdr *shdr; 1041 struct ipw_soft_buf *sbuf; 1042 int error, i, nsegs; 1043 1044 /* Allocate transmission buffer descriptors */ 1045 error = bus_dmamap_create(sc->sc_dmat, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, 1046 BUS_DMA_NOWAIT, &sc->tbd_map); 1047 if (error != 0) { 1048 errmsg = "could not create tbd dma map"; 1049 goto fail; 1050 } 1051 1052 error = bus_dmamem_alloc(sc->sc_dmat, IPW_TBD_SZ, PAGE_SIZE, 0, 1053 &sc->tbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 1054 if (error != 0) { 1055 errmsg = "could not allocate tbd dma memory"; 1056 goto fail; 1057 } 1058 1059 error = bus_dmamem_map(sc->sc_dmat, &sc->tbd_seg, nsegs, IPW_TBD_SZ, 1060 (caddr_t *)&sc->tbd_list, BUS_DMA_NOWAIT); 1061 if (error != 0) { 1062 errmsg = "could not map tbd dma memory"; 1063 goto fail; 1064 } 1065 1066 error = bus_dmamap_load(sc->sc_dmat, sc->tbd_map, sc->tbd_list, 1067 IPW_TBD_SZ, NULL, BUS_DMA_NOWAIT); 1068 if (error != 0) { 1069 errmsg = "could not load tbd dma memory"; 1070 goto fail; 1071 } 1072 1073 sc->stbd_list = malloc(IPW_NTBD * sizeof (struct ipw_soft_bd), 1074 M_DEVBUF, M_NOWAIT); 1075 if (sc->stbd_list == NULL) { 1076 errmsg = "could not allocate soft tbd"; 1077 error = ENOMEM; 1078 goto fail; 1079 } 1080 sbd = sc->stbd_list; 1081 bd = sc->tbd_list; 1082 for (i = 0; i < IPW_NTBD; i++, sbd++, bd++) { 1083 sbd->type = IPW_SBD_TYPE_NOASSOC; 1084 sbd->bd = bd; 1085 } 1086 1087 CSR_WRITE_4(sc, IPW_CSR_TX_BD_BASE, sc->tbd_map->dm_segs[0].ds_addr); 1088 CSR_WRITE_4(sc, IPW_CSR_TX_BD_SIZE, IPW_NTBD); 1089 CSR_WRITE_4(sc, IPW_CSR_TX_READ_INDEX, 0); 1090 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, 0); 1091 sc->txold = IPW_NTBD - 1; /* latest bd index ack'ed by firmware */ 1092 sc->txcur = 0; /* bd index to write to */ 1093 1094 /* Allocate a DMA-able command */ 1095 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_cmd), 1, 1096 sizeof (struct ipw_cmd), 0, BUS_DMA_NOWAIT, &sc->cmd_map); 1097 if (error != 0) { 1098 errmsg = "could not create cmd dma map"; 1099 goto fail; 1100 } 1101 1102 error = bus_dmamem_alloc(sc->sc_dmat, sizeof (struct ipw_cmd), 1103 PAGE_SIZE, 0, &sc->cmd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 1104 if (error != 0) { 1105 errmsg = "could not allocate cmd dma memory"; 1106 goto fail; 1107 } 1108 1109 error = bus_dmamem_map(sc->sc_dmat, &sc->cmd_seg, nsegs, 1110 sizeof (struct ipw_cmd), (caddr_t *)&sc->cmd, BUS_DMA_NOWAIT); 1111 if (error != 0) { 1112 errmsg = "could not map cmd dma memory"; 1113 goto fail; 1114 } 1115 1116 /* Allocate a pool of DMA-able headers */ 1117 sc->shdr_list = malloc(IPW_NDATA * sizeof (struct ipw_soft_hdr), 1118 M_DEVBUF, M_NOWAIT); 1119 if (sc->shdr_list == NULL) { 1120 errmsg = "could not allocate soft hdr"; 1121 error = ENOMEM; 1122 goto fail; 1123 } 1124 TAILQ_INIT(&sc->sc_free_shdr); 1125 for (i = 0, shdr = sc->shdr_list; i < IPW_NDATA; i++, shdr++) { 1126 error = bus_dmamap_create(sc->sc_dmat, 1127 sizeof (struct ipw_soft_hdr), 1, 1128 sizeof (struct ipw_soft_hdr), 0, BUS_DMA_NOWAIT, 1129 &shdr->map); 1130 if (error != 0) { 1131 errmsg = "could not create hdr dma map"; 1132 goto fail; 1133 } 1134 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 1135 } 1136 1137 /* Allocate a pool of DMA-able buffers */ 1138 sc->tx_sbuf_list = malloc(IPW_NDATA * sizeof (struct ipw_soft_buf), 1139 M_DEVBUF, M_NOWAIT); 1140 if (sc->tx_sbuf_list == NULL) { 1141 errmsg = "could not allocate soft txbuf"; 1142 error = ENOMEM; 1143 goto fail; 1144 } 1145 TAILQ_INIT(&sc->sc_free_sbuf); 1146 for (i = 0, sbuf = sc->tx_sbuf_list; i < IPW_NDATA; i++, sbuf++) { 1147 error = bus_dmamap_create(sc->sc_dmat, IPW_NDATA * MCLBYTES, 1148 IPW_NDATA, MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 1149 if (error != 0) { 1150 errmsg = "could not create txbuf dma map"; 1151 goto fail; 1152 } 1153 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 1154 } 1155 1156 return 0; 1157 1158 fail: aprint_error("%s: %s\n", sc->sc_dev.dv_xname, errmsg); 1159 ipw_tx_stop(sc); 1160 1161 return error; 1162 } 1163 1164 static void 1165 ipw_tx_stop(struct ipw_softc *sc) 1166 { 1167 struct ipw_soft_hdr *shdr; 1168 struct ipw_soft_buf *sbuf; 1169 int i; 1170 1171 if (sc->tbd_map != NULL) { 1172 if (sc->tbd_list != NULL) { 1173 bus_dmamap_unload(sc->sc_dmat, sc->tbd_map); 1174 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->tbd_list, 1175 IPW_TBD_SZ); 1176 bus_dmamem_free(sc->sc_dmat, &sc->tbd_seg, 1); 1177 sc->tbd_list = NULL; 1178 } 1179 bus_dmamap_destroy(sc->sc_dmat, sc->tbd_map); 1180 sc->tbd_map = NULL; 1181 } 1182 1183 if (sc->stbd_list != NULL) { 1184 for (i = 0; i < IPW_NTBD; i++) 1185 ipw_release_sbd(sc, &sc->stbd_list[i]); 1186 free(sc->stbd_list, M_DEVBUF); 1187 sc->stbd_list = NULL; 1188 } 1189 1190 if (sc->cmd_map != NULL) { 1191 if (sc->cmd != NULL) { 1192 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->cmd, 1193 sizeof (struct ipw_cmd)); 1194 bus_dmamem_free(sc->sc_dmat, &sc->cmd_seg, 1); 1195 sc->cmd = NULL; 1196 } 1197 bus_dmamap_destroy(sc->sc_dmat, sc->cmd_map); 1198 sc->cmd_map = NULL; 1199 } 1200 1201 if (sc->shdr_list != NULL) { 1202 TAILQ_FOREACH(shdr, &sc->sc_free_shdr, next) 1203 bus_dmamap_destroy(sc->sc_dmat, shdr->map); 1204 free(sc->shdr_list, M_DEVBUF); 1205 sc->shdr_list = NULL; 1206 } 1207 1208 1209 if (sc->tx_sbuf_list != NULL) { 1210 TAILQ_FOREACH(sbuf, &sc->sc_free_sbuf, next) 1211 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 1212 free(sc->tx_sbuf_list, M_DEVBUF); 1213 sc->tx_sbuf_list = NULL; 1214 } 1215 } 1216 1217 static int 1218 ipw_rx_init(struct ipw_softc *sc) 1219 { 1220 char *errmsg; 1221 struct ipw_bd *bd; 1222 struct ipw_soft_bd *sbd; 1223 struct ipw_soft_buf *sbuf; 1224 int error, i, nsegs; 1225 1226 /* Allocate reception buffer descriptors */ 1227 error = bus_dmamap_create(sc->sc_dmat, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, 1228 BUS_DMA_NOWAIT, &sc->rbd_map); 1229 if (error != 0) { 1230 errmsg = "could not create rbd dma map"; 1231 goto fail; 1232 } 1233 1234 error = bus_dmamem_alloc(sc->sc_dmat, IPW_RBD_SZ, PAGE_SIZE, 0, 1235 &sc->rbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 1236 if (error != 0) { 1237 errmsg = "could not allocate rbd dma memory"; 1238 goto fail; 1239 } 1240 1241 error = bus_dmamem_map(sc->sc_dmat, &sc->rbd_seg, nsegs, IPW_RBD_SZ, 1242 (caddr_t *)&sc->rbd_list, BUS_DMA_NOWAIT); 1243 if (error != 0) { 1244 errmsg = "could not map rbd dma memory"; 1245 goto fail; 1246 } 1247 1248 error = bus_dmamap_load(sc->sc_dmat, sc->rbd_map, sc->rbd_list, 1249 IPW_RBD_SZ, NULL, BUS_DMA_NOWAIT); 1250 if (error != 0) { 1251 errmsg = "could not load rbd dma memory"; 1252 goto fail; 1253 } 1254 1255 sc->srbd_list = malloc(IPW_NRBD * sizeof (struct ipw_soft_bd), 1256 M_DEVBUF, M_NOWAIT); 1257 if (sc->srbd_list == NULL) { 1258 errmsg = "could not allocate soft rbd"; 1259 error = ENOMEM; 1260 goto fail; 1261 } 1262 sbd = sc->srbd_list; 1263 bd = sc->rbd_list; 1264 for (i = 0; i < IPW_NRBD; i++, sbd++, bd++) { 1265 sbd->type = IPW_SBD_TYPE_NOASSOC; 1266 sbd->bd = bd; 1267 } 1268 1269 CSR_WRITE_4(sc, IPW_CSR_RX_BD_BASE, sc->rbd_map->dm_segs[0].ds_addr); 1270 CSR_WRITE_4(sc, IPW_CSR_RX_BD_SIZE, IPW_NRBD); 1271 CSR_WRITE_4(sc, IPW_CSR_RX_READ_INDEX, 0); 1272 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE_INDEX, IPW_NRBD - 1); 1273 sc->rxcur = IPW_NRBD - 1; /* latest bd index I've read */ 1274 1275 /* Allocate status descriptors */ 1276 error = bus_dmamap_create(sc->sc_dmat, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 1277 0, BUS_DMA_NOWAIT, &sc->status_map); 1278 if (error != 0) { 1279 errmsg = "could not create status dma map"; 1280 goto fail; 1281 } 1282 1283 error = bus_dmamem_alloc(sc->sc_dmat, IPW_STATUS_SZ, PAGE_SIZE, 0, 1284 &sc->status_seg, 1, &nsegs, BUS_DMA_NOWAIT); 1285 if (error != 0) { 1286 errmsg = "could not allocate status dma memory"; 1287 goto fail; 1288 } 1289 1290 error = bus_dmamem_map(sc->sc_dmat, &sc->status_seg, nsegs, 1291 IPW_STATUS_SZ, (caddr_t *)&sc->status_list, BUS_DMA_NOWAIT); 1292 if (error != 0) { 1293 errmsg = "could not map status dma memory"; 1294 goto fail; 1295 } 1296 1297 error = bus_dmamap_load(sc->sc_dmat, sc->status_map, sc->status_list, 1298 IPW_STATUS_SZ, NULL, BUS_DMA_NOWAIT); 1299 if (error != 0) { 1300 errmsg = "could not load status dma memory"; 1301 goto fail; 1302 } 1303 1304 CSR_WRITE_4(sc, IPW_CSR_RX_STATUS_BASE, 1305 sc->status_map->dm_segs[0].ds_addr); 1306 1307 sc->rx_sbuf_list = malloc(IPW_NRBD * sizeof (struct ipw_soft_buf), 1308 M_DEVBUF, M_NOWAIT); 1309 if (sc->rx_sbuf_list == NULL) { 1310 errmsg = "could not allocate soft rxbuf"; 1311 error = ENOMEM; 1312 goto fail; 1313 } 1314 1315 sbuf = sc->rx_sbuf_list; 1316 sbd = sc->srbd_list; 1317 for (i = 0; i < IPW_NRBD; i++, sbuf++, sbd++) { 1318 1319 MGETHDR(sbuf->m, M_DONTWAIT, MT_DATA); 1320 if (sbuf->m == NULL) { 1321 errmsg = "could not allocate rx mbuf"; 1322 error = ENOMEM; 1323 goto fail; 1324 } 1325 MCLGET(sbuf->m, M_DONTWAIT); 1326 if (!(sbuf->m->m_flags & M_EXT)) { 1327 m_freem(sbuf->m); 1328 errmsg = "could not allocate rx mbuf cluster"; 1329 error = ENOMEM; 1330 goto fail; 1331 } 1332 1333 error = bus_dmamap_create(sc->sc_dmat, IPW_NRBD * MCLBYTES, 1334 IPW_NRBD, MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 1335 if (error != 0) { 1336 m_freem(sbuf->m); 1337 errmsg = "could not create rxbuf dma map"; 1338 goto fail; 1339 } 1340 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, 1341 mtod(sbuf->m, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 1342 if (error != 0) { 1343 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 1344 m_freem(sbuf->m); 1345 errmsg = "could not map rxbuf dma memory"; 1346 goto fail; 1347 } 1348 sbd->type = IPW_SBD_TYPE_DATA; 1349 sbd->priv = sbuf; 1350 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 1351 sbd->bd->len = htole32(MCLBYTES); 1352 } 1353 1354 return 0; 1355 1356 fail: aprint_error("%s: %s\n", sc->sc_dev.dv_xname, errmsg); 1357 ipw_rx_stop(sc); 1358 1359 return error; 1360 } 1361 1362 static void 1363 ipw_rx_stop(struct ipw_softc *sc) 1364 { 1365 struct ipw_soft_bd *sbd; 1366 struct ipw_soft_buf *sbuf; 1367 int i; 1368 1369 if (sc->rbd_map != NULL) { 1370 if (sc->rbd_list != NULL) { 1371 bus_dmamap_unload(sc->sc_dmat, sc->rbd_map); 1372 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->rbd_list, 1373 IPW_RBD_SZ); 1374 bus_dmamem_free(sc->sc_dmat, &sc->rbd_seg, 1); 1375 sc->rbd_list = NULL; 1376 } 1377 bus_dmamap_destroy(sc->sc_dmat, sc->rbd_map); 1378 sc->rbd_map = NULL; 1379 } 1380 1381 if (sc->status_map != NULL) { 1382 if (sc->status_list != NULL) { 1383 bus_dmamap_unload(sc->sc_dmat, sc->status_map); 1384 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->status_list, 1385 IPW_STATUS_SZ); 1386 bus_dmamem_free(sc->sc_dmat, &sc->status_seg, 1); 1387 sc->status_list = NULL; 1388 } 1389 bus_dmamap_destroy(sc->sc_dmat, sc->status_map); 1390 sc->status_map = NULL; 1391 } 1392 1393 if (sc->srbd_list != NULL) { 1394 for (i = 0, sbd = sc->srbd_list; i < IPW_NRBD; i++, sbd++) { 1395 if (sbd->type == IPW_SBD_TYPE_NOASSOC) 1396 continue; 1397 1398 sbuf = sbd->priv; 1399 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1400 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 1401 m_freem(sbuf->m); 1402 } 1403 free(sc->srbd_list, M_DEVBUF); 1404 sc->srbd_list = NULL; 1405 } 1406 1407 if (sc->rx_sbuf_list != NULL) { 1408 free(sc->rx_sbuf_list, M_DEVBUF); 1409 sc->rx_sbuf_list = NULL; 1410 } 1411 } 1412 1413 static void 1414 ipw_reset(struct ipw_softc *sc) 1415 { 1416 struct ifnet *ifp = &sc->sc_ic.ic_if; 1417 int ntries; 1418 1419 ipw_stop(ifp, 1); 1420 1421 if (sc->flags & IPW_FLAG_FW_INITED) { 1422 ipw_cmd(sc, IPW_CMD_DISABLE_PHY, NULL, 0); 1423 ipw_cmd(sc, IPW_CMD_PREPARE_POWER_DOWN, NULL, 0); 1424 1425 sc->flags &= ~IPW_FLAG_FW_INITED; 1426 } 1427 1428 /* Disable interrupts */ 1429 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1430 1431 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1432 for (ntries = 0; ntries < 5; ntries++) { 1433 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1434 break; 1435 DELAY(10); 1436 } 1437 1438 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 1439 1440 ipw_rx_stop(sc); 1441 ipw_tx_stop(sc); 1442 1443 ifp->if_flags &= ~IFF_UP; 1444 } 1445 1446 static int 1447 ipw_clock_sync(struct ipw_softc *sc) 1448 { 1449 int ntries; 1450 u_int32_t r; 1451 1452 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 1453 for (ntries = 0; ntries < 1000; ntries++) { 1454 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_PRINCETON_RESET) 1455 break; 1456 DELAY(10); 1457 } 1458 if (ntries == 1000) 1459 return EIO; 1460 1461 CSR_WRITE_4(sc, IPW_CSR_CTL, IPW_CTL_INIT_DONE); 1462 for (ntries = 0; ntries < 1000; ntries++) { 1463 if ((r = CSR_READ_4(sc, IPW_CSR_CTL)) & IPW_CTL_CLOCK_READY) 1464 break; 1465 DELAY(200); 1466 } 1467 if (ntries == 1000) 1468 return EIO; 1469 1470 CSR_WRITE_4(sc, IPW_CSR_CTL, r | IPW_CTL_ALLOW_STANDBY); 1471 1472 return 0; 1473 } 1474 1475 static int 1476 ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size) 1477 { 1478 int ntries; 1479 1480 MEM_WRITE_2(sc, 0x220000, 0x0703); 1481 MEM_WRITE_2(sc, 0x220000, 0x0707); 1482 1483 MEM_WRITE_1(sc, 0x210014, 0x72); 1484 MEM_WRITE_1(sc, 0x210014, 0x72); 1485 1486 MEM_WRITE_1(sc, 0x210000, 0x40); 1487 MEM_WRITE_1(sc, 0x210000, 0x00); 1488 MEM_WRITE_1(sc, 0x210000, 0x40); 1489 1490 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1491 1492 MEM_WRITE_1(sc, 0x210000, 0x00); 1493 MEM_WRITE_1(sc, 0x210000, 0x00); 1494 MEM_WRITE_1(sc, 0x210000, 0x80); 1495 1496 MEM_WRITE_2(sc, 0x220000, 0x0703); 1497 MEM_WRITE_2(sc, 0x220000, 0x0707); 1498 1499 MEM_WRITE_1(sc, 0x210014, 0x72); 1500 MEM_WRITE_1(sc, 0x210014, 0x72); 1501 1502 MEM_WRITE_1(sc, 0x210000, 0x00); 1503 MEM_WRITE_1(sc, 0x210000, 0x80); 1504 1505 for (ntries = 0; ntries < 10; ntries++) { 1506 if (MEM_READ_1(sc, 0x210000) & 1) 1507 break; 1508 DELAY(10); 1509 } 1510 if (ntries == 10) 1511 return EIO; 1512 1513 return 0; 1514 } 1515 1516 /* set of macros to handle unaligned little endian data in firmware image */ 1517 #define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1518 #define GETLE16(p) ((p)[0] | (p)[1] << 8) 1519 static int 1520 ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size) 1521 { 1522 u_char *p, *end; 1523 u_int32_t addr; 1524 u_int16_t len; 1525 1526 p = fw; 1527 end = fw + size; 1528 while (p < end) { 1529 if (p + 6 > end) 1530 return EINVAL; 1531 1532 addr = GETLE32(p); 1533 p += 4; 1534 len = GETLE16(p); 1535 p += 2; 1536 1537 if (p + len > end) 1538 return EINVAL; 1539 1540 ipw_write_mem_1(sc, addr, p, len); 1541 p += len; 1542 } 1543 return 0; 1544 } 1545 1546 static int 1547 ipw_firmware_init(struct ipw_softc *sc, u_char *data) 1548 { 1549 struct ieee80211com *ic = &sc->sc_ic; 1550 struct ifnet *ifp = &ic->ic_if; 1551 struct ipw_fw_hdr hdr; 1552 u_int32_t r, len, fw_size, uc_size; 1553 u_char *fw, *uc; 1554 int error; 1555 1556 ipw_reset(sc); 1557 1558 if ((error = copyin(data, &hdr, sizeof hdr)) != 0) 1559 goto fail1; 1560 1561 fw_size = le32toh(hdr.fw_size); 1562 uc_size = le32toh(hdr.uc_size); 1563 data += sizeof hdr; 1564 1565 if ((fw = malloc(fw_size, M_DEVBUF, M_NOWAIT)) == NULL) { 1566 error = ENOMEM; 1567 goto fail1; 1568 } 1569 1570 if ((error = copyin(data, fw, fw_size)) != 0) 1571 goto fail2; 1572 1573 data += fw_size; 1574 1575 if ((uc = malloc(uc_size, M_DEVBUF, M_NOWAIT)) == NULL) { 1576 error = ENOMEM; 1577 goto fail2; 1578 } 1579 1580 if ((error = copyin(data, uc, uc_size)) != 0) 1581 goto fail3; 1582 1583 if ((error = ipw_clock_sync(sc)) != 0) { 1584 aprint_error("%s: clock synchronization failed\n", 1585 sc->sc_dev.dv_xname); 1586 goto fail3; 1587 } 1588 1589 MEM_WRITE_4(sc, 0x003000e0, 0x80000000); 1590 1591 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1592 1593 if ((error = ipw_load_ucode(sc, uc, uc_size)) != 0) { 1594 aprint_error("%s: could not load microcode\n", 1595 sc->sc_dev.dv_xname); 1596 goto fail3; 1597 } 1598 1599 MEM_WRITE_4(sc, 0x003000e0, 0); 1600 1601 if ((error = ipw_clock_sync(sc)) != 0) { 1602 aprint_error("%s: clock synchronization failed\n", 1603 sc->sc_dev.dv_xname); 1604 goto fail3; 1605 } 1606 1607 if ((error = ipw_load_firmware(sc, fw, fw_size))) { 1608 aprint_error("%s: could not load firmware\n", 1609 sc->sc_dev.dv_xname); 1610 goto fail3; 1611 } 1612 1613 ipw_zero_mem_4(sc, 0x0002f200, 196); 1614 ipw_zero_mem_4(sc, 0x0002f610, 8); 1615 ipw_zero_mem_4(sc, 0x0002fa00, 8); 1616 ipw_zero_mem_4(sc, 0x0002fc00, 4); 1617 ipw_zero_mem_4(sc, 0x0002ff80, 32); 1618 1619 if ((error = ipw_rx_init(sc)) != 0) { 1620 aprint_error("%s: could not initialize rx queue\n", 1621 sc->sc_dev.dv_xname); 1622 goto fail3; 1623 } 1624 1625 if ((error = ipw_tx_init(sc)) != 0) { 1626 aprint_error("%s: could not initialize tx queue\n", 1627 sc->sc_dev.dv_xname); 1628 goto fail3; 1629 } 1630 1631 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1632 IPW_IO_LED_OFF); 1633 1634 /* Enable interrupts */ 1635 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1636 1637 /* Let's go! */ 1638 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1639 1640 /* Wait at most 5 seconds for firmware initialization to complete */ 1641 if ((error = tsleep(sc, 0, "ipwinit", 5 * hz)) != 0) { 1642 aprint_error("%s: timeout waiting for firmware initialization " 1643 "to complete\n", sc->sc_dev.dv_xname); 1644 goto fail3; 1645 } 1646 1647 /* Firmware initialization completed */ 1648 sc->flags |= IPW_FLAG_FW_INITED; 1649 1650 free(uc, M_DEVBUF); 1651 free(fw, M_DEVBUF); 1652 1653 r = CSR_READ_4(sc, IPW_CSR_IO); 1654 CSR_WRITE_4(sc, IPW_CSR_IO, r | IPW_IO_GPIO1_MASK | IPW_IO_GPIO3_MASK); 1655 1656 /* Retrieve information tables base addresses */ 1657 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 1658 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 1659 1660 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 1661 1662 /* Retrieve adapter MAC address */ 1663 len = IEEE80211_ADDR_LEN; 1664 ipw_read_table2(sc, IPW_INFO_ADAPTER_MAC, ic->ic_myaddr, &len); 1665 1666 IEEE80211_ADDR_COPY(LLADDR(ifp->if_sadl), ic->ic_myaddr); 1667 1668 return 0; 1669 1670 fail3: free(uc, M_DEVBUF); 1671 fail2: free(fw, M_DEVBUF); 1672 fail1: ipw_reset(sc); 1673 1674 return error; 1675 } 1676 1677 static int 1678 ipw_config(struct ipw_softc *sc) 1679 { 1680 struct ieee80211com *ic = &sc->sc_ic; 1681 struct ifnet *ifp = &ic->ic_if; 1682 struct ipw_security security; 1683 struct ieee80211_wepkey *k; 1684 struct ipw_wep_key wepkey; 1685 struct ipw_scan_options options; 1686 struct ipw_configuration config; 1687 u_int32_t data; 1688 int error, i; 1689 1690 switch (ic->ic_opmode) { 1691 case IEEE80211_M_STA: 1692 case IEEE80211_M_HOSTAP: 1693 data = htole32(IPW_MODE_BSS); 1694 break; 1695 1696 case IEEE80211_M_IBSS: 1697 case IEEE80211_M_AHDEMO: 1698 data = htole32(IPW_MODE_IBSS); 1699 break; 1700 1701 case IEEE80211_M_MONITOR: 1702 data = htole32(IPW_MODE_MONITOR); 1703 break; 1704 } 1705 DPRINTF(("Setting adapter mode to %u\n", data)); 1706 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 1707 if (error != 0) 1708 return error; 1709 1710 if (ic->ic_opmode == IEEE80211_M_IBSS || 1711 ic->ic_opmode == IEEE80211_M_MONITOR) { 1712 data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); 1713 DPRINTF(("Setting adapter channel to %u\n", data)); 1714 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 1715 if (error != 0) 1716 return error; 1717 } 1718 1719 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1720 DPRINTF(("Enabling adapter\n")); 1721 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1722 } 1723 1724 DPRINTF(("Setting adapter MAC to %s\n", ether_sprintf(ic->ic_myaddr))); 1725 IEEE80211_ADDR_COPY(LLADDR(ifp->if_sadl), ic->ic_myaddr); 1726 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 1727 IEEE80211_ADDR_LEN); 1728 if (error != 0) 1729 return error; 1730 1731 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 1732 IPW_CFG_PREAMBLE_LEN | IPW_CFG_802_1x_ENABLE); 1733 if (ic->ic_opmode == IEEE80211_M_IBSS) 1734 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 1735 if (ifp->if_flags & IFF_PROMISC) 1736 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 1737 config.channels = htole32(0x3fff); /* channels 1-14 */ 1738 config.ibss_chan = htole32(0x7ff); 1739 DPRINTF(("Setting adapter configuration 0x%08x\n", config.flags)); 1740 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 1741 if (error != 0) 1742 return error; 1743 1744 data = htole32(0x3); /* 1, 2 */ 1745 DPRINTF(("Setting adapter basic tx rates to 0x%x\n", data)); 1746 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 1747 if (error != 0) 1748 return error; 1749 1750 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 1751 DPRINTF(("Setting adapter tx rates to 0x%x\n", data)); 1752 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 1753 if (error != 0) 1754 return error; 1755 1756 data = htole32(IPW_POWER_MODE_CAM); 1757 DPRINTF(("Setting adapter power mode to %u\n", data)); 1758 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 1759 if (error != 0) 1760 return error; 1761 1762 if (ic->ic_opmode == IEEE80211_M_IBSS) { 1763 data = htole32(ic->ic_txpower); 1764 DPRINTF(("Setting adapter tx power index to %u\n", data)); 1765 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 1766 sizeof data); 1767 if (error != 0) 1768 return error; 1769 } 1770 1771 data = htole32(ic->ic_rtsthreshold); 1772 DPRINTF(("Setting adapter RTS threshold to %u\n", data)); 1773 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 1774 if (error != 0) 1775 return error; 1776 1777 data = htole32(ic->ic_fragthreshold); 1778 DPRINTF(("Setting adapter frag threshold to %u\n", data)); 1779 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 1780 if (error != 0) 1781 return error; 1782 1783 #ifdef IPW_DEBUG 1784 if (ipw_debug > 0) { 1785 printf("Setting adapter ESSID to "); 1786 ieee80211_print_essid(ic->ic_des_essid, ic->ic_des_esslen); 1787 printf("\n"); 1788 } 1789 #endif 1790 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ic->ic_des_essid, 1791 ic->ic_des_esslen); 1792 if (error != 0) 1793 return error; 1794 1795 /* no mandatory BSSID */ 1796 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 1797 if (error != 0) 1798 return error; 1799 1800 if (ic->ic_flags & IEEE80211_F_DESBSSID) { 1801 DPRINTF(("Setting adapter desired BSSID to %s\n", 1802 ether_sprintf(ic->ic_des_bssid))); 1803 error = ipw_cmd(sc, IPW_CMD_SET_DESIRED_BSSID, 1804 ic->ic_des_bssid, IEEE80211_ADDR_LEN); 1805 if (error != 0) 1806 return error; 1807 } 1808 1809 security.authmode = IPW_AUTH_OPEN; 1810 security.ciphers = htole32(IPW_CIPHER_NONE); 1811 security.version = htole16(0); 1812 security.replay_counters_number = 0; 1813 security.unicast_using_group = 0; 1814 DPRINTF(("Setting adapter authmode to %u\n", security.authmode)); 1815 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 1816 sizeof security); 1817 if (error != 0) 1818 return error; 1819 1820 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 1821 k = ic->ic_nw_keys; 1822 for (i = 0; i < IEEE80211_WEP_NKID; i++, k++) { 1823 if (k->wk_len == 0) 1824 continue; 1825 1826 wepkey.idx = i; 1827 wepkey.len = k->wk_len; 1828 bzero(wepkey.key, sizeof wepkey.key); 1829 bcopy(k->wk_key, wepkey.key, k->wk_len); 1830 DPRINTF(("Setting wep key index %d len %d\n", 1831 wepkey.idx, wepkey.len)); 1832 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY, &wepkey, 1833 sizeof wepkey); 1834 if (error != 0) 1835 return error; 1836 } 1837 1838 data = htole32(ic->ic_wep_txkey); 1839 DPRINTF(("Setting adapter tx key index to %u\n", data)); 1840 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY_INDEX, &data, 1841 sizeof data); 1842 if (error != 0) 1843 return error; 1844 } 1845 1846 data = htole32((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) ? 0x8 : 0); 1847 DPRINTF(("Setting adapter wep flags to 0x%x\n", data)); 1848 error = ipw_cmd(sc, IPW_CMD_SET_WEP_FLAGS, &data, sizeof data); 1849 if (error != 0) 1850 return error; 1851 1852 if (ic->ic_opmode == IEEE80211_M_IBSS || 1853 ic->ic_opmode == IEEE80211_M_HOSTAP) { 1854 data = htole32(ic->ic_lintval); 1855 DPRINTF(("Setting adapter beacon interval to %u\n", data)); 1856 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 1857 sizeof data); 1858 if (error != 0) 1859 return error; 1860 } 1861 1862 options.flags = htole32(0); 1863 options.channels = htole32(0x3fff); /* scan channels 1-14 */ 1864 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &options, sizeof options); 1865 if (error != 0) 1866 return error; 1867 1868 /* finally, enable adapter (start scanning for an access point) */ 1869 DPRINTF(("Enabling adapter\n")); 1870 error = ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1871 if (error != 0) 1872 return error; 1873 1874 return 0; 1875 } 1876 1877 static int 1878 ipw_init(struct ifnet *ifp) 1879 { 1880 struct ipw_softc *sc = ifp->if_softc; 1881 struct ieee80211com *ic = &sc->sc_ic; 1882 1883 /* exit immediately if firmware has not been ioctl'd */ 1884 if (!(sc->flags & IPW_FLAG_FW_INITED)) { 1885 ifp->if_flags &= ~IFF_UP; 1886 return EIO; 1887 } 1888 1889 ipw_stop(ifp, 0); 1890 1891 if (ipw_config(sc) != 0) { 1892 aprint_error("%s: device configuration failed\n", 1893 sc->sc_dev.dv_xname); 1894 goto fail; 1895 } 1896 1897 ifp->if_flags &= ~IFF_OACTIVE; 1898 ifp->if_flags |= IFF_RUNNING; 1899 1900 ic->ic_bss->ni_chan = ic->ic_channels; 1901 1902 return 0; 1903 1904 fail: ipw_stop(ifp, 0); 1905 1906 return EIO; 1907 } 1908 1909 static void 1910 ipw_stop(struct ifnet *ifp, int disable) 1911 { 1912 struct ipw_softc *sc = ifp->if_softc; 1913 struct ieee80211com *ic = &sc->sc_ic; 1914 1915 if (ifp->if_flags & IFF_RUNNING) { 1916 DPRINTF(("Disabling adapter\n")); 1917 ipw_cmd(sc, IPW_CMD_DISABLE, NULL, 0); 1918 } 1919 1920 ifp->if_timer = 0; 1921 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1922 1923 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1924 } 1925 1926 static void 1927 ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, u_int8_t *datap, 1928 bus_size_t count) 1929 { 1930 for (; count > 0; offset++, datap++, count--) { 1931 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 1932 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 1933 } 1934 } 1935 1936 static void 1937 ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, u_int8_t *datap, 1938 bus_size_t count) 1939 { 1940 for (; count > 0; offset++, datap++, count--) { 1941 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 1942 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 1943 } 1944 } 1945 1946 static void 1947 ipw_zero_mem_4(struct ipw_softc *sc, bus_size_t offset, bus_size_t count) 1948 { 1949 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, offset); 1950 while (count-- > 0) 1951 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_DATA, 0); 1952 } 1953 1954
Indexes created Tue Sep 30 11:09:46 GMT 2025