if_ipw.c revision 1.60.2.1
1 /* $NetBSD: if_ipw.c,v 1.60.2.1 2017/01/07 08:56:33 pgoyette Exp $ */ 2 /* FreeBSD: src/sys/dev/ipw/if_ipw.c,v 1.15 2005/11/13 17:17:40 damien Exp */ 3 4 /*- 5 * Copyright (c) 2004, 2005 6 * Damien Bergamini <damien.bergamini (at) free.fr>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: if_ipw.c,v 1.60.2.1 2017/01/07 08:56:33 pgoyette Exp $"); 33 34 /*- 35 * Intel(R) PRO/Wireless 2100 MiniPCI driver 36 * http://www.intel.com/network/connectivity/products/wireless/prowireless_mobile.htm 37 */ 38 39 40 #include <sys/param.h> 41 #include <sys/sockio.h> 42 #include <sys/sysctl.h> 43 #include <sys/mbuf.h> 44 #include <sys/kernel.h> 45 #include <sys/socket.h> 46 #include <sys/systm.h> 47 #include <sys/malloc.h> 48 #include <sys/conf.h> 49 #include <sys/proc.h> 50 51 #include <sys/bus.h> 52 #include <machine/endian.h> 53 #include <sys/intr.h> 54 55 #include <dev/pci/pcireg.h> 56 #include <dev/pci/pcivar.h> 57 #include <dev/pci/pcidevs.h> 58 59 #include <net/bpf.h> 60 #include <net/if.h> 61 #include <net/if_arp.h> 62 #include <net/if_dl.h> 63 #include <net/if_ether.h> 64 #include <net/if_media.h> 65 #include <net/if_types.h> 66 67 #include <net80211/ieee80211_var.h> 68 #include <net80211/ieee80211_radiotap.h> 69 70 #include <netinet/in.h> 71 #include <netinet/in_systm.h> 72 #include <netinet/in_var.h> 73 #include <netinet/ip.h> 74 75 #include <dev/firmload.h> 76 77 #include <dev/pci/if_ipwreg.h> 78 #include <dev/pci/if_ipwvar.h> 79 80 #ifdef IPW_DEBUG 81 #define DPRINTF(x) if (ipw_debug > 0) printf x 82 #define DPRINTFN(n, x) if (ipw_debug >= (n)) printf x 83 int ipw_debug = 0; 84 #else 85 #define DPRINTF(x) 86 #define DPRINTFN(n, x) 87 #endif 88 89 /* Permit loading the Intel firmware */ 90 static int ipw_accept_eula; 91 92 static int ipw_dma_alloc(struct ipw_softc *); 93 static void ipw_release(struct ipw_softc *); 94 static int ipw_match(device_t, cfdata_t, void *); 95 static void ipw_attach(device_t, device_t, void *); 96 static int ipw_detach(device_t, int); 97 98 static int ipw_media_change(struct ifnet *); 99 static void ipw_media_status(struct ifnet *, struct ifmediareq *); 100 static int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 101 static uint16_t ipw_read_prom_word(struct ipw_softc *, uint8_t); 102 static void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 103 static void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 104 static void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 105 struct ipw_soft_bd *, struct ipw_soft_buf *); 106 static void ipw_rx_intr(struct ipw_softc *); 107 static void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 108 static void ipw_tx_intr(struct ipw_softc *); 109 static int ipw_intr(void *); 110 static int ipw_cmd(struct ipw_softc *, uint32_t, void *, uint32_t); 111 static int ipw_tx_start(struct ifnet *, struct mbuf *, 112 struct ieee80211_node *); 113 static void ipw_start(struct ifnet *); 114 static void ipw_watchdog(struct ifnet *); 115 static int ipw_ioctl(struct ifnet *, u_long, void *); 116 static int ipw_get_table1(struct ipw_softc *, uint32_t *); 117 static int ipw_get_radio(struct ipw_softc *, int *); 118 static void ipw_stop_master(struct ipw_softc *); 119 static int ipw_reset(struct ipw_softc *); 120 static int ipw_load_ucode(struct ipw_softc *, u_char *, int); 121 static int ipw_load_firmware(struct ipw_softc *, u_char *, int); 122 static int ipw_cache_firmware(struct ipw_softc *); 123 static void ipw_free_firmware(struct ipw_softc *); 124 static int ipw_config(struct ipw_softc *); 125 static int ipw_init(struct ifnet *); 126 static void ipw_stop(struct ifnet *, int); 127 static uint32_t ipw_read_table1(struct ipw_softc *, uint32_t); 128 static void ipw_write_table1(struct ipw_softc *, uint32_t, uint32_t); 129 static int ipw_read_table2(struct ipw_softc *, uint32_t, void *, uint32_t *); 130 static void ipw_read_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 131 bus_size_t); 132 static void ipw_write_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 133 bus_size_t); 134 135 /* 136 * Supported rates for 802.11b mode (in 500Kbps unit). 137 */ 138 static const struct ieee80211_rateset ipw_rateset_11b = 139 { 4, { 2, 4, 11, 22 } }; 140 141 static inline uint8_t 142 MEM_READ_1(struct ipw_softc *sc, uint32_t addr) 143 { 144 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 145 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); 146 } 147 148 static inline uint32_t 149 MEM_READ_4(struct ipw_softc *sc, uint32_t addr) 150 { 151 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 152 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); 153 } 154 155 CFATTACH_DECL_NEW(ipw, sizeof (struct ipw_softc), ipw_match, ipw_attach, 156 ipw_detach, NULL); 157 158 static int 159 ipw_match(device_t parent, cfdata_t match, void *aux) 160 { 161 struct pci_attach_args *pa = aux; 162 163 if (PCI_VENDOR (pa->pa_id) == PCI_VENDOR_INTEL && 164 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_PRO_WL_2100) 165 return 1; 166 167 return 0; 168 } 169 170 /* Base Address Register */ 171 #define IPW_PCI_BAR0 0x10 172 173 static void 174 ipw_attach(device_t parent, device_t self, void *aux) 175 { 176 struct ipw_softc *sc = device_private(self); 177 struct ieee80211com *ic = &sc->sc_ic; 178 struct ifnet *ifp = &sc->sc_if; 179 struct pci_attach_args *pa = aux; 180 const char *intrstr; 181 bus_space_tag_t memt; 182 bus_space_handle_t memh; 183 bus_addr_t base; 184 pci_intr_handle_t ih; 185 uint32_t data; 186 uint16_t val; 187 int i, error; 188 char intrbuf[PCI_INTRSTR_LEN]; 189 190 sc->sc_dev = self; 191 sc->sc_pct = pa->pa_pc; 192 sc->sc_pcitag = pa->pa_tag; 193 194 pci_aprint_devinfo(pa, NULL); 195 196 /* enable bus-mastering */ 197 data = pci_conf_read(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG); 198 data |= PCI_COMMAND_MASTER_ENABLE; 199 pci_conf_write(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG, data); 200 201 /* map the register window */ 202 error = pci_mapreg_map(pa, IPW_PCI_BAR0, PCI_MAPREG_TYPE_MEM | 203 PCI_MAPREG_MEM_TYPE_32BIT, 0, &memt, &memh, &base, &sc->sc_sz); 204 if (error != 0) { 205 aprint_error_dev(sc->sc_dev, "could not map memory space\n"); 206 return; 207 } 208 209 sc->sc_st = memt; 210 sc->sc_sh = memh; 211 sc->sc_dmat = pa->pa_dmat; 212 sc->sc_fwname = "ipw2100-1.2.fw"; 213 214 /* disable interrupts */ 215 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 216 217 if (pci_intr_map(pa, &ih) != 0) { 218 aprint_error_dev(sc->sc_dev, "could not map interrupt\n"); 219 return; 220 } 221 222 intrstr = pci_intr_string(sc->sc_pct, ih, intrbuf, sizeof(intrbuf)); 223 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, ipw_intr, sc); 224 if (sc->sc_ih == NULL) { 225 aprint_error_dev(sc->sc_dev, "could not establish interrupt"); 226 if (intrstr != NULL) 227 aprint_error(" at %s", intrstr); 228 aprint_error("\n"); 229 return; 230 } 231 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 232 233 if (ipw_reset(sc) != 0) { 234 aprint_error_dev(sc->sc_dev, "could not reset adapter\n"); 235 goto fail; 236 } 237 238 if (ipw_dma_alloc(sc) != 0) { 239 aprint_error_dev(sc->sc_dev, "could not allocate DMA resources\n"); 240 goto fail; 241 } 242 243 ifp->if_softc = sc; 244 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 245 ifp->if_init = ipw_init; 246 ifp->if_stop = ipw_stop; 247 ifp->if_ioctl = ipw_ioctl; 248 ifp->if_start = ipw_start; 249 ifp->if_watchdog = ipw_watchdog; 250 IFQ_SET_READY(&ifp->if_snd); 251 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 252 253 ic->ic_ifp = ifp; 254 ic->ic_phytype = IEEE80211_T_DS; 255 ic->ic_opmode = IEEE80211_M_STA; 256 ic->ic_state = IEEE80211_S_INIT; 257 258 /* set device capabilities */ 259 ic->ic_caps = 260 IEEE80211_C_SHPREAMBLE /* short preamble supported */ 261 | IEEE80211_C_TXPMGT /* tx power management */ 262 | IEEE80211_C_IBSS /* ibss mode */ 263 | IEEE80211_C_MONITOR /* monitor mode */ 264 ; 265 266 /* read MAC address from EEPROM */ 267 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0); 268 ic->ic_myaddr[0] = val >> 8; 269 ic->ic_myaddr[1] = val & 0xff; 270 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 1); 271 ic->ic_myaddr[2] = val >> 8; 272 ic->ic_myaddr[3] = val & 0xff; 273 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 2); 274 ic->ic_myaddr[4] = val >> 8; 275 ic->ic_myaddr[5] = val & 0xff; 276 277 /* set supported .11b rates */ 278 ic->ic_sup_rates[IEEE80211_MODE_11B] = ipw_rateset_11b; 279 280 /* set supported .11b channels (read from EEPROM) */ 281 if ((val = ipw_read_prom_word(sc, IPW_EEPROM_CHANNEL_LIST)) == 0) 282 val = 0x7ff; /* default to channels 1-11 */ 283 val <<= 1; 284 for (i = 1; i < 16; i++) { 285 if (val & (1 << i)) { 286 ic->ic_channels[i].ic_freq = 287 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 288 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 289 } 290 } 291 292 /* check support for radio transmitter switch in EEPROM */ 293 if (!(ipw_read_prom_word(sc, IPW_EEPROM_RADIO) & 8)) 294 sc->flags |= IPW_FLAG_HAS_RADIO_SWITCH; 295 296 aprint_normal_dev(sc->sc_dev, "802.11 address %s\n", 297 ether_sprintf(ic->ic_myaddr)); 298 299 if_attach(ifp); 300 if_deferred_start_init(ifp, NULL); 301 ieee80211_ifattach(ic); 302 303 /* override state transition machine */ 304 sc->sc_newstate = ic->ic_newstate; 305 ic->ic_newstate = ipw_newstate; 306 307 ieee80211_media_init(ic, ipw_media_change, ipw_media_status); 308 309 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 310 sizeof(struct ieee80211_frame) + 64, &sc->sc_drvbpf); 311 312 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 313 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 314 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 315 316 sc->sc_txtap_len = sizeof sc->sc_txtapu; 317 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 318 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 319 320 /* 321 * Add a few sysctl knobs. 322 * XXX: Not yet 323 */ 324 sc->dwelltime = 100; 325 326 if (pmf_device_register(self, NULL, NULL)) 327 pmf_class_network_register(self, ifp); 328 else 329 aprint_error_dev(self, "couldn't establish power handler\n"); 330 331 ieee80211_announce(ic); 332 333 return; 334 335 fail: ipw_detach(self, 0); 336 } 337 338 static int 339 ipw_detach(device_t self, int flags) 340 { 341 struct ipw_softc *sc = device_private(self); 342 struct ifnet *ifp = &sc->sc_if; 343 344 if (ifp->if_softc) { 345 ipw_stop(ifp, 1); 346 ipw_free_firmware(sc); 347 348 bpf_detach(ifp); 349 ieee80211_ifdetach(&sc->sc_ic); 350 if_detach(ifp); 351 352 ipw_release(sc); 353 } 354 355 if (sc->sc_ih != NULL) { 356 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 357 sc->sc_ih = NULL; 358 } 359 360 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 361 362 return 0; 363 } 364 365 static int 366 ipw_dma_alloc(struct ipw_softc *sc) 367 { 368 struct ipw_soft_bd *sbd; 369 struct ipw_soft_hdr *shdr; 370 struct ipw_soft_buf *sbuf; 371 int error, i, nsegs; 372 373 /* 374 * Allocate and map tx ring. 375 */ 376 error = bus_dmamap_create(sc->sc_dmat, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, 377 BUS_DMA_NOWAIT, &sc->tbd_map); 378 if (error != 0) { 379 aprint_error_dev(sc->sc_dev, "could not create tbd dma map\n"); 380 goto fail; 381 } 382 383 error = bus_dmamem_alloc(sc->sc_dmat, IPW_TBD_SZ, PAGE_SIZE, 0, 384 &sc->tbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 385 if (error != 0) { 386 aprint_error_dev(sc->sc_dev, "could not allocate tbd dma memory\n"); 387 goto fail; 388 } 389 390 error = bus_dmamem_map(sc->sc_dmat, &sc->tbd_seg, nsegs, IPW_TBD_SZ, 391 (void **)&sc->tbd_list, BUS_DMA_NOWAIT); 392 if (error != 0) { 393 aprint_error_dev(sc->sc_dev, "could not map tbd dma memory\n"); 394 goto fail; 395 } 396 397 error = bus_dmamap_load(sc->sc_dmat, sc->tbd_map, sc->tbd_list, 398 IPW_TBD_SZ, NULL, BUS_DMA_NOWAIT); 399 if (error != 0) { 400 aprint_error_dev(sc->sc_dev, "could not load tbd dma memory\n"); 401 goto fail; 402 } 403 404 (void)memset(sc->tbd_list, 0, IPW_TBD_SZ); 405 406 /* 407 * Allocate and map rx ring. 408 */ 409 error = bus_dmamap_create(sc->sc_dmat, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, 410 BUS_DMA_NOWAIT, &sc->rbd_map); 411 if (error != 0) { 412 aprint_error_dev(sc->sc_dev, "could not create rbd dma map\n"); 413 goto fail; 414 } 415 416 error = bus_dmamem_alloc(sc->sc_dmat, IPW_RBD_SZ, PAGE_SIZE, 0, 417 &sc->rbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 418 if (error != 0) { 419 aprint_error_dev(sc->sc_dev, "could not allocate rbd dma memory\n"); 420 goto fail; 421 } 422 423 error = bus_dmamem_map(sc->sc_dmat, &sc->rbd_seg, nsegs, IPW_RBD_SZ, 424 (void **)&sc->rbd_list, BUS_DMA_NOWAIT); 425 if (error != 0) { 426 aprint_error_dev(sc->sc_dev, "could not map rbd dma memory\n"); 427 goto fail; 428 } 429 430 error = bus_dmamap_load(sc->sc_dmat, sc->rbd_map, sc->rbd_list, 431 IPW_RBD_SZ, NULL, BUS_DMA_NOWAIT); 432 if (error != 0) { 433 aprint_error_dev(sc->sc_dev, "could not load rbd dma memory\n"); 434 goto fail; 435 } 436 437 (void)memset(sc->rbd_list, 0, IPW_RBD_SZ); 438 439 /* 440 * Allocate and map status ring. 441 */ 442 error = bus_dmamap_create(sc->sc_dmat, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 443 0, BUS_DMA_NOWAIT, &sc->status_map); 444 if (error != 0) { 445 aprint_error_dev(sc->sc_dev, "could not create status dma map\n"); 446 goto fail; 447 } 448 449 error = bus_dmamem_alloc(sc->sc_dmat, IPW_STATUS_SZ, PAGE_SIZE, 0, 450 &sc->status_seg, 1, &nsegs, BUS_DMA_NOWAIT); 451 if (error != 0) { 452 aprint_error_dev(sc->sc_dev, "could not allocate status dma memory\n"); 453 goto fail; 454 } 455 456 error = bus_dmamem_map(sc->sc_dmat, &sc->status_seg, nsegs, 457 IPW_STATUS_SZ, (void **)&sc->status_list, BUS_DMA_NOWAIT); 458 if (error != 0) { 459 aprint_error_dev(sc->sc_dev, "could not map status dma memory\n"); 460 goto fail; 461 } 462 463 error = bus_dmamap_load(sc->sc_dmat, sc->status_map, sc->status_list, 464 IPW_STATUS_SZ, NULL, BUS_DMA_NOWAIT); 465 if (error != 0) { 466 aprint_error_dev(sc->sc_dev, "could not load status dma memory\n"); 467 goto fail; 468 } 469 470 (void)memset(sc->status_list, 0, IPW_STATUS_SZ); 471 472 /* 473 * Allocate command DMA map. 474 */ 475 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_cmd), 476 1, sizeof (struct ipw_cmd), 0, BUS_DMA_NOWAIT, &sc->cmd_map); 477 if (error != 0) { 478 aprint_error_dev(sc->sc_dev, "could not create cmd dma map\n"); 479 goto fail; 480 } 481 482 error = bus_dmamem_alloc(sc->sc_dmat, sizeof (struct ipw_cmd), 483 PAGE_SIZE, 0, &sc->cmd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 484 if (error != 0) { 485 aprint_error_dev(sc->sc_dev, "could not allocate cmd dma memory\n"); 486 goto fail; 487 } 488 489 error = bus_dmamem_map(sc->sc_dmat, &sc->cmd_seg, nsegs, 490 sizeof (struct ipw_cmd), (void **)&sc->cmd, BUS_DMA_NOWAIT); 491 if (error != 0) { 492 aprint_error_dev(sc->sc_dev, "could not map cmd dma memory\n"); 493 goto fail; 494 } 495 496 error = bus_dmamap_load(sc->sc_dmat, sc->cmd_map, &sc->cmd, 497 sizeof (struct ipw_cmd), NULL, BUS_DMA_NOWAIT); 498 if (error != 0) { 499 aprint_error_dev(sc->sc_dev, "could not map cmd dma memory\n"); 500 return error; 501 } 502 503 /* 504 * Allocate and map hdr list. 505 */ 506 507 error = bus_dmamap_create(sc->sc_dmat, 508 IPW_NDATA * sizeof(struct ipw_hdr), 1, 509 sizeof(struct ipw_hdr), 0, BUS_DMA_NOWAIT, 510 &sc->hdr_map); 511 if (error != 0) { 512 aprint_error_dev(sc->sc_dev, "could not create hdr dma map\n"); 513 goto fail; 514 } 515 516 error = bus_dmamem_alloc(sc->sc_dmat, 517 IPW_NDATA * sizeof(struct ipw_hdr), PAGE_SIZE, 0, &sc->hdr_seg, 518 1, &nsegs, BUS_DMA_NOWAIT); 519 if (error != 0) { 520 aprint_error_dev(sc->sc_dev, "could not allocate hdr memory\n"); 521 goto fail; 522 } 523 524 error = bus_dmamem_map(sc->sc_dmat, &sc->hdr_seg, nsegs, 525 IPW_NDATA * sizeof(struct ipw_hdr), (void **)&sc->hdr_list, 526 BUS_DMA_NOWAIT); 527 if (error != 0) { 528 aprint_error_dev(sc->sc_dev, "could not map hdr memory\n"); 529 goto fail; 530 } 531 532 error = bus_dmamap_load(sc->sc_dmat, sc->hdr_map, sc->hdr_list, 533 IPW_NDATA * sizeof(struct ipw_hdr), NULL, BUS_DMA_NOWAIT); 534 if (error != 0) { 535 aprint_error_dev(sc->sc_dev, "could not load hdr memory\n"); 536 goto fail; 537 } 538 539 (void)memset(sc->hdr_list, 0, IPW_HDR_SZ); 540 541 /* 542 * Create DMA hdrs tailq. 543 */ 544 TAILQ_INIT(&sc->sc_free_shdr); 545 for (i = 0; i < IPW_NDATA; i++) { 546 shdr = &sc->shdr_list[i]; 547 shdr->hdr = sc->hdr_list + i; 548 shdr->offset = sizeof(struct ipw_hdr) * i; 549 shdr->addr = sc->hdr_map->dm_segs[0].ds_addr + shdr->offset; 550 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 551 } 552 553 /* 554 * Allocate tx buffers DMA maps. 555 */ 556 TAILQ_INIT(&sc->sc_free_sbuf); 557 for (i = 0; i < IPW_NDATA; i++) { 558 sbuf = &sc->tx_sbuf_list[i]; 559 560 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 561 IPW_MAX_NSEG, MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 562 if (error != 0) { 563 aprint_error_dev(sc->sc_dev, "could not create txbuf dma map\n"); 564 goto fail; 565 } 566 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 567 } 568 569 /* 570 * Initialize tx ring. 571 */ 572 for (i = 0; i < IPW_NTBD; i++) { 573 sbd = &sc->stbd_list[i]; 574 sbd->bd = &sc->tbd_list[i]; 575 sbd->type = IPW_SBD_TYPE_NOASSOC; 576 } 577 578 /* 579 * Pre-allocate rx buffers and DMA maps 580 */ 581 for (i = 0; i < IPW_NRBD; i++) { 582 sbd = &sc->srbd_list[i]; 583 sbuf = &sc->rx_sbuf_list[i]; 584 sbd->bd = &sc->rbd_list[i]; 585 586 MGETHDR(sbuf->m, M_DONTWAIT, MT_DATA); 587 if (sbuf->m == NULL) { 588 aprint_error_dev(sc->sc_dev, "could not allocate rx mbuf\n"); 589 error = ENOMEM; 590 goto fail; 591 } 592 593 MCLGET(sbuf->m, M_DONTWAIT); 594 if (!(sbuf->m->m_flags & M_EXT)) { 595 m_freem(sbuf->m); 596 aprint_error_dev(sc->sc_dev, "could not allocate rx mbuf cluster\n"); 597 error = ENOMEM; 598 goto fail; 599 } 600 601 sbuf->m->m_pkthdr.len = sbuf->m->m_len = sbuf->m->m_ext.ext_size; 602 603 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 604 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sbuf->map); 605 if (error != 0) { 606 aprint_error_dev(sc->sc_dev, "could not create rxbuf dma map\n"); 607 m_freem(sbuf->m); 608 goto fail; 609 } 610 611 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, 612 sbuf->m, BUS_DMA_READ | BUS_DMA_NOWAIT); 613 if (error != 0) { 614 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 615 m_freem(sbuf->m); 616 aprint_error_dev(sc->sc_dev, "could not map rxbuf dma memory\n"); 617 goto fail; 618 } 619 620 sbd->type = IPW_SBD_TYPE_DATA; 621 sbd->priv = sbuf; 622 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 623 sbd->bd->len = htole32(MCLBYTES); 624 625 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, 626 sbuf->map->dm_mapsize, BUS_DMASYNC_PREREAD); 627 628 } 629 630 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 0, IPW_RBD_SZ, 631 BUS_DMASYNC_PREREAD); 632 633 return 0; 634 635 fail: ipw_release(sc); 636 return error; 637 } 638 639 static void 640 ipw_release(struct ipw_softc *sc) 641 { 642 struct ipw_soft_buf *sbuf; 643 int i; 644 645 if (sc->tbd_map != NULL) { 646 if (sc->tbd_list != NULL) { 647 bus_dmamap_unload(sc->sc_dmat, sc->tbd_map); 648 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->tbd_list, 649 IPW_TBD_SZ); 650 bus_dmamem_free(sc->sc_dmat, &sc->tbd_seg, 1); 651 } 652 bus_dmamap_destroy(sc->sc_dmat, sc->tbd_map); 653 } 654 655 if (sc->rbd_map != NULL) { 656 if (sc->rbd_list != NULL) { 657 bus_dmamap_unload(sc->sc_dmat, sc->rbd_map); 658 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->rbd_list, 659 IPW_RBD_SZ); 660 bus_dmamem_free(sc->sc_dmat, &sc->rbd_seg, 1); 661 } 662 bus_dmamap_destroy(sc->sc_dmat, sc->rbd_map); 663 } 664 665 if (sc->status_map != NULL) { 666 if (sc->status_list != NULL) { 667 bus_dmamap_unload(sc->sc_dmat, sc->status_map); 668 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->status_list, 669 IPW_RBD_SZ); 670 bus_dmamem_free(sc->sc_dmat, &sc->status_seg, 1); 671 } 672 bus_dmamap_destroy(sc->sc_dmat, sc->status_map); 673 } 674 675 for (i = 0; i < IPW_NTBD; i++) 676 ipw_release_sbd(sc, &sc->stbd_list[i]); 677 678 if (sc->cmd_map != NULL) 679 bus_dmamap_destroy(sc->sc_dmat, sc->cmd_map); 680 681 if (sc->hdr_list != NULL) { 682 bus_dmamap_unload(sc->sc_dmat, sc->hdr_map); 683 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->hdr_list, 684 IPW_NDATA * sizeof(struct ipw_hdr)); 685 } 686 if (sc->hdr_map != NULL) { 687 bus_dmamem_free(sc->sc_dmat, &sc->hdr_seg, 1); 688 bus_dmamap_destroy(sc->sc_dmat, sc->hdr_map); 689 } 690 691 for (i = 0; i < IPW_NDATA; i++) 692 bus_dmamap_destroy(sc->sc_dmat, sc->tx_sbuf_list[i].map); 693 694 for (i = 0; i < IPW_NRBD; i++) { 695 sbuf = &sc->rx_sbuf_list[i]; 696 if (sbuf->map != NULL) { 697 if (sbuf->m != NULL) { 698 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 699 m_freem(sbuf->m); 700 } 701 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 702 } 703 } 704 705 } 706 707 static int 708 ipw_media_change(struct ifnet *ifp) 709 { 710 int error; 711 712 error = ieee80211_media_change(ifp); 713 if (error != ENETRESET) 714 return error; 715 716 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 717 ipw_init(ifp); 718 719 return 0; 720 } 721 722 /* 723 * The firmware automatically adapts the transmit speed. We report the current 724 * transmit speed here. 725 */ 726 static void 727 ipw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 728 { 729 #define N(a) (sizeof (a) / sizeof (a[0])) 730 struct ipw_softc *sc = ifp->if_softc; 731 struct ieee80211com *ic = &sc->sc_ic; 732 static const struct { 733 uint32_t val; 734 int rate; 735 } rates[] = { 736 { IPW_RATE_DS1, 2 }, 737 { IPW_RATE_DS2, 4 }, 738 { IPW_RATE_DS5, 11 }, 739 { IPW_RATE_DS11, 22 }, 740 }; 741 uint32_t val; 742 int rate, i; 743 744 imr->ifm_status = IFM_AVALID; 745 imr->ifm_active = IFM_IEEE80211; 746 if (ic->ic_state == IEEE80211_S_RUN) 747 imr->ifm_status |= IFM_ACTIVE; 748 749 /* read current transmission rate from adapter */ 750 val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE) & 0xf; 751 752 /* convert ipw rate to 802.11 rate */ 753 for (i = 0; i < N(rates) && rates[i].val != val; i++); 754 rate = (i < N(rates)) ? rates[i].rate : 0; 755 756 imr->ifm_active |= IFM_IEEE80211_11B; 757 imr->ifm_active |= ieee80211_rate2media(ic, rate, IEEE80211_MODE_11B); 758 switch (ic->ic_opmode) { 759 case IEEE80211_M_STA: 760 break; 761 762 case IEEE80211_M_IBSS: 763 imr->ifm_active |= IFM_IEEE80211_ADHOC; 764 break; 765 766 case IEEE80211_M_MONITOR: 767 imr->ifm_active |= IFM_IEEE80211_MONITOR; 768 break; 769 770 case IEEE80211_M_AHDEMO: 771 case IEEE80211_M_HOSTAP: 772 /* should not get there */ 773 break; 774 } 775 #undef N 776 } 777 778 static int 779 ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, 780 int arg) 781 { 782 struct ifnet *ifp = ic->ic_ifp; 783 struct ipw_softc *sc = ifp->if_softc; 784 struct ieee80211_node *ni; 785 uint8_t macaddr[IEEE80211_ADDR_LEN]; 786 uint32_t len; 787 struct ipw_rx_radiotap_header *wr = &sc->sc_rxtap; 788 struct ipw_tx_radiotap_header *wt = &sc->sc_txtap; 789 790 switch (nstate) { 791 case IEEE80211_S_INIT: 792 break; 793 default: 794 KASSERT(ic->ic_curchan != IEEE80211_CHAN_ANYC); 795 KASSERT(ic->ic_curchan != NULL); 796 wt->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 797 wt->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 798 wr->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 799 wr->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 800 break; 801 } 802 803 switch (nstate) { 804 case IEEE80211_S_RUN: 805 DELAY(200); /* firmware needs a short delay here */ 806 807 len = IEEE80211_ADDR_LEN; 808 ipw_read_table2(sc, IPW_INFO_CURRENT_BSSID, macaddr, &len); 809 810 ni = ieee80211_find_node(&ic->ic_scan, macaddr); 811 if (ni == NULL) 812 break; 813 814 ieee80211_ref_node(ni); 815 ieee80211_sta_join(ic, ni); 816 ieee80211_node_authorize(ni); 817 818 if (ic->ic_opmode == IEEE80211_M_STA) 819 ieee80211_notify_node_join(ic, ni, 1); 820 break; 821 822 case IEEE80211_S_INIT: 823 case IEEE80211_S_SCAN: 824 case IEEE80211_S_AUTH: 825 case IEEE80211_S_ASSOC: 826 break; 827 } 828 829 ic->ic_state = nstate; 830 return 0; 831 } 832 833 /* 834 * Read 16 bits at address 'addr' from the serial EEPROM. 835 */ 836 static uint16_t 837 ipw_read_prom_word(struct ipw_softc *sc, uint8_t addr) 838 { 839 uint32_t tmp; 840 uint16_t val; 841 int n; 842 843 /* clock C once before the first command */ 844 IPW_EEPROM_CTL(sc, 0); 845 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 846 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 847 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 848 849 /* write start bit (1) */ 850 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 851 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 852 853 /* write READ opcode (10) */ 854 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 855 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 856 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 857 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 858 859 /* write address A7-A0 */ 860 for (n = 7; n >= 0; n--) { 861 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 862 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D)); 863 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 864 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D) | IPW_EEPROM_C); 865 } 866 867 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 868 869 /* read data Q15-Q0 */ 870 val = 0; 871 for (n = 15; n >= 0; n--) { 872 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 873 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 874 tmp = MEM_READ_4(sc, IPW_MEM_EEPROM_CTL); 875 val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n; 876 } 877 878 IPW_EEPROM_CTL(sc, 0); 879 880 /* clear Chip Select and clock C */ 881 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 882 IPW_EEPROM_CTL(sc, 0); 883 IPW_EEPROM_CTL(sc, IPW_EEPROM_C); 884 885 return le16toh(val); 886 } 887 888 static void 889 ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 890 { 891 892 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof (struct ipw_cmd), 893 BUS_DMASYNC_POSTREAD); 894 895 #ifdef IPW_DEBUG 896 struct ipw_cmd *cmd = mtod(sbuf->m, struct ipw_cmd *); 897 898 DPRINTFN(2, ("cmd ack'ed (%u, %u, %u, %u, %u)\n", le32toh(cmd->type), 899 le32toh(cmd->subtype), le32toh(cmd->seq), le32toh(cmd->len), 900 le32toh(cmd->status))); 901 #endif 902 903 wakeup(&sc->cmd); 904 } 905 906 static void 907 ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 908 { 909 struct ieee80211com *ic = &sc->sc_ic; 910 struct ifnet *ifp = sc->sc_ic.ic_ifp; 911 uint32_t state; 912 913 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof state, 914 BUS_DMASYNC_POSTREAD); 915 916 state = le32toh(*mtod(sbuf->m, uint32_t *)); 917 918 DPRINTFN(2, ("entering state %u\n", state)); 919 920 switch (state) { 921 case IPW_STATE_ASSOCIATED: 922 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 923 break; 924 925 case IPW_STATE_SCANNING: 926 /* don't leave run state on background scan */ 927 if (ic->ic_state != IEEE80211_S_RUN) 928 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 929 930 ic->ic_flags |= IEEE80211_F_SCAN; 931 break; 932 933 case IPW_STATE_SCAN_COMPLETE: 934 ieee80211_notify_scan_done(ic); 935 ic->ic_flags &= ~IEEE80211_F_SCAN; 936 break; 937 938 case IPW_STATE_ASSOCIATION_LOST: 939 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 940 break; 941 942 case IPW_STATE_RADIO_DISABLED: 943 ic->ic_ifp->if_flags &= ~IFF_UP; 944 ipw_stop(ifp, 1); 945 break; 946 } 947 } 948 949 /* 950 * XXX: Hack to set the current channel to the value advertised in beacons or 951 * probe responses. Only used during AP detection. 952 */ 953 static void 954 ipw_fix_channel(struct ieee80211com *ic, struct mbuf *m) 955 { 956 struct ieee80211_frame *wh; 957 uint8_t subtype; 958 uint8_t *frm, *efrm; 959 960 wh = mtod(m, struct ieee80211_frame *); 961 962 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_MGT) 963 return; 964 965 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 966 967 if (subtype != IEEE80211_FC0_SUBTYPE_BEACON && 968 subtype != IEEE80211_FC0_SUBTYPE_PROBE_RESP) 969 return; 970 971 frm = (uint8_t *)(wh + 1); 972 efrm = mtod(m, uint8_t *) + m->m_len; 973 974 frm += 12; /* skip tstamp, bintval and capinfo fields */ 975 while (frm < efrm) { 976 if (*frm == IEEE80211_ELEMID_DSPARMS) 977 #if IEEE80211_CHAN_MAX < 255 978 if (frm[2] <= IEEE80211_CHAN_MAX) 979 #endif 980 ic->ic_curchan = &ic->ic_channels[frm[2]]; 981 982 frm += frm[1] + 2; 983 } 984 } 985 986 static void 987 ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 988 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 989 { 990 struct ieee80211com *ic = &sc->sc_ic; 991 struct ifnet *ifp = &sc->sc_if; 992 struct mbuf *mnew, *m; 993 struct ieee80211_frame *wh; 994 struct ieee80211_node *ni; 995 int error; 996 997 DPRINTFN(5, ("received frame len=%u, rssi=%u\n", le32toh(status->len), 998 status->rssi)); 999 1000 if (le32toh(status->len) < sizeof (struct ieee80211_frame_min) || 1001 le32toh(status->len) > MCLBYTES) 1002 return; 1003 1004 /* 1005 * Try to allocate a new mbuf for this ring element and load it before 1006 * processing the current mbuf. If the ring element cannot be loaded, 1007 * drop the received packet and reuse the old mbuf. In the unlikely 1008 * case that the old mbuf can't be reloaded either, explicitly panic. 1009 */ 1010 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1011 if (mnew == NULL) { 1012 aprint_error_dev(sc->sc_dev, "could not allocate rx mbuf\n"); 1013 ifp->if_ierrors++; 1014 return; 1015 } 1016 1017 MCLGET(mnew, M_DONTWAIT); 1018 if (!(mnew->m_flags & M_EXT)) { 1019 aprint_error_dev(sc->sc_dev, "could not allocate rx mbuf cluster\n"); 1020 m_freem(mnew); 1021 ifp->if_ierrors++; 1022 return; 1023 } 1024 1025 mnew->m_pkthdr.len = mnew->m_len = mnew->m_ext.ext_size; 1026 1027 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, le32toh(status->len), 1028 BUS_DMASYNC_POSTREAD); 1029 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1030 1031 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, mnew, 1032 BUS_DMA_READ | BUS_DMA_NOWAIT); 1033 if (error != 0) { 1034 aprint_error_dev(sc->sc_dev, "could not load rx buf DMA map\n"); 1035 m_freem(mnew); 1036 1037 /* try to reload the old mbuf */ 1038 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, 1039 sbuf->m, BUS_DMA_READ | BUS_DMA_NOWAIT); 1040 if (error != 0) { 1041 /* very unlikely that it will fail... */ 1042 panic("%s: unable to remap rx buf", 1043 device_xname(sc->sc_dev)); 1044 } 1045 ifp->if_ierrors++; 1046 return; 1047 } 1048 1049 /* 1050 * New mbuf successfully loaded, update Rx ring and continue 1051 * processing. 1052 */ 1053 m = sbuf->m; 1054 sbuf->m = mnew; 1055 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 1056 1057 /* finalize mbuf */ 1058 m_set_rcvif(m, ifp); 1059 m->m_pkthdr.len = m->m_len = le32toh(status->len); 1060 1061 if (sc->sc_drvbpf != NULL) { 1062 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 1063 1064 tap->wr_antsignal = status->rssi; 1065 1066 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 1067 } 1068 1069 if (ic->ic_state == IEEE80211_S_SCAN) 1070 ipw_fix_channel(ic, m); 1071 1072 wh = mtod(m, struct ieee80211_frame *); 1073 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 1074 1075 /* send the frame to the 802.11 layer */ 1076 ieee80211_input(ic, m, ni, status->rssi, 0); 1077 1078 /* node is no longer needed */ 1079 ieee80211_free_node(ni); 1080 1081 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, 1082 sbuf->map->dm_mapsize, BUS_DMASYNC_PREREAD); 1083 } 1084 1085 static void 1086 ipw_rx_intr(struct ipw_softc *sc) 1087 { 1088 struct ipw_status *status; 1089 struct ipw_soft_bd *sbd; 1090 struct ipw_soft_buf *sbuf; 1091 uint32_t r, i; 1092 1093 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1094 return; 1095 1096 r = CSR_READ_4(sc, IPW_CSR_RX_READ); 1097 1098 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 1099 1100 /* firmware was killed, stop processing received frames */ 1101 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1102 return; 1103 1104 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 1105 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1106 BUS_DMASYNC_POSTREAD); 1107 1108 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 1109 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 1110 BUS_DMASYNC_POSTREAD); 1111 1112 status = &sc->status_list[i]; 1113 sbd = &sc->srbd_list[i]; 1114 sbuf = sbd->priv; 1115 1116 switch (le16toh(status->code) & 0xf) { 1117 case IPW_STATUS_CODE_COMMAND: 1118 ipw_command_intr(sc, sbuf); 1119 break; 1120 1121 case IPW_STATUS_CODE_NEWSTATE: 1122 ipw_newstate_intr(sc, sbuf); 1123 break; 1124 1125 case IPW_STATUS_CODE_DATA_802_3: 1126 case IPW_STATUS_CODE_DATA_802_11: 1127 ipw_data_intr(sc, status, sbd, sbuf); 1128 break; 1129 1130 case IPW_STATUS_CODE_NOTIFICATION: 1131 DPRINTFN(2, ("received notification\n")); 1132 break; 1133 1134 default: 1135 aprint_error_dev(sc->sc_dev, "unknown status code %u\n", 1136 le16toh(status->code)); 1137 } 1138 1139 sbd->bd->flags = 0; 1140 1141 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 1142 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1143 BUS_DMASYNC_PREREAD); 1144 1145 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 1146 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 1147 BUS_DMASYNC_PREREAD); 1148 } 1149 1150 /* Tell the firmware what we have processed */ 1151 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 1152 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 1153 } 1154 1155 static void 1156 ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 1157 { 1158 struct ipw_soft_hdr *shdr; 1159 struct ipw_soft_buf *sbuf; 1160 1161 switch (sbd->type) { 1162 case IPW_SBD_TYPE_COMMAND: 1163 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 1164 0, sizeof(struct ipw_cmd), BUS_DMASYNC_POSTWRITE); 1165 /* bus_dmamap_unload(sc->sc_dmat, sc->cmd_map); */ 1166 break; 1167 1168 case IPW_SBD_TYPE_HEADER: 1169 shdr = sbd->priv; 1170 bus_dmamap_sync(sc->sc_dmat, sc->hdr_map, 1171 shdr->offset, sizeof(struct ipw_hdr), BUS_DMASYNC_POSTWRITE); 1172 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 1173 break; 1174 1175 case IPW_SBD_TYPE_DATA: 1176 sbuf = sbd->priv; 1177 1178 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 1179 0, MCLBYTES, BUS_DMASYNC_POSTWRITE); 1180 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1181 m_freem(sbuf->m); 1182 if (sbuf->ni != NULL) 1183 ieee80211_free_node(sbuf->ni); 1184 /* kill watchdog timer */ 1185 sc->sc_tx_timer = 0; 1186 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 1187 break; 1188 } 1189 sbd->type = IPW_SBD_TYPE_NOASSOC; 1190 } 1191 1192 static void 1193 ipw_tx_intr(struct ipw_softc *sc) 1194 { 1195 struct ifnet *ifp = &sc->sc_if; 1196 struct ipw_soft_bd *sbd; 1197 uint32_t r, i; 1198 1199 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1200 return; 1201 1202 r = CSR_READ_4(sc, IPW_CSR_TX_READ); 1203 1204 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) { 1205 sbd = &sc->stbd_list[i]; 1206 1207 if (sbd->type == IPW_SBD_TYPE_DATA) 1208 ifp->if_opackets++; 1209 1210 ipw_release_sbd(sc, sbd); 1211 sc->txfree++; 1212 } 1213 1214 /* remember what the firmware has processed */ 1215 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 1216 1217 /* Call start() since some buffer descriptors have been released */ 1218 ifp->if_flags &= ~IFF_OACTIVE; 1219 if_schedule_deferred_start(ifp); 1220 } 1221 1222 static int 1223 ipw_intr(void *arg) 1224 { 1225 struct ipw_softc *sc = arg; 1226 uint32_t r; 1227 1228 r = CSR_READ_4(sc, IPW_CSR_INTR); 1229 if (r == 0 || r == 0xffffffff) 1230 return 0; 1231 1232 /* Disable interrupts */ 1233 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1234 1235 if (r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR)) { 1236 aprint_error_dev(sc->sc_dev, "fatal error\n"); 1237 sc->sc_ic.ic_ifp->if_flags &= ~IFF_UP; 1238 ipw_stop(&sc->sc_if, 1); 1239 } 1240 1241 if (r & IPW_INTR_FW_INIT_DONE) { 1242 if (!(r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR))) 1243 wakeup(sc); 1244 } 1245 1246 if (r & IPW_INTR_RX_TRANSFER) 1247 ipw_rx_intr(sc); 1248 1249 if (r & IPW_INTR_TX_TRANSFER) 1250 ipw_tx_intr(sc); 1251 1252 /* Acknowledge all interrupts */ 1253 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 1254 1255 /* Re-enable interrupts */ 1256 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1257 1258 return 0; 1259 } 1260 1261 /* 1262 * Send a command to the firmware and wait for the acknowledgement. 1263 */ 1264 static int 1265 ipw_cmd(struct ipw_softc *sc, uint32_t type, void *data, uint32_t len) 1266 { 1267 struct ipw_soft_bd *sbd; 1268 1269 sbd = &sc->stbd_list[sc->txcur]; 1270 1271 sc->cmd.type = htole32(type); 1272 sc->cmd.subtype = 0; 1273 sc->cmd.len = htole32(len); 1274 sc->cmd.seq = 0; 1275 1276 (void)memcpy(sc->cmd.data, data, len); 1277 1278 sbd->type = IPW_SBD_TYPE_COMMAND; 1279 sbd->bd->physaddr = htole32(sc->cmd_map->dm_segs[0].ds_addr); 1280 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 1281 sbd->bd->nfrag = 1; 1282 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 1283 IPW_BD_FLAG_TX_LAST_FRAGMENT; 1284 1285 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 0, sizeof (struct ipw_cmd), 1286 BUS_DMASYNC_PREWRITE); 1287 1288 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1289 sc->txcur * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1290 BUS_DMASYNC_PREWRITE); 1291 1292 DPRINTFN(2, ("sending command (%u, %u, %u, %u)\n", type, 0, 0, len)); 1293 1294 /* kick firmware */ 1295 sc->txfree--; 1296 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1297 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1298 1299 /* Wait at most one second for command to complete */ 1300 return tsleep(&sc->cmd, 0, "ipwcmd", hz); 1301 } 1302 1303 static int 1304 ipw_tx_start(struct ifnet *ifp, struct mbuf *m0, struct ieee80211_node *ni) 1305 { 1306 struct ipw_softc *sc = ifp->if_softc; 1307 struct ieee80211com *ic = &sc->sc_ic; 1308 struct ieee80211_frame *wh; 1309 struct ipw_soft_bd *sbd; 1310 struct ipw_soft_hdr *shdr; 1311 struct ipw_soft_buf *sbuf; 1312 struct ieee80211_key *k; 1313 struct mbuf *mnew; 1314 int error, i; 1315 1316 wh = mtod(m0, struct ieee80211_frame *); 1317 1318 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1319 k = ieee80211_crypto_encap(ic, ni, m0); 1320 if (k == NULL) { 1321 m_freem(m0); 1322 return ENOBUFS; 1323 } 1324 1325 /* packet header may have moved, reset our local pointer */ 1326 wh = mtod(m0, struct ieee80211_frame *); 1327 } 1328 1329 if (sc->sc_drvbpf != NULL) { 1330 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 1331 1332 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 1333 } 1334 1335 shdr = TAILQ_FIRST(&sc->sc_free_shdr); 1336 sbuf = TAILQ_FIRST(&sc->sc_free_sbuf); 1337 KASSERT(shdr != NULL && sbuf != NULL); 1338 1339 shdr->hdr->type = htole32(IPW_HDR_TYPE_SEND); 1340 shdr->hdr->subtype = 0; 1341 shdr->hdr->encrypted = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0; 1342 shdr->hdr->encrypt = 0; 1343 shdr->hdr->keyidx = 0; 1344 shdr->hdr->keysz = 0; 1345 shdr->hdr->fragmentsz = 0; 1346 IEEE80211_ADDR_COPY(shdr->hdr->src_addr, wh->i_addr2); 1347 if (ic->ic_opmode == IEEE80211_M_STA) 1348 IEEE80211_ADDR_COPY(shdr->hdr->dst_addr, wh->i_addr3); 1349 else 1350 IEEE80211_ADDR_COPY(shdr->hdr->dst_addr, wh->i_addr1); 1351 1352 /* trim IEEE802.11 header */ 1353 m_adj(m0, sizeof (struct ieee80211_frame)); 1354 1355 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m0, BUS_DMA_NOWAIT); 1356 if (error != 0 && error != EFBIG) { 1357 aprint_error_dev(sc->sc_dev, "could not map mbuf (error %d)\n", 1358 error); 1359 m_freem(m0); 1360 return error; 1361 } 1362 1363 if (error != 0) { 1364 /* too many fragments, linearize */ 1365 1366 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1367 if (mnew == NULL) { 1368 m_freem(m0); 1369 return ENOMEM; 1370 } 1371 1372 M_COPY_PKTHDR(mnew, m0); 1373 1374 /* If the data won't fit in the header, get a cluster */ 1375 if (m0->m_pkthdr.len > MHLEN) { 1376 MCLGET(mnew, M_DONTWAIT); 1377 if (!(mnew->m_flags & M_EXT)) { 1378 m_freem(m0); 1379 m_freem(mnew); 1380 return ENOMEM; 1381 } 1382 } 1383 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(mnew, void *)); 1384 m_freem(m0); 1385 mnew->m_len = mnew->m_pkthdr.len; 1386 m0 = mnew; 1387 1388 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m0, 1389 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1390 if (error != 0) { 1391 aprint_error_dev(sc->sc_dev, "could not map mbuf (error %d)\n", error); 1392 m_freem(m0); 1393 return error; 1394 } 1395 } 1396 1397 TAILQ_REMOVE(&sc->sc_free_sbuf, sbuf, next); 1398 TAILQ_REMOVE(&sc->sc_free_shdr, shdr, next); 1399 1400 sbd = &sc->stbd_list[sc->txcur]; 1401 sbd->type = IPW_SBD_TYPE_HEADER; 1402 sbd->priv = shdr; 1403 sbd->bd->physaddr = htole32(shdr->addr); 1404 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 1405 sbd->bd->nfrag = 1 + sbuf->map->dm_nsegs; 1406 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 1407 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1408 1409 DPRINTFN(5, ("sending tx hdr (%u, %u, %u, %u, )\n", 1410 shdr->hdr->type, shdr->hdr->subtype, shdr->hdr->encrypted, 1411 shdr->hdr->encrypt)); 1412 DPRINTFN(5, ("%s->", ether_sprintf(shdr->hdr->src_addr))); 1413 DPRINTFN(5, ("%s\n", ether_sprintf(shdr->hdr->dst_addr))); 1414 1415 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1416 sc->txcur * sizeof (struct ipw_bd), 1417 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1418 1419 sc->txfree--; 1420 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1421 1422 sbuf->m = m0; 1423 sbuf->ni = ni; 1424 1425 for (i = 0; i < sbuf->map->dm_nsegs; i++) { 1426 sbd = &sc->stbd_list[sc->txcur]; 1427 1428 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[i].ds_addr); 1429 sbd->bd->len = htole32(sbuf->map->dm_segs[i].ds_len); 1430 sbd->bd->nfrag = 0; 1431 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 1432 if (i == sbuf->map->dm_nsegs - 1) { 1433 sbd->type = IPW_SBD_TYPE_DATA; 1434 sbd->priv = sbuf; 1435 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 1436 } else { 1437 sbd->type = IPW_SBD_TYPE_NOASSOC; 1438 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1439 } 1440 1441 DPRINTFN(5, ("sending fragment (%d, %d)\n", i, 1442 (int)sbuf->map->dm_segs[i].ds_len)); 1443 1444 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1445 sc->txcur * sizeof (struct ipw_bd), 1446 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1447 1448 sc->txfree--; 1449 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1450 } 1451 1452 bus_dmamap_sync(sc->sc_dmat, sc->hdr_map, shdr->offset, 1453 sizeof (struct ipw_hdr), BUS_DMASYNC_PREWRITE); 1454 1455 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, MCLBYTES, 1456 BUS_DMASYNC_PREWRITE); 1457 1458 /* Inform firmware about this new packet */ 1459 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1460 1461 return 0; 1462 } 1463 1464 static void 1465 ipw_start(struct ifnet *ifp) 1466 { 1467 struct ipw_softc *sc = ifp->if_softc; 1468 struct ieee80211com *ic = &sc->sc_ic; 1469 struct mbuf *m0; 1470 struct ether_header *eh; 1471 struct ieee80211_node *ni; 1472 1473 1474 if (ic->ic_state != IEEE80211_S_RUN) 1475 return; 1476 1477 for (;;) { 1478 IF_DEQUEUE(&ifp->if_snd, m0); 1479 if (m0 == NULL) 1480 break; 1481 1482 if (sc->txfree < 1 + IPW_MAX_NSEG) { 1483 IF_PREPEND(&ifp->if_snd, m0); 1484 ifp->if_flags |= IFF_OACTIVE; 1485 break; 1486 } 1487 1488 if (m0->m_len < sizeof (struct ether_header) && 1489 (m0 = m_pullup(m0, sizeof (struct ether_header))) == NULL) 1490 continue; 1491 1492 eh = mtod(m0, struct ether_header *); 1493 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1494 if (ni == NULL) { 1495 m_freem(m0); 1496 continue; 1497 } 1498 1499 bpf_mtap(ifp, m0); 1500 1501 m0 = ieee80211_encap(ic, m0, ni); 1502 if (m0 == NULL) { 1503 ieee80211_free_node(ni); 1504 continue; 1505 } 1506 1507 bpf_mtap3(ic->ic_rawbpf, m0); 1508 1509 if (ipw_tx_start(ifp, m0, ni) != 0) { 1510 ieee80211_free_node(ni); 1511 ifp->if_oerrors++; 1512 break; 1513 } 1514 1515 /* start watchdog timer */ 1516 sc->sc_tx_timer = 5; 1517 ifp->if_timer = 1; 1518 } 1519 } 1520 1521 static void 1522 ipw_watchdog(struct ifnet *ifp) 1523 { 1524 struct ipw_softc *sc = ifp->if_softc; 1525 1526 ifp->if_timer = 0; 1527 1528 if (sc->sc_tx_timer > 0) { 1529 if (--sc->sc_tx_timer == 0) { 1530 aprint_error_dev(sc->sc_dev, "device timeout\n"); 1531 ifp->if_oerrors++; 1532 ifp->if_flags &= ~IFF_UP; 1533 ipw_stop(ifp, 1); 1534 return; 1535 } 1536 ifp->if_timer = 1; 1537 } 1538 1539 ieee80211_watchdog(&sc->sc_ic); 1540 } 1541 1542 static int 1543 ipw_get_table1(struct ipw_softc *sc, uint32_t *tbl) 1544 { 1545 uint32_t addr, size, data, i; 1546 int error; 1547 1548 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1549 return ENOTTY; 1550 1551 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, sc->table1_base); 1552 1553 size = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 1554 if ((error = copyout(&size, tbl, sizeof(size))) != 0) 1555 return error; 1556 1557 for (i = 1, ++tbl; i < size; i++, tbl++) { 1558 addr = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 1559 data = MEM_READ_4(sc, addr); 1560 if ((error = copyout(&data, tbl, sizeof(data))) != 0) 1561 return error; 1562 } 1563 return 0; 1564 } 1565 1566 static int 1567 ipw_get_radio(struct ipw_softc *sc, int *ret) 1568 { 1569 uint32_t addr, data; 1570 1571 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1572 return ENOTTY; 1573 1574 addr = ipw_read_table1(sc, IPW_INFO_EEPROM_ADDRESS); 1575 if ((MEM_READ_4(sc, addr + 32) >> 24) & 1) 1576 data = -1; 1577 else if (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED) 1578 data = 0; 1579 else 1580 data = 1; 1581 1582 return copyout(&data, ret, sizeof(data)); 1583 } 1584 1585 static int 1586 ipw_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1587 { 1588 #define IS_RUNNING(ifp) \ 1589 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 1590 1591 struct ipw_softc *sc = ifp->if_softc; 1592 struct ieee80211com *ic = &sc->sc_ic; 1593 struct ifreq *ifr = (struct ifreq *)data; 1594 int s, error = 0; 1595 1596 s = splnet(); 1597 1598 switch (cmd) { 1599 case SIOCSIFFLAGS: 1600 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 1601 break; 1602 if (ifp->if_flags & IFF_UP) { 1603 if (!(ifp->if_flags & IFF_RUNNING)) 1604 ipw_init(ifp); 1605 } else { 1606 if (ifp->if_flags & IFF_RUNNING) 1607 ipw_stop(ifp, 1); 1608 } 1609 break; 1610 1611 case SIOCADDMULTI: 1612 case SIOCDELMULTI: 1613 /* XXX no h/w multicast filter? --dyoung */ 1614 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1615 /* setup multicast filter, etc */ 1616 error = 0; 1617 } 1618 break; 1619 1620 case SIOCGTABLE1: 1621 error = ipw_get_table1(sc, (uint32_t *)ifr->ifr_data); 1622 break; 1623 1624 case SIOCGRADIO: 1625 error = ipw_get_radio(sc, (int *)ifr->ifr_data); 1626 break; 1627 1628 case SIOCSIFMEDIA: 1629 if (ifr->ifr_media & IFM_IEEE80211_ADHOC) 1630 sc->sc_fwname = "ipw2100-1.2-i.fw"; 1631 else if (ifr->ifr_media & IFM_IEEE80211_MONITOR) 1632 sc->sc_fwname = "ipw2100-1.2-p.fw"; 1633 else 1634 sc->sc_fwname = "ipw2100-1.2.fw"; 1635 1636 ipw_free_firmware(sc); 1637 /* FALLTRHOUGH */ 1638 default: 1639 error = ieee80211_ioctl(&sc->sc_ic, cmd, data); 1640 if (error != ENETRESET) 1641 break; 1642 1643 if (error == ENETRESET) { 1644 if (IS_RUNNING(ifp) && 1645 (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)) 1646 ipw_init(ifp); 1647 error = 0; 1648 } 1649 1650 } 1651 1652 splx(s); 1653 return error; 1654 #undef IS_RUNNING 1655 } 1656 1657 static uint32_t 1658 ipw_read_table1(struct ipw_softc *sc, uint32_t off) 1659 { 1660 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 1661 } 1662 1663 static void 1664 ipw_write_table1(struct ipw_softc *sc, uint32_t off, uint32_t info) 1665 { 1666 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 1667 } 1668 1669 static int 1670 ipw_read_table2(struct ipw_softc *sc, uint32_t off, void *buf, uint32_t *len) 1671 { 1672 uint32_t addr, info; 1673 uint16_t count, size; 1674 uint32_t total; 1675 1676 /* addr[4] + count[2] + size[2] */ 1677 addr = MEM_READ_4(sc, sc->table2_base + off); 1678 info = MEM_READ_4(sc, sc->table2_base + off + 4); 1679 1680 count = info >> 16; 1681 size = info & 0xffff; 1682 total = count * size; 1683 1684 if (total > *len) { 1685 *len = total; 1686 return EINVAL; 1687 } 1688 1689 *len = total; 1690 ipw_read_mem_1(sc, addr, buf, total); 1691 1692 return 0; 1693 } 1694 1695 static void 1696 ipw_stop_master(struct ipw_softc *sc) 1697 { 1698 int ntries; 1699 1700 /* disable interrupts */ 1701 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1702 1703 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1704 for (ntries = 0; ntries < 50; ntries++) { 1705 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1706 break; 1707 DELAY(10); 1708 } 1709 if (ntries == 50) 1710 aprint_error_dev(sc->sc_dev, "timeout waiting for master\n"); 1711 1712 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1713 IPW_RST_PRINCETON_RESET); 1714 1715 sc->flags &= ~IPW_FLAG_FW_INITED; 1716 } 1717 1718 static int 1719 ipw_reset(struct ipw_softc *sc) 1720 { 1721 int ntries; 1722 1723 ipw_stop_master(sc); 1724 1725 /* move adapter to D0 state */ 1726 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1727 IPW_CTL_INIT); 1728 1729 /* wait for clock stabilization */ 1730 for (ntries = 0; ntries < 1000; ntries++) { 1731 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY) 1732 break; 1733 DELAY(200); 1734 } 1735 if (ntries == 1000) 1736 return EIO; 1737 1738 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1739 IPW_RST_SW_RESET); 1740 1741 DELAY(10); 1742 1743 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1744 IPW_CTL_INIT); 1745 1746 return 0; 1747 } 1748 1749 /* 1750 * Upload the microcode to the device. 1751 */ 1752 static int 1753 ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size) 1754 { 1755 int ntries; 1756 1757 MEM_WRITE_4(sc, 0x3000e0, 0x80000000); 1758 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1759 1760 MEM_WRITE_2(sc, 0x220000, 0x0703); 1761 MEM_WRITE_2(sc, 0x220000, 0x0707); 1762 1763 MEM_WRITE_1(sc, 0x210014, 0x72); 1764 MEM_WRITE_1(sc, 0x210014, 0x72); 1765 1766 MEM_WRITE_1(sc, 0x210000, 0x40); 1767 MEM_WRITE_1(sc, 0x210000, 0x00); 1768 MEM_WRITE_1(sc, 0x210000, 0x40); 1769 1770 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1771 1772 MEM_WRITE_1(sc, 0x210000, 0x00); 1773 MEM_WRITE_1(sc, 0x210000, 0x00); 1774 MEM_WRITE_1(sc, 0x210000, 0x80); 1775 1776 MEM_WRITE_2(sc, 0x220000, 0x0703); 1777 MEM_WRITE_2(sc, 0x220000, 0x0707); 1778 1779 MEM_WRITE_1(sc, 0x210014, 0x72); 1780 MEM_WRITE_1(sc, 0x210014, 0x72); 1781 1782 MEM_WRITE_1(sc, 0x210000, 0x00); 1783 MEM_WRITE_1(sc, 0x210000, 0x80); 1784 1785 for (ntries = 0; ntries < 10; ntries++) { 1786 if (MEM_READ_1(sc, 0x210000) & 1) 1787 break; 1788 DELAY(10); 1789 } 1790 if (ntries == 10) { 1791 aprint_error_dev(sc->sc_dev, "timeout waiting for ucode to initialize\n"); 1792 return EIO; 1793 } 1794 1795 MEM_WRITE_4(sc, 0x3000e0, 0); 1796 1797 return 0; 1798 } 1799 1800 /* set of macros to handle unaligned little endian data in firmware image */ 1801 #define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1802 #define GETLE16(p) ((p)[0] | (p)[1] << 8) 1803 static int 1804 ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size) 1805 { 1806 u_char *p, *end; 1807 uint32_t dst; 1808 uint16_t len; 1809 int error; 1810 1811 p = fw; 1812 end = fw + size; 1813 while (p < end) { 1814 dst = GETLE32(p); p += 4; 1815 len = GETLE16(p); p += 2; 1816 1817 ipw_write_mem_1(sc, dst, p, len); 1818 p += len; 1819 } 1820 1821 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1822 IPW_IO_LED_OFF); 1823 1824 /* enable interrupts */ 1825 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1826 1827 /* kick the firmware */ 1828 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1829 1830 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1831 IPW_CTL_ALLOW_STANDBY); 1832 1833 /* wait at most one second for firmware initialization to complete */ 1834 if ((error = tsleep(sc, 0, "ipwinit", hz)) != 0) { 1835 aprint_error_dev(sc->sc_dev, "timeout waiting for firmware initialization " 1836 "to complete\n"); 1837 return error; 1838 } 1839 1840 CSR_WRITE_4(sc, IPW_CSR_IO, CSR_READ_4(sc, IPW_CSR_IO) | 1841 IPW_IO_GPIO1_MASK | IPW_IO_GPIO3_MASK); 1842 1843 return 0; 1844 } 1845 1846 /* 1847 * Store firmware into kernel memory so we can download it when we need to, 1848 * e.g when the adapter wakes up from suspend mode. 1849 */ 1850 static int 1851 ipw_cache_firmware(struct ipw_softc *sc) 1852 { 1853 struct ipw_firmware *fw = &sc->fw; 1854 struct ipw_firmware_hdr hdr; 1855 firmware_handle_t fwh; 1856 off_t fwsz, p; 1857 int error; 1858 1859 ipw_free_firmware(sc); 1860 1861 if (ipw_accept_eula == 0) { 1862 aprint_error_dev(sc->sc_dev, 1863 "EULA not accepted; please see the ipw(4) man page.\n"); 1864 return EPERM; 1865 } 1866 1867 if ((error = firmware_open("if_ipw", sc->sc_fwname, &fwh)) != 0) 1868 goto fail0; 1869 1870 fwsz = firmware_get_size(fwh); 1871 1872 if (fwsz < sizeof(hdr)) 1873 goto fail2; 1874 1875 if ((error = firmware_read(fwh, 0, &hdr, sizeof(hdr))) != 0) 1876 goto fail2; 1877 1878 fw->main_size = le32toh(hdr.main_size); 1879 fw->ucode_size = le32toh(hdr.ucode_size); 1880 1881 fw->main = firmware_malloc(fw->main_size); 1882 if (fw->main == NULL) { 1883 error = ENOMEM; 1884 goto fail1; 1885 } 1886 1887 fw->ucode = firmware_malloc(fw->ucode_size); 1888 if (fw->ucode == NULL) { 1889 error = ENOMEM; 1890 goto fail2; 1891 } 1892 1893 p = sizeof(hdr); 1894 if ((error = firmware_read(fwh, p, fw->main, fw->main_size)) != 0) 1895 goto fail3; 1896 1897 p += fw->main_size; 1898 if ((error = firmware_read(fwh, p, fw->ucode, fw->ucode_size)) != 0) 1899 goto fail3; 1900 1901 DPRINTF(("Firmware cached: main %u, ucode %u\n", fw->main_size, 1902 fw->ucode_size)); 1903 1904 sc->flags |= IPW_FLAG_FW_CACHED; 1905 1906 firmware_close(fwh); 1907 1908 return 0; 1909 1910 fail3: firmware_free(fw->ucode, fw->ucode_size); 1911 fail2: firmware_free(fw->main, fw->main_size); 1912 fail1: firmware_close(fwh); 1913 fail0: 1914 return error; 1915 } 1916 1917 static void 1918 ipw_free_firmware(struct ipw_softc *sc) 1919 { 1920 if (!(sc->flags & IPW_FLAG_FW_CACHED)) 1921 return; 1922 1923 firmware_free(sc->fw.main, sc->fw.main_size); 1924 firmware_free(sc->fw.ucode, sc->fw.ucode_size); 1925 1926 sc->flags &= ~IPW_FLAG_FW_CACHED; 1927 } 1928 1929 static int 1930 ipw_config(struct ipw_softc *sc) 1931 { 1932 struct ieee80211com *ic = &sc->sc_ic; 1933 struct ifnet *ifp = &sc->sc_if; 1934 struct ipw_security security; 1935 struct ieee80211_key *k; 1936 struct ipw_wep_key wepkey; 1937 struct ipw_scan_options options; 1938 struct ipw_configuration config; 1939 uint32_t data; 1940 int error, i; 1941 1942 switch (ic->ic_opmode) { 1943 case IEEE80211_M_STA: 1944 case IEEE80211_M_HOSTAP: 1945 data = htole32(IPW_MODE_BSS); 1946 break; 1947 1948 case IEEE80211_M_IBSS: 1949 case IEEE80211_M_AHDEMO: 1950 data = htole32(IPW_MODE_IBSS); 1951 break; 1952 1953 case IEEE80211_M_MONITOR: 1954 data = htole32(IPW_MODE_MONITOR); 1955 break; 1956 } 1957 DPRINTF(("Setting mode to %u\n", le32toh(data))); 1958 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 1959 if (error != 0) 1960 return error; 1961 1962 if (ic->ic_opmode == IEEE80211_M_IBSS || 1963 ic->ic_opmode == IEEE80211_M_MONITOR) { 1964 data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); 1965 DPRINTF(("Setting channel to %u\n", le32toh(data))); 1966 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 1967 if (error != 0) 1968 return error; 1969 } 1970 1971 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1972 DPRINTF(("Enabling adapter\n")); 1973 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1974 } 1975 1976 DPRINTF(("Setting MAC to %s\n", ether_sprintf(ic->ic_myaddr))); 1977 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 1978 IEEE80211_ADDR_LEN); 1979 if (error != 0) 1980 return error; 1981 1982 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 1983 IPW_CFG_PREAMBLE_AUTO | IPW_CFG_802_1x_ENABLE); 1984 1985 if (ic->ic_opmode == IEEE80211_M_IBSS) 1986 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 1987 if (ifp->if_flags & IFF_PROMISC) 1988 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 1989 config.bss_chan = htole32(0x3fff); /* channels 1-14 */ 1990 config.ibss_chan = htole32(0x7ff); /* channels 1-11 */ 1991 DPRINTF(("Setting adapter configuration 0x%08x\n", config.flags)); 1992 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 1993 if (error != 0) 1994 return error; 1995 1996 data = htole32(0x3); /* 1, 2 */ 1997 DPRINTF(("Setting basic tx rates to 0x%x\n", le32toh(data))); 1998 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 1999 if (error != 0) 2000 return error; 2001 2002 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 2003 DPRINTF(("Setting tx rates to 0x%x\n", le32toh(data))); 2004 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 2005 if (error != 0) 2006 return error; 2007 2008 data = htole32(IPW_POWER_MODE_CAM); 2009 DPRINTF(("Setting power mode to %u\n", le32toh(data))); 2010 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 2011 if (error != 0) 2012 return error; 2013 2014 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2015 data = htole32(32); /* default value */ 2016 DPRINTF(("Setting tx power index to %u\n", le32toh(data))); 2017 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 2018 sizeof data); 2019 if (error != 0) 2020 return error; 2021 } 2022 2023 data = htole32(ic->ic_rtsthreshold); 2024 DPRINTF(("Setting RTS threshold to %u\n", le32toh(data))); 2025 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 2026 if (error != 0) 2027 return error; 2028 2029 data = htole32(ic->ic_fragthreshold); 2030 DPRINTF(("Setting frag threshold to %u\n", le32toh(data))); 2031 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 2032 if (error != 0) 2033 return error; 2034 2035 #ifdef IPW_DEBUG 2036 if (ipw_debug > 0) { 2037 printf("Setting ESSID to "); 2038 ieee80211_print_essid(ic->ic_des_essid, ic->ic_des_esslen); 2039 printf("\n"); 2040 } 2041 #endif 2042 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ic->ic_des_essid, 2043 ic->ic_des_esslen); 2044 if (error != 0) 2045 return error; 2046 2047 /* no mandatory BSSID */ 2048 DPRINTF(("Setting mandatory BSSID to null\n")); 2049 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 2050 if (error != 0) 2051 return error; 2052 2053 if (ic->ic_flags & IEEE80211_F_DESBSSID) { 2054 DPRINTF(("Setting desired BSSID to %s\n", 2055 ether_sprintf(ic->ic_des_bssid))); 2056 error = ipw_cmd(sc, IPW_CMD_SET_DESIRED_BSSID, 2057 ic->ic_des_bssid, IEEE80211_ADDR_LEN); 2058 if (error != 0) 2059 return error; 2060 } 2061 2062 (void)memset(&security, 0, sizeof(security)); 2063 security.authmode = (ic->ic_bss->ni_authmode == IEEE80211_AUTH_SHARED) ? 2064 IPW_AUTH_SHARED : IPW_AUTH_OPEN; 2065 security.ciphers = htole32(IPW_CIPHER_NONE); 2066 DPRINTF(("Setting authmode to %u\n", security.authmode)); 2067 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 2068 sizeof security); 2069 if (error != 0) 2070 return error; 2071 2072 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 2073 k = ic->ic_crypto.cs_nw_keys; 2074 for (i = 0; i < IEEE80211_WEP_NKID; i++, k++) { 2075 if (k->wk_keylen == 0) 2076 continue; 2077 2078 wepkey.idx = i; 2079 wepkey.len = k->wk_keylen; 2080 memset(wepkey.key, 0, sizeof(wepkey.key)); 2081 memcpy(wepkey.key, k->wk_key, k->wk_keylen); 2082 DPRINTF(("Setting wep key index %u len %u\n", 2083 wepkey.idx, wepkey.len)); 2084 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY, &wepkey, 2085 sizeof wepkey); 2086 if (error != 0) 2087 return error; 2088 } 2089 2090 data = htole32(ic->ic_crypto.cs_def_txkey); 2091 DPRINTF(("Setting tx key index to %u\n", le32toh(data))); 2092 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY_INDEX, &data, 2093 sizeof data); 2094 if (error != 0) 2095 return error; 2096 } 2097 2098 data = htole32((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) ? IPW_WEPON : 0); 2099 DPRINTF(("Setting wep flags to 0x%x\n", le32toh(data))); 2100 error = ipw_cmd(sc, IPW_CMD_SET_WEP_FLAGS, &data, sizeof data); 2101 if (error != 0) 2102 return error; 2103 2104 #if 0 2105 struct ipw_wpa_ie ie; 2106 2107 memset(&ie, 0 sizeof(ie)); 2108 ie.len = htole32(sizeof (struct ieee80211_ie_wpa)); 2109 DPRINTF(("Setting wpa ie\n")); 2110 error = ipw_cmd(sc, IPW_CMD_SET_WPA_IE, &ie, sizeof ie); 2111 if (error != 0) 2112 return error; 2113 #endif 2114 2115 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2116 data = htole32(ic->ic_bintval); 2117 DPRINTF(("Setting beacon interval to %u\n", le32toh(data))); 2118 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 2119 sizeof data); 2120 if (error != 0) 2121 return error; 2122 } 2123 2124 options.flags = 0; 2125 options.channels = htole32(0x3fff); /* scan channels 1-14 */ 2126 DPRINTF(("Setting scan options to 0x%x\n", le32toh(options.flags))); 2127 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &options, sizeof options); 2128 if (error != 0) 2129 return error; 2130 2131 /* finally, enable adapter (start scanning for an access point) */ 2132 DPRINTF(("Enabling adapter\n")); 2133 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 2134 } 2135 2136 static int 2137 ipw_init(struct ifnet *ifp) 2138 { 2139 struct ipw_softc *sc = ifp->if_softc; 2140 struct ipw_firmware *fw = &sc->fw; 2141 2142 if (!(sc->flags & IPW_FLAG_FW_CACHED)) { 2143 if (ipw_cache_firmware(sc) != 0) { 2144 aprint_error_dev(sc->sc_dev, "could not cache the firmware (%s)\n", 2145 sc->sc_fwname); 2146 goto fail; 2147 } 2148 } 2149 2150 ipw_stop(ifp, 0); 2151 2152 if (ipw_reset(sc) != 0) { 2153 aprint_error_dev(sc->sc_dev, "could not reset adapter\n"); 2154 goto fail; 2155 } 2156 2157 if (ipw_load_ucode(sc, fw->ucode, fw->ucode_size) != 0) { 2158 aprint_error_dev(sc->sc_dev, "could not load microcode\n"); 2159 goto fail; 2160 } 2161 2162 ipw_stop_master(sc); 2163 2164 /* 2165 * Setup tx, rx and status rings. 2166 */ 2167 sc->txold = IPW_NTBD - 1; 2168 sc->txcur = 0; 2169 sc->txfree = IPW_NTBD - 2; 2170 sc->rxcur = IPW_NRBD - 1; 2171 2172 CSR_WRITE_4(sc, IPW_CSR_TX_BASE, sc->tbd_map->dm_segs[0].ds_addr); 2173 CSR_WRITE_4(sc, IPW_CSR_TX_SIZE, IPW_NTBD); 2174 CSR_WRITE_4(sc, IPW_CSR_TX_READ, 0); 2175 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 2176 2177 CSR_WRITE_4(sc, IPW_CSR_RX_BASE, sc->rbd_map->dm_segs[0].ds_addr); 2178 CSR_WRITE_4(sc, IPW_CSR_RX_SIZE, IPW_NRBD); 2179 CSR_WRITE_4(sc, IPW_CSR_RX_READ, 0); 2180 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 2181 2182 CSR_WRITE_4(sc, IPW_CSR_STATUS_BASE, sc->status_map->dm_segs[0].ds_addr); 2183 2184 if (ipw_load_firmware(sc, fw->main, fw->main_size) != 0) { 2185 aprint_error_dev(sc->sc_dev, "could not load firmware\n"); 2186 goto fail; 2187 } 2188 2189 sc->flags |= IPW_FLAG_FW_INITED; 2190 2191 /* retrieve information tables base addresses */ 2192 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 2193 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 2194 2195 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 2196 2197 if (ipw_config(sc) != 0) { 2198 aprint_error_dev(sc->sc_dev, "device configuration failed\n"); 2199 goto fail; 2200 } 2201 2202 ifp->if_flags &= ~IFF_OACTIVE; 2203 ifp->if_flags |= IFF_RUNNING; 2204 2205 return 0; 2206 2207 fail: ifp->if_flags &= ~IFF_UP; 2208 ipw_stop(ifp, 0); 2209 2210 return EIO; 2211 } 2212 2213 static void 2214 ipw_stop(struct ifnet *ifp, int disable) 2215 { 2216 struct ipw_softc *sc = ifp->if_softc; 2217 struct ieee80211com *ic = &sc->sc_ic; 2218 int i; 2219 2220 ipw_stop_master(sc); 2221 2222 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 2223 2224 /* 2225 * Release tx buffers. 2226 */ 2227 for (i = 0; i < IPW_NTBD; i++) 2228 ipw_release_sbd(sc, &sc->stbd_list[i]); 2229 2230 sc->sc_tx_timer = 0; 2231 ifp->if_timer = 0; 2232 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2233 2234 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2235 } 2236 2237 static void 2238 ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2239 bus_size_t count) 2240 { 2241 for (; count > 0; offset++, datap++, count--) { 2242 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2243 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 2244 } 2245 } 2246 2247 static void 2248 ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2249 bus_size_t count) 2250 { 2251 for (; count > 0; offset++, datap++, count--) { 2252 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2253 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 2254 } 2255 } 2256 2257 SYSCTL_SETUP(sysctl_hw_ipw_accept_eula_setup, "sysctl hw.ipw.accept_eula") 2258 { 2259 const struct sysctlnode *rnode; 2260 const struct sysctlnode *cnode; 2261 2262 sysctl_createv(NULL, 0, NULL, &rnode, 2263 CTLFLAG_PERMANENT, 2264 CTLTYPE_NODE, "ipw", 2265 NULL, 2266 NULL, 0, 2267 NULL, 0, 2268 CTL_HW, CTL_CREATE, CTL_EOL); 2269 2270 sysctl_createv(NULL, 0, &rnode, &cnode, 2271 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, 2272 CTLTYPE_INT, "accept_eula", 2273 SYSCTL_DESCR("Accept Intel EULA and permit use of ipw(4) firmware"), 2274 NULL, 0, 2275 &ipw_accept_eula, sizeof(ipw_accept_eula), 2276 CTL_CREATE, CTL_EOL); 2277 } 2278
Indexes created Tue Sep 30 17:09:57 GMT 2025