if_ipw.c revision 1.65
1 /* $NetBSD: if_ipw.c,v 1.65 2017/07/29 01:54:56 riastradh Exp $ */ 2 /* FreeBSD: src/sys/dev/ipw/if_ipw.c,v 1.15 2005/11/13 17:17:40 damien Exp */ 3 4 /*- 5 * Copyright (c) 2004, 2005 6 * Damien Bergamini <damien.bergamini (at) free.fr>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: if_ipw.c,v 1.65 2017/07/29 01:54:56 riastradh Exp $"); 33 34 /*- 35 * Intel(R) PRO/Wireless 2100 MiniPCI driver 36 * http://www.intel.com/network/connectivity/products/wireless/prowireless_mobile.htm 37 */ 38 39 40 #include <sys/param.h> 41 #include <sys/sockio.h> 42 #include <sys/sysctl.h> 43 #include <sys/mbuf.h> 44 #include <sys/kernel.h> 45 #include <sys/socket.h> 46 #include <sys/systm.h> 47 #include <sys/malloc.h> 48 #include <sys/conf.h> 49 #include <sys/proc.h> 50 51 #include <sys/bus.h> 52 #include <machine/endian.h> 53 #include <sys/intr.h> 54 55 #include <dev/pci/pcireg.h> 56 #include <dev/pci/pcivar.h> 57 #include <dev/pci/pcidevs.h> 58 59 #include <net/bpf.h> 60 #include <net/if.h> 61 #include <net/if_arp.h> 62 #include <net/if_dl.h> 63 #include <net/if_ether.h> 64 #include <net/if_media.h> 65 #include <net/if_types.h> 66 67 #include <net80211/ieee80211_var.h> 68 #include <net80211/ieee80211_radiotap.h> 69 70 #include <netinet/in.h> 71 #include <netinet/in_systm.h> 72 #include <netinet/in_var.h> 73 #include <netinet/ip.h> 74 75 #include <dev/firmload.h> 76 77 #include <dev/pci/if_ipwreg.h> 78 #include <dev/pci/if_ipwvar.h> 79 80 #ifdef IPW_DEBUG 81 #define DPRINTF(x) if (ipw_debug > 0) printf x 82 #define DPRINTFN(n, x) if (ipw_debug >= (n)) printf x 83 int ipw_debug = 0; 84 #else 85 #define DPRINTF(x) 86 #define DPRINTFN(n, x) 87 #endif 88 89 /* Permit loading the Intel firmware */ 90 static int ipw_accept_eula; 91 92 static int ipw_dma_alloc(struct ipw_softc *); 93 static void ipw_release(struct ipw_softc *); 94 static int ipw_match(device_t, cfdata_t, void *); 95 static void ipw_attach(device_t, device_t, void *); 96 static int ipw_detach(device_t, int); 97 98 static int ipw_media_change(struct ifnet *); 99 static void ipw_media_status(struct ifnet *, struct ifmediareq *); 100 static int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 101 static uint16_t ipw_read_prom_word(struct ipw_softc *, uint8_t); 102 static void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 103 static void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 104 static void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 105 struct ipw_soft_bd *, struct ipw_soft_buf *); 106 static void ipw_rx_intr(struct ipw_softc *); 107 static void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 108 static void ipw_tx_intr(struct ipw_softc *); 109 static int ipw_intr(void *); 110 static void ipw_softintr(void *); 111 static int ipw_cmd(struct ipw_softc *, uint32_t, void *, uint32_t); 112 static int ipw_tx_start(struct ifnet *, struct mbuf *, 113 struct ieee80211_node *); 114 static void ipw_start(struct ifnet *); 115 static void ipw_watchdog(struct ifnet *); 116 static int ipw_ioctl(struct ifnet *, u_long, void *); 117 static int ipw_get_table1(struct ipw_softc *, uint32_t *); 118 static int ipw_get_radio(struct ipw_softc *, int *); 119 static void ipw_stop_master(struct ipw_softc *); 120 static int ipw_reset(struct ipw_softc *); 121 static int ipw_load_ucode(struct ipw_softc *, u_char *, int); 122 static int ipw_load_firmware(struct ipw_softc *, u_char *, int); 123 static int ipw_cache_firmware(struct ipw_softc *); 124 static void ipw_free_firmware(struct ipw_softc *); 125 static int ipw_config(struct ipw_softc *); 126 static int ipw_init(struct ifnet *); 127 static void ipw_stop(struct ifnet *, int); 128 static uint32_t ipw_read_table1(struct ipw_softc *, uint32_t); 129 static void ipw_write_table1(struct ipw_softc *, uint32_t, uint32_t); 130 static int ipw_read_table2(struct ipw_softc *, uint32_t, void *, uint32_t *); 131 static void ipw_read_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 132 bus_size_t); 133 static void ipw_write_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 134 bus_size_t); 135 136 /* 137 * Supported rates for 802.11b mode (in 500Kbps unit). 138 */ 139 static const struct ieee80211_rateset ipw_rateset_11b = 140 { 4, { 2, 4, 11, 22 } }; 141 142 static inline uint8_t 143 MEM_READ_1(struct ipw_softc *sc, uint32_t addr) 144 { 145 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 146 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); 147 } 148 149 static inline uint32_t 150 MEM_READ_4(struct ipw_softc *sc, uint32_t addr) 151 { 152 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 153 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); 154 } 155 156 CFATTACH_DECL_NEW(ipw, sizeof (struct ipw_softc), ipw_match, ipw_attach, 157 ipw_detach, NULL); 158 159 static int 160 ipw_match(device_t parent, cfdata_t match, void *aux) 161 { 162 struct pci_attach_args *pa = aux; 163 164 if (PCI_VENDOR (pa->pa_id) == PCI_VENDOR_INTEL && 165 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_PRO_WL_2100) 166 return 1; 167 168 return 0; 169 } 170 171 /* Base Address Register */ 172 #define IPW_PCI_BAR0 0x10 173 174 static void 175 ipw_attach(device_t parent, device_t self, void *aux) 176 { 177 struct ipw_softc *sc = device_private(self); 178 struct ieee80211com *ic = &sc->sc_ic; 179 struct ifnet *ifp = &sc->sc_if; 180 struct pci_attach_args *pa = aux; 181 const char *intrstr; 182 bus_space_tag_t memt; 183 bus_space_handle_t memh; 184 bus_addr_t base; 185 pci_intr_handle_t ih; 186 uint32_t data; 187 uint16_t val; 188 int i, error; 189 char intrbuf[PCI_INTRSTR_LEN]; 190 191 sc->sc_dev = self; 192 sc->sc_pct = pa->pa_pc; 193 sc->sc_pcitag = pa->pa_tag; 194 195 pci_aprint_devinfo(pa, NULL); 196 197 /* enable bus-mastering */ 198 data = pci_conf_read(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG); 199 data |= PCI_COMMAND_MASTER_ENABLE; 200 pci_conf_write(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG, data); 201 202 /* map the register window */ 203 error = pci_mapreg_map(pa, IPW_PCI_BAR0, PCI_MAPREG_TYPE_MEM | 204 PCI_MAPREG_MEM_TYPE_32BIT, 0, &memt, &memh, &base, &sc->sc_sz); 205 if (error != 0) { 206 aprint_error_dev(sc->sc_dev, "could not map memory space\n"); 207 return; 208 } 209 210 sc->sc_st = memt; 211 sc->sc_sh = memh; 212 sc->sc_dmat = pa->pa_dmat; 213 sc->sc_fwname = "ipw2100-1.2.fw"; 214 215 /* disable interrupts */ 216 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 217 218 if (pci_intr_map(pa, &ih) != 0) { 219 aprint_error_dev(sc->sc_dev, "could not map interrupt\n"); 220 goto fail; 221 } 222 223 sc->sc_soft_ih = softint_establish(SOFTINT_NET, ipw_softintr, sc); 224 if (sc->sc_soft_ih == NULL) { 225 aprint_error_dev(sc->sc_dev, "could not establish softint\n"); 226 goto fail; 227 } 228 229 intrstr = pci_intr_string(sc->sc_pct, ih, intrbuf, sizeof(intrbuf)); 230 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, ipw_intr, sc); 231 if (sc->sc_ih == NULL) { 232 aprint_error_dev(sc->sc_dev, "could not establish interrupt"); 233 if (intrstr != NULL) 234 aprint_error(" at %s", intrstr); 235 aprint_error("\n"); 236 goto fail; 237 } 238 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 239 240 if (ipw_reset(sc) != 0) { 241 aprint_error_dev(sc->sc_dev, "could not reset adapter\n"); 242 goto fail; 243 } 244 245 if (ipw_dma_alloc(sc) != 0) { 246 aprint_error_dev(sc->sc_dev, "could not allocate DMA resources\n"); 247 goto fail; 248 } 249 250 ifp->if_softc = sc; 251 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 252 ifp->if_init = ipw_init; 253 ifp->if_stop = ipw_stop; 254 ifp->if_ioctl = ipw_ioctl; 255 ifp->if_start = ipw_start; 256 ifp->if_watchdog = ipw_watchdog; 257 IFQ_SET_READY(&ifp->if_snd); 258 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 259 260 ic->ic_ifp = ifp; 261 ic->ic_phytype = IEEE80211_T_DS; 262 ic->ic_opmode = IEEE80211_M_STA; 263 ic->ic_state = IEEE80211_S_INIT; 264 265 /* set device capabilities */ 266 ic->ic_caps = 267 IEEE80211_C_SHPREAMBLE /* short preamble supported */ 268 | IEEE80211_C_TXPMGT /* tx power management */ 269 | IEEE80211_C_IBSS /* ibss mode */ 270 | IEEE80211_C_MONITOR /* monitor mode */ 271 ; 272 273 /* read MAC address from EEPROM */ 274 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0); 275 ic->ic_myaddr[0] = val >> 8; 276 ic->ic_myaddr[1] = val & 0xff; 277 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 1); 278 ic->ic_myaddr[2] = val >> 8; 279 ic->ic_myaddr[3] = val & 0xff; 280 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 2); 281 ic->ic_myaddr[4] = val >> 8; 282 ic->ic_myaddr[5] = val & 0xff; 283 284 /* set supported .11b rates */ 285 ic->ic_sup_rates[IEEE80211_MODE_11B] = ipw_rateset_11b; 286 287 /* set supported .11b channels (read from EEPROM) */ 288 if ((val = ipw_read_prom_word(sc, IPW_EEPROM_CHANNEL_LIST)) == 0) 289 val = 0x7ff; /* default to channels 1-11 */ 290 val <<= 1; 291 for (i = 1; i < 16; i++) { 292 if (val & (1 << i)) { 293 ic->ic_channels[i].ic_freq = 294 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 295 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 296 } 297 } 298 299 /* check support for radio transmitter switch in EEPROM */ 300 if (!(ipw_read_prom_word(sc, IPW_EEPROM_RADIO) & 8)) 301 sc->flags |= IPW_FLAG_HAS_RADIO_SWITCH; 302 303 aprint_normal_dev(sc->sc_dev, "802.11 address %s\n", 304 ether_sprintf(ic->ic_myaddr)); 305 306 if_initialize(ifp); 307 ieee80211_ifattach(ic); 308 /* Use common softint-based if_input */ 309 ifp->if_percpuq = if_percpuq_create(ifp); 310 if_register(ifp); 311 312 /* override state transition machine */ 313 sc->sc_newstate = ic->ic_newstate; 314 ic->ic_newstate = ipw_newstate; 315 316 ieee80211_media_init(ic, ipw_media_change, ipw_media_status); 317 318 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 319 sizeof(struct ieee80211_frame) + 64, &sc->sc_drvbpf); 320 321 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 322 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 323 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 324 325 sc->sc_txtap_len = sizeof sc->sc_txtapu; 326 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 327 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 328 329 /* 330 * Add a few sysctl knobs. 331 * XXX: Not yet 332 */ 333 sc->dwelltime = 100; 334 335 if (pmf_device_register(self, NULL, NULL)) 336 pmf_class_network_register(self, ifp); 337 else 338 aprint_error_dev(self, "couldn't establish power handler\n"); 339 340 ieee80211_announce(ic); 341 342 return; 343 344 fail: ipw_detach(self, 0); 345 } 346 347 static int 348 ipw_detach(device_t self, int flags) 349 { 350 struct ipw_softc *sc = device_private(self); 351 struct ifnet *ifp = &sc->sc_if; 352 353 if (ifp->if_softc) { 354 ipw_stop(ifp, 1); 355 ipw_free_firmware(sc); 356 357 bpf_detach(ifp); 358 ieee80211_ifdetach(&sc->sc_ic); 359 if_detach(ifp); 360 361 ipw_release(sc); 362 } 363 364 if (sc->sc_ih != NULL) { 365 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 366 sc->sc_ih = NULL; 367 } 368 369 if (sc->sc_soft_ih != NULL) { 370 softint_disestablish(sc->sc_soft_ih); 371 sc->sc_soft_ih = NULL; 372 } 373 374 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 375 376 return 0; 377 } 378 379 static int 380 ipw_dma_alloc(struct ipw_softc *sc) 381 { 382 struct ipw_soft_bd *sbd; 383 struct ipw_soft_hdr *shdr; 384 struct ipw_soft_buf *sbuf; 385 int error, i, nsegs; 386 387 /* 388 * Allocate and map tx ring. 389 */ 390 error = bus_dmamap_create(sc->sc_dmat, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, 391 BUS_DMA_NOWAIT, &sc->tbd_map); 392 if (error != 0) { 393 aprint_error_dev(sc->sc_dev, "could not create tbd dma map\n"); 394 goto fail; 395 } 396 397 error = bus_dmamem_alloc(sc->sc_dmat, IPW_TBD_SZ, PAGE_SIZE, 0, 398 &sc->tbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 399 if (error != 0) { 400 aprint_error_dev(sc->sc_dev, "could not allocate tbd dma memory\n"); 401 goto fail; 402 } 403 404 error = bus_dmamem_map(sc->sc_dmat, &sc->tbd_seg, nsegs, IPW_TBD_SZ, 405 (void **)&sc->tbd_list, BUS_DMA_NOWAIT); 406 if (error != 0) { 407 aprint_error_dev(sc->sc_dev, "could not map tbd dma memory\n"); 408 goto fail; 409 } 410 411 error = bus_dmamap_load(sc->sc_dmat, sc->tbd_map, sc->tbd_list, 412 IPW_TBD_SZ, NULL, BUS_DMA_NOWAIT); 413 if (error != 0) { 414 aprint_error_dev(sc->sc_dev, "could not load tbd dma memory\n"); 415 goto fail; 416 } 417 418 (void)memset(sc->tbd_list, 0, IPW_TBD_SZ); 419 420 /* 421 * Allocate and map rx ring. 422 */ 423 error = bus_dmamap_create(sc->sc_dmat, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, 424 BUS_DMA_NOWAIT, &sc->rbd_map); 425 if (error != 0) { 426 aprint_error_dev(sc->sc_dev, "could not create rbd dma map\n"); 427 goto fail; 428 } 429 430 error = bus_dmamem_alloc(sc->sc_dmat, IPW_RBD_SZ, PAGE_SIZE, 0, 431 &sc->rbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 432 if (error != 0) { 433 aprint_error_dev(sc->sc_dev, "could not allocate rbd dma memory\n"); 434 goto fail; 435 } 436 437 error = bus_dmamem_map(sc->sc_dmat, &sc->rbd_seg, nsegs, IPW_RBD_SZ, 438 (void **)&sc->rbd_list, BUS_DMA_NOWAIT); 439 if (error != 0) { 440 aprint_error_dev(sc->sc_dev, "could not map rbd dma memory\n"); 441 goto fail; 442 } 443 444 error = bus_dmamap_load(sc->sc_dmat, sc->rbd_map, sc->rbd_list, 445 IPW_RBD_SZ, NULL, BUS_DMA_NOWAIT); 446 if (error != 0) { 447 aprint_error_dev(sc->sc_dev, "could not load rbd dma memory\n"); 448 goto fail; 449 } 450 451 (void)memset(sc->rbd_list, 0, IPW_RBD_SZ); 452 453 /* 454 * Allocate and map status ring. 455 */ 456 error = bus_dmamap_create(sc->sc_dmat, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 457 0, BUS_DMA_NOWAIT, &sc->status_map); 458 if (error != 0) { 459 aprint_error_dev(sc->sc_dev, "could not create status dma map\n"); 460 goto fail; 461 } 462 463 error = bus_dmamem_alloc(sc->sc_dmat, IPW_STATUS_SZ, PAGE_SIZE, 0, 464 &sc->status_seg, 1, &nsegs, BUS_DMA_NOWAIT); 465 if (error != 0) { 466 aprint_error_dev(sc->sc_dev, "could not allocate status dma memory\n"); 467 goto fail; 468 } 469 470 error = bus_dmamem_map(sc->sc_dmat, &sc->status_seg, nsegs, 471 IPW_STATUS_SZ, (void **)&sc->status_list, BUS_DMA_NOWAIT); 472 if (error != 0) { 473 aprint_error_dev(sc->sc_dev, "could not map status dma memory\n"); 474 goto fail; 475 } 476 477 error = bus_dmamap_load(sc->sc_dmat, sc->status_map, sc->status_list, 478 IPW_STATUS_SZ, NULL, BUS_DMA_NOWAIT); 479 if (error != 0) { 480 aprint_error_dev(sc->sc_dev, "could not load status dma memory\n"); 481 goto fail; 482 } 483 484 (void)memset(sc->status_list, 0, IPW_STATUS_SZ); 485 486 /* 487 * Allocate command DMA map. 488 */ 489 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_cmd), 490 1, sizeof (struct ipw_cmd), 0, BUS_DMA_NOWAIT, &sc->cmd_map); 491 if (error != 0) { 492 aprint_error_dev(sc->sc_dev, "could not create cmd dma map\n"); 493 goto fail; 494 } 495 496 error = bus_dmamem_alloc(sc->sc_dmat, sizeof (struct ipw_cmd), 497 PAGE_SIZE, 0, &sc->cmd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 498 if (error != 0) { 499 aprint_error_dev(sc->sc_dev, "could not allocate cmd dma memory\n"); 500 goto fail; 501 } 502 503 error = bus_dmamem_map(sc->sc_dmat, &sc->cmd_seg, nsegs, 504 sizeof (struct ipw_cmd), (void **)&sc->cmd, BUS_DMA_NOWAIT); 505 if (error != 0) { 506 aprint_error_dev(sc->sc_dev, "could not map cmd dma memory\n"); 507 goto fail; 508 } 509 510 error = bus_dmamap_load(sc->sc_dmat, sc->cmd_map, &sc->cmd, 511 sizeof (struct ipw_cmd), NULL, BUS_DMA_NOWAIT); 512 if (error != 0) { 513 aprint_error_dev(sc->sc_dev, "could not map cmd dma memory\n"); 514 return error; 515 } 516 517 /* 518 * Allocate and map hdr list. 519 */ 520 521 error = bus_dmamap_create(sc->sc_dmat, 522 IPW_NDATA * sizeof(struct ipw_hdr), 1, 523 sizeof(struct ipw_hdr), 0, BUS_DMA_NOWAIT, 524 &sc->hdr_map); 525 if (error != 0) { 526 aprint_error_dev(sc->sc_dev, "could not create hdr dma map\n"); 527 goto fail; 528 } 529 530 error = bus_dmamem_alloc(sc->sc_dmat, 531 IPW_NDATA * sizeof(struct ipw_hdr), PAGE_SIZE, 0, &sc->hdr_seg, 532 1, &nsegs, BUS_DMA_NOWAIT); 533 if (error != 0) { 534 aprint_error_dev(sc->sc_dev, "could not allocate hdr memory\n"); 535 goto fail; 536 } 537 538 error = bus_dmamem_map(sc->sc_dmat, &sc->hdr_seg, nsegs, 539 IPW_NDATA * sizeof(struct ipw_hdr), (void **)&sc->hdr_list, 540 BUS_DMA_NOWAIT); 541 if (error != 0) { 542 aprint_error_dev(sc->sc_dev, "could not map hdr memory\n"); 543 goto fail; 544 } 545 546 error = bus_dmamap_load(sc->sc_dmat, sc->hdr_map, sc->hdr_list, 547 IPW_NDATA * sizeof(struct ipw_hdr), NULL, BUS_DMA_NOWAIT); 548 if (error != 0) { 549 aprint_error_dev(sc->sc_dev, "could not load hdr memory\n"); 550 goto fail; 551 } 552 553 (void)memset(sc->hdr_list, 0, IPW_HDR_SZ); 554 555 /* 556 * Create DMA hdrs tailq. 557 */ 558 TAILQ_INIT(&sc->sc_free_shdr); 559 for (i = 0; i < IPW_NDATA; i++) { 560 shdr = &sc->shdr_list[i]; 561 shdr->hdr = sc->hdr_list + i; 562 shdr->offset = sizeof(struct ipw_hdr) * i; 563 shdr->addr = sc->hdr_map->dm_segs[0].ds_addr + shdr->offset; 564 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 565 } 566 567 /* 568 * Allocate tx buffers DMA maps. 569 */ 570 TAILQ_INIT(&sc->sc_free_sbuf); 571 for (i = 0; i < IPW_NDATA; i++) { 572 sbuf = &sc->tx_sbuf_list[i]; 573 574 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 575 IPW_MAX_NSEG, MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 576 if (error != 0) { 577 aprint_error_dev(sc->sc_dev, "could not create txbuf dma map\n"); 578 goto fail; 579 } 580 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 581 } 582 583 /* 584 * Initialize tx ring. 585 */ 586 for (i = 0; i < IPW_NTBD; i++) { 587 sbd = &sc->stbd_list[i]; 588 sbd->bd = &sc->tbd_list[i]; 589 sbd->type = IPW_SBD_TYPE_NOASSOC; 590 } 591 592 /* 593 * Pre-allocate rx buffers and DMA maps 594 */ 595 for (i = 0; i < IPW_NRBD; i++) { 596 sbd = &sc->srbd_list[i]; 597 sbuf = &sc->rx_sbuf_list[i]; 598 sbd->bd = &sc->rbd_list[i]; 599 600 MGETHDR(sbuf->m, M_DONTWAIT, MT_DATA); 601 if (sbuf->m == NULL) { 602 aprint_error_dev(sc->sc_dev, "could not allocate rx mbuf\n"); 603 error = ENOMEM; 604 goto fail; 605 } 606 607 MCLGET(sbuf->m, M_DONTWAIT); 608 if (!(sbuf->m->m_flags & M_EXT)) { 609 m_freem(sbuf->m); 610 sbuf->m = NULL; 611 aprint_error_dev(sc->sc_dev, "could not allocate rx mbuf cluster\n"); 612 error = ENOMEM; 613 goto fail; 614 } 615 616 sbuf->m->m_pkthdr.len = sbuf->m->m_len = sbuf->m->m_ext.ext_size; 617 618 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 619 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sbuf->map); 620 if (error != 0) { 621 aprint_error_dev(sc->sc_dev, "could not create rxbuf dma map\n"); 622 m_freem(sbuf->m); 623 sbuf->m = NULL; 624 goto fail; 625 } 626 627 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, 628 sbuf->m, BUS_DMA_READ | BUS_DMA_NOWAIT); 629 if (error != 0) { 630 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 631 sbuf->map = NULL; 632 m_freem(sbuf->m); 633 sbuf->m = NULL; 634 aprint_error_dev(sc->sc_dev, "could not map rxbuf dma memory\n"); 635 goto fail; 636 } 637 638 sbd->type = IPW_SBD_TYPE_DATA; 639 sbd->priv = sbuf; 640 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 641 sbd->bd->len = htole32(MCLBYTES); 642 643 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, 644 sbuf->map->dm_mapsize, BUS_DMASYNC_PREREAD); 645 646 } 647 648 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 0, IPW_RBD_SZ, 649 BUS_DMASYNC_PREREAD); 650 651 return 0; 652 653 fail: ipw_release(sc); 654 return error; 655 } 656 657 static void 658 ipw_release(struct ipw_softc *sc) 659 { 660 struct ipw_soft_buf *sbuf; 661 int i; 662 663 if (sc->tbd_map != NULL) { 664 if (sc->tbd_list != NULL) { 665 bus_dmamap_unload(sc->sc_dmat, sc->tbd_map); 666 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->tbd_list, 667 IPW_TBD_SZ); 668 bus_dmamem_free(sc->sc_dmat, &sc->tbd_seg, 1); 669 } 670 bus_dmamap_destroy(sc->sc_dmat, sc->tbd_map); 671 } 672 673 if (sc->rbd_map != NULL) { 674 if (sc->rbd_list != NULL) { 675 bus_dmamap_unload(sc->sc_dmat, sc->rbd_map); 676 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->rbd_list, 677 IPW_RBD_SZ); 678 bus_dmamem_free(sc->sc_dmat, &sc->rbd_seg, 1); 679 } 680 bus_dmamap_destroy(sc->sc_dmat, sc->rbd_map); 681 } 682 683 if (sc->status_map != NULL) { 684 if (sc->status_list != NULL) { 685 bus_dmamap_unload(sc->sc_dmat, sc->status_map); 686 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->status_list, 687 IPW_RBD_SZ); 688 bus_dmamem_free(sc->sc_dmat, &sc->status_seg, 1); 689 } 690 bus_dmamap_destroy(sc->sc_dmat, sc->status_map); 691 } 692 693 for (i = 0; i < IPW_NTBD; i++) 694 ipw_release_sbd(sc, &sc->stbd_list[i]); 695 696 if (sc->cmd_map != NULL) 697 bus_dmamap_destroy(sc->sc_dmat, sc->cmd_map); 698 699 if (sc->hdr_list != NULL) { 700 bus_dmamap_unload(sc->sc_dmat, sc->hdr_map); 701 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->hdr_list, 702 IPW_NDATA * sizeof(struct ipw_hdr)); 703 } 704 if (sc->hdr_map != NULL) { 705 bus_dmamem_free(sc->sc_dmat, &sc->hdr_seg, 1); 706 bus_dmamap_destroy(sc->sc_dmat, sc->hdr_map); 707 } 708 709 for (i = 0; i < IPW_NDATA; i++) 710 bus_dmamap_destroy(sc->sc_dmat, sc->tx_sbuf_list[i].map); 711 712 for (i = 0; i < IPW_NRBD; i++) { 713 sbuf = &sc->rx_sbuf_list[i]; 714 if (sbuf->map != NULL) { 715 if (sbuf->m != NULL) { 716 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 717 m_freem(sbuf->m); 718 } 719 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 720 } 721 } 722 723 } 724 725 static int 726 ipw_media_change(struct ifnet *ifp) 727 { 728 int error; 729 730 error = ieee80211_media_change(ifp); 731 if (error != ENETRESET) 732 return error; 733 734 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 735 ipw_init(ifp); 736 737 return 0; 738 } 739 740 /* 741 * The firmware automatically adapts the transmit speed. We report the current 742 * transmit speed here. 743 */ 744 static void 745 ipw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 746 { 747 #define N(a) (sizeof (a) / sizeof (a[0])) 748 struct ipw_softc *sc = ifp->if_softc; 749 struct ieee80211com *ic = &sc->sc_ic; 750 static const struct { 751 uint32_t val; 752 int rate; 753 } rates[] = { 754 { IPW_RATE_DS1, 2 }, 755 { IPW_RATE_DS2, 4 }, 756 { IPW_RATE_DS5, 11 }, 757 { IPW_RATE_DS11, 22 }, 758 }; 759 uint32_t val; 760 int rate, i; 761 762 imr->ifm_status = IFM_AVALID; 763 imr->ifm_active = IFM_IEEE80211; 764 if (ic->ic_state == IEEE80211_S_RUN) 765 imr->ifm_status |= IFM_ACTIVE; 766 767 /* read current transmission rate from adapter */ 768 val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE) & 0xf; 769 770 /* convert ipw rate to 802.11 rate */ 771 for (i = 0; i < N(rates) && rates[i].val != val; i++); 772 rate = (i < N(rates)) ? rates[i].rate : 0; 773 774 imr->ifm_active |= IFM_IEEE80211_11B; 775 imr->ifm_active |= ieee80211_rate2media(ic, rate, IEEE80211_MODE_11B); 776 switch (ic->ic_opmode) { 777 case IEEE80211_M_STA: 778 break; 779 780 case IEEE80211_M_IBSS: 781 imr->ifm_active |= IFM_IEEE80211_ADHOC; 782 break; 783 784 case IEEE80211_M_MONITOR: 785 imr->ifm_active |= IFM_IEEE80211_MONITOR; 786 break; 787 788 case IEEE80211_M_AHDEMO: 789 case IEEE80211_M_HOSTAP: 790 /* should not get there */ 791 break; 792 } 793 #undef N 794 } 795 796 static int 797 ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, 798 int arg) 799 { 800 struct ifnet *ifp = ic->ic_ifp; 801 struct ipw_softc *sc = ifp->if_softc; 802 struct ieee80211_node *ni; 803 uint8_t macaddr[IEEE80211_ADDR_LEN]; 804 uint32_t len; 805 struct ipw_rx_radiotap_header *wr = &sc->sc_rxtap; 806 struct ipw_tx_radiotap_header *wt = &sc->sc_txtap; 807 808 switch (nstate) { 809 case IEEE80211_S_INIT: 810 break; 811 default: 812 KASSERT(ic->ic_curchan != IEEE80211_CHAN_ANYC); 813 KASSERT(ic->ic_curchan != NULL); 814 wt->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 815 wt->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 816 wr->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 817 wr->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 818 break; 819 } 820 821 switch (nstate) { 822 case IEEE80211_S_RUN: 823 DELAY(200); /* firmware needs a short delay here */ 824 825 len = IEEE80211_ADDR_LEN; 826 ipw_read_table2(sc, IPW_INFO_CURRENT_BSSID, macaddr, &len); 827 828 ni = ieee80211_find_node(&ic->ic_scan, macaddr); 829 if (ni == NULL) 830 break; 831 832 ieee80211_ref_node(ni); 833 ieee80211_sta_join(ic, ni); 834 ieee80211_node_authorize(ni); 835 836 if (ic->ic_opmode == IEEE80211_M_STA) 837 ieee80211_notify_node_join(ic, ni, 1); 838 break; 839 840 case IEEE80211_S_INIT: 841 case IEEE80211_S_SCAN: 842 case IEEE80211_S_AUTH: 843 case IEEE80211_S_ASSOC: 844 break; 845 } 846 847 ic->ic_state = nstate; 848 return 0; 849 } 850 851 /* 852 * Read 16 bits at address 'addr' from the serial EEPROM. 853 */ 854 static uint16_t 855 ipw_read_prom_word(struct ipw_softc *sc, uint8_t addr) 856 { 857 uint32_t tmp; 858 uint16_t val; 859 int n; 860 861 /* clock C once before the first command */ 862 IPW_EEPROM_CTL(sc, 0); 863 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 864 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 865 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 866 867 /* write start bit (1) */ 868 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 869 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 870 871 /* write READ opcode (10) */ 872 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 873 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 874 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 875 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 876 877 /* write address A7-A0 */ 878 for (n = 7; n >= 0; n--) { 879 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 880 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D)); 881 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 882 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D) | IPW_EEPROM_C); 883 } 884 885 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 886 887 /* read data Q15-Q0 */ 888 val = 0; 889 for (n = 15; n >= 0; n--) { 890 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 891 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 892 tmp = MEM_READ_4(sc, IPW_MEM_EEPROM_CTL); 893 val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n; 894 } 895 896 IPW_EEPROM_CTL(sc, 0); 897 898 /* clear Chip Select and clock C */ 899 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 900 IPW_EEPROM_CTL(sc, 0); 901 IPW_EEPROM_CTL(sc, IPW_EEPROM_C); 902 903 return le16toh(val); 904 } 905 906 static void 907 ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 908 { 909 910 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof (struct ipw_cmd), 911 BUS_DMASYNC_POSTREAD); 912 913 #ifdef IPW_DEBUG 914 struct ipw_cmd *cmd = mtod(sbuf->m, struct ipw_cmd *); 915 916 DPRINTFN(2, ("cmd ack'ed (%u, %u, %u, %u, %u)\n", le32toh(cmd->type), 917 le32toh(cmd->subtype), le32toh(cmd->seq), le32toh(cmd->len), 918 le32toh(cmd->status))); 919 #endif 920 921 wakeup(&sc->cmd); 922 } 923 924 static void 925 ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 926 { 927 struct ieee80211com *ic = &sc->sc_ic; 928 struct ifnet *ifp = sc->sc_ic.ic_ifp; 929 uint32_t state; 930 int s; 931 932 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof state, 933 BUS_DMASYNC_POSTREAD); 934 935 state = le32toh(*mtod(sbuf->m, uint32_t *)); 936 937 DPRINTFN(2, ("entering state %u\n", state)); 938 939 s = splnet(); 940 941 switch (state) { 942 case IPW_STATE_ASSOCIATED: 943 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 944 break; 945 946 case IPW_STATE_SCANNING: 947 /* don't leave run state on background scan */ 948 if (ic->ic_state != IEEE80211_S_RUN) 949 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 950 951 ic->ic_flags |= IEEE80211_F_SCAN; 952 break; 953 954 case IPW_STATE_SCAN_COMPLETE: 955 ieee80211_notify_scan_done(ic); 956 ic->ic_flags &= ~IEEE80211_F_SCAN; 957 break; 958 959 case IPW_STATE_ASSOCIATION_LOST: 960 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 961 break; 962 963 case IPW_STATE_RADIO_DISABLED: 964 ic->ic_ifp->if_flags &= ~IFF_UP; 965 ipw_stop(ifp, 1); 966 break; 967 } 968 969 splx(s); 970 } 971 972 /* 973 * XXX: Hack to set the current channel to the value advertised in beacons or 974 * probe responses. Only used during AP detection. 975 */ 976 static void 977 ipw_fix_channel(struct ieee80211com *ic, struct mbuf *m) 978 { 979 struct ieee80211_frame *wh; 980 uint8_t subtype; 981 uint8_t *frm, *efrm; 982 983 wh = mtod(m, struct ieee80211_frame *); 984 985 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_MGT) 986 return; 987 988 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 989 990 if (subtype != IEEE80211_FC0_SUBTYPE_BEACON && 991 subtype != IEEE80211_FC0_SUBTYPE_PROBE_RESP) 992 return; 993 994 frm = (uint8_t *)(wh + 1); 995 efrm = mtod(m, uint8_t *) + m->m_len; 996 997 frm += 12; /* skip tstamp, bintval and capinfo fields */ 998 while (frm < efrm) { 999 if (*frm == IEEE80211_ELEMID_DSPARMS) 1000 #if IEEE80211_CHAN_MAX < 255 1001 if (frm[2] <= IEEE80211_CHAN_MAX) 1002 #endif 1003 ic->ic_curchan = &ic->ic_channels[frm[2]]; 1004 1005 frm += frm[1] + 2; 1006 } 1007 } 1008 1009 static void 1010 ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 1011 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 1012 { 1013 struct ieee80211com *ic = &sc->sc_ic; 1014 struct ifnet *ifp = &sc->sc_if; 1015 struct mbuf *mnew, *m; 1016 struct ieee80211_frame *wh; 1017 struct ieee80211_node *ni; 1018 int error, s; 1019 1020 DPRINTFN(5, ("received frame len=%u, rssi=%u\n", le32toh(status->len), 1021 status->rssi)); 1022 1023 if (le32toh(status->len) < sizeof (struct ieee80211_frame_min) || 1024 le32toh(status->len) > MCLBYTES) 1025 return; 1026 1027 /* 1028 * Try to allocate a new mbuf for this ring element and load it before 1029 * processing the current mbuf. If the ring element cannot be loaded, 1030 * drop the received packet and reuse the old mbuf. In the unlikely 1031 * case that the old mbuf can't be reloaded either, explicitly panic. 1032 */ 1033 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1034 if (mnew == NULL) { 1035 aprint_error_dev(sc->sc_dev, "could not allocate rx mbuf\n"); 1036 ifp->if_ierrors++; 1037 return; 1038 } 1039 1040 MCLGET(mnew, M_DONTWAIT); 1041 if (!(mnew->m_flags & M_EXT)) { 1042 aprint_error_dev(sc->sc_dev, "could not allocate rx mbuf cluster\n"); 1043 m_freem(mnew); 1044 ifp->if_ierrors++; 1045 return; 1046 } 1047 1048 mnew->m_pkthdr.len = mnew->m_len = mnew->m_ext.ext_size; 1049 1050 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, le32toh(status->len), 1051 BUS_DMASYNC_POSTREAD); 1052 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1053 1054 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, mnew, 1055 BUS_DMA_READ | BUS_DMA_NOWAIT); 1056 if (error != 0) { 1057 aprint_error_dev(sc->sc_dev, "could not load rx buf DMA map\n"); 1058 m_freem(mnew); 1059 1060 /* try to reload the old mbuf */ 1061 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, 1062 sbuf->m, BUS_DMA_READ | BUS_DMA_NOWAIT); 1063 if (error != 0) { 1064 /* very unlikely that it will fail... */ 1065 panic("%s: unable to remap rx buf", 1066 device_xname(sc->sc_dev)); 1067 } 1068 ifp->if_ierrors++; 1069 return; 1070 } 1071 1072 /* 1073 * New mbuf successfully loaded, update Rx ring and continue 1074 * processing. 1075 */ 1076 m = sbuf->m; 1077 sbuf->m = mnew; 1078 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 1079 1080 /* finalize mbuf */ 1081 m_set_rcvif(m, ifp); 1082 m->m_pkthdr.len = m->m_len = le32toh(status->len); 1083 1084 s = splnet(); 1085 1086 if (sc->sc_drvbpf != NULL) { 1087 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 1088 1089 tap->wr_antsignal = status->rssi; 1090 1091 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 1092 } 1093 1094 if (ic->ic_state == IEEE80211_S_SCAN) 1095 ipw_fix_channel(ic, m); 1096 1097 wh = mtod(m, struct ieee80211_frame *); 1098 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 1099 1100 /* send the frame to the 802.11 layer */ 1101 ieee80211_input(ic, m, ni, status->rssi, 0); 1102 1103 /* node is no longer needed */ 1104 ieee80211_free_node(ni); 1105 1106 splx(s); 1107 1108 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, 1109 sbuf->map->dm_mapsize, BUS_DMASYNC_PREREAD); 1110 } 1111 1112 static void 1113 ipw_rx_intr(struct ipw_softc *sc) 1114 { 1115 struct ipw_status *status; 1116 struct ipw_soft_bd *sbd; 1117 struct ipw_soft_buf *sbuf; 1118 uint32_t r, i; 1119 1120 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1121 return; 1122 1123 r = CSR_READ_4(sc, IPW_CSR_RX_READ); 1124 1125 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 1126 1127 /* firmware was killed, stop processing received frames */ 1128 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1129 return; 1130 1131 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 1132 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1133 BUS_DMASYNC_POSTREAD); 1134 1135 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 1136 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 1137 BUS_DMASYNC_POSTREAD); 1138 1139 status = &sc->status_list[i]; 1140 sbd = &sc->srbd_list[i]; 1141 sbuf = sbd->priv; 1142 1143 switch (le16toh(status->code) & 0xf) { 1144 case IPW_STATUS_CODE_COMMAND: 1145 ipw_command_intr(sc, sbuf); 1146 break; 1147 1148 case IPW_STATUS_CODE_NEWSTATE: 1149 ipw_newstate_intr(sc, sbuf); 1150 break; 1151 1152 case IPW_STATUS_CODE_DATA_802_3: 1153 case IPW_STATUS_CODE_DATA_802_11: 1154 ipw_data_intr(sc, status, sbd, sbuf); 1155 break; 1156 1157 case IPW_STATUS_CODE_NOTIFICATION: 1158 DPRINTFN(2, ("received notification\n")); 1159 break; 1160 1161 default: 1162 aprint_error_dev(sc->sc_dev, "unknown status code %u\n", 1163 le16toh(status->code)); 1164 } 1165 1166 sbd->bd->flags = 0; 1167 1168 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 1169 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1170 BUS_DMASYNC_PREREAD); 1171 1172 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 1173 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 1174 BUS_DMASYNC_PREREAD); 1175 } 1176 1177 /* Tell the firmware what we have processed */ 1178 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 1179 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 1180 } 1181 1182 static void 1183 ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 1184 { 1185 struct ipw_soft_hdr *shdr; 1186 struct ipw_soft_buf *sbuf; 1187 1188 switch (sbd->type) { 1189 case IPW_SBD_TYPE_COMMAND: 1190 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 1191 0, sizeof(struct ipw_cmd), BUS_DMASYNC_POSTWRITE); 1192 /* bus_dmamap_unload(sc->sc_dmat, sc->cmd_map); */ 1193 break; 1194 1195 case IPW_SBD_TYPE_HEADER: 1196 shdr = sbd->priv; 1197 bus_dmamap_sync(sc->sc_dmat, sc->hdr_map, 1198 shdr->offset, sizeof(struct ipw_hdr), BUS_DMASYNC_POSTWRITE); 1199 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 1200 break; 1201 1202 case IPW_SBD_TYPE_DATA: 1203 sbuf = sbd->priv; 1204 1205 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 1206 0, sbuf->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1207 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1208 m_freem(sbuf->m); 1209 if (sbuf->ni != NULL) 1210 ieee80211_free_node(sbuf->ni); 1211 /* kill watchdog timer */ 1212 sc->sc_tx_timer = 0; 1213 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 1214 break; 1215 } 1216 sbd->type = IPW_SBD_TYPE_NOASSOC; 1217 } 1218 1219 static void 1220 ipw_tx_intr(struct ipw_softc *sc) 1221 { 1222 struct ifnet *ifp = &sc->sc_if; 1223 struct ipw_soft_bd *sbd; 1224 uint32_t r, i; 1225 int s; 1226 1227 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1228 return; 1229 1230 s = splnet(); 1231 1232 r = CSR_READ_4(sc, IPW_CSR_TX_READ); 1233 1234 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) { 1235 sbd = &sc->stbd_list[i]; 1236 1237 if (sbd->type == IPW_SBD_TYPE_DATA) 1238 ifp->if_opackets++; 1239 1240 ipw_release_sbd(sc, sbd); 1241 sc->txfree++; 1242 } 1243 1244 /* remember what the firmware has processed */ 1245 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 1246 1247 /* Call start() since some buffer descriptors have been released */ 1248 ifp->if_flags &= ~IFF_OACTIVE; 1249 ipw_start(ifp); /* in softint */ 1250 1251 splx(s); 1252 } 1253 1254 static int 1255 ipw_intr(void *arg) 1256 { 1257 struct ipw_softc *sc = arg; 1258 uint32_t r; 1259 1260 r = CSR_READ_4(sc, IPW_CSR_INTR); 1261 if (r == 0 || r == 0xffffffff) 1262 return 0; 1263 1264 /* Disable interrupts */ 1265 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1266 1267 softint_schedule(sc->sc_soft_ih); 1268 return 1; 1269 } 1270 1271 static void 1272 ipw_softintr(void *arg) 1273 { 1274 struct ipw_softc *sc = arg; 1275 uint32_t r; 1276 int s; 1277 1278 r = CSR_READ_4(sc, IPW_CSR_INTR); 1279 if (r == 0 || r == 0xffffffff) 1280 goto out; 1281 1282 if (r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR)) { 1283 aprint_error_dev(sc->sc_dev, "fatal error\n"); 1284 s = splnet(); 1285 sc->sc_ic.ic_ifp->if_flags &= ~IFF_UP; 1286 ipw_stop(&sc->sc_if, 1); 1287 splx(s); 1288 } 1289 1290 if (r & IPW_INTR_FW_INIT_DONE) { 1291 if (!(r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR))) 1292 wakeup(sc); 1293 } 1294 1295 if (r & IPW_INTR_RX_TRANSFER) 1296 ipw_rx_intr(sc); 1297 1298 if (r & IPW_INTR_TX_TRANSFER) 1299 ipw_tx_intr(sc); 1300 1301 /* Acknowledge all interrupts */ 1302 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 1303 1304 out: 1305 /* Re-enable interrupts */ 1306 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1307 } 1308 1309 /* 1310 * Send a command to the firmware and wait for the acknowledgement. 1311 */ 1312 static int 1313 ipw_cmd(struct ipw_softc *sc, uint32_t type, void *data, uint32_t len) 1314 { 1315 struct ipw_soft_bd *sbd; 1316 1317 sbd = &sc->stbd_list[sc->txcur]; 1318 1319 sc->cmd.type = htole32(type); 1320 sc->cmd.subtype = 0; 1321 sc->cmd.len = htole32(len); 1322 sc->cmd.seq = 0; 1323 1324 (void)memcpy(sc->cmd.data, data, len); 1325 1326 sbd->type = IPW_SBD_TYPE_COMMAND; 1327 sbd->bd->physaddr = htole32(sc->cmd_map->dm_segs[0].ds_addr); 1328 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 1329 sbd->bd->nfrag = 1; 1330 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 1331 IPW_BD_FLAG_TX_LAST_FRAGMENT; 1332 1333 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 0, sizeof (struct ipw_cmd), 1334 BUS_DMASYNC_PREWRITE); 1335 1336 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1337 sc->txcur * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1338 BUS_DMASYNC_PREWRITE); 1339 1340 DPRINTFN(2, ("sending command (%u, %u, %u, %u)\n", type, 0, 0, len)); 1341 1342 /* kick firmware */ 1343 sc->txfree--; 1344 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1345 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1346 1347 /* Wait at most one second for command to complete */ 1348 return tsleep(&sc->cmd, 0, "ipwcmd", hz); 1349 } 1350 1351 static int 1352 ipw_tx_start(struct ifnet *ifp, struct mbuf *m0, struct ieee80211_node *ni) 1353 { 1354 struct ipw_softc *sc = ifp->if_softc; 1355 struct ieee80211com *ic = &sc->sc_ic; 1356 struct ieee80211_frame *wh; 1357 struct ipw_soft_bd *sbd; 1358 struct ipw_soft_hdr *shdr; 1359 struct ipw_soft_buf *sbuf; 1360 struct ieee80211_key *k; 1361 struct mbuf *mnew; 1362 int error, i; 1363 1364 wh = mtod(m0, struct ieee80211_frame *); 1365 1366 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1367 k = ieee80211_crypto_encap(ic, ni, m0); 1368 if (k == NULL) { 1369 m_freem(m0); 1370 return ENOBUFS; 1371 } 1372 1373 /* packet header may have moved, reset our local pointer */ 1374 wh = mtod(m0, struct ieee80211_frame *); 1375 } 1376 1377 if (sc->sc_drvbpf != NULL) { 1378 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 1379 1380 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 1381 } 1382 1383 shdr = TAILQ_FIRST(&sc->sc_free_shdr); 1384 sbuf = TAILQ_FIRST(&sc->sc_free_sbuf); 1385 KASSERT(shdr != NULL && sbuf != NULL); 1386 1387 shdr->hdr->type = htole32(IPW_HDR_TYPE_SEND); 1388 shdr->hdr->subtype = 0; 1389 shdr->hdr->encrypted = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0; 1390 shdr->hdr->encrypt = 0; 1391 shdr->hdr->keyidx = 0; 1392 shdr->hdr->keysz = 0; 1393 shdr->hdr->fragmentsz = 0; 1394 IEEE80211_ADDR_COPY(shdr->hdr->src_addr, wh->i_addr2); 1395 if (ic->ic_opmode == IEEE80211_M_STA) 1396 IEEE80211_ADDR_COPY(shdr->hdr->dst_addr, wh->i_addr3); 1397 else 1398 IEEE80211_ADDR_COPY(shdr->hdr->dst_addr, wh->i_addr1); 1399 1400 /* trim IEEE802.11 header */ 1401 m_adj(m0, sizeof (struct ieee80211_frame)); 1402 1403 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m0, 1404 BUS_DMA_NOWAIT); 1405 if (error != 0 && error != EFBIG) { 1406 aprint_error_dev(sc->sc_dev, "could not map mbuf (error %d)\n", 1407 error); 1408 m_freem(m0); 1409 return error; 1410 } 1411 1412 if (error != 0) { 1413 /* too many fragments, linearize */ 1414 1415 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1416 if (mnew == NULL) { 1417 m_freem(m0); 1418 return ENOMEM; 1419 } 1420 1421 M_COPY_PKTHDR(mnew, m0); 1422 1423 /* If the data won't fit in the header, get a cluster */ 1424 if (m0->m_pkthdr.len > MHLEN) { 1425 MCLGET(mnew, M_DONTWAIT); 1426 if (!(mnew->m_flags & M_EXT)) { 1427 m_freem(m0); 1428 m_freem(mnew); 1429 return ENOMEM; 1430 } 1431 } 1432 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(mnew, void *)); 1433 m_freem(m0); 1434 mnew->m_len = mnew->m_pkthdr.len; 1435 m0 = mnew; 1436 1437 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m0, 1438 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1439 if (error != 0) { 1440 aprint_error_dev(sc->sc_dev, 1441 "could not map mbuf (error %d)\n", error); 1442 m_freem(m0); 1443 return error; 1444 } 1445 } 1446 1447 TAILQ_REMOVE(&sc->sc_free_sbuf, sbuf, next); 1448 TAILQ_REMOVE(&sc->sc_free_shdr, shdr, next); 1449 1450 sbd = &sc->stbd_list[sc->txcur]; 1451 sbd->type = IPW_SBD_TYPE_HEADER; 1452 sbd->priv = shdr; 1453 sbd->bd->physaddr = htole32(shdr->addr); 1454 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 1455 sbd->bd->nfrag = 1 + sbuf->map->dm_nsegs; 1456 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 1457 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1458 1459 DPRINTFN(5, ("sending tx hdr (%u, %u, %u, %u, )\n", 1460 shdr->hdr->type, shdr->hdr->subtype, shdr->hdr->encrypted, 1461 shdr->hdr->encrypt)); 1462 DPRINTFN(5, ("%s->", ether_sprintf(shdr->hdr->src_addr))); 1463 DPRINTFN(5, ("%s\n", ether_sprintf(shdr->hdr->dst_addr))); 1464 1465 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1466 sc->txcur * sizeof (struct ipw_bd), 1467 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1468 1469 sc->txfree--; 1470 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1471 1472 sbuf->m = m0; 1473 sbuf->ni = ni; 1474 1475 for (i = 0; i < sbuf->map->dm_nsegs; i++) { 1476 sbd = &sc->stbd_list[sc->txcur]; 1477 1478 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[i].ds_addr); 1479 sbd->bd->len = htole32(sbuf->map->dm_segs[i].ds_len); 1480 sbd->bd->nfrag = 0; 1481 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 1482 if (i == sbuf->map->dm_nsegs - 1) { 1483 sbd->type = IPW_SBD_TYPE_DATA; 1484 sbd->priv = sbuf; 1485 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 1486 } else { 1487 sbd->type = IPW_SBD_TYPE_NOASSOC; 1488 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1489 } 1490 1491 DPRINTFN(5, ("sending fragment (%d, %d)\n", i, 1492 (int)sbuf->map->dm_segs[i].ds_len)); 1493 1494 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1495 sc->txcur * sizeof (struct ipw_bd), 1496 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1497 1498 sc->txfree--; 1499 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1500 } 1501 1502 bus_dmamap_sync(sc->sc_dmat, sc->hdr_map, shdr->offset, 1503 sizeof (struct ipw_hdr), BUS_DMASYNC_PREWRITE); 1504 1505 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sbuf->map->dm_mapsize, 1506 BUS_DMASYNC_PREWRITE); 1507 1508 /* Inform firmware about this new packet */ 1509 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1510 1511 return 0; 1512 } 1513 1514 static void 1515 ipw_start(struct ifnet *ifp) 1516 { 1517 struct ipw_softc *sc = ifp->if_softc; 1518 struct ieee80211com *ic = &sc->sc_ic; 1519 struct mbuf *m0; 1520 struct ether_header *eh; 1521 struct ieee80211_node *ni; 1522 1523 if (ic->ic_state != IEEE80211_S_RUN) 1524 return; 1525 1526 for (;;) { 1527 IF_DEQUEUE(&ifp->if_snd, m0); 1528 if (m0 == NULL) 1529 break; 1530 1531 if (sc->txfree < 1 + IPW_MAX_NSEG) { 1532 IF_PREPEND(&ifp->if_snd, m0); 1533 ifp->if_flags |= IFF_OACTIVE; 1534 break; 1535 } 1536 1537 if (m0->m_len < sizeof (struct ether_header) && 1538 (m0 = m_pullup(m0, sizeof (struct ether_header))) == NULL) 1539 continue; 1540 1541 eh = mtod(m0, struct ether_header *); 1542 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1543 if (ni == NULL) { 1544 m_freem(m0); 1545 continue; 1546 } 1547 1548 bpf_mtap(ifp, m0); 1549 1550 m0 = ieee80211_encap(ic, m0, ni); 1551 if (m0 == NULL) { 1552 ieee80211_free_node(ni); 1553 continue; 1554 } 1555 1556 bpf_mtap3(ic->ic_rawbpf, m0); 1557 1558 if (ipw_tx_start(ifp, m0, ni) != 0) { 1559 ieee80211_free_node(ni); 1560 ifp->if_oerrors++; 1561 break; 1562 } 1563 1564 /* start watchdog timer */ 1565 sc->sc_tx_timer = 5; 1566 ifp->if_timer = 1; 1567 } 1568 } 1569 1570 static void 1571 ipw_watchdog(struct ifnet *ifp) 1572 { 1573 struct ipw_softc *sc = ifp->if_softc; 1574 1575 ifp->if_timer = 0; 1576 1577 if (sc->sc_tx_timer > 0) { 1578 if (--sc->sc_tx_timer == 0) { 1579 aprint_error_dev(sc->sc_dev, "device timeout\n"); 1580 ifp->if_oerrors++; 1581 ifp->if_flags &= ~IFF_UP; 1582 ipw_stop(ifp, 1); 1583 return; 1584 } 1585 ifp->if_timer = 1; 1586 } 1587 1588 ieee80211_watchdog(&sc->sc_ic); 1589 } 1590 1591 static int 1592 ipw_get_table1(struct ipw_softc *sc, uint32_t *tbl) 1593 { 1594 uint32_t addr, size, data, i; 1595 int error; 1596 1597 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1598 return ENOTTY; 1599 1600 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, sc->table1_base); 1601 1602 size = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 1603 if ((error = copyout(&size, tbl, sizeof(size))) != 0) 1604 return error; 1605 1606 for (i = 1, ++tbl; i < size; i++, tbl++) { 1607 addr = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 1608 data = MEM_READ_4(sc, addr); 1609 if ((error = copyout(&data, tbl, sizeof(data))) != 0) 1610 return error; 1611 } 1612 return 0; 1613 } 1614 1615 static int 1616 ipw_get_radio(struct ipw_softc *sc, int *ret) 1617 { 1618 uint32_t addr, data; 1619 1620 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1621 return ENOTTY; 1622 1623 addr = ipw_read_table1(sc, IPW_INFO_EEPROM_ADDRESS); 1624 if ((MEM_READ_4(sc, addr + 32) >> 24) & 1) 1625 data = -1; 1626 else if (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED) 1627 data = 0; 1628 else 1629 data = 1; 1630 1631 return copyout(&data, ret, sizeof(data)); 1632 } 1633 1634 static int 1635 ipw_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1636 { 1637 #define IS_RUNNING(ifp) \ 1638 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 1639 1640 struct ipw_softc *sc = ifp->if_softc; 1641 struct ieee80211com *ic = &sc->sc_ic; 1642 struct ifreq *ifr = (struct ifreq *)data; 1643 int s, error = 0; 1644 1645 s = splnet(); 1646 1647 switch (cmd) { 1648 case SIOCSIFFLAGS: 1649 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 1650 break; 1651 if (ifp->if_flags & IFF_UP) { 1652 if (!(ifp->if_flags & IFF_RUNNING)) 1653 ipw_init(ifp); 1654 } else { 1655 if (ifp->if_flags & IFF_RUNNING) 1656 ipw_stop(ifp, 1); 1657 } 1658 break; 1659 1660 case SIOCADDMULTI: 1661 case SIOCDELMULTI: 1662 /* XXX no h/w multicast filter? --dyoung */ 1663 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1664 /* setup multicast filter, etc */ 1665 error = 0; 1666 } 1667 break; 1668 1669 case SIOCGTABLE1: 1670 error = ipw_get_table1(sc, (uint32_t *)ifr->ifr_data); 1671 break; 1672 1673 case SIOCGRADIO: 1674 error = ipw_get_radio(sc, (int *)ifr->ifr_data); 1675 break; 1676 1677 case SIOCSIFMEDIA: 1678 if (ifr->ifr_media & IFM_IEEE80211_ADHOC) 1679 sc->sc_fwname = "ipw2100-1.2-i.fw"; 1680 else if (ifr->ifr_media & IFM_IEEE80211_MONITOR) 1681 sc->sc_fwname = "ipw2100-1.2-p.fw"; 1682 else 1683 sc->sc_fwname = "ipw2100-1.2.fw"; 1684 1685 ipw_free_firmware(sc); 1686 /* FALLTRHOUGH */ 1687 default: 1688 error = ieee80211_ioctl(&sc->sc_ic, cmd, data); 1689 if (error != ENETRESET) 1690 break; 1691 1692 if (error == ENETRESET) { 1693 if (IS_RUNNING(ifp) && 1694 (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)) 1695 ipw_init(ifp); 1696 error = 0; 1697 } 1698 1699 } 1700 1701 splx(s); 1702 return error; 1703 #undef IS_RUNNING 1704 } 1705 1706 static uint32_t 1707 ipw_read_table1(struct ipw_softc *sc, uint32_t off) 1708 { 1709 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 1710 } 1711 1712 static void 1713 ipw_write_table1(struct ipw_softc *sc, uint32_t off, uint32_t info) 1714 { 1715 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 1716 } 1717 1718 static int 1719 ipw_read_table2(struct ipw_softc *sc, uint32_t off, void *buf, uint32_t *len) 1720 { 1721 uint32_t addr, info; 1722 uint16_t count, size; 1723 uint32_t total; 1724 1725 /* addr[4] + count[2] + size[2] */ 1726 addr = MEM_READ_4(sc, sc->table2_base + off); 1727 info = MEM_READ_4(sc, sc->table2_base + off + 4); 1728 1729 count = info >> 16; 1730 size = info & 0xffff; 1731 total = count * size; 1732 1733 if (total > *len) { 1734 *len = total; 1735 return EINVAL; 1736 } 1737 1738 *len = total; 1739 ipw_read_mem_1(sc, addr, buf, total); 1740 1741 return 0; 1742 } 1743 1744 static void 1745 ipw_stop_master(struct ipw_softc *sc) 1746 { 1747 int ntries; 1748 1749 /* disable interrupts */ 1750 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1751 1752 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1753 for (ntries = 0; ntries < 50; ntries++) { 1754 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1755 break; 1756 DELAY(10); 1757 } 1758 if (ntries == 50) 1759 aprint_error_dev(sc->sc_dev, "timeout waiting for master\n"); 1760 1761 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1762 IPW_RST_PRINCETON_RESET); 1763 1764 sc->flags &= ~IPW_FLAG_FW_INITED; 1765 } 1766 1767 static int 1768 ipw_reset(struct ipw_softc *sc) 1769 { 1770 int ntries; 1771 1772 ipw_stop_master(sc); 1773 1774 /* move adapter to D0 state */ 1775 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1776 IPW_CTL_INIT); 1777 1778 /* wait for clock stabilization */ 1779 for (ntries = 0; ntries < 1000; ntries++) { 1780 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY) 1781 break; 1782 DELAY(200); 1783 } 1784 if (ntries == 1000) 1785 return EIO; 1786 1787 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1788 IPW_RST_SW_RESET); 1789 1790 DELAY(10); 1791 1792 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1793 IPW_CTL_INIT); 1794 1795 return 0; 1796 } 1797 1798 /* 1799 * Upload the microcode to the device. 1800 */ 1801 static int 1802 ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size) 1803 { 1804 int ntries; 1805 1806 MEM_WRITE_4(sc, 0x3000e0, 0x80000000); 1807 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1808 1809 MEM_WRITE_2(sc, 0x220000, 0x0703); 1810 MEM_WRITE_2(sc, 0x220000, 0x0707); 1811 1812 MEM_WRITE_1(sc, 0x210014, 0x72); 1813 MEM_WRITE_1(sc, 0x210014, 0x72); 1814 1815 MEM_WRITE_1(sc, 0x210000, 0x40); 1816 MEM_WRITE_1(sc, 0x210000, 0x00); 1817 MEM_WRITE_1(sc, 0x210000, 0x40); 1818 1819 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1820 1821 MEM_WRITE_1(sc, 0x210000, 0x00); 1822 MEM_WRITE_1(sc, 0x210000, 0x00); 1823 MEM_WRITE_1(sc, 0x210000, 0x80); 1824 1825 MEM_WRITE_2(sc, 0x220000, 0x0703); 1826 MEM_WRITE_2(sc, 0x220000, 0x0707); 1827 1828 MEM_WRITE_1(sc, 0x210014, 0x72); 1829 MEM_WRITE_1(sc, 0x210014, 0x72); 1830 1831 MEM_WRITE_1(sc, 0x210000, 0x00); 1832 MEM_WRITE_1(sc, 0x210000, 0x80); 1833 1834 for (ntries = 0; ntries < 10; ntries++) { 1835 if (MEM_READ_1(sc, 0x210000) & 1) 1836 break; 1837 DELAY(10); 1838 } 1839 if (ntries == 10) { 1840 aprint_error_dev(sc->sc_dev, "timeout waiting for ucode to initialize\n"); 1841 return EIO; 1842 } 1843 1844 MEM_WRITE_4(sc, 0x3000e0, 0); 1845 1846 return 0; 1847 } 1848 1849 /* set of macros to handle unaligned little endian data in firmware image */ 1850 #define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1851 #define GETLE16(p) ((p)[0] | (p)[1] << 8) 1852 static int 1853 ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size) 1854 { 1855 u_char *p, *end; 1856 uint32_t dst; 1857 uint16_t len; 1858 int error; 1859 1860 p = fw; 1861 end = fw + size; 1862 while (p < end) { 1863 dst = GETLE32(p); p += 4; 1864 len = GETLE16(p); p += 2; 1865 1866 ipw_write_mem_1(sc, dst, p, len); 1867 p += len; 1868 } 1869 1870 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1871 IPW_IO_LED_OFF); 1872 1873 /* enable interrupts */ 1874 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1875 1876 /* kick the firmware */ 1877 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1878 1879 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1880 IPW_CTL_ALLOW_STANDBY); 1881 1882 /* wait at most one second for firmware initialization to complete */ 1883 if ((error = tsleep(sc, 0, "ipwinit", hz)) != 0) { 1884 aprint_error_dev(sc->sc_dev, 1885 "timeout waiting for firmware initialization " 1886 "to complete\n"); 1887 return error; 1888 } 1889 1890 CSR_WRITE_4(sc, IPW_CSR_IO, CSR_READ_4(sc, IPW_CSR_IO) | 1891 IPW_IO_GPIO1_MASK | IPW_IO_GPIO3_MASK); 1892 1893 return 0; 1894 } 1895 1896 /* 1897 * Store firmware into kernel memory so we can download it when we need to, 1898 * e.g when the adapter wakes up from suspend mode. 1899 */ 1900 static int 1901 ipw_cache_firmware(struct ipw_softc *sc) 1902 { 1903 struct ipw_firmware *fw = &sc->fw; 1904 struct ipw_firmware_hdr hdr; 1905 firmware_handle_t fwh; 1906 off_t fwsz, p; 1907 int error; 1908 1909 ipw_free_firmware(sc); 1910 1911 if (ipw_accept_eula == 0) { 1912 aprint_error_dev(sc->sc_dev, 1913 "EULA not accepted; please see the ipw(4) man page.\n"); 1914 return EPERM; 1915 } 1916 1917 if ((error = firmware_open("if_ipw", sc->sc_fwname, &fwh)) != 0) 1918 goto fail0; 1919 1920 fwsz = firmware_get_size(fwh); 1921 1922 if (fwsz < sizeof(hdr)) 1923 goto fail2; 1924 1925 if ((error = firmware_read(fwh, 0, &hdr, sizeof(hdr))) != 0) 1926 goto fail2; 1927 1928 fw->main_size = le32toh(hdr.main_size); 1929 fw->ucode_size = le32toh(hdr.ucode_size); 1930 1931 fw->main = firmware_malloc(fw->main_size); 1932 if (fw->main == NULL) { 1933 error = ENOMEM; 1934 goto fail1; 1935 } 1936 1937 fw->ucode = firmware_malloc(fw->ucode_size); 1938 if (fw->ucode == NULL) { 1939 error = ENOMEM; 1940 goto fail2; 1941 } 1942 1943 p = sizeof(hdr); 1944 if ((error = firmware_read(fwh, p, fw->main, fw->main_size)) != 0) 1945 goto fail3; 1946 1947 p += fw->main_size; 1948 if ((error = firmware_read(fwh, p, fw->ucode, fw->ucode_size)) != 0) 1949 goto fail3; 1950 1951 DPRINTF(("Firmware cached: main %u, ucode %u\n", fw->main_size, 1952 fw->ucode_size)); 1953 1954 sc->flags |= IPW_FLAG_FW_CACHED; 1955 1956 firmware_close(fwh); 1957 1958 return 0; 1959 1960 fail3: firmware_free(fw->ucode, fw->ucode_size); 1961 fail2: firmware_free(fw->main, fw->main_size); 1962 fail1: firmware_close(fwh); 1963 fail0: 1964 return error; 1965 } 1966 1967 static void 1968 ipw_free_firmware(struct ipw_softc *sc) 1969 { 1970 if (!(sc->flags & IPW_FLAG_FW_CACHED)) 1971 return; 1972 1973 firmware_free(sc->fw.main, sc->fw.main_size); 1974 firmware_free(sc->fw.ucode, sc->fw.ucode_size); 1975 1976 sc->flags &= ~IPW_FLAG_FW_CACHED; 1977 } 1978 1979 static int 1980 ipw_config(struct ipw_softc *sc) 1981 { 1982 struct ieee80211com *ic = &sc->sc_ic; 1983 struct ifnet *ifp = &sc->sc_if; 1984 struct ipw_security security; 1985 struct ieee80211_key *k; 1986 struct ipw_wep_key wepkey; 1987 struct ipw_scan_options options; 1988 struct ipw_configuration config; 1989 uint32_t data; 1990 int error, i; 1991 1992 switch (ic->ic_opmode) { 1993 case IEEE80211_M_STA: 1994 case IEEE80211_M_HOSTAP: 1995 data = htole32(IPW_MODE_BSS); 1996 break; 1997 1998 case IEEE80211_M_IBSS: 1999 case IEEE80211_M_AHDEMO: 2000 data = htole32(IPW_MODE_IBSS); 2001 break; 2002 2003 case IEEE80211_M_MONITOR: 2004 data = htole32(IPW_MODE_MONITOR); 2005 break; 2006 } 2007 DPRINTF(("Setting mode to %u\n", le32toh(data))); 2008 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 2009 if (error != 0) 2010 return error; 2011 2012 if (ic->ic_opmode == IEEE80211_M_IBSS || 2013 ic->ic_opmode == IEEE80211_M_MONITOR) { 2014 data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); 2015 DPRINTF(("Setting channel to %u\n", le32toh(data))); 2016 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 2017 if (error != 0) 2018 return error; 2019 } 2020 2021 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2022 DPRINTF(("Enabling adapter\n")); 2023 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 2024 } 2025 2026 DPRINTF(("Setting MAC to %s\n", ether_sprintf(ic->ic_myaddr))); 2027 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 2028 IEEE80211_ADDR_LEN); 2029 if (error != 0) 2030 return error; 2031 2032 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 2033 IPW_CFG_PREAMBLE_AUTO | IPW_CFG_802_1x_ENABLE); 2034 2035 if (ic->ic_opmode == IEEE80211_M_IBSS) 2036 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 2037 if (ifp->if_flags & IFF_PROMISC) 2038 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 2039 config.bss_chan = htole32(0x3fff); /* channels 1-14 */ 2040 config.ibss_chan = htole32(0x7ff); /* channels 1-11 */ 2041 DPRINTF(("Setting adapter configuration 0x%08x\n", config.flags)); 2042 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 2043 if (error != 0) 2044 return error; 2045 2046 data = htole32(0x3); /* 1, 2 */ 2047 DPRINTF(("Setting basic tx rates to 0x%x\n", le32toh(data))); 2048 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 2049 if (error != 0) 2050 return error; 2051 2052 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 2053 DPRINTF(("Setting tx rates to 0x%x\n", le32toh(data))); 2054 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 2055 if (error != 0) 2056 return error; 2057 2058 data = htole32(IPW_POWER_MODE_CAM); 2059 DPRINTF(("Setting power mode to %u\n", le32toh(data))); 2060 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 2061 if (error != 0) 2062 return error; 2063 2064 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2065 data = htole32(32); /* default value */ 2066 DPRINTF(("Setting tx power index to %u\n", le32toh(data))); 2067 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 2068 sizeof data); 2069 if (error != 0) 2070 return error; 2071 } 2072 2073 data = htole32(ic->ic_rtsthreshold); 2074 DPRINTF(("Setting RTS threshold to %u\n", le32toh(data))); 2075 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 2076 if (error != 0) 2077 return error; 2078 2079 data = htole32(ic->ic_fragthreshold); 2080 DPRINTF(("Setting frag threshold to %u\n", le32toh(data))); 2081 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 2082 if (error != 0) 2083 return error; 2084 2085 #ifdef IPW_DEBUG 2086 if (ipw_debug > 0) { 2087 printf("Setting ESSID to "); 2088 ieee80211_print_essid(ic->ic_des_essid, ic->ic_des_esslen); 2089 printf("\n"); 2090 } 2091 #endif 2092 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ic->ic_des_essid, 2093 ic->ic_des_esslen); 2094 if (error != 0) 2095 return error; 2096 2097 /* no mandatory BSSID */ 2098 DPRINTF(("Setting mandatory BSSID to null\n")); 2099 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 2100 if (error != 0) 2101 return error; 2102 2103 if (ic->ic_flags & IEEE80211_F_DESBSSID) { 2104 DPRINTF(("Setting desired BSSID to %s\n", 2105 ether_sprintf(ic->ic_des_bssid))); 2106 error = ipw_cmd(sc, IPW_CMD_SET_DESIRED_BSSID, 2107 ic->ic_des_bssid, IEEE80211_ADDR_LEN); 2108 if (error != 0) 2109 return error; 2110 } 2111 2112 (void)memset(&security, 0, sizeof(security)); 2113 security.authmode = (ic->ic_bss->ni_authmode == IEEE80211_AUTH_SHARED) ? 2114 IPW_AUTH_SHARED : IPW_AUTH_OPEN; 2115 security.ciphers = htole32(IPW_CIPHER_NONE); 2116 DPRINTF(("Setting authmode to %u\n", security.authmode)); 2117 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 2118 sizeof security); 2119 if (error != 0) 2120 return error; 2121 2122 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 2123 k = ic->ic_crypto.cs_nw_keys; 2124 for (i = 0; i < IEEE80211_WEP_NKID; i++, k++) { 2125 if (k->wk_keylen == 0) 2126 continue; 2127 2128 wepkey.idx = i; 2129 wepkey.len = k->wk_keylen; 2130 memset(wepkey.key, 0, sizeof(wepkey.key)); 2131 memcpy(wepkey.key, k->wk_key, k->wk_keylen); 2132 DPRINTF(("Setting wep key index %u len %u\n", 2133 wepkey.idx, wepkey.len)); 2134 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY, &wepkey, 2135 sizeof wepkey); 2136 if (error != 0) 2137 return error; 2138 } 2139 2140 data = htole32(ic->ic_crypto.cs_def_txkey); 2141 DPRINTF(("Setting tx key index to %u\n", le32toh(data))); 2142 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY_INDEX, &data, 2143 sizeof data); 2144 if (error != 0) 2145 return error; 2146 } 2147 2148 data = htole32((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) ? IPW_WEPON : 0); 2149 DPRINTF(("Setting wep flags to 0x%x\n", le32toh(data))); 2150 error = ipw_cmd(sc, IPW_CMD_SET_WEP_FLAGS, &data, sizeof data); 2151 if (error != 0) 2152 return error; 2153 2154 #if 0 2155 struct ipw_wpa_ie ie; 2156 2157 memset(&ie, 0 sizeof(ie)); 2158 ie.len = htole32(sizeof (struct ieee80211_ie_wpa)); 2159 DPRINTF(("Setting wpa ie\n")); 2160 error = ipw_cmd(sc, IPW_CMD_SET_WPA_IE, &ie, sizeof ie); 2161 if (error != 0) 2162 return error; 2163 #endif 2164 2165 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2166 data = htole32(ic->ic_bintval); 2167 DPRINTF(("Setting beacon interval to %u\n", le32toh(data))); 2168 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 2169 sizeof data); 2170 if (error != 0) 2171 return error; 2172 } 2173 2174 options.flags = 0; 2175 options.channels = htole32(0x3fff); /* scan channels 1-14 */ 2176 DPRINTF(("Setting scan options to 0x%x\n", le32toh(options.flags))); 2177 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &options, sizeof options); 2178 if (error != 0) 2179 return error; 2180 2181 /* finally, enable adapter (start scanning for an access point) */ 2182 DPRINTF(("Enabling adapter\n")); 2183 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 2184 } 2185 2186 static int 2187 ipw_init(struct ifnet *ifp) 2188 { 2189 struct ipw_softc *sc = ifp->if_softc; 2190 struct ipw_firmware *fw = &sc->fw; 2191 2192 if (!(sc->flags & IPW_FLAG_FW_CACHED)) { 2193 if (ipw_cache_firmware(sc) != 0) { 2194 aprint_error_dev(sc->sc_dev, 2195 "could not cache the firmware (%s)\n", 2196 sc->sc_fwname); 2197 goto fail; 2198 } 2199 } 2200 2201 ipw_stop(ifp, 0); 2202 2203 if (ipw_reset(sc) != 0) { 2204 aprint_error_dev(sc->sc_dev, "could not reset adapter\n"); 2205 goto fail; 2206 } 2207 2208 if (ipw_load_ucode(sc, fw->ucode, fw->ucode_size) != 0) { 2209 aprint_error_dev(sc->sc_dev, "could not load microcode\n"); 2210 goto fail; 2211 } 2212 2213 ipw_stop_master(sc); 2214 2215 /* 2216 * Setup tx, rx and status rings. 2217 */ 2218 sc->txold = IPW_NTBD - 1; 2219 sc->txcur = 0; 2220 sc->txfree = IPW_NTBD - 2; 2221 sc->rxcur = IPW_NRBD - 1; 2222 2223 CSR_WRITE_4(sc, IPW_CSR_TX_BASE, sc->tbd_map->dm_segs[0].ds_addr); 2224 CSR_WRITE_4(sc, IPW_CSR_TX_SIZE, IPW_NTBD); 2225 CSR_WRITE_4(sc, IPW_CSR_TX_READ, 0); 2226 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 2227 2228 CSR_WRITE_4(sc, IPW_CSR_RX_BASE, sc->rbd_map->dm_segs[0].ds_addr); 2229 CSR_WRITE_4(sc, IPW_CSR_RX_SIZE, IPW_NRBD); 2230 CSR_WRITE_4(sc, IPW_CSR_RX_READ, 0); 2231 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 2232 2233 CSR_WRITE_4(sc, IPW_CSR_STATUS_BASE, sc->status_map->dm_segs[0].ds_addr); 2234 2235 if (ipw_load_firmware(sc, fw->main, fw->main_size) != 0) { 2236 aprint_error_dev(sc->sc_dev, "could not load firmware\n"); 2237 goto fail; 2238 } 2239 2240 sc->flags |= IPW_FLAG_FW_INITED; 2241 2242 /* retrieve information tables base addresses */ 2243 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 2244 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 2245 2246 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 2247 2248 if (ipw_config(sc) != 0) { 2249 aprint_error_dev(sc->sc_dev, "device configuration failed\n"); 2250 goto fail; 2251 } 2252 2253 ifp->if_flags &= ~IFF_OACTIVE; 2254 ifp->if_flags |= IFF_RUNNING; 2255 2256 return 0; 2257 2258 fail: ifp->if_flags &= ~IFF_UP; 2259 ipw_stop(ifp, 0); 2260 2261 return EIO; 2262 } 2263 2264 static void 2265 ipw_stop(struct ifnet *ifp, int disable) 2266 { 2267 struct ipw_softc *sc = ifp->if_softc; 2268 struct ieee80211com *ic = &sc->sc_ic; 2269 int i; 2270 2271 ipw_stop_master(sc); 2272 2273 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 2274 2275 /* 2276 * Release tx buffers. 2277 */ 2278 for (i = 0; i < IPW_NTBD; i++) 2279 ipw_release_sbd(sc, &sc->stbd_list[i]); 2280 2281 sc->sc_tx_timer = 0; 2282 ifp->if_timer = 0; 2283 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2284 2285 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2286 } 2287 2288 static void 2289 ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2290 bus_size_t count) 2291 { 2292 for (; count > 0; offset++, datap++, count--) { 2293 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2294 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 2295 } 2296 } 2297 2298 static void 2299 ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2300 bus_size_t count) 2301 { 2302 for (; count > 0; offset++, datap++, count--) { 2303 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2304 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 2305 } 2306 } 2307 2308 SYSCTL_SETUP(sysctl_hw_ipw_accept_eula_setup, "sysctl hw.ipw.accept_eula") 2309 { 2310 const struct sysctlnode *rnode; 2311 const struct sysctlnode *cnode; 2312 2313 sysctl_createv(NULL, 0, NULL, &rnode, 2314 CTLFLAG_PERMANENT, 2315 CTLTYPE_NODE, "ipw", 2316 NULL, 2317 NULL, 0, 2318 NULL, 0, 2319 CTL_HW, CTL_CREATE, CTL_EOL); 2320 2321 sysctl_createv(NULL, 0, &rnode, &cnode, 2322 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, 2323 CTLTYPE_INT, "accept_eula", 2324 SYSCTL_DESCR("Accept Intel EULA and permit use of ipw(4) firmware"), 2325 NULL, 0, 2326 &ipw_accept_eula, sizeof(ipw_accept_eula), 2327 CTL_CREATE, CTL_EOL); 2328 } 2329
Indexes created Tue Sep 30 11:09:46 GMT 2025