if_ipw.c revision 1.66
1 /* $NetBSD: if_ipw.c,v 1.66 2017/10/23 09:31:18 msaitoh Exp $ */ 2 /* FreeBSD: src/sys/dev/ipw/if_ipw.c,v 1.15 2005/11/13 17:17:40 damien Exp */ 3 4 /*- 5 * Copyright (c) 2004, 2005 6 * Damien Bergamini <damien.bergamini (at) free.fr>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: if_ipw.c,v 1.66 2017/10/23 09:31:18 msaitoh Exp $"); 33 34 /*- 35 * Intel(R) PRO/Wireless 2100 MiniPCI driver 36 * http://www.intel.com/network/connectivity/products/wireless/prowireless_mobile.htm 37 */ 38 39 40 #include <sys/param.h> 41 #include <sys/sockio.h> 42 #include <sys/sysctl.h> 43 #include <sys/mbuf.h> 44 #include <sys/kernel.h> 45 #include <sys/socket.h> 46 #include <sys/systm.h> 47 #include <sys/malloc.h> 48 #include <sys/conf.h> 49 #include <sys/proc.h> 50 51 #include <sys/bus.h> 52 #include <machine/endian.h> 53 #include <sys/intr.h> 54 55 #include <dev/pci/pcireg.h> 56 #include <dev/pci/pcivar.h> 57 #include <dev/pci/pcidevs.h> 58 59 #include <net/bpf.h> 60 #include <net/if.h> 61 #include <net/if_arp.h> 62 #include <net/if_dl.h> 63 #include <net/if_ether.h> 64 #include <net/if_media.h> 65 #include <net/if_types.h> 66 67 #include <net80211/ieee80211_var.h> 68 #include <net80211/ieee80211_radiotap.h> 69 70 #include <netinet/in.h> 71 #include <netinet/in_systm.h> 72 #include <netinet/in_var.h> 73 #include <netinet/ip.h> 74 75 #include <dev/firmload.h> 76 77 #include <dev/pci/if_ipwreg.h> 78 #include <dev/pci/if_ipwvar.h> 79 80 #ifdef IPW_DEBUG 81 #define DPRINTF(x) if (ipw_debug > 0) printf x 82 #define DPRINTFN(n, x) if (ipw_debug >= (n)) printf x 83 int ipw_debug = 0; 84 #else 85 #define DPRINTF(x) 86 #define DPRINTFN(n, x) 87 #endif 88 89 /* Permit loading the Intel firmware */ 90 static int ipw_accept_eula; 91 92 static int ipw_dma_alloc(struct ipw_softc *); 93 static void ipw_release(struct ipw_softc *); 94 static int ipw_match(device_t, cfdata_t, void *); 95 static void ipw_attach(device_t, device_t, void *); 96 static int ipw_detach(device_t, int); 97 98 static int ipw_media_change(struct ifnet *); 99 static void ipw_media_status(struct ifnet *, struct ifmediareq *); 100 static int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 101 static uint16_t ipw_read_prom_word(struct ipw_softc *, uint8_t); 102 static void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 103 static void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 104 static void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 105 struct ipw_soft_bd *, struct ipw_soft_buf *); 106 static void ipw_rx_intr(struct ipw_softc *); 107 static void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 108 static void ipw_tx_intr(struct ipw_softc *); 109 static int ipw_intr(void *); 110 static void ipw_softintr(void *); 111 static int ipw_cmd(struct ipw_softc *, uint32_t, void *, uint32_t); 112 static int ipw_tx_start(struct ifnet *, struct mbuf *, 113 struct ieee80211_node *); 114 static void ipw_start(struct ifnet *); 115 static void ipw_watchdog(struct ifnet *); 116 static int ipw_ioctl(struct ifnet *, u_long, void *); 117 static int ipw_get_table1(struct ipw_softc *, uint32_t *); 118 static int ipw_get_radio(struct ipw_softc *, int *); 119 static void ipw_stop_master(struct ipw_softc *); 120 static int ipw_reset(struct ipw_softc *); 121 static int ipw_load_ucode(struct ipw_softc *, u_char *, int); 122 static int ipw_load_firmware(struct ipw_softc *, u_char *, int); 123 static int ipw_cache_firmware(struct ipw_softc *); 124 static void ipw_free_firmware(struct ipw_softc *); 125 static int ipw_config(struct ipw_softc *); 126 static int ipw_init(struct ifnet *); 127 static void ipw_stop(struct ifnet *, int); 128 static uint32_t ipw_read_table1(struct ipw_softc *, uint32_t); 129 static void ipw_write_table1(struct ipw_softc *, uint32_t, uint32_t); 130 static int ipw_read_table2(struct ipw_softc *, uint32_t, void *, uint32_t *); 131 static void ipw_read_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 132 bus_size_t); 133 static void ipw_write_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 134 bus_size_t); 135 136 /* 137 * Supported rates for 802.11b mode (in 500Kbps unit). 138 */ 139 static const struct ieee80211_rateset ipw_rateset_11b = 140 { 4, { 2, 4, 11, 22 } }; 141 142 static inline uint8_t 143 MEM_READ_1(struct ipw_softc *sc, uint32_t addr) 144 { 145 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 146 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); 147 } 148 149 static inline uint32_t 150 MEM_READ_4(struct ipw_softc *sc, uint32_t addr) 151 { 152 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 153 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); 154 } 155 156 CFATTACH_DECL_NEW(ipw, sizeof (struct ipw_softc), ipw_match, ipw_attach, 157 ipw_detach, NULL); 158 159 static int 160 ipw_match(device_t parent, cfdata_t match, void *aux) 161 { 162 struct pci_attach_args *pa = aux; 163 164 if (PCI_VENDOR (pa->pa_id) == PCI_VENDOR_INTEL && 165 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_PRO_WL_2100) 166 return 1; 167 168 return 0; 169 } 170 171 /* Base Address Register */ 172 #define IPW_PCI_BAR0 0x10 173 174 static void 175 ipw_attach(device_t parent, device_t self, void *aux) 176 { 177 struct ipw_softc *sc = device_private(self); 178 struct ieee80211com *ic = &sc->sc_ic; 179 struct ifnet *ifp = &sc->sc_if; 180 struct pci_attach_args *pa = aux; 181 const char *intrstr; 182 bus_space_tag_t memt; 183 bus_space_handle_t memh; 184 bus_addr_t base; 185 pci_intr_handle_t ih; 186 uint32_t data; 187 uint16_t val; 188 int i, error; 189 char intrbuf[PCI_INTRSTR_LEN]; 190 191 sc->sc_dev = self; 192 sc->sc_pct = pa->pa_pc; 193 sc->sc_pcitag = pa->pa_tag; 194 195 pci_aprint_devinfo(pa, NULL); 196 197 /* enable bus-mastering */ 198 data = pci_conf_read(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG); 199 data |= PCI_COMMAND_MASTER_ENABLE; 200 pci_conf_write(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG, data); 201 202 /* map the register window */ 203 error = pci_mapreg_map(pa, IPW_PCI_BAR0, PCI_MAPREG_TYPE_MEM | 204 PCI_MAPREG_MEM_TYPE_32BIT, 0, &memt, &memh, &base, &sc->sc_sz); 205 if (error != 0) { 206 aprint_error_dev(sc->sc_dev, "could not map memory space\n"); 207 return; 208 } 209 210 sc->sc_st = memt; 211 sc->sc_sh = memh; 212 sc->sc_dmat = pa->pa_dmat; 213 sc->sc_fwname = "ipw2100-1.2.fw"; 214 215 /* disable interrupts */ 216 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 217 218 if (pci_intr_map(pa, &ih) != 0) { 219 aprint_error_dev(sc->sc_dev, "could not map interrupt\n"); 220 goto fail; 221 } 222 223 sc->sc_soft_ih = softint_establish(SOFTINT_NET, ipw_softintr, sc); 224 if (sc->sc_soft_ih == NULL) { 225 aprint_error_dev(sc->sc_dev, "could not establish softint\n"); 226 goto fail; 227 } 228 229 intrstr = pci_intr_string(sc->sc_pct, ih, intrbuf, sizeof(intrbuf)); 230 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, ipw_intr, sc); 231 if (sc->sc_ih == NULL) { 232 aprint_error_dev(sc->sc_dev, "could not establish interrupt"); 233 if (intrstr != NULL) 234 aprint_error(" at %s", intrstr); 235 aprint_error("\n"); 236 goto fail; 237 } 238 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 239 240 if (ipw_reset(sc) != 0) { 241 aprint_error_dev(sc->sc_dev, "could not reset adapter\n"); 242 goto fail; 243 } 244 245 if (ipw_dma_alloc(sc) != 0) { 246 aprint_error_dev(sc->sc_dev, "could not allocate DMA resources\n"); 247 goto fail; 248 } 249 250 ifp->if_softc = sc; 251 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 252 ifp->if_init = ipw_init; 253 ifp->if_stop = ipw_stop; 254 ifp->if_ioctl = ipw_ioctl; 255 ifp->if_start = ipw_start; 256 ifp->if_watchdog = ipw_watchdog; 257 IFQ_SET_READY(&ifp->if_snd); 258 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 259 260 ic->ic_ifp = ifp; 261 ic->ic_phytype = IEEE80211_T_DS; 262 ic->ic_opmode = IEEE80211_M_STA; 263 ic->ic_state = IEEE80211_S_INIT; 264 265 /* set device capabilities */ 266 ic->ic_caps = 267 IEEE80211_C_SHPREAMBLE /* short preamble supported */ 268 | IEEE80211_C_TXPMGT /* tx power management */ 269 | IEEE80211_C_IBSS /* ibss mode */ 270 | IEEE80211_C_MONITOR /* monitor mode */ 271 ; 272 273 /* read MAC address from EEPROM */ 274 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0); 275 ic->ic_myaddr[0] = val >> 8; 276 ic->ic_myaddr[1] = val & 0xff; 277 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 1); 278 ic->ic_myaddr[2] = val >> 8; 279 ic->ic_myaddr[3] = val & 0xff; 280 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 2); 281 ic->ic_myaddr[4] = val >> 8; 282 ic->ic_myaddr[5] = val & 0xff; 283 284 /* set supported .11b rates */ 285 ic->ic_sup_rates[IEEE80211_MODE_11B] = ipw_rateset_11b; 286 287 /* set supported .11b channels (read from EEPROM) */ 288 if ((val = ipw_read_prom_word(sc, IPW_EEPROM_CHANNEL_LIST)) == 0) 289 val = 0x7ff; /* default to channels 1-11 */ 290 val <<= 1; 291 for (i = 1; i < 16; i++) { 292 if (val & (1 << i)) { 293 ic->ic_channels[i].ic_freq = 294 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 295 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 296 } 297 } 298 299 /* check support for radio transmitter switch in EEPROM */ 300 if (!(ipw_read_prom_word(sc, IPW_EEPROM_RADIO) & 8)) 301 sc->flags |= IPW_FLAG_HAS_RADIO_SWITCH; 302 303 aprint_normal_dev(sc->sc_dev, "802.11 address %s\n", 304 ether_sprintf(ic->ic_myaddr)); 305 306 error = if_initialize(ifp); 307 if (error != 0) { 308 ifp->if_softc = NULL; /* For ipw_detach(). */ 309 aprint_error_dev(sc->sc_dev, "if_initialize failed(%d)\n", 310 error); 311 goto fail; 312 } 313 ieee80211_ifattach(ic); 314 /* Use common softint-based if_input */ 315 ifp->if_percpuq = if_percpuq_create(ifp); 316 if_register(ifp); 317 318 /* override state transition machine */ 319 sc->sc_newstate = ic->ic_newstate; 320 ic->ic_newstate = ipw_newstate; 321 322 ieee80211_media_init(ic, ipw_media_change, ipw_media_status); 323 324 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 325 sizeof(struct ieee80211_frame) + 64, &sc->sc_drvbpf); 326 327 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 328 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 329 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 330 331 sc->sc_txtap_len = sizeof sc->sc_txtapu; 332 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 333 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 334 335 /* 336 * Add a few sysctl knobs. 337 * XXX: Not yet 338 */ 339 sc->dwelltime = 100; 340 341 if (pmf_device_register(self, NULL, NULL)) 342 pmf_class_network_register(self, ifp); 343 else 344 aprint_error_dev(self, "couldn't establish power handler\n"); 345 346 ieee80211_announce(ic); 347 348 return; 349 350 fail: ipw_detach(self, 0); 351 } 352 353 static int 354 ipw_detach(device_t self, int flags) 355 { 356 struct ipw_softc *sc = device_private(self); 357 struct ifnet *ifp = &sc->sc_if; 358 359 if (ifp->if_softc) { 360 ipw_stop(ifp, 1); 361 ipw_free_firmware(sc); 362 363 bpf_detach(ifp); 364 ieee80211_ifdetach(&sc->sc_ic); 365 if_detach(ifp); 366 367 ipw_release(sc); 368 } 369 370 if (sc->sc_ih != NULL) { 371 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 372 sc->sc_ih = NULL; 373 } 374 375 if (sc->sc_soft_ih != NULL) { 376 softint_disestablish(sc->sc_soft_ih); 377 sc->sc_soft_ih = NULL; 378 } 379 380 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 381 382 return 0; 383 } 384 385 static int 386 ipw_dma_alloc(struct ipw_softc *sc) 387 { 388 struct ipw_soft_bd *sbd; 389 struct ipw_soft_hdr *shdr; 390 struct ipw_soft_buf *sbuf; 391 int error, i, nsegs; 392 393 /* 394 * Allocate and map tx ring. 395 */ 396 error = bus_dmamap_create(sc->sc_dmat, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, 397 BUS_DMA_NOWAIT, &sc->tbd_map); 398 if (error != 0) { 399 aprint_error_dev(sc->sc_dev, "could not create tbd dma map\n"); 400 goto fail; 401 } 402 403 error = bus_dmamem_alloc(sc->sc_dmat, IPW_TBD_SZ, PAGE_SIZE, 0, 404 &sc->tbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 405 if (error != 0) { 406 aprint_error_dev(sc->sc_dev, "could not allocate tbd dma memory\n"); 407 goto fail; 408 } 409 410 error = bus_dmamem_map(sc->sc_dmat, &sc->tbd_seg, nsegs, IPW_TBD_SZ, 411 (void **)&sc->tbd_list, BUS_DMA_NOWAIT); 412 if (error != 0) { 413 aprint_error_dev(sc->sc_dev, "could not map tbd dma memory\n"); 414 goto fail; 415 } 416 417 error = bus_dmamap_load(sc->sc_dmat, sc->tbd_map, sc->tbd_list, 418 IPW_TBD_SZ, NULL, BUS_DMA_NOWAIT); 419 if (error != 0) { 420 aprint_error_dev(sc->sc_dev, "could not load tbd dma memory\n"); 421 goto fail; 422 } 423 424 (void)memset(sc->tbd_list, 0, IPW_TBD_SZ); 425 426 /* 427 * Allocate and map rx ring. 428 */ 429 error = bus_dmamap_create(sc->sc_dmat, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, 430 BUS_DMA_NOWAIT, &sc->rbd_map); 431 if (error != 0) { 432 aprint_error_dev(sc->sc_dev, "could not create rbd dma map\n"); 433 goto fail; 434 } 435 436 error = bus_dmamem_alloc(sc->sc_dmat, IPW_RBD_SZ, PAGE_SIZE, 0, 437 &sc->rbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 438 if (error != 0) { 439 aprint_error_dev(sc->sc_dev, "could not allocate rbd dma memory\n"); 440 goto fail; 441 } 442 443 error = bus_dmamem_map(sc->sc_dmat, &sc->rbd_seg, nsegs, IPW_RBD_SZ, 444 (void **)&sc->rbd_list, BUS_DMA_NOWAIT); 445 if (error != 0) { 446 aprint_error_dev(sc->sc_dev, "could not map rbd dma memory\n"); 447 goto fail; 448 } 449 450 error = bus_dmamap_load(sc->sc_dmat, sc->rbd_map, sc->rbd_list, 451 IPW_RBD_SZ, NULL, BUS_DMA_NOWAIT); 452 if (error != 0) { 453 aprint_error_dev(sc->sc_dev, "could not load rbd dma memory\n"); 454 goto fail; 455 } 456 457 (void)memset(sc->rbd_list, 0, IPW_RBD_SZ); 458 459 /* 460 * Allocate and map status ring. 461 */ 462 error = bus_dmamap_create(sc->sc_dmat, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 463 0, BUS_DMA_NOWAIT, &sc->status_map); 464 if (error != 0) { 465 aprint_error_dev(sc->sc_dev, "could not create status dma map\n"); 466 goto fail; 467 } 468 469 error = bus_dmamem_alloc(sc->sc_dmat, IPW_STATUS_SZ, PAGE_SIZE, 0, 470 &sc->status_seg, 1, &nsegs, BUS_DMA_NOWAIT); 471 if (error != 0) { 472 aprint_error_dev(sc->sc_dev, "could not allocate status dma memory\n"); 473 goto fail; 474 } 475 476 error = bus_dmamem_map(sc->sc_dmat, &sc->status_seg, nsegs, 477 IPW_STATUS_SZ, (void **)&sc->status_list, BUS_DMA_NOWAIT); 478 if (error != 0) { 479 aprint_error_dev(sc->sc_dev, "could not map status dma memory\n"); 480 goto fail; 481 } 482 483 error = bus_dmamap_load(sc->sc_dmat, sc->status_map, sc->status_list, 484 IPW_STATUS_SZ, NULL, BUS_DMA_NOWAIT); 485 if (error != 0) { 486 aprint_error_dev(sc->sc_dev, "could not load status dma memory\n"); 487 goto fail; 488 } 489 490 (void)memset(sc->status_list, 0, IPW_STATUS_SZ); 491 492 /* 493 * Allocate command DMA map. 494 */ 495 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_cmd), 496 1, sizeof (struct ipw_cmd), 0, BUS_DMA_NOWAIT, &sc->cmd_map); 497 if (error != 0) { 498 aprint_error_dev(sc->sc_dev, "could not create cmd dma map\n"); 499 goto fail; 500 } 501 502 error = bus_dmamem_alloc(sc->sc_dmat, sizeof (struct ipw_cmd), 503 PAGE_SIZE, 0, &sc->cmd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 504 if (error != 0) { 505 aprint_error_dev(sc->sc_dev, "could not allocate cmd dma memory\n"); 506 goto fail; 507 } 508 509 error = bus_dmamem_map(sc->sc_dmat, &sc->cmd_seg, nsegs, 510 sizeof (struct ipw_cmd), (void **)&sc->cmd, BUS_DMA_NOWAIT); 511 if (error != 0) { 512 aprint_error_dev(sc->sc_dev, "could not map cmd dma memory\n"); 513 goto fail; 514 } 515 516 error = bus_dmamap_load(sc->sc_dmat, sc->cmd_map, &sc->cmd, 517 sizeof (struct ipw_cmd), NULL, BUS_DMA_NOWAIT); 518 if (error != 0) { 519 aprint_error_dev(sc->sc_dev, "could not map cmd dma memory\n"); 520 return error; 521 } 522 523 /* 524 * Allocate and map hdr list. 525 */ 526 527 error = bus_dmamap_create(sc->sc_dmat, 528 IPW_NDATA * sizeof(struct ipw_hdr), 1, 529 sizeof(struct ipw_hdr), 0, BUS_DMA_NOWAIT, 530 &sc->hdr_map); 531 if (error != 0) { 532 aprint_error_dev(sc->sc_dev, "could not create hdr dma map\n"); 533 goto fail; 534 } 535 536 error = bus_dmamem_alloc(sc->sc_dmat, 537 IPW_NDATA * sizeof(struct ipw_hdr), PAGE_SIZE, 0, &sc->hdr_seg, 538 1, &nsegs, BUS_DMA_NOWAIT); 539 if (error != 0) { 540 aprint_error_dev(sc->sc_dev, "could not allocate hdr memory\n"); 541 goto fail; 542 } 543 544 error = bus_dmamem_map(sc->sc_dmat, &sc->hdr_seg, nsegs, 545 IPW_NDATA * sizeof(struct ipw_hdr), (void **)&sc->hdr_list, 546 BUS_DMA_NOWAIT); 547 if (error != 0) { 548 aprint_error_dev(sc->sc_dev, "could not map hdr memory\n"); 549 goto fail; 550 } 551 552 error = bus_dmamap_load(sc->sc_dmat, sc->hdr_map, sc->hdr_list, 553 IPW_NDATA * sizeof(struct ipw_hdr), NULL, BUS_DMA_NOWAIT); 554 if (error != 0) { 555 aprint_error_dev(sc->sc_dev, "could not load hdr memory\n"); 556 goto fail; 557 } 558 559 (void)memset(sc->hdr_list, 0, IPW_HDR_SZ); 560 561 /* 562 * Create DMA hdrs tailq. 563 */ 564 TAILQ_INIT(&sc->sc_free_shdr); 565 for (i = 0; i < IPW_NDATA; i++) { 566 shdr = &sc->shdr_list[i]; 567 shdr->hdr = sc->hdr_list + i; 568 shdr->offset = sizeof(struct ipw_hdr) * i; 569 shdr->addr = sc->hdr_map->dm_segs[0].ds_addr + shdr->offset; 570 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 571 } 572 573 /* 574 * Allocate tx buffers DMA maps. 575 */ 576 TAILQ_INIT(&sc->sc_free_sbuf); 577 for (i = 0; i < IPW_NDATA; i++) { 578 sbuf = &sc->tx_sbuf_list[i]; 579 580 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 581 IPW_MAX_NSEG, MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 582 if (error != 0) { 583 aprint_error_dev(sc->sc_dev, "could not create txbuf dma map\n"); 584 goto fail; 585 } 586 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 587 } 588 589 /* 590 * Initialize tx ring. 591 */ 592 for (i = 0; i < IPW_NTBD; i++) { 593 sbd = &sc->stbd_list[i]; 594 sbd->bd = &sc->tbd_list[i]; 595 sbd->type = IPW_SBD_TYPE_NOASSOC; 596 } 597 598 /* 599 * Pre-allocate rx buffers and DMA maps 600 */ 601 for (i = 0; i < IPW_NRBD; i++) { 602 sbd = &sc->srbd_list[i]; 603 sbuf = &sc->rx_sbuf_list[i]; 604 sbd->bd = &sc->rbd_list[i]; 605 606 MGETHDR(sbuf->m, M_DONTWAIT, MT_DATA); 607 if (sbuf->m == NULL) { 608 aprint_error_dev(sc->sc_dev, "could not allocate rx mbuf\n"); 609 error = ENOMEM; 610 goto fail; 611 } 612 613 MCLGET(sbuf->m, M_DONTWAIT); 614 if (!(sbuf->m->m_flags & M_EXT)) { 615 m_freem(sbuf->m); 616 sbuf->m = NULL; 617 aprint_error_dev(sc->sc_dev, "could not allocate rx mbuf cluster\n"); 618 error = ENOMEM; 619 goto fail; 620 } 621 622 sbuf->m->m_pkthdr.len = sbuf->m->m_len = sbuf->m->m_ext.ext_size; 623 624 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 625 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sbuf->map); 626 if (error != 0) { 627 aprint_error_dev(sc->sc_dev, "could not create rxbuf dma map\n"); 628 m_freem(sbuf->m); 629 sbuf->m = NULL; 630 goto fail; 631 } 632 633 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, 634 sbuf->m, BUS_DMA_READ | BUS_DMA_NOWAIT); 635 if (error != 0) { 636 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 637 sbuf->map = NULL; 638 m_freem(sbuf->m); 639 sbuf->m = NULL; 640 aprint_error_dev(sc->sc_dev, "could not map rxbuf dma memory\n"); 641 goto fail; 642 } 643 644 sbd->type = IPW_SBD_TYPE_DATA; 645 sbd->priv = sbuf; 646 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 647 sbd->bd->len = htole32(MCLBYTES); 648 649 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, 650 sbuf->map->dm_mapsize, BUS_DMASYNC_PREREAD); 651 652 } 653 654 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 0, IPW_RBD_SZ, 655 BUS_DMASYNC_PREREAD); 656 657 return 0; 658 659 fail: ipw_release(sc); 660 return error; 661 } 662 663 static void 664 ipw_release(struct ipw_softc *sc) 665 { 666 struct ipw_soft_buf *sbuf; 667 int i; 668 669 if (sc->tbd_map != NULL) { 670 if (sc->tbd_list != NULL) { 671 bus_dmamap_unload(sc->sc_dmat, sc->tbd_map); 672 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->tbd_list, 673 IPW_TBD_SZ); 674 bus_dmamem_free(sc->sc_dmat, &sc->tbd_seg, 1); 675 } 676 bus_dmamap_destroy(sc->sc_dmat, sc->tbd_map); 677 } 678 679 if (sc->rbd_map != NULL) { 680 if (sc->rbd_list != NULL) { 681 bus_dmamap_unload(sc->sc_dmat, sc->rbd_map); 682 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->rbd_list, 683 IPW_RBD_SZ); 684 bus_dmamem_free(sc->sc_dmat, &sc->rbd_seg, 1); 685 } 686 bus_dmamap_destroy(sc->sc_dmat, sc->rbd_map); 687 } 688 689 if (sc->status_map != NULL) { 690 if (sc->status_list != NULL) { 691 bus_dmamap_unload(sc->sc_dmat, sc->status_map); 692 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->status_list, 693 IPW_RBD_SZ); 694 bus_dmamem_free(sc->sc_dmat, &sc->status_seg, 1); 695 } 696 bus_dmamap_destroy(sc->sc_dmat, sc->status_map); 697 } 698 699 for (i = 0; i < IPW_NTBD; i++) 700 ipw_release_sbd(sc, &sc->stbd_list[i]); 701 702 if (sc->cmd_map != NULL) 703 bus_dmamap_destroy(sc->sc_dmat, sc->cmd_map); 704 705 if (sc->hdr_list != NULL) { 706 bus_dmamap_unload(sc->sc_dmat, sc->hdr_map); 707 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->hdr_list, 708 IPW_NDATA * sizeof(struct ipw_hdr)); 709 } 710 if (sc->hdr_map != NULL) { 711 bus_dmamem_free(sc->sc_dmat, &sc->hdr_seg, 1); 712 bus_dmamap_destroy(sc->sc_dmat, sc->hdr_map); 713 } 714 715 for (i = 0; i < IPW_NDATA; i++) 716 bus_dmamap_destroy(sc->sc_dmat, sc->tx_sbuf_list[i].map); 717 718 for (i = 0; i < IPW_NRBD; i++) { 719 sbuf = &sc->rx_sbuf_list[i]; 720 if (sbuf->map != NULL) { 721 if (sbuf->m != NULL) { 722 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 723 m_freem(sbuf->m); 724 } 725 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 726 } 727 } 728 729 } 730 731 static int 732 ipw_media_change(struct ifnet *ifp) 733 { 734 int error; 735 736 error = ieee80211_media_change(ifp); 737 if (error != ENETRESET) 738 return error; 739 740 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 741 ipw_init(ifp); 742 743 return 0; 744 } 745 746 /* 747 * The firmware automatically adapts the transmit speed. We report the current 748 * transmit speed here. 749 */ 750 static void 751 ipw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 752 { 753 #define N(a) (sizeof (a) / sizeof (a[0])) 754 struct ipw_softc *sc = ifp->if_softc; 755 struct ieee80211com *ic = &sc->sc_ic; 756 static const struct { 757 uint32_t val; 758 int rate; 759 } rates[] = { 760 { IPW_RATE_DS1, 2 }, 761 { IPW_RATE_DS2, 4 }, 762 { IPW_RATE_DS5, 11 }, 763 { IPW_RATE_DS11, 22 }, 764 }; 765 uint32_t val; 766 int rate, i; 767 768 imr->ifm_status = IFM_AVALID; 769 imr->ifm_active = IFM_IEEE80211; 770 if (ic->ic_state == IEEE80211_S_RUN) 771 imr->ifm_status |= IFM_ACTIVE; 772 773 /* read current transmission rate from adapter */ 774 val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE) & 0xf; 775 776 /* convert ipw rate to 802.11 rate */ 777 for (i = 0; i < N(rates) && rates[i].val != val; i++); 778 rate = (i < N(rates)) ? rates[i].rate : 0; 779 780 imr->ifm_active |= IFM_IEEE80211_11B; 781 imr->ifm_active |= ieee80211_rate2media(ic, rate, IEEE80211_MODE_11B); 782 switch (ic->ic_opmode) { 783 case IEEE80211_M_STA: 784 break; 785 786 case IEEE80211_M_IBSS: 787 imr->ifm_active |= IFM_IEEE80211_ADHOC; 788 break; 789 790 case IEEE80211_M_MONITOR: 791 imr->ifm_active |= IFM_IEEE80211_MONITOR; 792 break; 793 794 case IEEE80211_M_AHDEMO: 795 case IEEE80211_M_HOSTAP: 796 /* should not get there */ 797 break; 798 } 799 #undef N 800 } 801 802 static int 803 ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, 804 int arg) 805 { 806 struct ifnet *ifp = ic->ic_ifp; 807 struct ipw_softc *sc = ifp->if_softc; 808 struct ieee80211_node *ni; 809 uint8_t macaddr[IEEE80211_ADDR_LEN]; 810 uint32_t len; 811 struct ipw_rx_radiotap_header *wr = &sc->sc_rxtap; 812 struct ipw_tx_radiotap_header *wt = &sc->sc_txtap; 813 814 switch (nstate) { 815 case IEEE80211_S_INIT: 816 break; 817 default: 818 KASSERT(ic->ic_curchan != IEEE80211_CHAN_ANYC); 819 KASSERT(ic->ic_curchan != NULL); 820 wt->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 821 wt->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 822 wr->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 823 wr->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 824 break; 825 } 826 827 switch (nstate) { 828 case IEEE80211_S_RUN: 829 DELAY(200); /* firmware needs a short delay here */ 830 831 len = IEEE80211_ADDR_LEN; 832 ipw_read_table2(sc, IPW_INFO_CURRENT_BSSID, macaddr, &len); 833 834 ni = ieee80211_find_node(&ic->ic_scan, macaddr); 835 if (ni == NULL) 836 break; 837 838 ieee80211_ref_node(ni); 839 ieee80211_sta_join(ic, ni); 840 ieee80211_node_authorize(ni); 841 842 if (ic->ic_opmode == IEEE80211_M_STA) 843 ieee80211_notify_node_join(ic, ni, 1); 844 break; 845 846 case IEEE80211_S_INIT: 847 case IEEE80211_S_SCAN: 848 case IEEE80211_S_AUTH: 849 case IEEE80211_S_ASSOC: 850 break; 851 } 852 853 ic->ic_state = nstate; 854 return 0; 855 } 856 857 /* 858 * Read 16 bits at address 'addr' from the serial EEPROM. 859 */ 860 static uint16_t 861 ipw_read_prom_word(struct ipw_softc *sc, uint8_t addr) 862 { 863 uint32_t tmp; 864 uint16_t val; 865 int n; 866 867 /* clock C once before the first command */ 868 IPW_EEPROM_CTL(sc, 0); 869 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 870 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 871 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 872 873 /* write start bit (1) */ 874 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 875 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 876 877 /* write READ opcode (10) */ 878 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 879 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 880 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 881 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 882 883 /* write address A7-A0 */ 884 for (n = 7; n >= 0; n--) { 885 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 886 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D)); 887 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 888 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D) | IPW_EEPROM_C); 889 } 890 891 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 892 893 /* read data Q15-Q0 */ 894 val = 0; 895 for (n = 15; n >= 0; n--) { 896 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 897 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 898 tmp = MEM_READ_4(sc, IPW_MEM_EEPROM_CTL); 899 val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n; 900 } 901 902 IPW_EEPROM_CTL(sc, 0); 903 904 /* clear Chip Select and clock C */ 905 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 906 IPW_EEPROM_CTL(sc, 0); 907 IPW_EEPROM_CTL(sc, IPW_EEPROM_C); 908 909 return le16toh(val); 910 } 911 912 static void 913 ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 914 { 915 916 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof (struct ipw_cmd), 917 BUS_DMASYNC_POSTREAD); 918 919 #ifdef IPW_DEBUG 920 struct ipw_cmd *cmd = mtod(sbuf->m, struct ipw_cmd *); 921 922 DPRINTFN(2, ("cmd ack'ed (%u, %u, %u, %u, %u)\n", le32toh(cmd->type), 923 le32toh(cmd->subtype), le32toh(cmd->seq), le32toh(cmd->len), 924 le32toh(cmd->status))); 925 #endif 926 927 wakeup(&sc->cmd); 928 } 929 930 static void 931 ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 932 { 933 struct ieee80211com *ic = &sc->sc_ic; 934 struct ifnet *ifp = sc->sc_ic.ic_ifp; 935 uint32_t state; 936 int s; 937 938 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof state, 939 BUS_DMASYNC_POSTREAD); 940 941 state = le32toh(*mtod(sbuf->m, uint32_t *)); 942 943 DPRINTFN(2, ("entering state %u\n", state)); 944 945 s = splnet(); 946 947 switch (state) { 948 case IPW_STATE_ASSOCIATED: 949 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 950 break; 951 952 case IPW_STATE_SCANNING: 953 /* don't leave run state on background scan */ 954 if (ic->ic_state != IEEE80211_S_RUN) 955 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 956 957 ic->ic_flags |= IEEE80211_F_SCAN; 958 break; 959 960 case IPW_STATE_SCAN_COMPLETE: 961 ieee80211_notify_scan_done(ic); 962 ic->ic_flags &= ~IEEE80211_F_SCAN; 963 break; 964 965 case IPW_STATE_ASSOCIATION_LOST: 966 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 967 break; 968 969 case IPW_STATE_RADIO_DISABLED: 970 ic->ic_ifp->if_flags &= ~IFF_UP; 971 ipw_stop(ifp, 1); 972 break; 973 } 974 975 splx(s); 976 } 977 978 /* 979 * XXX: Hack to set the current channel to the value advertised in beacons or 980 * probe responses. Only used during AP detection. 981 */ 982 static void 983 ipw_fix_channel(struct ieee80211com *ic, struct mbuf *m) 984 { 985 struct ieee80211_frame *wh; 986 uint8_t subtype; 987 uint8_t *frm, *efrm; 988 989 wh = mtod(m, struct ieee80211_frame *); 990 991 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_MGT) 992 return; 993 994 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 995 996 if (subtype != IEEE80211_FC0_SUBTYPE_BEACON && 997 subtype != IEEE80211_FC0_SUBTYPE_PROBE_RESP) 998 return; 999 1000 frm = (uint8_t *)(wh + 1); 1001 efrm = mtod(m, uint8_t *) + m->m_len; 1002 1003 frm += 12; /* skip tstamp, bintval and capinfo fields */ 1004 while (frm < efrm) { 1005 if (*frm == IEEE80211_ELEMID_DSPARMS) 1006 #if IEEE80211_CHAN_MAX < 255 1007 if (frm[2] <= IEEE80211_CHAN_MAX) 1008 #endif 1009 ic->ic_curchan = &ic->ic_channels[frm[2]]; 1010 1011 frm += frm[1] + 2; 1012 } 1013 } 1014 1015 static void 1016 ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 1017 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 1018 { 1019 struct ieee80211com *ic = &sc->sc_ic; 1020 struct ifnet *ifp = &sc->sc_if; 1021 struct mbuf *mnew, *m; 1022 struct ieee80211_frame *wh; 1023 struct ieee80211_node *ni; 1024 int error, s; 1025 1026 DPRINTFN(5, ("received frame len=%u, rssi=%u\n", le32toh(status->len), 1027 status->rssi)); 1028 1029 if (le32toh(status->len) < sizeof (struct ieee80211_frame_min) || 1030 le32toh(status->len) > MCLBYTES) 1031 return; 1032 1033 /* 1034 * Try to allocate a new mbuf for this ring element and load it before 1035 * processing the current mbuf. If the ring element cannot be loaded, 1036 * drop the received packet and reuse the old mbuf. In the unlikely 1037 * case that the old mbuf can't be reloaded either, explicitly panic. 1038 */ 1039 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1040 if (mnew == NULL) { 1041 aprint_error_dev(sc->sc_dev, "could not allocate rx mbuf\n"); 1042 ifp->if_ierrors++; 1043 return; 1044 } 1045 1046 MCLGET(mnew, M_DONTWAIT); 1047 if (!(mnew->m_flags & M_EXT)) { 1048 aprint_error_dev(sc->sc_dev, "could not allocate rx mbuf cluster\n"); 1049 m_freem(mnew); 1050 ifp->if_ierrors++; 1051 return; 1052 } 1053 1054 mnew->m_pkthdr.len = mnew->m_len = mnew->m_ext.ext_size; 1055 1056 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, le32toh(status->len), 1057 BUS_DMASYNC_POSTREAD); 1058 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1059 1060 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, mnew, 1061 BUS_DMA_READ | BUS_DMA_NOWAIT); 1062 if (error != 0) { 1063 aprint_error_dev(sc->sc_dev, "could not load rx buf DMA map\n"); 1064 m_freem(mnew); 1065 1066 /* try to reload the old mbuf */ 1067 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, 1068 sbuf->m, BUS_DMA_READ | BUS_DMA_NOWAIT); 1069 if (error != 0) { 1070 /* very unlikely that it will fail... */ 1071 panic("%s: unable to remap rx buf", 1072 device_xname(sc->sc_dev)); 1073 } 1074 ifp->if_ierrors++; 1075 return; 1076 } 1077 1078 /* 1079 * New mbuf successfully loaded, update Rx ring and continue 1080 * processing. 1081 */ 1082 m = sbuf->m; 1083 sbuf->m = mnew; 1084 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 1085 1086 /* finalize mbuf */ 1087 m_set_rcvif(m, ifp); 1088 m->m_pkthdr.len = m->m_len = le32toh(status->len); 1089 1090 s = splnet(); 1091 1092 if (sc->sc_drvbpf != NULL) { 1093 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 1094 1095 tap->wr_antsignal = status->rssi; 1096 1097 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 1098 } 1099 1100 if (ic->ic_state == IEEE80211_S_SCAN) 1101 ipw_fix_channel(ic, m); 1102 1103 wh = mtod(m, struct ieee80211_frame *); 1104 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 1105 1106 /* send the frame to the 802.11 layer */ 1107 ieee80211_input(ic, m, ni, status->rssi, 0); 1108 1109 /* node is no longer needed */ 1110 ieee80211_free_node(ni); 1111 1112 splx(s); 1113 1114 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, 1115 sbuf->map->dm_mapsize, BUS_DMASYNC_PREREAD); 1116 } 1117 1118 static void 1119 ipw_rx_intr(struct ipw_softc *sc) 1120 { 1121 struct ipw_status *status; 1122 struct ipw_soft_bd *sbd; 1123 struct ipw_soft_buf *sbuf; 1124 uint32_t r, i; 1125 1126 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1127 return; 1128 1129 r = CSR_READ_4(sc, IPW_CSR_RX_READ); 1130 1131 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 1132 1133 /* firmware was killed, stop processing received frames */ 1134 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1135 return; 1136 1137 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 1138 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1139 BUS_DMASYNC_POSTREAD); 1140 1141 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 1142 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 1143 BUS_DMASYNC_POSTREAD); 1144 1145 status = &sc->status_list[i]; 1146 sbd = &sc->srbd_list[i]; 1147 sbuf = sbd->priv; 1148 1149 switch (le16toh(status->code) & 0xf) { 1150 case IPW_STATUS_CODE_COMMAND: 1151 ipw_command_intr(sc, sbuf); 1152 break; 1153 1154 case IPW_STATUS_CODE_NEWSTATE: 1155 ipw_newstate_intr(sc, sbuf); 1156 break; 1157 1158 case IPW_STATUS_CODE_DATA_802_3: 1159 case IPW_STATUS_CODE_DATA_802_11: 1160 ipw_data_intr(sc, status, sbd, sbuf); 1161 break; 1162 1163 case IPW_STATUS_CODE_NOTIFICATION: 1164 DPRINTFN(2, ("received notification\n")); 1165 break; 1166 1167 default: 1168 aprint_error_dev(sc->sc_dev, "unknown status code %u\n", 1169 le16toh(status->code)); 1170 } 1171 1172 sbd->bd->flags = 0; 1173 1174 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 1175 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1176 BUS_DMASYNC_PREREAD); 1177 1178 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 1179 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 1180 BUS_DMASYNC_PREREAD); 1181 } 1182 1183 /* Tell the firmware what we have processed */ 1184 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 1185 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 1186 } 1187 1188 static void 1189 ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 1190 { 1191 struct ipw_soft_hdr *shdr; 1192 struct ipw_soft_buf *sbuf; 1193 1194 switch (sbd->type) { 1195 case IPW_SBD_TYPE_COMMAND: 1196 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 1197 0, sizeof(struct ipw_cmd), BUS_DMASYNC_POSTWRITE); 1198 /* bus_dmamap_unload(sc->sc_dmat, sc->cmd_map); */ 1199 break; 1200 1201 case IPW_SBD_TYPE_HEADER: 1202 shdr = sbd->priv; 1203 bus_dmamap_sync(sc->sc_dmat, sc->hdr_map, 1204 shdr->offset, sizeof(struct ipw_hdr), BUS_DMASYNC_POSTWRITE); 1205 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 1206 break; 1207 1208 case IPW_SBD_TYPE_DATA: 1209 sbuf = sbd->priv; 1210 1211 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 1212 0, sbuf->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1213 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1214 m_freem(sbuf->m); 1215 if (sbuf->ni != NULL) 1216 ieee80211_free_node(sbuf->ni); 1217 /* kill watchdog timer */ 1218 sc->sc_tx_timer = 0; 1219 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 1220 break; 1221 } 1222 sbd->type = IPW_SBD_TYPE_NOASSOC; 1223 } 1224 1225 static void 1226 ipw_tx_intr(struct ipw_softc *sc) 1227 { 1228 struct ifnet *ifp = &sc->sc_if; 1229 struct ipw_soft_bd *sbd; 1230 uint32_t r, i; 1231 int s; 1232 1233 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1234 return; 1235 1236 s = splnet(); 1237 1238 r = CSR_READ_4(sc, IPW_CSR_TX_READ); 1239 1240 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) { 1241 sbd = &sc->stbd_list[i]; 1242 1243 if (sbd->type == IPW_SBD_TYPE_DATA) 1244 ifp->if_opackets++; 1245 1246 ipw_release_sbd(sc, sbd); 1247 sc->txfree++; 1248 } 1249 1250 /* remember what the firmware has processed */ 1251 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 1252 1253 /* Call start() since some buffer descriptors have been released */ 1254 ifp->if_flags &= ~IFF_OACTIVE; 1255 ipw_start(ifp); /* in softint */ 1256 1257 splx(s); 1258 } 1259 1260 static int 1261 ipw_intr(void *arg) 1262 { 1263 struct ipw_softc *sc = arg; 1264 uint32_t r; 1265 1266 r = CSR_READ_4(sc, IPW_CSR_INTR); 1267 if (r == 0 || r == 0xffffffff) 1268 return 0; 1269 1270 /* Disable interrupts */ 1271 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1272 1273 softint_schedule(sc->sc_soft_ih); 1274 return 1; 1275 } 1276 1277 static void 1278 ipw_softintr(void *arg) 1279 { 1280 struct ipw_softc *sc = arg; 1281 uint32_t r; 1282 int s; 1283 1284 r = CSR_READ_4(sc, IPW_CSR_INTR); 1285 if (r == 0 || r == 0xffffffff) 1286 goto out; 1287 1288 if (r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR)) { 1289 aprint_error_dev(sc->sc_dev, "fatal error\n"); 1290 s = splnet(); 1291 sc->sc_ic.ic_ifp->if_flags &= ~IFF_UP; 1292 ipw_stop(&sc->sc_if, 1); 1293 splx(s); 1294 } 1295 1296 if (r & IPW_INTR_FW_INIT_DONE) { 1297 if (!(r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR))) 1298 wakeup(sc); 1299 } 1300 1301 if (r & IPW_INTR_RX_TRANSFER) 1302 ipw_rx_intr(sc); 1303 1304 if (r & IPW_INTR_TX_TRANSFER) 1305 ipw_tx_intr(sc); 1306 1307 /* Acknowledge all interrupts */ 1308 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 1309 1310 out: 1311 /* Re-enable interrupts */ 1312 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1313 } 1314 1315 /* 1316 * Send a command to the firmware and wait for the acknowledgement. 1317 */ 1318 static int 1319 ipw_cmd(struct ipw_softc *sc, uint32_t type, void *data, uint32_t len) 1320 { 1321 struct ipw_soft_bd *sbd; 1322 1323 sbd = &sc->stbd_list[sc->txcur]; 1324 1325 sc->cmd.type = htole32(type); 1326 sc->cmd.subtype = 0; 1327 sc->cmd.len = htole32(len); 1328 sc->cmd.seq = 0; 1329 1330 (void)memcpy(sc->cmd.data, data, len); 1331 1332 sbd->type = IPW_SBD_TYPE_COMMAND; 1333 sbd->bd->physaddr = htole32(sc->cmd_map->dm_segs[0].ds_addr); 1334 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 1335 sbd->bd->nfrag = 1; 1336 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 1337 IPW_BD_FLAG_TX_LAST_FRAGMENT; 1338 1339 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 0, sizeof (struct ipw_cmd), 1340 BUS_DMASYNC_PREWRITE); 1341 1342 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1343 sc->txcur * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1344 BUS_DMASYNC_PREWRITE); 1345 1346 DPRINTFN(2, ("sending command (%u, %u, %u, %u)\n", type, 0, 0, len)); 1347 1348 /* kick firmware */ 1349 sc->txfree--; 1350 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1351 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1352 1353 /* Wait at most one second for command to complete */ 1354 return tsleep(&sc->cmd, 0, "ipwcmd", hz); 1355 } 1356 1357 static int 1358 ipw_tx_start(struct ifnet *ifp, struct mbuf *m0, struct ieee80211_node *ni) 1359 { 1360 struct ipw_softc *sc = ifp->if_softc; 1361 struct ieee80211com *ic = &sc->sc_ic; 1362 struct ieee80211_frame *wh; 1363 struct ipw_soft_bd *sbd; 1364 struct ipw_soft_hdr *shdr; 1365 struct ipw_soft_buf *sbuf; 1366 struct ieee80211_key *k; 1367 struct mbuf *mnew; 1368 int error, i; 1369 1370 wh = mtod(m0, struct ieee80211_frame *); 1371 1372 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1373 k = ieee80211_crypto_encap(ic, ni, m0); 1374 if (k == NULL) { 1375 m_freem(m0); 1376 return ENOBUFS; 1377 } 1378 1379 /* packet header may have moved, reset our local pointer */ 1380 wh = mtod(m0, struct ieee80211_frame *); 1381 } 1382 1383 if (sc->sc_drvbpf != NULL) { 1384 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 1385 1386 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 1387 } 1388 1389 shdr = TAILQ_FIRST(&sc->sc_free_shdr); 1390 sbuf = TAILQ_FIRST(&sc->sc_free_sbuf); 1391 KASSERT(shdr != NULL && sbuf != NULL); 1392 1393 shdr->hdr->type = htole32(IPW_HDR_TYPE_SEND); 1394 shdr->hdr->subtype = 0; 1395 shdr->hdr->encrypted = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0; 1396 shdr->hdr->encrypt = 0; 1397 shdr->hdr->keyidx = 0; 1398 shdr->hdr->keysz = 0; 1399 shdr->hdr->fragmentsz = 0; 1400 IEEE80211_ADDR_COPY(shdr->hdr->src_addr, wh->i_addr2); 1401 if (ic->ic_opmode == IEEE80211_M_STA) 1402 IEEE80211_ADDR_COPY(shdr->hdr->dst_addr, wh->i_addr3); 1403 else 1404 IEEE80211_ADDR_COPY(shdr->hdr->dst_addr, wh->i_addr1); 1405 1406 /* trim IEEE802.11 header */ 1407 m_adj(m0, sizeof (struct ieee80211_frame)); 1408 1409 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m0, 1410 BUS_DMA_NOWAIT); 1411 if (error != 0 && error != EFBIG) { 1412 aprint_error_dev(sc->sc_dev, "could not map mbuf (error %d)\n", 1413 error); 1414 m_freem(m0); 1415 return error; 1416 } 1417 1418 if (error != 0) { 1419 /* too many fragments, linearize */ 1420 1421 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1422 if (mnew == NULL) { 1423 m_freem(m0); 1424 return ENOMEM; 1425 } 1426 1427 M_COPY_PKTHDR(mnew, m0); 1428 1429 /* If the data won't fit in the header, get a cluster */ 1430 if (m0->m_pkthdr.len > MHLEN) { 1431 MCLGET(mnew, M_DONTWAIT); 1432 if (!(mnew->m_flags & M_EXT)) { 1433 m_freem(m0); 1434 m_freem(mnew); 1435 return ENOMEM; 1436 } 1437 } 1438 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(mnew, void *)); 1439 m_freem(m0); 1440 mnew->m_len = mnew->m_pkthdr.len; 1441 m0 = mnew; 1442 1443 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m0, 1444 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1445 if (error != 0) { 1446 aprint_error_dev(sc->sc_dev, 1447 "could not map mbuf (error %d)\n", error); 1448 m_freem(m0); 1449 return error; 1450 } 1451 } 1452 1453 TAILQ_REMOVE(&sc->sc_free_sbuf, sbuf, next); 1454 TAILQ_REMOVE(&sc->sc_free_shdr, shdr, next); 1455 1456 sbd = &sc->stbd_list[sc->txcur]; 1457 sbd->type = IPW_SBD_TYPE_HEADER; 1458 sbd->priv = shdr; 1459 sbd->bd->physaddr = htole32(shdr->addr); 1460 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 1461 sbd->bd->nfrag = 1 + sbuf->map->dm_nsegs; 1462 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 1463 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1464 1465 DPRINTFN(5, ("sending tx hdr (%u, %u, %u, %u, )\n", 1466 shdr->hdr->type, shdr->hdr->subtype, shdr->hdr->encrypted, 1467 shdr->hdr->encrypt)); 1468 DPRINTFN(5, ("%s->", ether_sprintf(shdr->hdr->src_addr))); 1469 DPRINTFN(5, ("%s\n", ether_sprintf(shdr->hdr->dst_addr))); 1470 1471 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1472 sc->txcur * sizeof (struct ipw_bd), 1473 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1474 1475 sc->txfree--; 1476 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1477 1478 sbuf->m = m0; 1479 sbuf->ni = ni; 1480 1481 for (i = 0; i < sbuf->map->dm_nsegs; i++) { 1482 sbd = &sc->stbd_list[sc->txcur]; 1483 1484 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[i].ds_addr); 1485 sbd->bd->len = htole32(sbuf->map->dm_segs[i].ds_len); 1486 sbd->bd->nfrag = 0; 1487 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 1488 if (i == sbuf->map->dm_nsegs - 1) { 1489 sbd->type = IPW_SBD_TYPE_DATA; 1490 sbd->priv = sbuf; 1491 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 1492 } else { 1493 sbd->type = IPW_SBD_TYPE_NOASSOC; 1494 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1495 } 1496 1497 DPRINTFN(5, ("sending fragment (%d, %d)\n", i, 1498 (int)sbuf->map->dm_segs[i].ds_len)); 1499 1500 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1501 sc->txcur * sizeof (struct ipw_bd), 1502 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1503 1504 sc->txfree--; 1505 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1506 } 1507 1508 bus_dmamap_sync(sc->sc_dmat, sc->hdr_map, shdr->offset, 1509 sizeof (struct ipw_hdr), BUS_DMASYNC_PREWRITE); 1510 1511 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sbuf->map->dm_mapsize, 1512 BUS_DMASYNC_PREWRITE); 1513 1514 /* Inform firmware about this new packet */ 1515 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1516 1517 return 0; 1518 } 1519 1520 static void 1521 ipw_start(struct ifnet *ifp) 1522 { 1523 struct ipw_softc *sc = ifp->if_softc; 1524 struct ieee80211com *ic = &sc->sc_ic; 1525 struct mbuf *m0; 1526 struct ether_header *eh; 1527 struct ieee80211_node *ni; 1528 1529 if (ic->ic_state != IEEE80211_S_RUN) 1530 return; 1531 1532 for (;;) { 1533 IF_DEQUEUE(&ifp->if_snd, m0); 1534 if (m0 == NULL) 1535 break; 1536 1537 if (sc->txfree < 1 + IPW_MAX_NSEG) { 1538 IF_PREPEND(&ifp->if_snd, m0); 1539 ifp->if_flags |= IFF_OACTIVE; 1540 break; 1541 } 1542 1543 if (m0->m_len < sizeof (struct ether_header) && 1544 (m0 = m_pullup(m0, sizeof (struct ether_header))) == NULL) 1545 continue; 1546 1547 eh = mtod(m0, struct ether_header *); 1548 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1549 if (ni == NULL) { 1550 m_freem(m0); 1551 continue; 1552 } 1553 1554 bpf_mtap(ifp, m0); 1555 1556 m0 = ieee80211_encap(ic, m0, ni); 1557 if (m0 == NULL) { 1558 ieee80211_free_node(ni); 1559 continue; 1560 } 1561 1562 bpf_mtap3(ic->ic_rawbpf, m0); 1563 1564 if (ipw_tx_start(ifp, m0, ni) != 0) { 1565 ieee80211_free_node(ni); 1566 ifp->if_oerrors++; 1567 break; 1568 } 1569 1570 /* start watchdog timer */ 1571 sc->sc_tx_timer = 5; 1572 ifp->if_timer = 1; 1573 } 1574 } 1575 1576 static void 1577 ipw_watchdog(struct ifnet *ifp) 1578 { 1579 struct ipw_softc *sc = ifp->if_softc; 1580 1581 ifp->if_timer = 0; 1582 1583 if (sc->sc_tx_timer > 0) { 1584 if (--sc->sc_tx_timer == 0) { 1585 aprint_error_dev(sc->sc_dev, "device timeout\n"); 1586 ifp->if_oerrors++; 1587 ifp->if_flags &= ~IFF_UP; 1588 ipw_stop(ifp, 1); 1589 return; 1590 } 1591 ifp->if_timer = 1; 1592 } 1593 1594 ieee80211_watchdog(&sc->sc_ic); 1595 } 1596 1597 static int 1598 ipw_get_table1(struct ipw_softc *sc, uint32_t *tbl) 1599 { 1600 uint32_t addr, size, data, i; 1601 int error; 1602 1603 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1604 return ENOTTY; 1605 1606 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, sc->table1_base); 1607 1608 size = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 1609 if ((error = copyout(&size, tbl, sizeof(size))) != 0) 1610 return error; 1611 1612 for (i = 1, ++tbl; i < size; i++, tbl++) { 1613 addr = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 1614 data = MEM_READ_4(sc, addr); 1615 if ((error = copyout(&data, tbl, sizeof(data))) != 0) 1616 return error; 1617 } 1618 return 0; 1619 } 1620 1621 static int 1622 ipw_get_radio(struct ipw_softc *sc, int *ret) 1623 { 1624 uint32_t addr, data; 1625 1626 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1627 return ENOTTY; 1628 1629 addr = ipw_read_table1(sc, IPW_INFO_EEPROM_ADDRESS); 1630 if ((MEM_READ_4(sc, addr + 32) >> 24) & 1) 1631 data = -1; 1632 else if (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED) 1633 data = 0; 1634 else 1635 data = 1; 1636 1637 return copyout(&data, ret, sizeof(data)); 1638 } 1639 1640 static int 1641 ipw_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1642 { 1643 #define IS_RUNNING(ifp) \ 1644 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 1645 1646 struct ipw_softc *sc = ifp->if_softc; 1647 struct ieee80211com *ic = &sc->sc_ic; 1648 struct ifreq *ifr = (struct ifreq *)data; 1649 int s, error = 0; 1650 1651 s = splnet(); 1652 1653 switch (cmd) { 1654 case SIOCSIFFLAGS: 1655 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 1656 break; 1657 if (ifp->if_flags & IFF_UP) { 1658 if (!(ifp->if_flags & IFF_RUNNING)) 1659 ipw_init(ifp); 1660 } else { 1661 if (ifp->if_flags & IFF_RUNNING) 1662 ipw_stop(ifp, 1); 1663 } 1664 break; 1665 1666 case SIOCADDMULTI: 1667 case SIOCDELMULTI: 1668 /* XXX no h/w multicast filter? --dyoung */ 1669 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1670 /* setup multicast filter, etc */ 1671 error = 0; 1672 } 1673 break; 1674 1675 case SIOCGTABLE1: 1676 error = ipw_get_table1(sc, (uint32_t *)ifr->ifr_data); 1677 break; 1678 1679 case SIOCGRADIO: 1680 error = ipw_get_radio(sc, (int *)ifr->ifr_data); 1681 break; 1682 1683 case SIOCSIFMEDIA: 1684 if (ifr->ifr_media & IFM_IEEE80211_ADHOC) 1685 sc->sc_fwname = "ipw2100-1.2-i.fw"; 1686 else if (ifr->ifr_media & IFM_IEEE80211_MONITOR) 1687 sc->sc_fwname = "ipw2100-1.2-p.fw"; 1688 else 1689 sc->sc_fwname = "ipw2100-1.2.fw"; 1690 1691 ipw_free_firmware(sc); 1692 /* FALLTRHOUGH */ 1693 default: 1694 error = ieee80211_ioctl(&sc->sc_ic, cmd, data); 1695 if (error != ENETRESET) 1696 break; 1697 1698 if (error == ENETRESET) { 1699 if (IS_RUNNING(ifp) && 1700 (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)) 1701 ipw_init(ifp); 1702 error = 0; 1703 } 1704 1705 } 1706 1707 splx(s); 1708 return error; 1709 #undef IS_RUNNING 1710 } 1711 1712 static uint32_t 1713 ipw_read_table1(struct ipw_softc *sc, uint32_t off) 1714 { 1715 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 1716 } 1717 1718 static void 1719 ipw_write_table1(struct ipw_softc *sc, uint32_t off, uint32_t info) 1720 { 1721 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 1722 } 1723 1724 static int 1725 ipw_read_table2(struct ipw_softc *sc, uint32_t off, void *buf, uint32_t *len) 1726 { 1727 uint32_t addr, info; 1728 uint16_t count, size; 1729 uint32_t total; 1730 1731 /* addr[4] + count[2] + size[2] */ 1732 addr = MEM_READ_4(sc, sc->table2_base + off); 1733 info = MEM_READ_4(sc, sc->table2_base + off + 4); 1734 1735 count = info >> 16; 1736 size = info & 0xffff; 1737 total = count * size; 1738 1739 if (total > *len) { 1740 *len = total; 1741 return EINVAL; 1742 } 1743 1744 *len = total; 1745 ipw_read_mem_1(sc, addr, buf, total); 1746 1747 return 0; 1748 } 1749 1750 static void 1751 ipw_stop_master(struct ipw_softc *sc) 1752 { 1753 int ntries; 1754 1755 /* disable interrupts */ 1756 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1757 1758 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1759 for (ntries = 0; ntries < 50; ntries++) { 1760 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1761 break; 1762 DELAY(10); 1763 } 1764 if (ntries == 50) 1765 aprint_error_dev(sc->sc_dev, "timeout waiting for master\n"); 1766 1767 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1768 IPW_RST_PRINCETON_RESET); 1769 1770 sc->flags &= ~IPW_FLAG_FW_INITED; 1771 } 1772 1773 static int 1774 ipw_reset(struct ipw_softc *sc) 1775 { 1776 int ntries; 1777 1778 ipw_stop_master(sc); 1779 1780 /* move adapter to D0 state */ 1781 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1782 IPW_CTL_INIT); 1783 1784 /* wait for clock stabilization */ 1785 for (ntries = 0; ntries < 1000; ntries++) { 1786 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY) 1787 break; 1788 DELAY(200); 1789 } 1790 if (ntries == 1000) 1791 return EIO; 1792 1793 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1794 IPW_RST_SW_RESET); 1795 1796 DELAY(10); 1797 1798 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1799 IPW_CTL_INIT); 1800 1801 return 0; 1802 } 1803 1804 /* 1805 * Upload the microcode to the device. 1806 */ 1807 static int 1808 ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size) 1809 { 1810 int ntries; 1811 1812 MEM_WRITE_4(sc, 0x3000e0, 0x80000000); 1813 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1814 1815 MEM_WRITE_2(sc, 0x220000, 0x0703); 1816 MEM_WRITE_2(sc, 0x220000, 0x0707); 1817 1818 MEM_WRITE_1(sc, 0x210014, 0x72); 1819 MEM_WRITE_1(sc, 0x210014, 0x72); 1820 1821 MEM_WRITE_1(sc, 0x210000, 0x40); 1822 MEM_WRITE_1(sc, 0x210000, 0x00); 1823 MEM_WRITE_1(sc, 0x210000, 0x40); 1824 1825 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1826 1827 MEM_WRITE_1(sc, 0x210000, 0x00); 1828 MEM_WRITE_1(sc, 0x210000, 0x00); 1829 MEM_WRITE_1(sc, 0x210000, 0x80); 1830 1831 MEM_WRITE_2(sc, 0x220000, 0x0703); 1832 MEM_WRITE_2(sc, 0x220000, 0x0707); 1833 1834 MEM_WRITE_1(sc, 0x210014, 0x72); 1835 MEM_WRITE_1(sc, 0x210014, 0x72); 1836 1837 MEM_WRITE_1(sc, 0x210000, 0x00); 1838 MEM_WRITE_1(sc, 0x210000, 0x80); 1839 1840 for (ntries = 0; ntries < 10; ntries++) { 1841 if (MEM_READ_1(sc, 0x210000) & 1) 1842 break; 1843 DELAY(10); 1844 } 1845 if (ntries == 10) { 1846 aprint_error_dev(sc->sc_dev, "timeout waiting for ucode to initialize\n"); 1847 return EIO; 1848 } 1849 1850 MEM_WRITE_4(sc, 0x3000e0, 0); 1851 1852 return 0; 1853 } 1854 1855 /* set of macros to handle unaligned little endian data in firmware image */ 1856 #define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1857 #define GETLE16(p) ((p)[0] | (p)[1] << 8) 1858 static int 1859 ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size) 1860 { 1861 u_char *p, *end; 1862 uint32_t dst; 1863 uint16_t len; 1864 int error; 1865 1866 p = fw; 1867 end = fw + size; 1868 while (p < end) { 1869 dst = GETLE32(p); p += 4; 1870 len = GETLE16(p); p += 2; 1871 1872 ipw_write_mem_1(sc, dst, p, len); 1873 p += len; 1874 } 1875 1876 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1877 IPW_IO_LED_OFF); 1878 1879 /* enable interrupts */ 1880 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1881 1882 /* kick the firmware */ 1883 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1884 1885 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1886 IPW_CTL_ALLOW_STANDBY); 1887 1888 /* wait at most one second for firmware initialization to complete */ 1889 if ((error = tsleep(sc, 0, "ipwinit", hz)) != 0) { 1890 aprint_error_dev(sc->sc_dev, 1891 "timeout waiting for firmware initialization " 1892 "to complete\n"); 1893 return error; 1894 } 1895 1896 CSR_WRITE_4(sc, IPW_CSR_IO, CSR_READ_4(sc, IPW_CSR_IO) | 1897 IPW_IO_GPIO1_MASK | IPW_IO_GPIO3_MASK); 1898 1899 return 0; 1900 } 1901 1902 /* 1903 * Store firmware into kernel memory so we can download it when we need to, 1904 * e.g when the adapter wakes up from suspend mode. 1905 */ 1906 static int 1907 ipw_cache_firmware(struct ipw_softc *sc) 1908 { 1909 struct ipw_firmware *fw = &sc->fw; 1910 struct ipw_firmware_hdr hdr; 1911 firmware_handle_t fwh; 1912 off_t fwsz, p; 1913 int error; 1914 1915 ipw_free_firmware(sc); 1916 1917 if (ipw_accept_eula == 0) { 1918 aprint_error_dev(sc->sc_dev, 1919 "EULA not accepted; please see the ipw(4) man page.\n"); 1920 return EPERM; 1921 } 1922 1923 if ((error = firmware_open("if_ipw", sc->sc_fwname, &fwh)) != 0) 1924 goto fail0; 1925 1926 fwsz = firmware_get_size(fwh); 1927 1928 if (fwsz < sizeof(hdr)) 1929 goto fail2; 1930 1931 if ((error = firmware_read(fwh, 0, &hdr, sizeof(hdr))) != 0) 1932 goto fail2; 1933 1934 fw->main_size = le32toh(hdr.main_size); 1935 fw->ucode_size = le32toh(hdr.ucode_size); 1936 1937 fw->main = firmware_malloc(fw->main_size); 1938 if (fw->main == NULL) { 1939 error = ENOMEM; 1940 goto fail1; 1941 } 1942 1943 fw->ucode = firmware_malloc(fw->ucode_size); 1944 if (fw->ucode == NULL) { 1945 error = ENOMEM; 1946 goto fail2; 1947 } 1948 1949 p = sizeof(hdr); 1950 if ((error = firmware_read(fwh, p, fw->main, fw->main_size)) != 0) 1951 goto fail3; 1952 1953 p += fw->main_size; 1954 if ((error = firmware_read(fwh, p, fw->ucode, fw->ucode_size)) != 0) 1955 goto fail3; 1956 1957 DPRINTF(("Firmware cached: main %u, ucode %u\n", fw->main_size, 1958 fw->ucode_size)); 1959 1960 sc->flags |= IPW_FLAG_FW_CACHED; 1961 1962 firmware_close(fwh); 1963 1964 return 0; 1965 1966 fail3: firmware_free(fw->ucode, fw->ucode_size); 1967 fail2: firmware_free(fw->main, fw->main_size); 1968 fail1: firmware_close(fwh); 1969 fail0: 1970 return error; 1971 } 1972 1973 static void 1974 ipw_free_firmware(struct ipw_softc *sc) 1975 { 1976 if (!(sc->flags & IPW_FLAG_FW_CACHED)) 1977 return; 1978 1979 firmware_free(sc->fw.main, sc->fw.main_size); 1980 firmware_free(sc->fw.ucode, sc->fw.ucode_size); 1981 1982 sc->flags &= ~IPW_FLAG_FW_CACHED; 1983 } 1984 1985 static int 1986 ipw_config(struct ipw_softc *sc) 1987 { 1988 struct ieee80211com *ic = &sc->sc_ic; 1989 struct ifnet *ifp = &sc->sc_if; 1990 struct ipw_security security; 1991 struct ieee80211_key *k; 1992 struct ipw_wep_key wepkey; 1993 struct ipw_scan_options options; 1994 struct ipw_configuration config; 1995 uint32_t data; 1996 int error, i; 1997 1998 switch (ic->ic_opmode) { 1999 case IEEE80211_M_STA: 2000 case IEEE80211_M_HOSTAP: 2001 data = htole32(IPW_MODE_BSS); 2002 break; 2003 2004 case IEEE80211_M_IBSS: 2005 case IEEE80211_M_AHDEMO: 2006 data = htole32(IPW_MODE_IBSS); 2007 break; 2008 2009 case IEEE80211_M_MONITOR: 2010 data = htole32(IPW_MODE_MONITOR); 2011 break; 2012 } 2013 DPRINTF(("Setting mode to %u\n", le32toh(data))); 2014 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 2015 if (error != 0) 2016 return error; 2017 2018 if (ic->ic_opmode == IEEE80211_M_IBSS || 2019 ic->ic_opmode == IEEE80211_M_MONITOR) { 2020 data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); 2021 DPRINTF(("Setting channel to %u\n", le32toh(data))); 2022 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 2023 if (error != 0) 2024 return error; 2025 } 2026 2027 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2028 DPRINTF(("Enabling adapter\n")); 2029 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 2030 } 2031 2032 DPRINTF(("Setting MAC to %s\n", ether_sprintf(ic->ic_myaddr))); 2033 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 2034 IEEE80211_ADDR_LEN); 2035 if (error != 0) 2036 return error; 2037 2038 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 2039 IPW_CFG_PREAMBLE_AUTO | IPW_CFG_802_1x_ENABLE); 2040 2041 if (ic->ic_opmode == IEEE80211_M_IBSS) 2042 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 2043 if (ifp->if_flags & IFF_PROMISC) 2044 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 2045 config.bss_chan = htole32(0x3fff); /* channels 1-14 */ 2046 config.ibss_chan = htole32(0x7ff); /* channels 1-11 */ 2047 DPRINTF(("Setting adapter configuration 0x%08x\n", config.flags)); 2048 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 2049 if (error != 0) 2050 return error; 2051 2052 data = htole32(0x3); /* 1, 2 */ 2053 DPRINTF(("Setting basic tx rates to 0x%x\n", le32toh(data))); 2054 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 2055 if (error != 0) 2056 return error; 2057 2058 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 2059 DPRINTF(("Setting tx rates to 0x%x\n", le32toh(data))); 2060 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 2061 if (error != 0) 2062 return error; 2063 2064 data = htole32(IPW_POWER_MODE_CAM); 2065 DPRINTF(("Setting power mode to %u\n", le32toh(data))); 2066 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 2067 if (error != 0) 2068 return error; 2069 2070 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2071 data = htole32(32); /* default value */ 2072 DPRINTF(("Setting tx power index to %u\n", le32toh(data))); 2073 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 2074 sizeof data); 2075 if (error != 0) 2076 return error; 2077 } 2078 2079 data = htole32(ic->ic_rtsthreshold); 2080 DPRINTF(("Setting RTS threshold to %u\n", le32toh(data))); 2081 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 2082 if (error != 0) 2083 return error; 2084 2085 data = htole32(ic->ic_fragthreshold); 2086 DPRINTF(("Setting frag threshold to %u\n", le32toh(data))); 2087 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 2088 if (error != 0) 2089 return error; 2090 2091 #ifdef IPW_DEBUG 2092 if (ipw_debug > 0) { 2093 printf("Setting ESSID to "); 2094 ieee80211_print_essid(ic->ic_des_essid, ic->ic_des_esslen); 2095 printf("\n"); 2096 } 2097 #endif 2098 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ic->ic_des_essid, 2099 ic->ic_des_esslen); 2100 if (error != 0) 2101 return error; 2102 2103 /* no mandatory BSSID */ 2104 DPRINTF(("Setting mandatory BSSID to null\n")); 2105 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 2106 if (error != 0) 2107 return error; 2108 2109 if (ic->ic_flags & IEEE80211_F_DESBSSID) { 2110 DPRINTF(("Setting desired BSSID to %s\n", 2111 ether_sprintf(ic->ic_des_bssid))); 2112 error = ipw_cmd(sc, IPW_CMD_SET_DESIRED_BSSID, 2113 ic->ic_des_bssid, IEEE80211_ADDR_LEN); 2114 if (error != 0) 2115 return error; 2116 } 2117 2118 (void)memset(&security, 0, sizeof(security)); 2119 security.authmode = (ic->ic_bss->ni_authmode == IEEE80211_AUTH_SHARED) ? 2120 IPW_AUTH_SHARED : IPW_AUTH_OPEN; 2121 security.ciphers = htole32(IPW_CIPHER_NONE); 2122 DPRINTF(("Setting authmode to %u\n", security.authmode)); 2123 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 2124 sizeof security); 2125 if (error != 0) 2126 return error; 2127 2128 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 2129 k = ic->ic_crypto.cs_nw_keys; 2130 for (i = 0; i < IEEE80211_WEP_NKID; i++, k++) { 2131 if (k->wk_keylen == 0) 2132 continue; 2133 2134 wepkey.idx = i; 2135 wepkey.len = k->wk_keylen; 2136 memset(wepkey.key, 0, sizeof(wepkey.key)); 2137 memcpy(wepkey.key, k->wk_key, k->wk_keylen); 2138 DPRINTF(("Setting wep key index %u len %u\n", 2139 wepkey.idx, wepkey.len)); 2140 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY, &wepkey, 2141 sizeof wepkey); 2142 if (error != 0) 2143 return error; 2144 } 2145 2146 data = htole32(ic->ic_crypto.cs_def_txkey); 2147 DPRINTF(("Setting tx key index to %u\n", le32toh(data))); 2148 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY_INDEX, &data, 2149 sizeof data); 2150 if (error != 0) 2151 return error; 2152 } 2153 2154 data = htole32((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) ? IPW_WEPON : 0); 2155 DPRINTF(("Setting wep flags to 0x%x\n", le32toh(data))); 2156 error = ipw_cmd(sc, IPW_CMD_SET_WEP_FLAGS, &data, sizeof data); 2157 if (error != 0) 2158 return error; 2159 2160 #if 0 2161 struct ipw_wpa_ie ie; 2162 2163 memset(&ie, 0 sizeof(ie)); 2164 ie.len = htole32(sizeof (struct ieee80211_ie_wpa)); 2165 DPRINTF(("Setting wpa ie\n")); 2166 error = ipw_cmd(sc, IPW_CMD_SET_WPA_IE, &ie, sizeof ie); 2167 if (error != 0) 2168 return error; 2169 #endif 2170 2171 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2172 data = htole32(ic->ic_bintval); 2173 DPRINTF(("Setting beacon interval to %u\n", le32toh(data))); 2174 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 2175 sizeof data); 2176 if (error != 0) 2177 return error; 2178 } 2179 2180 options.flags = 0; 2181 options.channels = htole32(0x3fff); /* scan channels 1-14 */ 2182 DPRINTF(("Setting scan options to 0x%x\n", le32toh(options.flags))); 2183 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &options, sizeof options); 2184 if (error != 0) 2185 return error; 2186 2187 /* finally, enable adapter (start scanning for an access point) */ 2188 DPRINTF(("Enabling adapter\n")); 2189 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 2190 } 2191 2192 static int 2193 ipw_init(struct ifnet *ifp) 2194 { 2195 struct ipw_softc *sc = ifp->if_softc; 2196 struct ipw_firmware *fw = &sc->fw; 2197 2198 if (!(sc->flags & IPW_FLAG_FW_CACHED)) { 2199 if (ipw_cache_firmware(sc) != 0) { 2200 aprint_error_dev(sc->sc_dev, 2201 "could not cache the firmware (%s)\n", 2202 sc->sc_fwname); 2203 goto fail; 2204 } 2205 } 2206 2207 ipw_stop(ifp, 0); 2208 2209 if (ipw_reset(sc) != 0) { 2210 aprint_error_dev(sc->sc_dev, "could not reset adapter\n"); 2211 goto fail; 2212 } 2213 2214 if (ipw_load_ucode(sc, fw->ucode, fw->ucode_size) != 0) { 2215 aprint_error_dev(sc->sc_dev, "could not load microcode\n"); 2216 goto fail; 2217 } 2218 2219 ipw_stop_master(sc); 2220 2221 /* 2222 * Setup tx, rx and status rings. 2223 */ 2224 sc->txold = IPW_NTBD - 1; 2225 sc->txcur = 0; 2226 sc->txfree = IPW_NTBD - 2; 2227 sc->rxcur = IPW_NRBD - 1; 2228 2229 CSR_WRITE_4(sc, IPW_CSR_TX_BASE, sc->tbd_map->dm_segs[0].ds_addr); 2230 CSR_WRITE_4(sc, IPW_CSR_TX_SIZE, IPW_NTBD); 2231 CSR_WRITE_4(sc, IPW_CSR_TX_READ, 0); 2232 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 2233 2234 CSR_WRITE_4(sc, IPW_CSR_RX_BASE, sc->rbd_map->dm_segs[0].ds_addr); 2235 CSR_WRITE_4(sc, IPW_CSR_RX_SIZE, IPW_NRBD); 2236 CSR_WRITE_4(sc, IPW_CSR_RX_READ, 0); 2237 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 2238 2239 CSR_WRITE_4(sc, IPW_CSR_STATUS_BASE, sc->status_map->dm_segs[0].ds_addr); 2240 2241 if (ipw_load_firmware(sc, fw->main, fw->main_size) != 0) { 2242 aprint_error_dev(sc->sc_dev, "could not load firmware\n"); 2243 goto fail; 2244 } 2245 2246 sc->flags |= IPW_FLAG_FW_INITED; 2247 2248 /* retrieve information tables base addresses */ 2249 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 2250 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 2251 2252 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 2253 2254 if (ipw_config(sc) != 0) { 2255 aprint_error_dev(sc->sc_dev, "device configuration failed\n"); 2256 goto fail; 2257 } 2258 2259 ifp->if_flags &= ~IFF_OACTIVE; 2260 ifp->if_flags |= IFF_RUNNING; 2261 2262 return 0; 2263 2264 fail: ifp->if_flags &= ~IFF_UP; 2265 ipw_stop(ifp, 0); 2266 2267 return EIO; 2268 } 2269 2270 static void 2271 ipw_stop(struct ifnet *ifp, int disable) 2272 { 2273 struct ipw_softc *sc = ifp->if_softc; 2274 struct ieee80211com *ic = &sc->sc_ic; 2275 int i; 2276 2277 ipw_stop_master(sc); 2278 2279 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 2280 2281 /* 2282 * Release tx buffers. 2283 */ 2284 for (i = 0; i < IPW_NTBD; i++) 2285 ipw_release_sbd(sc, &sc->stbd_list[i]); 2286 2287 sc->sc_tx_timer = 0; 2288 ifp->if_timer = 0; 2289 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2290 2291 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2292 } 2293 2294 static void 2295 ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2296 bus_size_t count) 2297 { 2298 for (; count > 0; offset++, datap++, count--) { 2299 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2300 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 2301 } 2302 } 2303 2304 static void 2305 ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2306 bus_size_t count) 2307 { 2308 for (; count > 0; offset++, datap++, count--) { 2309 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2310 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 2311 } 2312 } 2313 2314 SYSCTL_SETUP(sysctl_hw_ipw_accept_eula_setup, "sysctl hw.ipw.accept_eula") 2315 { 2316 const struct sysctlnode *rnode; 2317 const struct sysctlnode *cnode; 2318 2319 sysctl_createv(NULL, 0, NULL, &rnode, 2320 CTLFLAG_PERMANENT, 2321 CTLTYPE_NODE, "ipw", 2322 NULL, 2323 NULL, 0, 2324 NULL, 0, 2325 CTL_HW, CTL_CREATE, CTL_EOL); 2326 2327 sysctl_createv(NULL, 0, &rnode, &cnode, 2328 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, 2329 CTLTYPE_INT, "accept_eula", 2330 SYSCTL_DESCR("Accept Intel EULA and permit use of ipw(4) firmware"), 2331 NULL, 0, 2332 &ipw_accept_eula, sizeof(ipw_accept_eula), 2333 CTL_CREATE, CTL_EOL); 2334 } 2335
Indexes created Tue Sep 30 06:09:59 GMT 2025