if_ipw.c revision 1.67.2.1
1 /* $NetBSD: if_ipw.c,v 1.67.2.1 2018/05/02 07:20:06 pgoyette Exp $ */ 2 /* FreeBSD: src/sys/dev/ipw/if_ipw.c,v 1.15 2005/11/13 17:17:40 damien Exp */ 3 4 /*- 5 * Copyright (c) 2004, 2005 6 * Damien Bergamini <damien.bergamini (at) free.fr>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: if_ipw.c,v 1.67.2.1 2018/05/02 07:20:06 pgoyette Exp $"); 33 34 /*- 35 * Intel(R) PRO/Wireless 2100 MiniPCI driver 36 * http://www.intel.com/network/connectivity/products/wireless/prowireless_mobile.htm 37 */ 38 39 40 #include <sys/param.h> 41 #include <sys/sockio.h> 42 #include <sys/sysctl.h> 43 #include <sys/mbuf.h> 44 #include <sys/kernel.h> 45 #include <sys/socket.h> 46 #include <sys/systm.h> 47 #include <sys/malloc.h> 48 #include <sys/conf.h> 49 #include <sys/proc.h> 50 51 #include <sys/bus.h> 52 #include <machine/endian.h> 53 #include <sys/intr.h> 54 55 #include <dev/pci/pcireg.h> 56 #include <dev/pci/pcivar.h> 57 #include <dev/pci/pcidevs.h> 58 59 #include <net/bpf.h> 60 #include <net/if.h> 61 #include <net/if_arp.h> 62 #include <net/if_dl.h> 63 #include <net/if_ether.h> 64 #include <net/if_media.h> 65 #include <net/if_types.h> 66 67 #include <net80211/ieee80211_var.h> 68 #include <net80211/ieee80211_radiotap.h> 69 70 #include <netinet/in.h> 71 #include <netinet/in_systm.h> 72 #include <netinet/in_var.h> 73 #include <netinet/ip.h> 74 75 #include <dev/firmload.h> 76 77 #include <dev/pci/if_ipwreg.h> 78 #include <dev/pci/if_ipwvar.h> 79 80 #ifdef IPW_DEBUG 81 #define DPRINTF(x) if (ipw_debug > 0) printf x 82 #define DPRINTFN(n, x) if (ipw_debug >= (n)) printf x 83 int ipw_debug = 0; 84 #else 85 #define DPRINTF(x) 86 #define DPRINTFN(n, x) 87 #endif 88 89 /* Permit loading the Intel firmware */ 90 static int ipw_accept_eula; 91 92 static int ipw_dma_alloc(struct ipw_softc *); 93 static void ipw_release(struct ipw_softc *); 94 static int ipw_match(device_t, cfdata_t, void *); 95 static void ipw_attach(device_t, device_t, void *); 96 static int ipw_detach(device_t, int); 97 98 static int ipw_media_change(struct ifnet *); 99 static void ipw_media_status(struct ifnet *, struct ifmediareq *); 100 static int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 101 static uint16_t ipw_read_prom_word(struct ipw_softc *, uint8_t); 102 static void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 103 static void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 104 static void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 105 struct ipw_soft_bd *, struct ipw_soft_buf *); 106 static void ipw_rx_intr(struct ipw_softc *); 107 static void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 108 static void ipw_tx_intr(struct ipw_softc *); 109 static int ipw_intr(void *); 110 static void ipw_softintr(void *); 111 static int ipw_cmd(struct ipw_softc *, uint32_t, void *, uint32_t); 112 static int ipw_tx_start(struct ifnet *, struct mbuf *, 113 struct ieee80211_node *); 114 static void ipw_start(struct ifnet *); 115 static void ipw_watchdog(struct ifnet *); 116 static int ipw_ioctl(struct ifnet *, u_long, void *); 117 static int ipw_get_table1(struct ipw_softc *, uint32_t *); 118 static int ipw_get_radio(struct ipw_softc *, int *); 119 static void ipw_stop_master(struct ipw_softc *); 120 static int ipw_reset(struct ipw_softc *); 121 static int ipw_load_ucode(struct ipw_softc *, u_char *, int); 122 static int ipw_load_firmware(struct ipw_softc *, u_char *, int); 123 static int ipw_cache_firmware(struct ipw_softc *); 124 static void ipw_free_firmware(struct ipw_softc *); 125 static int ipw_config(struct ipw_softc *); 126 static int ipw_init(struct ifnet *); 127 static void ipw_stop(struct ifnet *, int); 128 static uint32_t ipw_read_table1(struct ipw_softc *, uint32_t); 129 static void ipw_write_table1(struct ipw_softc *, uint32_t, uint32_t); 130 static int ipw_read_table2(struct ipw_softc *, uint32_t, void *, uint32_t *); 131 static void ipw_read_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 132 bus_size_t); 133 static void ipw_write_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 134 bus_size_t); 135 136 static inline uint8_t 137 MEM_READ_1(struct ipw_softc *sc, uint32_t addr) 138 { 139 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 140 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); 141 } 142 143 static inline uint32_t 144 MEM_READ_4(struct ipw_softc *sc, uint32_t addr) 145 { 146 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 147 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); 148 } 149 150 CFATTACH_DECL_NEW(ipw, sizeof (struct ipw_softc), ipw_match, ipw_attach, 151 ipw_detach, NULL); 152 153 static int 154 ipw_match(device_t parent, cfdata_t match, void *aux) 155 { 156 struct pci_attach_args *pa = aux; 157 158 if (PCI_VENDOR (pa->pa_id) == PCI_VENDOR_INTEL && 159 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_PRO_WL_2100) 160 return 1; 161 162 return 0; 163 } 164 165 /* Base Address Register */ 166 #define IPW_PCI_BAR0 0x10 167 168 static void 169 ipw_attach(device_t parent, device_t self, void *aux) 170 { 171 struct ipw_softc *sc = device_private(self); 172 struct ieee80211com *ic = &sc->sc_ic; 173 struct ifnet *ifp = &sc->sc_if; 174 struct pci_attach_args *pa = aux; 175 const char *intrstr; 176 bus_space_tag_t memt; 177 bus_space_handle_t memh; 178 bus_addr_t base; 179 pci_intr_handle_t ih; 180 uint32_t data; 181 uint16_t val; 182 int i, error; 183 char intrbuf[PCI_INTRSTR_LEN]; 184 185 sc->sc_dev = self; 186 sc->sc_pct = pa->pa_pc; 187 sc->sc_pcitag = pa->pa_tag; 188 189 pci_aprint_devinfo(pa, NULL); 190 191 /* enable bus-mastering */ 192 data = pci_conf_read(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG); 193 data |= PCI_COMMAND_MASTER_ENABLE; 194 pci_conf_write(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG, data); 195 196 /* map the register window */ 197 error = pci_mapreg_map(pa, IPW_PCI_BAR0, PCI_MAPREG_TYPE_MEM | 198 PCI_MAPREG_MEM_TYPE_32BIT, 0, &memt, &memh, &base, &sc->sc_sz); 199 if (error != 0) { 200 aprint_error_dev(sc->sc_dev, "could not map memory space\n"); 201 return; 202 } 203 204 sc->sc_st = memt; 205 sc->sc_sh = memh; 206 sc->sc_dmat = pa->pa_dmat; 207 sc->sc_fwname = "ipw2100-1.2.fw"; 208 209 /* disable interrupts */ 210 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 211 212 if (pci_intr_map(pa, &ih) != 0) { 213 aprint_error_dev(sc->sc_dev, "could not map interrupt\n"); 214 goto fail; 215 } 216 217 sc->sc_soft_ih = softint_establish(SOFTINT_NET, ipw_softintr, sc); 218 if (sc->sc_soft_ih == NULL) { 219 aprint_error_dev(sc->sc_dev, "could not establish softint\n"); 220 goto fail; 221 } 222 223 intrstr = pci_intr_string(sc->sc_pct, ih, intrbuf, sizeof(intrbuf)); 224 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, ipw_intr, sc); 225 if (sc->sc_ih == NULL) { 226 aprint_error_dev(sc->sc_dev, "could not establish interrupt"); 227 if (intrstr != NULL) 228 aprint_error(" at %s", intrstr); 229 aprint_error("\n"); 230 goto fail; 231 } 232 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 233 234 if (ipw_reset(sc) != 0) { 235 aprint_error_dev(sc->sc_dev, "could not reset adapter\n"); 236 goto fail; 237 } 238 239 if (ipw_dma_alloc(sc) != 0) { 240 aprint_error_dev(sc->sc_dev, "could not allocate DMA resources\n"); 241 goto fail; 242 } 243 244 ifp->if_softc = sc; 245 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 246 ifp->if_init = ipw_init; 247 ifp->if_stop = ipw_stop; 248 ifp->if_ioctl = ipw_ioctl; 249 ifp->if_start = ipw_start; 250 ifp->if_watchdog = ipw_watchdog; 251 IFQ_SET_READY(&ifp->if_snd); 252 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 253 254 ic->ic_ifp = ifp; 255 ic->ic_phytype = IEEE80211_T_DS; 256 ic->ic_opmode = IEEE80211_M_STA; 257 ic->ic_state = IEEE80211_S_INIT; 258 259 /* set device capabilities */ 260 ic->ic_caps = 261 IEEE80211_C_SHPREAMBLE /* short preamble supported */ 262 | IEEE80211_C_TXPMGT /* tx power management */ 263 | IEEE80211_C_IBSS /* ibss mode */ 264 | IEEE80211_C_MONITOR /* monitor mode */ 265 ; 266 267 /* read MAC address from EEPROM */ 268 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0); 269 ic->ic_myaddr[0] = val >> 8; 270 ic->ic_myaddr[1] = val & 0xff; 271 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 1); 272 ic->ic_myaddr[2] = val >> 8; 273 ic->ic_myaddr[3] = val & 0xff; 274 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 2); 275 ic->ic_myaddr[4] = val >> 8; 276 ic->ic_myaddr[5] = val & 0xff; 277 278 /* set supported .11b rates */ 279 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 280 281 /* set supported .11b channels (read from EEPROM) */ 282 if ((val = ipw_read_prom_word(sc, IPW_EEPROM_CHANNEL_LIST)) == 0) 283 val = 0x7ff; /* default to channels 1-11 */ 284 val <<= 1; 285 for (i = 1; i < 16; i++) { 286 if (val & (1 << i)) { 287 ic->ic_channels[i].ic_freq = 288 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 289 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 290 } 291 } 292 293 /* check support for radio transmitter switch in EEPROM */ 294 if (!(ipw_read_prom_word(sc, IPW_EEPROM_RADIO) & 8)) 295 sc->flags |= IPW_FLAG_HAS_RADIO_SWITCH; 296 297 aprint_normal_dev(sc->sc_dev, "802.11 address %s\n", 298 ether_sprintf(ic->ic_myaddr)); 299 300 error = if_initialize(ifp); 301 if (error != 0) { 302 ifp->if_softc = NULL; /* For ipw_detach(). */ 303 aprint_error_dev(sc->sc_dev, "if_initialize failed(%d)\n", 304 error); 305 goto fail; 306 } 307 ieee80211_ifattach(ic); 308 /* Use common softint-based if_input */ 309 ifp->if_percpuq = if_percpuq_create(ifp); 310 if_register(ifp); 311 312 /* override state transition machine */ 313 sc->sc_newstate = ic->ic_newstate; 314 ic->ic_newstate = ipw_newstate; 315 316 ieee80211_media_init(ic, ipw_media_change, ipw_media_status); 317 318 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 319 sizeof(struct ieee80211_frame) + 64, &sc->sc_drvbpf); 320 321 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 322 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 323 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 324 325 sc->sc_txtap_len = sizeof sc->sc_txtapu; 326 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 327 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 328 329 /* 330 * Add a few sysctl knobs. 331 * XXX: Not yet 332 */ 333 sc->dwelltime = 100; 334 335 if (pmf_device_register(self, NULL, NULL)) 336 pmf_class_network_register(self, ifp); 337 else 338 aprint_error_dev(self, "couldn't establish power handler\n"); 339 340 ieee80211_announce(ic); 341 342 return; 343 344 fail: ipw_detach(self, 0); 345 } 346 347 static int 348 ipw_detach(device_t self, int flags) 349 { 350 struct ipw_softc *sc = device_private(self); 351 struct ifnet *ifp = &sc->sc_if; 352 353 if (ifp->if_softc) { 354 ipw_stop(ifp, 1); 355 ipw_free_firmware(sc); 356 357 bpf_detach(ifp); 358 ieee80211_ifdetach(&sc->sc_ic); 359 if_detach(ifp); 360 361 ipw_release(sc); 362 } 363 364 if (sc->sc_ih != NULL) { 365 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 366 sc->sc_ih = NULL; 367 } 368 369 if (sc->sc_soft_ih != NULL) { 370 softint_disestablish(sc->sc_soft_ih); 371 sc->sc_soft_ih = NULL; 372 } 373 374 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 375 376 return 0; 377 } 378 379 static int 380 ipw_dma_alloc(struct ipw_softc *sc) 381 { 382 struct ipw_soft_bd *sbd; 383 struct ipw_soft_hdr *shdr; 384 struct ipw_soft_buf *sbuf; 385 int error, i, nsegs; 386 387 /* 388 * Allocate and map tx ring. 389 */ 390 error = bus_dmamap_create(sc->sc_dmat, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, 391 BUS_DMA_NOWAIT, &sc->tbd_map); 392 if (error != 0) { 393 aprint_error_dev(sc->sc_dev, "could not create tbd dma map\n"); 394 goto fail; 395 } 396 397 error = bus_dmamem_alloc(sc->sc_dmat, IPW_TBD_SZ, PAGE_SIZE, 0, 398 &sc->tbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 399 if (error != 0) { 400 aprint_error_dev(sc->sc_dev, "could not allocate tbd dma memory\n"); 401 goto fail; 402 } 403 404 error = bus_dmamem_map(sc->sc_dmat, &sc->tbd_seg, nsegs, IPW_TBD_SZ, 405 (void **)&sc->tbd_list, BUS_DMA_NOWAIT); 406 if (error != 0) { 407 aprint_error_dev(sc->sc_dev, "could not map tbd dma memory\n"); 408 goto fail; 409 } 410 411 error = bus_dmamap_load(sc->sc_dmat, sc->tbd_map, sc->tbd_list, 412 IPW_TBD_SZ, NULL, BUS_DMA_NOWAIT); 413 if (error != 0) { 414 aprint_error_dev(sc->sc_dev, "could not load tbd dma memory\n"); 415 goto fail; 416 } 417 418 (void)memset(sc->tbd_list, 0, IPW_TBD_SZ); 419 420 /* 421 * Allocate and map rx ring. 422 */ 423 error = bus_dmamap_create(sc->sc_dmat, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, 424 BUS_DMA_NOWAIT, &sc->rbd_map); 425 if (error != 0) { 426 aprint_error_dev(sc->sc_dev, "could not create rbd dma map\n"); 427 goto fail; 428 } 429 430 error = bus_dmamem_alloc(sc->sc_dmat, IPW_RBD_SZ, PAGE_SIZE, 0, 431 &sc->rbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 432 if (error != 0) { 433 aprint_error_dev(sc->sc_dev, "could not allocate rbd dma memory\n"); 434 goto fail; 435 } 436 437 error = bus_dmamem_map(sc->sc_dmat, &sc->rbd_seg, nsegs, IPW_RBD_SZ, 438 (void **)&sc->rbd_list, BUS_DMA_NOWAIT); 439 if (error != 0) { 440 aprint_error_dev(sc->sc_dev, "could not map rbd dma memory\n"); 441 goto fail; 442 } 443 444 error = bus_dmamap_load(sc->sc_dmat, sc->rbd_map, sc->rbd_list, 445 IPW_RBD_SZ, NULL, BUS_DMA_NOWAIT); 446 if (error != 0) { 447 aprint_error_dev(sc->sc_dev, "could not load rbd dma memory\n"); 448 goto fail; 449 } 450 451 (void)memset(sc->rbd_list, 0, IPW_RBD_SZ); 452 453 /* 454 * Allocate and map status ring. 455 */ 456 error = bus_dmamap_create(sc->sc_dmat, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 457 0, BUS_DMA_NOWAIT, &sc->status_map); 458 if (error != 0) { 459 aprint_error_dev(sc->sc_dev, "could not create status dma map\n"); 460 goto fail; 461 } 462 463 error = bus_dmamem_alloc(sc->sc_dmat, IPW_STATUS_SZ, PAGE_SIZE, 0, 464 &sc->status_seg, 1, &nsegs, BUS_DMA_NOWAIT); 465 if (error != 0) { 466 aprint_error_dev(sc->sc_dev, "could not allocate status dma memory\n"); 467 goto fail; 468 } 469 470 error = bus_dmamem_map(sc->sc_dmat, &sc->status_seg, nsegs, 471 IPW_STATUS_SZ, (void **)&sc->status_list, BUS_DMA_NOWAIT); 472 if (error != 0) { 473 aprint_error_dev(sc->sc_dev, "could not map status dma memory\n"); 474 goto fail; 475 } 476 477 error = bus_dmamap_load(sc->sc_dmat, sc->status_map, sc->status_list, 478 IPW_STATUS_SZ, NULL, BUS_DMA_NOWAIT); 479 if (error != 0) { 480 aprint_error_dev(sc->sc_dev, "could not load status dma memory\n"); 481 goto fail; 482 } 483 484 (void)memset(sc->status_list, 0, IPW_STATUS_SZ); 485 486 /* 487 * Allocate command DMA map. 488 */ 489 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_cmd), 490 1, sizeof (struct ipw_cmd), 0, BUS_DMA_NOWAIT, &sc->cmd_map); 491 if (error != 0) { 492 aprint_error_dev(sc->sc_dev, "could not create cmd dma map\n"); 493 goto fail; 494 } 495 496 error = bus_dmamem_alloc(sc->sc_dmat, sizeof (struct ipw_cmd), 497 PAGE_SIZE, 0, &sc->cmd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 498 if (error != 0) { 499 aprint_error_dev(sc->sc_dev, "could not allocate cmd dma memory\n"); 500 goto fail; 501 } 502 503 error = bus_dmamem_map(sc->sc_dmat, &sc->cmd_seg, nsegs, 504 sizeof (struct ipw_cmd), (void **)&sc->cmd, BUS_DMA_NOWAIT); 505 if (error != 0) { 506 aprint_error_dev(sc->sc_dev, "could not map cmd dma memory\n"); 507 goto fail; 508 } 509 510 error = bus_dmamap_load(sc->sc_dmat, sc->cmd_map, &sc->cmd, 511 sizeof (struct ipw_cmd), NULL, BUS_DMA_NOWAIT); 512 if (error != 0) { 513 aprint_error_dev(sc->sc_dev, "could not map cmd dma memory\n"); 514 return error; 515 } 516 517 /* 518 * Allocate and map hdr list. 519 */ 520 521 error = bus_dmamap_create(sc->sc_dmat, 522 IPW_NDATA * sizeof(struct ipw_hdr), 1, 523 sizeof(struct ipw_hdr), 0, BUS_DMA_NOWAIT, 524 &sc->hdr_map); 525 if (error != 0) { 526 aprint_error_dev(sc->sc_dev, "could not create hdr dma map\n"); 527 goto fail; 528 } 529 530 error = bus_dmamem_alloc(sc->sc_dmat, 531 IPW_NDATA * sizeof(struct ipw_hdr), PAGE_SIZE, 0, &sc->hdr_seg, 532 1, &nsegs, BUS_DMA_NOWAIT); 533 if (error != 0) { 534 aprint_error_dev(sc->sc_dev, "could not allocate hdr memory\n"); 535 goto fail; 536 } 537 538 error = bus_dmamem_map(sc->sc_dmat, &sc->hdr_seg, nsegs, 539 IPW_NDATA * sizeof(struct ipw_hdr), (void **)&sc->hdr_list, 540 BUS_DMA_NOWAIT); 541 if (error != 0) { 542 aprint_error_dev(sc->sc_dev, "could not map hdr memory\n"); 543 goto fail; 544 } 545 546 error = bus_dmamap_load(sc->sc_dmat, sc->hdr_map, sc->hdr_list, 547 IPW_NDATA * sizeof(struct ipw_hdr), NULL, BUS_DMA_NOWAIT); 548 if (error != 0) { 549 aprint_error_dev(sc->sc_dev, "could not load hdr memory\n"); 550 goto fail; 551 } 552 553 (void)memset(sc->hdr_list, 0, IPW_HDR_SZ); 554 555 /* 556 * Create DMA hdrs tailq. 557 */ 558 TAILQ_INIT(&sc->sc_free_shdr); 559 for (i = 0; i < IPW_NDATA; i++) { 560 shdr = &sc->shdr_list[i]; 561 shdr->hdr = sc->hdr_list + i; 562 shdr->offset = sizeof(struct ipw_hdr) * i; 563 shdr->addr = sc->hdr_map->dm_segs[0].ds_addr + shdr->offset; 564 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 565 } 566 567 /* 568 * Allocate tx buffers DMA maps. 569 */ 570 TAILQ_INIT(&sc->sc_free_sbuf); 571 for (i = 0; i < IPW_NDATA; i++) { 572 sbuf = &sc->tx_sbuf_list[i]; 573 574 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 575 IPW_MAX_NSEG, MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 576 if (error != 0) { 577 aprint_error_dev(sc->sc_dev, "could not create txbuf dma map\n"); 578 goto fail; 579 } 580 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 581 } 582 583 /* 584 * Initialize tx ring. 585 */ 586 for (i = 0; i < IPW_NTBD; i++) { 587 sbd = &sc->stbd_list[i]; 588 sbd->bd = &sc->tbd_list[i]; 589 sbd->type = IPW_SBD_TYPE_NOASSOC; 590 } 591 592 /* 593 * Pre-allocate rx buffers and DMA maps 594 */ 595 for (i = 0; i < IPW_NRBD; i++) { 596 sbd = &sc->srbd_list[i]; 597 sbuf = &sc->rx_sbuf_list[i]; 598 sbd->bd = &sc->rbd_list[i]; 599 600 MGETHDR(sbuf->m, M_DONTWAIT, MT_DATA); 601 if (sbuf->m == NULL) { 602 aprint_error_dev(sc->sc_dev, "could not allocate rx mbuf\n"); 603 error = ENOMEM; 604 goto fail; 605 } 606 607 MCLGET(sbuf->m, M_DONTWAIT); 608 if (!(sbuf->m->m_flags & M_EXT)) { 609 m_freem(sbuf->m); 610 sbuf->m = NULL; 611 aprint_error_dev(sc->sc_dev, "could not allocate rx mbuf cluster\n"); 612 error = ENOMEM; 613 goto fail; 614 } 615 616 sbuf->m->m_pkthdr.len = sbuf->m->m_len = sbuf->m->m_ext.ext_size; 617 618 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 619 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sbuf->map); 620 if (error != 0) { 621 aprint_error_dev(sc->sc_dev, "could not create rxbuf dma map\n"); 622 m_freem(sbuf->m); 623 sbuf->m = NULL; 624 goto fail; 625 } 626 627 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, 628 sbuf->m, BUS_DMA_READ | BUS_DMA_NOWAIT); 629 if (error != 0) { 630 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 631 sbuf->map = NULL; 632 m_freem(sbuf->m); 633 sbuf->m = NULL; 634 aprint_error_dev(sc->sc_dev, "could not map rxbuf dma memory\n"); 635 goto fail; 636 } 637 638 sbd->type = IPW_SBD_TYPE_DATA; 639 sbd->priv = sbuf; 640 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 641 sbd->bd->len = htole32(MCLBYTES); 642 643 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, 644 sbuf->map->dm_mapsize, BUS_DMASYNC_PREREAD); 645 646 } 647 648 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 0, IPW_RBD_SZ, 649 BUS_DMASYNC_PREREAD); 650 651 return 0; 652 653 fail: ipw_release(sc); 654 return error; 655 } 656 657 static void 658 ipw_release(struct ipw_softc *sc) 659 { 660 struct ipw_soft_buf *sbuf; 661 int i; 662 663 if (sc->tbd_map != NULL) { 664 if (sc->tbd_list != NULL) { 665 bus_dmamap_unload(sc->sc_dmat, sc->tbd_map); 666 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->tbd_list, 667 IPW_TBD_SZ); 668 bus_dmamem_free(sc->sc_dmat, &sc->tbd_seg, 1); 669 } 670 bus_dmamap_destroy(sc->sc_dmat, sc->tbd_map); 671 } 672 673 if (sc->rbd_map != NULL) { 674 if (sc->rbd_list != NULL) { 675 bus_dmamap_unload(sc->sc_dmat, sc->rbd_map); 676 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->rbd_list, 677 IPW_RBD_SZ); 678 bus_dmamem_free(sc->sc_dmat, &sc->rbd_seg, 1); 679 } 680 bus_dmamap_destroy(sc->sc_dmat, sc->rbd_map); 681 } 682 683 if (sc->status_map != NULL) { 684 if (sc->status_list != NULL) { 685 bus_dmamap_unload(sc->sc_dmat, sc->status_map); 686 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->status_list, 687 IPW_RBD_SZ); 688 bus_dmamem_free(sc->sc_dmat, &sc->status_seg, 1); 689 } 690 bus_dmamap_destroy(sc->sc_dmat, sc->status_map); 691 } 692 693 for (i = 0; i < IPW_NTBD; i++) 694 ipw_release_sbd(sc, &sc->stbd_list[i]); 695 696 if (sc->cmd_map != NULL) 697 bus_dmamap_destroy(sc->sc_dmat, sc->cmd_map); 698 699 if (sc->hdr_list != NULL) { 700 bus_dmamap_unload(sc->sc_dmat, sc->hdr_map); 701 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->hdr_list, 702 IPW_NDATA * sizeof(struct ipw_hdr)); 703 } 704 if (sc->hdr_map != NULL) { 705 bus_dmamem_free(sc->sc_dmat, &sc->hdr_seg, 1); 706 bus_dmamap_destroy(sc->sc_dmat, sc->hdr_map); 707 } 708 709 for (i = 0; i < IPW_NDATA; i++) 710 bus_dmamap_destroy(sc->sc_dmat, sc->tx_sbuf_list[i].map); 711 712 for (i = 0; i < IPW_NRBD; i++) { 713 sbuf = &sc->rx_sbuf_list[i]; 714 if (sbuf->map != NULL) { 715 if (sbuf->m != NULL) { 716 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 717 m_freem(sbuf->m); 718 } 719 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 720 } 721 } 722 723 } 724 725 static int 726 ipw_media_change(struct ifnet *ifp) 727 { 728 int error; 729 730 error = ieee80211_media_change(ifp); 731 if (error != ENETRESET) 732 return error; 733 734 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 735 ipw_init(ifp); 736 737 return 0; 738 } 739 740 /* 741 * The firmware automatically adapts the transmit speed. We report the current 742 * transmit speed here. 743 */ 744 static void 745 ipw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 746 { 747 #define N(a) (sizeof (a) / sizeof (a[0])) 748 struct ipw_softc *sc = ifp->if_softc; 749 struct ieee80211com *ic = &sc->sc_ic; 750 static const struct { 751 uint32_t val; 752 int rate; 753 } rates[] = { 754 { IPW_RATE_DS1, 2 }, 755 { IPW_RATE_DS2, 4 }, 756 { IPW_RATE_DS5, 11 }, 757 { IPW_RATE_DS11, 22 }, 758 }; 759 uint32_t val; 760 int rate, i; 761 762 imr->ifm_status = IFM_AVALID; 763 imr->ifm_active = IFM_IEEE80211; 764 if (ic->ic_state == IEEE80211_S_RUN) 765 imr->ifm_status |= IFM_ACTIVE; 766 767 /* read current transmission rate from adapter */ 768 val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE) & 0xf; 769 770 /* convert ipw rate to 802.11 rate */ 771 for (i = 0; i < N(rates) && rates[i].val != val; i++); 772 rate = (i < N(rates)) ? rates[i].rate : 0; 773 774 imr->ifm_active |= IFM_IEEE80211_11B; 775 imr->ifm_active |= ieee80211_rate2media(ic, rate, IEEE80211_MODE_11B); 776 switch (ic->ic_opmode) { 777 case IEEE80211_M_STA: 778 break; 779 780 case IEEE80211_M_IBSS: 781 imr->ifm_active |= IFM_IEEE80211_ADHOC; 782 break; 783 784 case IEEE80211_M_MONITOR: 785 imr->ifm_active |= IFM_IEEE80211_MONITOR; 786 break; 787 788 case IEEE80211_M_AHDEMO: 789 case IEEE80211_M_HOSTAP: 790 /* should not get there */ 791 break; 792 } 793 #undef N 794 } 795 796 static int 797 ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, 798 int arg) 799 { 800 struct ifnet *ifp = ic->ic_ifp; 801 struct ipw_softc *sc = ifp->if_softc; 802 struct ieee80211_node *ni; 803 uint8_t macaddr[IEEE80211_ADDR_LEN]; 804 uint32_t len; 805 struct ipw_rx_radiotap_header *wr = &sc->sc_rxtap; 806 struct ipw_tx_radiotap_header *wt = &sc->sc_txtap; 807 808 switch (nstate) { 809 case IEEE80211_S_INIT: 810 break; 811 default: 812 KASSERT(ic->ic_curchan != IEEE80211_CHAN_ANYC); 813 KASSERT(ic->ic_curchan != NULL); 814 wt->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 815 wt->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 816 wr->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 817 wr->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 818 break; 819 } 820 821 switch (nstate) { 822 case IEEE80211_S_RUN: 823 DELAY(200); /* firmware needs a short delay here */ 824 825 len = IEEE80211_ADDR_LEN; 826 ipw_read_table2(sc, IPW_INFO_CURRENT_BSSID, macaddr, &len); 827 828 ni = ieee80211_find_node(&ic->ic_scan, macaddr); 829 if (ni == NULL) 830 break; 831 832 ieee80211_ref_node(ni); 833 ieee80211_sta_join(ic, ni); 834 ieee80211_node_authorize(ni); 835 836 if (ic->ic_opmode == IEEE80211_M_STA) 837 ieee80211_notify_node_join(ic, ni, 1); 838 break; 839 840 case IEEE80211_S_INIT: 841 case IEEE80211_S_SCAN: 842 case IEEE80211_S_AUTH: 843 case IEEE80211_S_ASSOC: 844 break; 845 } 846 847 ic->ic_state = nstate; 848 return 0; 849 } 850 851 /* 852 * Read 16 bits at address 'addr' from the serial EEPROM. 853 */ 854 static uint16_t 855 ipw_read_prom_word(struct ipw_softc *sc, uint8_t addr) 856 { 857 uint32_t tmp; 858 uint16_t val; 859 int n; 860 861 /* clock C once before the first command */ 862 IPW_EEPROM_CTL(sc, 0); 863 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 864 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 865 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 866 867 /* write start bit (1) */ 868 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 869 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 870 871 /* write READ opcode (10) */ 872 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 873 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 874 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 875 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 876 877 /* write address A7-A0 */ 878 for (n = 7; n >= 0; n--) { 879 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 880 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D)); 881 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 882 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D) | IPW_EEPROM_C); 883 } 884 885 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 886 887 /* read data Q15-Q0 */ 888 val = 0; 889 for (n = 15; n >= 0; n--) { 890 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 891 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 892 tmp = MEM_READ_4(sc, IPW_MEM_EEPROM_CTL); 893 val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n; 894 } 895 896 IPW_EEPROM_CTL(sc, 0); 897 898 /* clear Chip Select and clock C */ 899 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 900 IPW_EEPROM_CTL(sc, 0); 901 IPW_EEPROM_CTL(sc, IPW_EEPROM_C); 902 903 return le16toh(val); 904 } 905 906 static void 907 ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 908 { 909 910 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof (struct ipw_cmd), 911 BUS_DMASYNC_POSTREAD); 912 913 #ifdef IPW_DEBUG 914 struct ipw_cmd *cmd = mtod(sbuf->m, struct ipw_cmd *); 915 916 DPRINTFN(2, ("cmd ack'ed (%u, %u, %u, %u, %u)\n", le32toh(cmd->type), 917 le32toh(cmd->subtype), le32toh(cmd->seq), le32toh(cmd->len), 918 le32toh(cmd->status))); 919 #endif 920 921 wakeup(&sc->cmd); 922 } 923 924 static void 925 ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 926 { 927 struct ieee80211com *ic = &sc->sc_ic; 928 struct ifnet *ifp = sc->sc_ic.ic_ifp; 929 uint32_t state; 930 int s; 931 932 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof state, 933 BUS_DMASYNC_POSTREAD); 934 935 state = le32toh(*mtod(sbuf->m, uint32_t *)); 936 937 DPRINTFN(2, ("entering state %u\n", state)); 938 939 s = splnet(); 940 941 switch (state) { 942 case IPW_STATE_ASSOCIATED: 943 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 944 break; 945 946 case IPW_STATE_SCANNING: 947 /* don't leave run state on background scan */ 948 if (ic->ic_state != IEEE80211_S_RUN) 949 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 950 951 ic->ic_flags |= IEEE80211_F_SCAN; 952 break; 953 954 case IPW_STATE_SCAN_COMPLETE: 955 ieee80211_notify_scan_done(ic); 956 ic->ic_flags &= ~IEEE80211_F_SCAN; 957 break; 958 959 case IPW_STATE_ASSOCIATION_LOST: 960 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 961 break; 962 963 case IPW_STATE_RADIO_DISABLED: 964 ic->ic_ifp->if_flags &= ~IFF_UP; 965 ipw_stop(ifp, 1); 966 break; 967 } 968 969 splx(s); 970 } 971 972 /* 973 * XXX: Hack to set the current channel to the value advertised in beacons or 974 * probe responses. Only used during AP detection. 975 */ 976 static void 977 ipw_fix_channel(struct ieee80211com *ic, struct mbuf *m) 978 { 979 struct ieee80211_frame *wh; 980 uint8_t subtype; 981 uint8_t *frm, *efrm; 982 983 wh = mtod(m, struct ieee80211_frame *); 984 985 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_MGT) 986 return; 987 988 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 989 990 if (subtype != IEEE80211_FC0_SUBTYPE_BEACON && 991 subtype != IEEE80211_FC0_SUBTYPE_PROBE_RESP) 992 return; 993 994 frm = (uint8_t *)(wh + 1); 995 efrm = mtod(m, uint8_t *) + m->m_len; 996 997 frm += 12; /* skip tstamp, bintval and capinfo fields */ 998 while (frm + 2 < efrm) { 999 if (*frm == IEEE80211_ELEMID_DSPARMS) { 1000 #if IEEE80211_CHAN_MAX < 255 1001 if (frm[2] <= IEEE80211_CHAN_MAX) 1002 #endif 1003 ic->ic_curchan = &ic->ic_channels[frm[2]]; 1004 } 1005 1006 frm += frm[1] + 2; 1007 } 1008 } 1009 1010 static void 1011 ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 1012 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 1013 { 1014 struct ieee80211com *ic = &sc->sc_ic; 1015 struct ifnet *ifp = &sc->sc_if; 1016 struct mbuf *mnew, *m; 1017 struct ieee80211_frame *wh; 1018 struct ieee80211_node *ni; 1019 int error, s; 1020 1021 DPRINTFN(5, ("received frame len=%u, rssi=%u\n", le32toh(status->len), 1022 status->rssi)); 1023 1024 if (le32toh(status->len) < sizeof (struct ieee80211_frame_min) || 1025 le32toh(status->len) > MCLBYTES) 1026 return; 1027 1028 /* 1029 * Try to allocate a new mbuf for this ring element and load it before 1030 * processing the current mbuf. If the ring element cannot be loaded, 1031 * drop the received packet and reuse the old mbuf. In the unlikely 1032 * case that the old mbuf can't be reloaded either, explicitly panic. 1033 */ 1034 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1035 if (mnew == NULL) { 1036 aprint_error_dev(sc->sc_dev, "could not allocate rx mbuf\n"); 1037 ifp->if_ierrors++; 1038 return; 1039 } 1040 1041 MCLGET(mnew, M_DONTWAIT); 1042 if (!(mnew->m_flags & M_EXT)) { 1043 aprint_error_dev(sc->sc_dev, "could not allocate rx mbuf cluster\n"); 1044 m_freem(mnew); 1045 ifp->if_ierrors++; 1046 return; 1047 } 1048 1049 mnew->m_pkthdr.len = mnew->m_len = mnew->m_ext.ext_size; 1050 1051 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, le32toh(status->len), 1052 BUS_DMASYNC_POSTREAD); 1053 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1054 1055 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, mnew, 1056 BUS_DMA_READ | BUS_DMA_NOWAIT); 1057 if (error != 0) { 1058 aprint_error_dev(sc->sc_dev, "could not load rx buf DMA map\n"); 1059 m_freem(mnew); 1060 1061 /* try to reload the old mbuf */ 1062 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, 1063 sbuf->m, BUS_DMA_READ | BUS_DMA_NOWAIT); 1064 if (error != 0) { 1065 /* very unlikely that it will fail... */ 1066 panic("%s: unable to remap rx buf", 1067 device_xname(sc->sc_dev)); 1068 } 1069 ifp->if_ierrors++; 1070 return; 1071 } 1072 1073 /* 1074 * New mbuf successfully loaded, update Rx ring and continue 1075 * processing. 1076 */ 1077 m = sbuf->m; 1078 sbuf->m = mnew; 1079 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 1080 1081 /* finalize mbuf */ 1082 m_set_rcvif(m, ifp); 1083 m->m_pkthdr.len = m->m_len = le32toh(status->len); 1084 1085 s = splnet(); 1086 1087 if (sc->sc_drvbpf != NULL) { 1088 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 1089 1090 tap->wr_antsignal = status->rssi; 1091 1092 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 1093 } 1094 1095 if (ic->ic_state == IEEE80211_S_SCAN) 1096 ipw_fix_channel(ic, m); 1097 1098 wh = mtod(m, struct ieee80211_frame *); 1099 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 1100 1101 /* send the frame to the 802.11 layer */ 1102 ieee80211_input(ic, m, ni, status->rssi, 0); 1103 1104 /* node is no longer needed */ 1105 ieee80211_free_node(ni); 1106 1107 splx(s); 1108 1109 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, 1110 sbuf->map->dm_mapsize, BUS_DMASYNC_PREREAD); 1111 } 1112 1113 static void 1114 ipw_rx_intr(struct ipw_softc *sc) 1115 { 1116 struct ipw_status *status; 1117 struct ipw_soft_bd *sbd; 1118 struct ipw_soft_buf *sbuf; 1119 uint32_t r, i; 1120 1121 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1122 return; 1123 1124 r = CSR_READ_4(sc, IPW_CSR_RX_READ); 1125 1126 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 1127 1128 /* firmware was killed, stop processing received frames */ 1129 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1130 return; 1131 1132 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 1133 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1134 BUS_DMASYNC_POSTREAD); 1135 1136 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 1137 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 1138 BUS_DMASYNC_POSTREAD); 1139 1140 status = &sc->status_list[i]; 1141 sbd = &sc->srbd_list[i]; 1142 sbuf = sbd->priv; 1143 1144 switch (le16toh(status->code) & 0xf) { 1145 case IPW_STATUS_CODE_COMMAND: 1146 ipw_command_intr(sc, sbuf); 1147 break; 1148 1149 case IPW_STATUS_CODE_NEWSTATE: 1150 ipw_newstate_intr(sc, sbuf); 1151 break; 1152 1153 case IPW_STATUS_CODE_DATA_802_3: 1154 case IPW_STATUS_CODE_DATA_802_11: 1155 ipw_data_intr(sc, status, sbd, sbuf); 1156 break; 1157 1158 case IPW_STATUS_CODE_NOTIFICATION: 1159 DPRINTFN(2, ("received notification\n")); 1160 break; 1161 1162 default: 1163 aprint_error_dev(sc->sc_dev, "unknown status code %u\n", 1164 le16toh(status->code)); 1165 } 1166 1167 sbd->bd->flags = 0; 1168 1169 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 1170 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1171 BUS_DMASYNC_PREREAD); 1172 1173 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 1174 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 1175 BUS_DMASYNC_PREREAD); 1176 } 1177 1178 /* Tell the firmware what we have processed */ 1179 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 1180 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 1181 } 1182 1183 static void 1184 ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 1185 { 1186 struct ipw_soft_hdr *shdr; 1187 struct ipw_soft_buf *sbuf; 1188 1189 switch (sbd->type) { 1190 case IPW_SBD_TYPE_COMMAND: 1191 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 1192 0, sizeof(struct ipw_cmd), BUS_DMASYNC_POSTWRITE); 1193 /* bus_dmamap_unload(sc->sc_dmat, sc->cmd_map); */ 1194 break; 1195 1196 case IPW_SBD_TYPE_HEADER: 1197 shdr = sbd->priv; 1198 bus_dmamap_sync(sc->sc_dmat, sc->hdr_map, 1199 shdr->offset, sizeof(struct ipw_hdr), BUS_DMASYNC_POSTWRITE); 1200 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 1201 break; 1202 1203 case IPW_SBD_TYPE_DATA: 1204 sbuf = sbd->priv; 1205 1206 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 1207 0, sbuf->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1208 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1209 m_freem(sbuf->m); 1210 if (sbuf->ni != NULL) 1211 ieee80211_free_node(sbuf->ni); 1212 /* kill watchdog timer */ 1213 sc->sc_tx_timer = 0; 1214 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 1215 break; 1216 } 1217 sbd->type = IPW_SBD_TYPE_NOASSOC; 1218 } 1219 1220 static void 1221 ipw_tx_intr(struct ipw_softc *sc) 1222 { 1223 struct ifnet *ifp = &sc->sc_if; 1224 struct ipw_soft_bd *sbd; 1225 uint32_t r, i; 1226 int s; 1227 1228 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1229 return; 1230 1231 s = splnet(); 1232 1233 r = CSR_READ_4(sc, IPW_CSR_TX_READ); 1234 1235 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) { 1236 sbd = &sc->stbd_list[i]; 1237 1238 if (sbd->type == IPW_SBD_TYPE_DATA) 1239 ifp->if_opackets++; 1240 1241 ipw_release_sbd(sc, sbd); 1242 sc->txfree++; 1243 } 1244 1245 /* remember what the firmware has processed */ 1246 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 1247 1248 /* Call start() since some buffer descriptors have been released */ 1249 ifp->if_flags &= ~IFF_OACTIVE; 1250 ipw_start(ifp); /* in softint */ 1251 1252 splx(s); 1253 } 1254 1255 static int 1256 ipw_intr(void *arg) 1257 { 1258 struct ipw_softc *sc = arg; 1259 uint32_t r; 1260 1261 r = CSR_READ_4(sc, IPW_CSR_INTR); 1262 if (r == 0 || r == 0xffffffff) 1263 return 0; 1264 1265 /* Disable interrupts */ 1266 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1267 1268 softint_schedule(sc->sc_soft_ih); 1269 return 1; 1270 } 1271 1272 static void 1273 ipw_softintr(void *arg) 1274 { 1275 struct ipw_softc *sc = arg; 1276 uint32_t r; 1277 int s; 1278 1279 r = CSR_READ_4(sc, IPW_CSR_INTR); 1280 if (r == 0 || r == 0xffffffff) 1281 goto out; 1282 1283 if (r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR)) { 1284 aprint_error_dev(sc->sc_dev, "fatal error\n"); 1285 s = splnet(); 1286 sc->sc_ic.ic_ifp->if_flags &= ~IFF_UP; 1287 ipw_stop(&sc->sc_if, 1); 1288 splx(s); 1289 } 1290 1291 if (r & IPW_INTR_FW_INIT_DONE) { 1292 if (!(r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR))) 1293 wakeup(sc); 1294 } 1295 1296 if (r & IPW_INTR_RX_TRANSFER) 1297 ipw_rx_intr(sc); 1298 1299 if (r & IPW_INTR_TX_TRANSFER) 1300 ipw_tx_intr(sc); 1301 1302 /* Acknowledge all interrupts */ 1303 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 1304 1305 out: 1306 /* Re-enable interrupts */ 1307 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1308 } 1309 1310 /* 1311 * Send a command to the firmware and wait for the acknowledgement. 1312 */ 1313 static int 1314 ipw_cmd(struct ipw_softc *sc, uint32_t type, void *data, uint32_t len) 1315 { 1316 struct ipw_soft_bd *sbd; 1317 1318 sbd = &sc->stbd_list[sc->txcur]; 1319 1320 sc->cmd.type = htole32(type); 1321 sc->cmd.subtype = 0; 1322 sc->cmd.len = htole32(len); 1323 sc->cmd.seq = 0; 1324 1325 (void)memcpy(sc->cmd.data, data, len); 1326 1327 sbd->type = IPW_SBD_TYPE_COMMAND; 1328 sbd->bd->physaddr = htole32(sc->cmd_map->dm_segs[0].ds_addr); 1329 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 1330 sbd->bd->nfrag = 1; 1331 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 1332 IPW_BD_FLAG_TX_LAST_FRAGMENT; 1333 1334 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 0, sizeof (struct ipw_cmd), 1335 BUS_DMASYNC_PREWRITE); 1336 1337 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1338 sc->txcur * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1339 BUS_DMASYNC_PREWRITE); 1340 1341 DPRINTFN(2, ("sending command (%u, %u, %u, %u)\n", type, 0, 0, len)); 1342 1343 /* kick firmware */ 1344 sc->txfree--; 1345 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1346 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1347 1348 /* Wait at most one second for command to complete */ 1349 return tsleep(&sc->cmd, 0, "ipwcmd", hz); 1350 } 1351 1352 static int 1353 ipw_tx_start(struct ifnet *ifp, struct mbuf *m0, struct ieee80211_node *ni) 1354 { 1355 struct ipw_softc *sc = ifp->if_softc; 1356 struct ieee80211com *ic = &sc->sc_ic; 1357 struct ieee80211_frame *wh; 1358 struct ipw_soft_bd *sbd; 1359 struct ipw_soft_hdr *shdr; 1360 struct ipw_soft_buf *sbuf; 1361 struct ieee80211_key *k; 1362 struct mbuf *mnew; 1363 int error, i; 1364 1365 wh = mtod(m0, struct ieee80211_frame *); 1366 1367 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1368 k = ieee80211_crypto_encap(ic, ni, m0); 1369 if (k == NULL) { 1370 m_freem(m0); 1371 return ENOBUFS; 1372 } 1373 1374 /* packet header may have moved, reset our local pointer */ 1375 wh = mtod(m0, struct ieee80211_frame *); 1376 } 1377 1378 if (sc->sc_drvbpf != NULL) { 1379 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 1380 1381 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 1382 } 1383 1384 shdr = TAILQ_FIRST(&sc->sc_free_shdr); 1385 sbuf = TAILQ_FIRST(&sc->sc_free_sbuf); 1386 KASSERT(shdr != NULL && sbuf != NULL); 1387 1388 shdr->hdr->type = htole32(IPW_HDR_TYPE_SEND); 1389 shdr->hdr->subtype = 0; 1390 shdr->hdr->encrypted = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0; 1391 shdr->hdr->encrypt = 0; 1392 shdr->hdr->keyidx = 0; 1393 shdr->hdr->keysz = 0; 1394 shdr->hdr->fragmentsz = 0; 1395 IEEE80211_ADDR_COPY(shdr->hdr->src_addr, wh->i_addr2); 1396 if (ic->ic_opmode == IEEE80211_M_STA) 1397 IEEE80211_ADDR_COPY(shdr->hdr->dst_addr, wh->i_addr3); 1398 else 1399 IEEE80211_ADDR_COPY(shdr->hdr->dst_addr, wh->i_addr1); 1400 1401 /* trim IEEE802.11 header */ 1402 m_adj(m0, sizeof (struct ieee80211_frame)); 1403 1404 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m0, 1405 BUS_DMA_NOWAIT); 1406 if (error != 0 && error != EFBIG) { 1407 aprint_error_dev(sc->sc_dev, "could not map mbuf (error %d)\n", 1408 error); 1409 m_freem(m0); 1410 return error; 1411 } 1412 1413 if (error != 0) { 1414 /* too many fragments, linearize */ 1415 1416 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1417 if (mnew == NULL) { 1418 m_freem(m0); 1419 return ENOMEM; 1420 } 1421 1422 M_COPY_PKTHDR(mnew, m0); 1423 1424 /* If the data won't fit in the header, get a cluster */ 1425 if (m0->m_pkthdr.len > MHLEN) { 1426 MCLGET(mnew, M_DONTWAIT); 1427 if (!(mnew->m_flags & M_EXT)) { 1428 m_freem(m0); 1429 m_freem(mnew); 1430 return ENOMEM; 1431 } 1432 } 1433 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(mnew, void *)); 1434 m_freem(m0); 1435 mnew->m_len = mnew->m_pkthdr.len; 1436 m0 = mnew; 1437 1438 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m0, 1439 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1440 if (error != 0) { 1441 aprint_error_dev(sc->sc_dev, 1442 "could not map mbuf (error %d)\n", error); 1443 m_freem(m0); 1444 return error; 1445 } 1446 } 1447 1448 TAILQ_REMOVE(&sc->sc_free_sbuf, sbuf, next); 1449 TAILQ_REMOVE(&sc->sc_free_shdr, shdr, next); 1450 1451 sbd = &sc->stbd_list[sc->txcur]; 1452 sbd->type = IPW_SBD_TYPE_HEADER; 1453 sbd->priv = shdr; 1454 sbd->bd->physaddr = htole32(shdr->addr); 1455 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 1456 sbd->bd->nfrag = 1 + sbuf->map->dm_nsegs; 1457 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 1458 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1459 1460 DPRINTFN(5, ("sending tx hdr (%u, %u, %u, %u, )\n", 1461 shdr->hdr->type, shdr->hdr->subtype, shdr->hdr->encrypted, 1462 shdr->hdr->encrypt)); 1463 DPRINTFN(5, ("%s->", ether_sprintf(shdr->hdr->src_addr))); 1464 DPRINTFN(5, ("%s\n", ether_sprintf(shdr->hdr->dst_addr))); 1465 1466 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1467 sc->txcur * sizeof (struct ipw_bd), 1468 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1469 1470 sc->txfree--; 1471 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1472 1473 sbuf->m = m0; 1474 sbuf->ni = ni; 1475 1476 for (i = 0; i < sbuf->map->dm_nsegs; i++) { 1477 sbd = &sc->stbd_list[sc->txcur]; 1478 1479 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[i].ds_addr); 1480 sbd->bd->len = htole32(sbuf->map->dm_segs[i].ds_len); 1481 sbd->bd->nfrag = 0; 1482 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 1483 if (i == sbuf->map->dm_nsegs - 1) { 1484 sbd->type = IPW_SBD_TYPE_DATA; 1485 sbd->priv = sbuf; 1486 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 1487 } else { 1488 sbd->type = IPW_SBD_TYPE_NOASSOC; 1489 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1490 } 1491 1492 DPRINTFN(5, ("sending fragment (%d, %d)\n", i, 1493 (int)sbuf->map->dm_segs[i].ds_len)); 1494 1495 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1496 sc->txcur * sizeof (struct ipw_bd), 1497 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1498 1499 sc->txfree--; 1500 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1501 } 1502 1503 bus_dmamap_sync(sc->sc_dmat, sc->hdr_map, shdr->offset, 1504 sizeof (struct ipw_hdr), BUS_DMASYNC_PREWRITE); 1505 1506 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sbuf->map->dm_mapsize, 1507 BUS_DMASYNC_PREWRITE); 1508 1509 /* Inform firmware about this new packet */ 1510 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1511 1512 return 0; 1513 } 1514 1515 static void 1516 ipw_start(struct ifnet *ifp) 1517 { 1518 struct ipw_softc *sc = ifp->if_softc; 1519 struct ieee80211com *ic = &sc->sc_ic; 1520 struct mbuf *m0; 1521 struct ether_header *eh; 1522 struct ieee80211_node *ni; 1523 1524 if (ic->ic_state != IEEE80211_S_RUN) 1525 return; 1526 1527 for (;;) { 1528 IF_DEQUEUE(&ifp->if_snd, m0); 1529 if (m0 == NULL) 1530 break; 1531 1532 if (sc->txfree < 1 + IPW_MAX_NSEG) { 1533 IF_PREPEND(&ifp->if_snd, m0); 1534 ifp->if_flags |= IFF_OACTIVE; 1535 break; 1536 } 1537 1538 if (m0->m_len < sizeof (struct ether_header) && 1539 (m0 = m_pullup(m0, sizeof (struct ether_header))) == NULL) 1540 continue; 1541 1542 eh = mtod(m0, struct ether_header *); 1543 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1544 if (ni == NULL) { 1545 m_freem(m0); 1546 continue; 1547 } 1548 1549 bpf_mtap(ifp, m0); 1550 1551 m0 = ieee80211_encap(ic, m0, ni); 1552 if (m0 == NULL) { 1553 ieee80211_free_node(ni); 1554 continue; 1555 } 1556 1557 bpf_mtap3(ic->ic_rawbpf, m0); 1558 1559 if (ipw_tx_start(ifp, m0, ni) != 0) { 1560 ieee80211_free_node(ni); 1561 ifp->if_oerrors++; 1562 break; 1563 } 1564 1565 /* start watchdog timer */ 1566 sc->sc_tx_timer = 5; 1567 ifp->if_timer = 1; 1568 } 1569 } 1570 1571 static void 1572 ipw_watchdog(struct ifnet *ifp) 1573 { 1574 struct ipw_softc *sc = ifp->if_softc; 1575 1576 ifp->if_timer = 0; 1577 1578 if (sc->sc_tx_timer > 0) { 1579 if (--sc->sc_tx_timer == 0) { 1580 aprint_error_dev(sc->sc_dev, "device timeout\n"); 1581 ifp->if_oerrors++; 1582 ifp->if_flags &= ~IFF_UP; 1583 ipw_stop(ifp, 1); 1584 return; 1585 } 1586 ifp->if_timer = 1; 1587 } 1588 1589 ieee80211_watchdog(&sc->sc_ic); 1590 } 1591 1592 static int 1593 ipw_get_table1(struct ipw_softc *sc, uint32_t *tbl) 1594 { 1595 uint32_t addr, size, data, i; 1596 int error; 1597 1598 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1599 return ENOTTY; 1600 1601 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, sc->table1_base); 1602 1603 size = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 1604 if ((error = copyout(&size, tbl, sizeof(size))) != 0) 1605 return error; 1606 1607 for (i = 1, ++tbl; i < size; i++, tbl++) { 1608 addr = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 1609 data = MEM_READ_4(sc, addr); 1610 if ((error = copyout(&data, tbl, sizeof(data))) != 0) 1611 return error; 1612 } 1613 return 0; 1614 } 1615 1616 static int 1617 ipw_get_radio(struct ipw_softc *sc, int *ret) 1618 { 1619 uint32_t addr, data; 1620 1621 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1622 return ENOTTY; 1623 1624 addr = ipw_read_table1(sc, IPW_INFO_EEPROM_ADDRESS); 1625 if ((MEM_READ_4(sc, addr + 32) >> 24) & 1) 1626 data = -1; 1627 else if (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED) 1628 data = 0; 1629 else 1630 data = 1; 1631 1632 return copyout(&data, ret, sizeof(data)); 1633 } 1634 1635 static int 1636 ipw_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1637 { 1638 #define IS_RUNNING(ifp) \ 1639 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 1640 1641 struct ipw_softc *sc = ifp->if_softc; 1642 struct ieee80211com *ic = &sc->sc_ic; 1643 struct ifreq *ifr = (struct ifreq *)data; 1644 int s, error = 0; 1645 1646 s = splnet(); 1647 1648 switch (cmd) { 1649 case SIOCSIFFLAGS: 1650 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 1651 break; 1652 if (ifp->if_flags & IFF_UP) { 1653 if (!(ifp->if_flags & IFF_RUNNING)) 1654 ipw_init(ifp); 1655 } else { 1656 if (ifp->if_flags & IFF_RUNNING) 1657 ipw_stop(ifp, 1); 1658 } 1659 break; 1660 1661 case SIOCADDMULTI: 1662 case SIOCDELMULTI: 1663 /* XXX no h/w multicast filter? --dyoung */ 1664 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1665 /* setup multicast filter, etc */ 1666 error = 0; 1667 } 1668 break; 1669 1670 case SIOCGTABLE1: 1671 error = ipw_get_table1(sc, (uint32_t *)ifr->ifr_data); 1672 break; 1673 1674 case SIOCGRADIO: 1675 error = ipw_get_radio(sc, (int *)ifr->ifr_data); 1676 break; 1677 1678 case SIOCSIFMEDIA: 1679 if (ifr->ifr_media & IFM_IEEE80211_ADHOC) 1680 sc->sc_fwname = "ipw2100-1.2-i.fw"; 1681 else if (ifr->ifr_media & IFM_IEEE80211_MONITOR) 1682 sc->sc_fwname = "ipw2100-1.2-p.fw"; 1683 else 1684 sc->sc_fwname = "ipw2100-1.2.fw"; 1685 1686 ipw_free_firmware(sc); 1687 /* FALLTRHOUGH */ 1688 default: 1689 error = ieee80211_ioctl(&sc->sc_ic, cmd, data); 1690 if (error != ENETRESET) 1691 break; 1692 1693 if (error == ENETRESET) { 1694 if (IS_RUNNING(ifp) && 1695 (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)) 1696 ipw_init(ifp); 1697 error = 0; 1698 } 1699 1700 } 1701 1702 splx(s); 1703 return error; 1704 #undef IS_RUNNING 1705 } 1706 1707 static uint32_t 1708 ipw_read_table1(struct ipw_softc *sc, uint32_t off) 1709 { 1710 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 1711 } 1712 1713 static void 1714 ipw_write_table1(struct ipw_softc *sc, uint32_t off, uint32_t info) 1715 { 1716 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 1717 } 1718 1719 static int 1720 ipw_read_table2(struct ipw_softc *sc, uint32_t off, void *buf, uint32_t *len) 1721 { 1722 uint32_t addr, info; 1723 uint16_t count, size; 1724 uint32_t total; 1725 1726 /* addr[4] + count[2] + size[2] */ 1727 addr = MEM_READ_4(sc, sc->table2_base + off); 1728 info = MEM_READ_4(sc, sc->table2_base + off + 4); 1729 1730 count = info >> 16; 1731 size = info & 0xffff; 1732 total = count * size; 1733 1734 if (total > *len) { 1735 *len = total; 1736 return EINVAL; 1737 } 1738 1739 *len = total; 1740 ipw_read_mem_1(sc, addr, buf, total); 1741 1742 return 0; 1743 } 1744 1745 static void 1746 ipw_stop_master(struct ipw_softc *sc) 1747 { 1748 int ntries; 1749 1750 /* disable interrupts */ 1751 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1752 1753 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1754 for (ntries = 0; ntries < 50; ntries++) { 1755 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1756 break; 1757 DELAY(10); 1758 } 1759 if (ntries == 50) 1760 aprint_error_dev(sc->sc_dev, "timeout waiting for master\n"); 1761 1762 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1763 IPW_RST_PRINCETON_RESET); 1764 1765 sc->flags &= ~IPW_FLAG_FW_INITED; 1766 } 1767 1768 static int 1769 ipw_reset(struct ipw_softc *sc) 1770 { 1771 int ntries; 1772 1773 ipw_stop_master(sc); 1774 1775 /* move adapter to D0 state */ 1776 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1777 IPW_CTL_INIT); 1778 1779 /* wait for clock stabilization */ 1780 for (ntries = 0; ntries < 1000; ntries++) { 1781 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY) 1782 break; 1783 DELAY(200); 1784 } 1785 if (ntries == 1000) 1786 return EIO; 1787 1788 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1789 IPW_RST_SW_RESET); 1790 1791 DELAY(10); 1792 1793 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1794 IPW_CTL_INIT); 1795 1796 return 0; 1797 } 1798 1799 /* 1800 * Upload the microcode to the device. 1801 */ 1802 static int 1803 ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size) 1804 { 1805 int ntries; 1806 1807 MEM_WRITE_4(sc, 0x3000e0, 0x80000000); 1808 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1809 1810 MEM_WRITE_2(sc, 0x220000, 0x0703); 1811 MEM_WRITE_2(sc, 0x220000, 0x0707); 1812 1813 MEM_WRITE_1(sc, 0x210014, 0x72); 1814 MEM_WRITE_1(sc, 0x210014, 0x72); 1815 1816 MEM_WRITE_1(sc, 0x210000, 0x40); 1817 MEM_WRITE_1(sc, 0x210000, 0x00); 1818 MEM_WRITE_1(sc, 0x210000, 0x40); 1819 1820 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1821 1822 MEM_WRITE_1(sc, 0x210000, 0x00); 1823 MEM_WRITE_1(sc, 0x210000, 0x00); 1824 MEM_WRITE_1(sc, 0x210000, 0x80); 1825 1826 MEM_WRITE_2(sc, 0x220000, 0x0703); 1827 MEM_WRITE_2(sc, 0x220000, 0x0707); 1828 1829 MEM_WRITE_1(sc, 0x210014, 0x72); 1830 MEM_WRITE_1(sc, 0x210014, 0x72); 1831 1832 MEM_WRITE_1(sc, 0x210000, 0x00); 1833 MEM_WRITE_1(sc, 0x210000, 0x80); 1834 1835 for (ntries = 0; ntries < 10; ntries++) { 1836 if (MEM_READ_1(sc, 0x210000) & 1) 1837 break; 1838 DELAY(10); 1839 } 1840 if (ntries == 10) { 1841 aprint_error_dev(sc->sc_dev, "timeout waiting for ucode to initialize\n"); 1842 return EIO; 1843 } 1844 1845 MEM_WRITE_4(sc, 0x3000e0, 0); 1846 1847 return 0; 1848 } 1849 1850 /* set of macros to handle unaligned little endian data in firmware image */ 1851 #define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1852 #define GETLE16(p) ((p)[0] | (p)[1] << 8) 1853 static int 1854 ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size) 1855 { 1856 u_char *p, *end; 1857 uint32_t dst; 1858 uint16_t len; 1859 int error; 1860 1861 p = fw; 1862 end = fw + size; 1863 while (p < end) { 1864 dst = GETLE32(p); p += 4; 1865 len = GETLE16(p); p += 2; 1866 1867 ipw_write_mem_1(sc, dst, p, len); 1868 p += len; 1869 } 1870 1871 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1872 IPW_IO_LED_OFF); 1873 1874 /* enable interrupts */ 1875 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1876 1877 /* kick the firmware */ 1878 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1879 1880 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1881 IPW_CTL_ALLOW_STANDBY); 1882 1883 /* wait at most one second for firmware initialization to complete */ 1884 if ((error = tsleep(sc, 0, "ipwinit", hz)) != 0) { 1885 aprint_error_dev(sc->sc_dev, 1886 "timeout waiting for firmware initialization " 1887 "to complete\n"); 1888 return error; 1889 } 1890 1891 CSR_WRITE_4(sc, IPW_CSR_IO, CSR_READ_4(sc, IPW_CSR_IO) | 1892 IPW_IO_GPIO1_MASK | IPW_IO_GPIO3_MASK); 1893 1894 return 0; 1895 } 1896 1897 /* 1898 * Store firmware into kernel memory so we can download it when we need to, 1899 * e.g when the adapter wakes up from suspend mode. 1900 */ 1901 static int 1902 ipw_cache_firmware(struct ipw_softc *sc) 1903 { 1904 struct ipw_firmware *fw = &sc->fw; 1905 struct ipw_firmware_hdr hdr; 1906 firmware_handle_t fwh; 1907 off_t fwsz, p; 1908 int error; 1909 1910 ipw_free_firmware(sc); 1911 1912 if (ipw_accept_eula == 0) { 1913 aprint_error_dev(sc->sc_dev, 1914 "EULA not accepted; please see the ipw(4) man page.\n"); 1915 return EPERM; 1916 } 1917 1918 if ((error = firmware_open("if_ipw", sc->sc_fwname, &fwh)) != 0) 1919 goto fail0; 1920 1921 fwsz = firmware_get_size(fwh); 1922 1923 if (fwsz < sizeof(hdr)) 1924 goto fail2; 1925 1926 if ((error = firmware_read(fwh, 0, &hdr, sizeof(hdr))) != 0) 1927 goto fail2; 1928 1929 fw->main_size = le32toh(hdr.main_size); 1930 fw->ucode_size = le32toh(hdr.ucode_size); 1931 1932 fw->main = firmware_malloc(fw->main_size); 1933 if (fw->main == NULL) { 1934 error = ENOMEM; 1935 goto fail1; 1936 } 1937 1938 fw->ucode = firmware_malloc(fw->ucode_size); 1939 if (fw->ucode == NULL) { 1940 error = ENOMEM; 1941 goto fail2; 1942 } 1943 1944 p = sizeof(hdr); 1945 if ((error = firmware_read(fwh, p, fw->main, fw->main_size)) != 0) 1946 goto fail3; 1947 1948 p += fw->main_size; 1949 if ((error = firmware_read(fwh, p, fw->ucode, fw->ucode_size)) != 0) 1950 goto fail3; 1951 1952 DPRINTF(("Firmware cached: main %u, ucode %u\n", fw->main_size, 1953 fw->ucode_size)); 1954 1955 sc->flags |= IPW_FLAG_FW_CACHED; 1956 1957 firmware_close(fwh); 1958 1959 return 0; 1960 1961 fail3: firmware_free(fw->ucode, fw->ucode_size); 1962 fail2: firmware_free(fw->main, fw->main_size); 1963 fail1: firmware_close(fwh); 1964 fail0: 1965 return error; 1966 } 1967 1968 static void 1969 ipw_free_firmware(struct ipw_softc *sc) 1970 { 1971 if (!(sc->flags & IPW_FLAG_FW_CACHED)) 1972 return; 1973 1974 firmware_free(sc->fw.main, sc->fw.main_size); 1975 firmware_free(sc->fw.ucode, sc->fw.ucode_size); 1976 1977 sc->flags &= ~IPW_FLAG_FW_CACHED; 1978 } 1979 1980 static int 1981 ipw_config(struct ipw_softc *sc) 1982 { 1983 struct ieee80211com *ic = &sc->sc_ic; 1984 struct ifnet *ifp = &sc->sc_if; 1985 struct ipw_security security; 1986 struct ieee80211_key *k; 1987 struct ipw_wep_key wepkey; 1988 struct ipw_scan_options options; 1989 struct ipw_configuration config; 1990 uint32_t data; 1991 int error, i; 1992 1993 switch (ic->ic_opmode) { 1994 case IEEE80211_M_STA: 1995 case IEEE80211_M_HOSTAP: 1996 data = htole32(IPW_MODE_BSS); 1997 break; 1998 1999 case IEEE80211_M_IBSS: 2000 case IEEE80211_M_AHDEMO: 2001 data = htole32(IPW_MODE_IBSS); 2002 break; 2003 2004 case IEEE80211_M_MONITOR: 2005 data = htole32(IPW_MODE_MONITOR); 2006 break; 2007 } 2008 DPRINTF(("Setting mode to %u\n", le32toh(data))); 2009 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 2010 if (error != 0) 2011 return error; 2012 2013 if (ic->ic_opmode == IEEE80211_M_IBSS || 2014 ic->ic_opmode == IEEE80211_M_MONITOR) { 2015 data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); 2016 DPRINTF(("Setting channel to %u\n", le32toh(data))); 2017 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 2018 if (error != 0) 2019 return error; 2020 } 2021 2022 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2023 DPRINTF(("Enabling adapter\n")); 2024 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 2025 } 2026 2027 DPRINTF(("Setting MAC to %s\n", ether_sprintf(ic->ic_myaddr))); 2028 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 2029 IEEE80211_ADDR_LEN); 2030 if (error != 0) 2031 return error; 2032 2033 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 2034 IPW_CFG_PREAMBLE_AUTO | IPW_CFG_802_1x_ENABLE); 2035 2036 if (ic->ic_opmode == IEEE80211_M_IBSS) 2037 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 2038 if (ifp->if_flags & IFF_PROMISC) 2039 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 2040 config.bss_chan = htole32(0x3fff); /* channels 1-14 */ 2041 config.ibss_chan = htole32(0x7ff); /* channels 1-11 */ 2042 DPRINTF(("Setting adapter configuration 0x%08x\n", config.flags)); 2043 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 2044 if (error != 0) 2045 return error; 2046 2047 data = htole32(0x3); /* 1, 2 */ 2048 DPRINTF(("Setting basic tx rates to 0x%x\n", le32toh(data))); 2049 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 2050 if (error != 0) 2051 return error; 2052 2053 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 2054 DPRINTF(("Setting tx rates to 0x%x\n", le32toh(data))); 2055 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 2056 if (error != 0) 2057 return error; 2058 2059 data = htole32(IPW_POWER_MODE_CAM); 2060 DPRINTF(("Setting power mode to %u\n", le32toh(data))); 2061 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 2062 if (error != 0) 2063 return error; 2064 2065 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2066 data = htole32(32); /* default value */ 2067 DPRINTF(("Setting tx power index to %u\n", le32toh(data))); 2068 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 2069 sizeof data); 2070 if (error != 0) 2071 return error; 2072 } 2073 2074 data = htole32(ic->ic_rtsthreshold); 2075 DPRINTF(("Setting RTS threshold to %u\n", le32toh(data))); 2076 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 2077 if (error != 0) 2078 return error; 2079 2080 data = htole32(ic->ic_fragthreshold); 2081 DPRINTF(("Setting frag threshold to %u\n", le32toh(data))); 2082 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 2083 if (error != 0) 2084 return error; 2085 2086 #ifdef IPW_DEBUG 2087 if (ipw_debug > 0) { 2088 printf("Setting ESSID to "); 2089 ieee80211_print_essid(ic->ic_des_essid, ic->ic_des_esslen); 2090 printf("\n"); 2091 } 2092 #endif 2093 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ic->ic_des_essid, 2094 ic->ic_des_esslen); 2095 if (error != 0) 2096 return error; 2097 2098 /* no mandatory BSSID */ 2099 DPRINTF(("Setting mandatory BSSID to null\n")); 2100 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 2101 if (error != 0) 2102 return error; 2103 2104 if (ic->ic_flags & IEEE80211_F_DESBSSID) { 2105 DPRINTF(("Setting desired BSSID to %s\n", 2106 ether_sprintf(ic->ic_des_bssid))); 2107 error = ipw_cmd(sc, IPW_CMD_SET_DESIRED_BSSID, 2108 ic->ic_des_bssid, IEEE80211_ADDR_LEN); 2109 if (error != 0) 2110 return error; 2111 } 2112 2113 (void)memset(&security, 0, sizeof(security)); 2114 security.authmode = (ic->ic_bss->ni_authmode == IEEE80211_AUTH_SHARED) ? 2115 IPW_AUTH_SHARED : IPW_AUTH_OPEN; 2116 security.ciphers = htole32(IPW_CIPHER_NONE); 2117 DPRINTF(("Setting authmode to %u\n", security.authmode)); 2118 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 2119 sizeof security); 2120 if (error != 0) 2121 return error; 2122 2123 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 2124 k = ic->ic_crypto.cs_nw_keys; 2125 for (i = 0; i < IEEE80211_WEP_NKID; i++, k++) { 2126 if (k->wk_keylen == 0) 2127 continue; 2128 2129 wepkey.idx = i; 2130 wepkey.len = k->wk_keylen; 2131 memset(wepkey.key, 0, sizeof(wepkey.key)); 2132 memcpy(wepkey.key, k->wk_key, k->wk_keylen); 2133 DPRINTF(("Setting wep key index %u len %u\n", 2134 wepkey.idx, wepkey.len)); 2135 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY, &wepkey, 2136 sizeof wepkey); 2137 if (error != 0) 2138 return error; 2139 } 2140 2141 data = htole32(ic->ic_crypto.cs_def_txkey); 2142 DPRINTF(("Setting tx key index to %u\n", le32toh(data))); 2143 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY_INDEX, &data, 2144 sizeof data); 2145 if (error != 0) 2146 return error; 2147 } 2148 2149 data = htole32((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) ? IPW_WEPON : 0); 2150 DPRINTF(("Setting wep flags to 0x%x\n", le32toh(data))); 2151 error = ipw_cmd(sc, IPW_CMD_SET_WEP_FLAGS, &data, sizeof data); 2152 if (error != 0) 2153 return error; 2154 2155 #if 0 2156 struct ipw_wpa_ie ie; 2157 2158 memset(&ie, 0 sizeof(ie)); 2159 ie.len = htole32(sizeof (struct ieee80211_ie_wpa)); 2160 DPRINTF(("Setting wpa ie\n")); 2161 error = ipw_cmd(sc, IPW_CMD_SET_WPA_IE, &ie, sizeof ie); 2162 if (error != 0) 2163 return error; 2164 #endif 2165 2166 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2167 data = htole32(ic->ic_bintval); 2168 DPRINTF(("Setting beacon interval to %u\n", le32toh(data))); 2169 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 2170 sizeof data); 2171 if (error != 0) 2172 return error; 2173 } 2174 2175 options.flags = 0; 2176 options.channels = htole32(0x3fff); /* scan channels 1-14 */ 2177 DPRINTF(("Setting scan options to 0x%x\n", le32toh(options.flags))); 2178 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &options, sizeof options); 2179 if (error != 0) 2180 return error; 2181 2182 /* finally, enable adapter (start scanning for an access point) */ 2183 DPRINTF(("Enabling adapter\n")); 2184 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 2185 } 2186 2187 static int 2188 ipw_init(struct ifnet *ifp) 2189 { 2190 struct ipw_softc *sc = ifp->if_softc; 2191 struct ipw_firmware *fw = &sc->fw; 2192 2193 if (!(sc->flags & IPW_FLAG_FW_CACHED)) { 2194 if (ipw_cache_firmware(sc) != 0) { 2195 aprint_error_dev(sc->sc_dev, 2196 "could not cache the firmware (%s)\n", 2197 sc->sc_fwname); 2198 goto fail; 2199 } 2200 } 2201 2202 ipw_stop(ifp, 0); 2203 2204 if (ipw_reset(sc) != 0) { 2205 aprint_error_dev(sc->sc_dev, "could not reset adapter\n"); 2206 goto fail; 2207 } 2208 2209 if (ipw_load_ucode(sc, fw->ucode, fw->ucode_size) != 0) { 2210 aprint_error_dev(sc->sc_dev, "could not load microcode\n"); 2211 goto fail; 2212 } 2213 2214 ipw_stop_master(sc); 2215 2216 /* 2217 * Setup tx, rx and status rings. 2218 */ 2219 sc->txold = IPW_NTBD - 1; 2220 sc->txcur = 0; 2221 sc->txfree = IPW_NTBD - 2; 2222 sc->rxcur = IPW_NRBD - 1; 2223 2224 CSR_WRITE_4(sc, IPW_CSR_TX_BASE, sc->tbd_map->dm_segs[0].ds_addr); 2225 CSR_WRITE_4(sc, IPW_CSR_TX_SIZE, IPW_NTBD); 2226 CSR_WRITE_4(sc, IPW_CSR_TX_READ, 0); 2227 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 2228 2229 CSR_WRITE_4(sc, IPW_CSR_RX_BASE, sc->rbd_map->dm_segs[0].ds_addr); 2230 CSR_WRITE_4(sc, IPW_CSR_RX_SIZE, IPW_NRBD); 2231 CSR_WRITE_4(sc, IPW_CSR_RX_READ, 0); 2232 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 2233 2234 CSR_WRITE_4(sc, IPW_CSR_STATUS_BASE, sc->status_map->dm_segs[0].ds_addr); 2235 2236 if (ipw_load_firmware(sc, fw->main, fw->main_size) != 0) { 2237 aprint_error_dev(sc->sc_dev, "could not load firmware\n"); 2238 goto fail; 2239 } 2240 2241 sc->flags |= IPW_FLAG_FW_INITED; 2242 2243 /* retrieve information tables base addresses */ 2244 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 2245 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 2246 2247 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 2248 2249 if (ipw_config(sc) != 0) { 2250 aprint_error_dev(sc->sc_dev, "device configuration failed\n"); 2251 goto fail; 2252 } 2253 2254 ifp->if_flags &= ~IFF_OACTIVE; 2255 ifp->if_flags |= IFF_RUNNING; 2256 2257 return 0; 2258 2259 fail: ifp->if_flags &= ~IFF_UP; 2260 ipw_stop(ifp, 0); 2261 2262 return EIO; 2263 } 2264 2265 static void 2266 ipw_stop(struct ifnet *ifp, int disable) 2267 { 2268 struct ipw_softc *sc = ifp->if_softc; 2269 struct ieee80211com *ic = &sc->sc_ic; 2270 int i; 2271 2272 ipw_stop_master(sc); 2273 2274 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 2275 2276 /* 2277 * Release tx buffers. 2278 */ 2279 for (i = 0; i < IPW_NTBD; i++) 2280 ipw_release_sbd(sc, &sc->stbd_list[i]); 2281 2282 sc->sc_tx_timer = 0; 2283 ifp->if_timer = 0; 2284 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2285 2286 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2287 } 2288 2289 static void 2290 ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2291 bus_size_t count) 2292 { 2293 for (; count > 0; offset++, datap++, count--) { 2294 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2295 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 2296 } 2297 } 2298 2299 static void 2300 ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2301 bus_size_t count) 2302 { 2303 for (; count > 0; offset++, datap++, count--) { 2304 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2305 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 2306 } 2307 } 2308 2309 SYSCTL_SETUP(sysctl_hw_ipw_accept_eula_setup, "sysctl hw.ipw.accept_eula") 2310 { 2311 const struct sysctlnode *rnode; 2312 const struct sysctlnode *cnode; 2313 2314 sysctl_createv(NULL, 0, NULL, &rnode, 2315 CTLFLAG_PERMANENT, 2316 CTLTYPE_NODE, "ipw", 2317 NULL, 2318 NULL, 0, 2319 NULL, 0, 2320 CTL_HW, CTL_CREATE, CTL_EOL); 2321 2322 sysctl_createv(NULL, 0, &rnode, &cnode, 2323 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, 2324 CTLTYPE_INT, "accept_eula", 2325 SYSCTL_DESCR("Accept Intel EULA and permit use of ipw(4) firmware"), 2326 NULL, 0, 2327 &ipw_accept_eula, sizeof(ipw_accept_eula), 2328 CTL_CREATE, CTL_EOL); 2329 } 2330
Indexes created Tue Sep 30 17:09:57 GMT 2025