if_ipw.c revision 1.69.2.2
1 /* $NetBSD: if_ipw.c,v 1.69.2.2 2020/04/08 14:08:09 martin Exp $ */ 2 /* FreeBSD: src/sys/dev/ipw/if_ipw.c,v 1.15 2005/11/13 17:17:40 damien Exp */ 3 4 /*- 5 * Copyright (c) 2004, 2005 6 * Damien Bergamini <damien.bergamini (at) free.fr>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: if_ipw.c,v 1.69.2.2 2020/04/08 14:08:09 martin Exp $"); 33 34 /*- 35 * Intel(R) PRO/Wireless 2100 MiniPCI driver 36 * http://www.intel.com/network/connectivity/products/wireless/prowireless_mobile.htm 37 */ 38 39 40 #include <sys/param.h> 41 #include <sys/sockio.h> 42 #include <sys/sysctl.h> 43 #include <sys/mbuf.h> 44 #include <sys/kernel.h> 45 #include <sys/socket.h> 46 #include <sys/systm.h> 47 #include <sys/malloc.h> 48 #include <sys/conf.h> 49 #include <sys/proc.h> 50 51 #include <sys/bus.h> 52 #include <machine/endian.h> 53 #include <sys/intr.h> 54 55 #include <dev/pci/pcireg.h> 56 #include <dev/pci/pcivar.h> 57 #include <dev/pci/pcidevs.h> 58 59 #include <net/bpf.h> 60 #include <net/if.h> 61 #include <net/if_arp.h> 62 #include <net/if_dl.h> 63 #include <net/if_ether.h> 64 #include <net/if_media.h> 65 #include <net/if_types.h> 66 67 #include <net80211/ieee80211_var.h> 68 #include <net80211/ieee80211_radiotap.h> 69 70 #include <netinet/in.h> 71 #include <netinet/in_systm.h> 72 #include <netinet/in_var.h> 73 #include <netinet/ip.h> 74 75 #include <dev/firmload.h> 76 77 #include <dev/pci/if_ipwreg.h> 78 #include <dev/pci/if_ipwvar.h> 79 80 #ifdef IPW_DEBUG 81 #define DPRINTF(x) if (ipw_debug > 0) printf x 82 #define DPRINTFN(n, x) if (ipw_debug >= (n)) printf x 83 int ipw_debug = 0; 84 #else 85 #define DPRINTF(x) 86 #define DPRINTFN(n, x) 87 #endif 88 89 /* Permit loading the Intel firmware */ 90 static int ipw_accept_eula; 91 92 static int ipw_dma_alloc(struct ipw_softc *); 93 static void ipw_release(struct ipw_softc *); 94 static int ipw_match(device_t, cfdata_t, void *); 95 static void ipw_attach(device_t, device_t, void *); 96 static int ipw_detach(device_t, int); 97 98 static int ipw_media_change(struct ifnet *); 99 static void ipw_media_status(struct ifnet *, struct ifmediareq *); 100 static int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 101 static uint16_t ipw_read_prom_word(struct ipw_softc *, uint8_t); 102 static void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 103 static void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 104 static void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 105 struct ipw_soft_bd *, struct ipw_soft_buf *); 106 static void ipw_rx_intr(struct ipw_softc *); 107 static void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 108 static void ipw_tx_intr(struct ipw_softc *); 109 static int ipw_intr(void *); 110 static void ipw_softintr(void *); 111 static int ipw_cmd(struct ipw_softc *, uint32_t, void *, uint32_t); 112 static int ipw_tx_start(struct ifnet *, struct mbuf *, 113 struct ieee80211_node *); 114 static void ipw_start(struct ifnet *); 115 static void ipw_watchdog(struct ifnet *); 116 static int ipw_ioctl(struct ifnet *, u_long, void *); 117 static int ipw_get_table1(struct ipw_softc *, uint32_t *); 118 static int ipw_get_radio(struct ipw_softc *, int *); 119 static void ipw_stop_master(struct ipw_softc *); 120 static int ipw_reset(struct ipw_softc *); 121 static int ipw_load_ucode(struct ipw_softc *, u_char *, int); 122 static int ipw_load_firmware(struct ipw_softc *, u_char *, int); 123 static int ipw_cache_firmware(struct ipw_softc *); 124 static void ipw_free_firmware(struct ipw_softc *); 125 static int ipw_config(struct ipw_softc *); 126 static int ipw_init(struct ifnet *); 127 static void ipw_stop(struct ifnet *, int); 128 static uint32_t ipw_read_table1(struct ipw_softc *, uint32_t); 129 static void ipw_write_table1(struct ipw_softc *, uint32_t, uint32_t); 130 static int ipw_read_table2(struct ipw_softc *, uint32_t, void *, uint32_t *); 131 static void ipw_read_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 132 bus_size_t); 133 static void ipw_write_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 134 bus_size_t); 135 136 static inline uint8_t 137 MEM_READ_1(struct ipw_softc *sc, uint32_t addr) 138 { 139 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 140 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); 141 } 142 143 static inline uint32_t 144 MEM_READ_4(struct ipw_softc *sc, uint32_t addr) 145 { 146 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 147 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); 148 } 149 150 CFATTACH_DECL_NEW(ipw, sizeof (struct ipw_softc), ipw_match, ipw_attach, 151 ipw_detach, NULL); 152 153 static int 154 ipw_match(device_t parent, cfdata_t match, void *aux) 155 { 156 struct pci_attach_args *pa = aux; 157 158 if (PCI_VENDOR (pa->pa_id) == PCI_VENDOR_INTEL && 159 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_PRO_WL_2100) 160 return 1; 161 162 return 0; 163 } 164 165 /* Base Address Register */ 166 #define IPW_PCI_BAR0 0x10 167 168 static void 169 ipw_attach(device_t parent, device_t self, void *aux) 170 { 171 struct ipw_softc *sc = device_private(self); 172 struct ieee80211com *ic = &sc->sc_ic; 173 struct ifnet *ifp = &sc->sc_if; 174 struct pci_attach_args *pa = aux; 175 const char *intrstr; 176 bus_space_tag_t memt; 177 bus_space_handle_t memh; 178 bus_addr_t base; 179 pci_intr_handle_t ih; 180 uint32_t data; 181 uint16_t val; 182 int i, error; 183 char intrbuf[PCI_INTRSTR_LEN]; 184 185 sc->sc_dev = self; 186 sc->sc_pct = pa->pa_pc; 187 sc->sc_pcitag = pa->pa_tag; 188 189 pci_aprint_devinfo(pa, NULL); 190 191 /* enable bus-mastering */ 192 data = pci_conf_read(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG); 193 data |= PCI_COMMAND_MASTER_ENABLE; 194 pci_conf_write(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG, data); 195 196 /* map the register window */ 197 error = pci_mapreg_map(pa, IPW_PCI_BAR0, PCI_MAPREG_TYPE_MEM | 198 PCI_MAPREG_MEM_TYPE_32BIT, 0, &memt, &memh, &base, &sc->sc_sz); 199 if (error != 0) { 200 aprint_error_dev(sc->sc_dev, "could not map memory space\n"); 201 return; 202 } 203 204 sc->sc_st = memt; 205 sc->sc_sh = memh; 206 sc->sc_dmat = pa->pa_dmat; 207 sc->sc_fwname = "ipw2100-1.2.fw"; 208 209 /* disable interrupts */ 210 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 211 212 if (pci_intr_map(pa, &ih) != 0) { 213 aprint_error_dev(sc->sc_dev, "could not map interrupt\n"); 214 goto fail; 215 } 216 217 sc->sc_soft_ih = softint_establish(SOFTINT_NET, ipw_softintr, sc); 218 if (sc->sc_soft_ih == NULL) { 219 aprint_error_dev(sc->sc_dev, "could not establish softint\n"); 220 goto fail; 221 } 222 223 intrstr = pci_intr_string(sc->sc_pct, ih, intrbuf, sizeof(intrbuf)); 224 sc->sc_ih = pci_intr_establish_xname(sc->sc_pct, ih, IPL_NET, ipw_intr, 225 sc, device_xname(self)); 226 if (sc->sc_ih == NULL) { 227 aprint_error_dev(sc->sc_dev, "could not establish interrupt"); 228 if (intrstr != NULL) 229 aprint_error(" at %s", intrstr); 230 aprint_error("\n"); 231 goto fail; 232 } 233 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 234 235 if (ipw_reset(sc) != 0) { 236 aprint_error_dev(sc->sc_dev, "could not reset adapter\n"); 237 goto fail; 238 } 239 240 if (ipw_dma_alloc(sc) != 0) { 241 aprint_error_dev(sc->sc_dev, "could not allocate DMA resources\n"); 242 goto fail; 243 } 244 245 ifp->if_softc = sc; 246 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 247 ifp->if_init = ipw_init; 248 ifp->if_stop = ipw_stop; 249 ifp->if_ioctl = ipw_ioctl; 250 ifp->if_start = ipw_start; 251 ifp->if_watchdog = ipw_watchdog; 252 IFQ_SET_READY(&ifp->if_snd); 253 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 254 255 ic->ic_ifp = ifp; 256 ic->ic_phytype = IEEE80211_T_DS; 257 ic->ic_opmode = IEEE80211_M_STA; 258 ic->ic_state = IEEE80211_S_INIT; 259 260 /* set device capabilities */ 261 ic->ic_caps = 262 IEEE80211_C_SHPREAMBLE /* short preamble supported */ 263 | IEEE80211_C_TXPMGT /* tx power management */ 264 | IEEE80211_C_IBSS /* ibss mode */ 265 | IEEE80211_C_MONITOR /* monitor mode */ 266 ; 267 268 /* read MAC address from EEPROM */ 269 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0); 270 ic->ic_myaddr[0] = val >> 8; 271 ic->ic_myaddr[1] = val & 0xff; 272 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 1); 273 ic->ic_myaddr[2] = val >> 8; 274 ic->ic_myaddr[3] = val & 0xff; 275 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 2); 276 ic->ic_myaddr[4] = val >> 8; 277 ic->ic_myaddr[5] = val & 0xff; 278 279 /* set supported .11b rates */ 280 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 281 282 /* set supported .11b channels (read from EEPROM) */ 283 if ((val = ipw_read_prom_word(sc, IPW_EEPROM_CHANNEL_LIST)) == 0) 284 val = 0x7ff; /* default to channels 1-11 */ 285 val <<= 1; 286 for (i = 1; i < 16; i++) { 287 if (val & (1 << i)) { 288 ic->ic_channels[i].ic_freq = 289 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 290 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 291 } 292 } 293 294 /* check support for radio transmitter switch in EEPROM */ 295 if (!(ipw_read_prom_word(sc, IPW_EEPROM_RADIO) & 8)) 296 sc->flags |= IPW_FLAG_HAS_RADIO_SWITCH; 297 298 aprint_normal_dev(sc->sc_dev, "802.11 address %s\n", 299 ether_sprintf(ic->ic_myaddr)); 300 301 error = if_initialize(ifp); 302 if (error != 0) { 303 ifp->if_softc = NULL; /* For ipw_detach(). */ 304 aprint_error_dev(sc->sc_dev, "if_initialize failed(%d)\n", 305 error); 306 goto fail; 307 } 308 ieee80211_ifattach(ic); 309 /* Use common softint-based if_input */ 310 ifp->if_percpuq = if_percpuq_create(ifp); 311 if_register(ifp); 312 313 /* override state transition machine */ 314 sc->sc_newstate = ic->ic_newstate; 315 ic->ic_newstate = ipw_newstate; 316 317 ieee80211_media_init(ic, ipw_media_change, ipw_media_status); 318 319 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 320 sizeof(struct ieee80211_frame) + 64, &sc->sc_drvbpf); 321 322 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 323 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 324 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 325 326 sc->sc_txtap_len = sizeof sc->sc_txtapu; 327 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 328 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 329 330 /* 331 * Add a few sysctl knobs. 332 * XXX: Not yet 333 */ 334 sc->dwelltime = 100; 335 336 if (pmf_device_register(self, NULL, NULL)) 337 pmf_class_network_register(self, ifp); 338 else 339 aprint_error_dev(self, "couldn't establish power handler\n"); 340 341 ieee80211_announce(ic); 342 343 return; 344 345 fail: ipw_detach(self, 0); 346 } 347 348 static int 349 ipw_detach(device_t self, int flags) 350 { 351 struct ipw_softc *sc = device_private(self); 352 struct ifnet *ifp = &sc->sc_if; 353 354 if (ifp->if_softc) { 355 ipw_stop(ifp, 1); 356 ipw_free_firmware(sc); 357 358 bpf_detach(ifp); 359 ieee80211_ifdetach(&sc->sc_ic); 360 if_detach(ifp); 361 362 ipw_release(sc); 363 } 364 365 if (sc->sc_ih != NULL) { 366 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 367 sc->sc_ih = NULL; 368 } 369 370 if (sc->sc_soft_ih != NULL) { 371 softint_disestablish(sc->sc_soft_ih); 372 sc->sc_soft_ih = NULL; 373 } 374 375 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 376 377 return 0; 378 } 379 380 static int 381 ipw_dma_alloc(struct ipw_softc *sc) 382 { 383 struct ipw_soft_bd *sbd; 384 struct ipw_soft_hdr *shdr; 385 struct ipw_soft_buf *sbuf; 386 int error, i, nsegs; 387 388 /* 389 * Allocate and map tx ring. 390 */ 391 error = bus_dmamap_create(sc->sc_dmat, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, 392 BUS_DMA_NOWAIT, &sc->tbd_map); 393 if (error != 0) { 394 aprint_error_dev(sc->sc_dev, "could not create tbd dma map\n"); 395 goto fail; 396 } 397 398 error = bus_dmamem_alloc(sc->sc_dmat, IPW_TBD_SZ, PAGE_SIZE, 0, 399 &sc->tbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 400 if (error != 0) { 401 aprint_error_dev(sc->sc_dev, "could not allocate tbd dma memory\n"); 402 goto fail; 403 } 404 405 error = bus_dmamem_map(sc->sc_dmat, &sc->tbd_seg, nsegs, IPW_TBD_SZ, 406 (void **)&sc->tbd_list, BUS_DMA_NOWAIT); 407 if (error != 0) { 408 aprint_error_dev(sc->sc_dev, "could not map tbd dma memory\n"); 409 goto fail; 410 } 411 412 error = bus_dmamap_load(sc->sc_dmat, sc->tbd_map, sc->tbd_list, 413 IPW_TBD_SZ, NULL, BUS_DMA_NOWAIT); 414 if (error != 0) { 415 aprint_error_dev(sc->sc_dev, "could not load tbd dma memory\n"); 416 goto fail; 417 } 418 419 (void)memset(sc->tbd_list, 0, IPW_TBD_SZ); 420 421 /* 422 * Allocate and map rx ring. 423 */ 424 error = bus_dmamap_create(sc->sc_dmat, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, 425 BUS_DMA_NOWAIT, &sc->rbd_map); 426 if (error != 0) { 427 aprint_error_dev(sc->sc_dev, "could not create rbd dma map\n"); 428 goto fail; 429 } 430 431 error = bus_dmamem_alloc(sc->sc_dmat, IPW_RBD_SZ, PAGE_SIZE, 0, 432 &sc->rbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 433 if (error != 0) { 434 aprint_error_dev(sc->sc_dev, "could not allocate rbd dma memory\n"); 435 goto fail; 436 } 437 438 error = bus_dmamem_map(sc->sc_dmat, &sc->rbd_seg, nsegs, IPW_RBD_SZ, 439 (void **)&sc->rbd_list, BUS_DMA_NOWAIT); 440 if (error != 0) { 441 aprint_error_dev(sc->sc_dev, "could not map rbd dma memory\n"); 442 goto fail; 443 } 444 445 error = bus_dmamap_load(sc->sc_dmat, sc->rbd_map, sc->rbd_list, 446 IPW_RBD_SZ, NULL, BUS_DMA_NOWAIT); 447 if (error != 0) { 448 aprint_error_dev(sc->sc_dev, "could not load rbd dma memory\n"); 449 goto fail; 450 } 451 452 (void)memset(sc->rbd_list, 0, IPW_RBD_SZ); 453 454 /* 455 * Allocate and map status ring. 456 */ 457 error = bus_dmamap_create(sc->sc_dmat, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 458 0, BUS_DMA_NOWAIT, &sc->status_map); 459 if (error != 0) { 460 aprint_error_dev(sc->sc_dev, "could not create status dma map\n"); 461 goto fail; 462 } 463 464 error = bus_dmamem_alloc(sc->sc_dmat, IPW_STATUS_SZ, PAGE_SIZE, 0, 465 &sc->status_seg, 1, &nsegs, BUS_DMA_NOWAIT); 466 if (error != 0) { 467 aprint_error_dev(sc->sc_dev, "could not allocate status dma memory\n"); 468 goto fail; 469 } 470 471 error = bus_dmamem_map(sc->sc_dmat, &sc->status_seg, nsegs, 472 IPW_STATUS_SZ, (void **)&sc->status_list, BUS_DMA_NOWAIT); 473 if (error != 0) { 474 aprint_error_dev(sc->sc_dev, "could not map status dma memory\n"); 475 goto fail; 476 } 477 478 error = bus_dmamap_load(sc->sc_dmat, sc->status_map, sc->status_list, 479 IPW_STATUS_SZ, NULL, BUS_DMA_NOWAIT); 480 if (error != 0) { 481 aprint_error_dev(sc->sc_dev, "could not load status dma memory\n"); 482 goto fail; 483 } 484 485 (void)memset(sc->status_list, 0, IPW_STATUS_SZ); 486 487 /* 488 * Allocate command DMA map. 489 */ 490 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_cmd), 491 1, sizeof (struct ipw_cmd), 0, BUS_DMA_NOWAIT, &sc->cmd_map); 492 if (error != 0) { 493 aprint_error_dev(sc->sc_dev, "could not create cmd dma map\n"); 494 goto fail; 495 } 496 497 error = bus_dmamem_alloc(sc->sc_dmat, sizeof (struct ipw_cmd), 498 PAGE_SIZE, 0, &sc->cmd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 499 if (error != 0) { 500 aprint_error_dev(sc->sc_dev, "could not allocate cmd dma memory\n"); 501 goto fail; 502 } 503 504 error = bus_dmamem_map(sc->sc_dmat, &sc->cmd_seg, nsegs, 505 sizeof (struct ipw_cmd), (void **)&sc->cmd, BUS_DMA_NOWAIT); 506 if (error != 0) { 507 aprint_error_dev(sc->sc_dev, "could not map cmd dma memory\n"); 508 goto fail; 509 } 510 511 error = bus_dmamap_load(sc->sc_dmat, sc->cmd_map, &sc->cmd, 512 sizeof (struct ipw_cmd), NULL, BUS_DMA_NOWAIT); 513 if (error != 0) { 514 aprint_error_dev(sc->sc_dev, "could not map cmd dma memory\n"); 515 return error; 516 } 517 518 /* 519 * Allocate and map hdr list. 520 */ 521 522 error = bus_dmamap_create(sc->sc_dmat, 523 IPW_NDATA * sizeof(struct ipw_hdr), 1, 524 sizeof(struct ipw_hdr), 0, BUS_DMA_NOWAIT, 525 &sc->hdr_map); 526 if (error != 0) { 527 aprint_error_dev(sc->sc_dev, "could not create hdr dma map\n"); 528 goto fail; 529 } 530 531 error = bus_dmamem_alloc(sc->sc_dmat, 532 IPW_NDATA * sizeof(struct ipw_hdr), PAGE_SIZE, 0, &sc->hdr_seg, 533 1, &nsegs, BUS_DMA_NOWAIT); 534 if (error != 0) { 535 aprint_error_dev(sc->sc_dev, "could not allocate hdr memory\n"); 536 goto fail; 537 } 538 539 error = bus_dmamem_map(sc->sc_dmat, &sc->hdr_seg, nsegs, 540 IPW_NDATA * sizeof(struct ipw_hdr), (void **)&sc->hdr_list, 541 BUS_DMA_NOWAIT); 542 if (error != 0) { 543 aprint_error_dev(sc->sc_dev, "could not map hdr memory\n"); 544 goto fail; 545 } 546 547 error = bus_dmamap_load(sc->sc_dmat, sc->hdr_map, sc->hdr_list, 548 IPW_NDATA * sizeof(struct ipw_hdr), NULL, BUS_DMA_NOWAIT); 549 if (error != 0) { 550 aprint_error_dev(sc->sc_dev, "could not load hdr memory\n"); 551 goto fail; 552 } 553 554 (void)memset(sc->hdr_list, 0, IPW_HDR_SZ); 555 556 /* 557 * Create DMA hdrs tailq. 558 */ 559 TAILQ_INIT(&sc->sc_free_shdr); 560 for (i = 0; i < IPW_NDATA; i++) { 561 shdr = &sc->shdr_list[i]; 562 shdr->hdr = sc->hdr_list + i; 563 shdr->offset = sizeof(struct ipw_hdr) * i; 564 shdr->addr = sc->hdr_map->dm_segs[0].ds_addr + shdr->offset; 565 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 566 } 567 568 /* 569 * Allocate tx buffers DMA maps. 570 */ 571 TAILQ_INIT(&sc->sc_free_sbuf); 572 for (i = 0; i < IPW_NDATA; i++) { 573 sbuf = &sc->tx_sbuf_list[i]; 574 575 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 576 IPW_MAX_NSEG, MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 577 if (error != 0) { 578 aprint_error_dev(sc->sc_dev, "could not create txbuf dma map\n"); 579 goto fail; 580 } 581 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 582 } 583 584 /* 585 * Initialize tx ring. 586 */ 587 for (i = 0; i < IPW_NTBD; i++) { 588 sbd = &sc->stbd_list[i]; 589 sbd->bd = &sc->tbd_list[i]; 590 sbd->type = IPW_SBD_TYPE_NOASSOC; 591 } 592 593 /* 594 * Pre-allocate rx buffers and DMA maps 595 */ 596 for (i = 0; i < IPW_NRBD; i++) { 597 sbd = &sc->srbd_list[i]; 598 sbuf = &sc->rx_sbuf_list[i]; 599 sbd->bd = &sc->rbd_list[i]; 600 601 MGETHDR(sbuf->m, M_DONTWAIT, MT_DATA); 602 if (sbuf->m == NULL) { 603 aprint_error_dev(sc->sc_dev, "could not allocate rx mbuf\n"); 604 error = ENOMEM; 605 goto fail; 606 } 607 608 MCLGET(sbuf->m, M_DONTWAIT); 609 if (!(sbuf->m->m_flags & M_EXT)) { 610 m_freem(sbuf->m); 611 sbuf->m = NULL; 612 aprint_error_dev(sc->sc_dev, "could not allocate rx mbuf cluster\n"); 613 error = ENOMEM; 614 goto fail; 615 } 616 617 sbuf->m->m_pkthdr.len = sbuf->m->m_len = sbuf->m->m_ext.ext_size; 618 619 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 620 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sbuf->map); 621 if (error != 0) { 622 aprint_error_dev(sc->sc_dev, "could not create rxbuf dma map\n"); 623 m_freem(sbuf->m); 624 sbuf->m = NULL; 625 goto fail; 626 } 627 628 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, 629 sbuf->m, BUS_DMA_READ | BUS_DMA_NOWAIT); 630 if (error != 0) { 631 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 632 sbuf->map = NULL; 633 m_freem(sbuf->m); 634 sbuf->m = NULL; 635 aprint_error_dev(sc->sc_dev, "could not map rxbuf dma memory\n"); 636 goto fail; 637 } 638 639 sbd->type = IPW_SBD_TYPE_DATA; 640 sbd->priv = sbuf; 641 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 642 sbd->bd->len = htole32(MCLBYTES); 643 644 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, 645 sbuf->map->dm_mapsize, BUS_DMASYNC_PREREAD); 646 647 } 648 649 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 0, IPW_RBD_SZ, 650 BUS_DMASYNC_PREREAD); 651 652 return 0; 653 654 fail: ipw_release(sc); 655 return error; 656 } 657 658 static void 659 ipw_release(struct ipw_softc *sc) 660 { 661 struct ipw_soft_buf *sbuf; 662 int i; 663 664 if (sc->tbd_map != NULL) { 665 if (sc->tbd_list != NULL) { 666 bus_dmamap_unload(sc->sc_dmat, sc->tbd_map); 667 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->tbd_list, 668 IPW_TBD_SZ); 669 bus_dmamem_free(sc->sc_dmat, &sc->tbd_seg, 1); 670 } 671 bus_dmamap_destroy(sc->sc_dmat, sc->tbd_map); 672 } 673 674 if (sc->rbd_map != NULL) { 675 if (sc->rbd_list != NULL) { 676 bus_dmamap_unload(sc->sc_dmat, sc->rbd_map); 677 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->rbd_list, 678 IPW_RBD_SZ); 679 bus_dmamem_free(sc->sc_dmat, &sc->rbd_seg, 1); 680 } 681 bus_dmamap_destroy(sc->sc_dmat, sc->rbd_map); 682 } 683 684 if (sc->status_map != NULL) { 685 if (sc->status_list != NULL) { 686 bus_dmamap_unload(sc->sc_dmat, sc->status_map); 687 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->status_list, 688 IPW_RBD_SZ); 689 bus_dmamem_free(sc->sc_dmat, &sc->status_seg, 1); 690 } 691 bus_dmamap_destroy(sc->sc_dmat, sc->status_map); 692 } 693 694 for (i = 0; i < IPW_NTBD; i++) 695 ipw_release_sbd(sc, &sc->stbd_list[i]); 696 697 if (sc->cmd_map != NULL) 698 bus_dmamap_destroy(sc->sc_dmat, sc->cmd_map); 699 700 if (sc->hdr_list != NULL) { 701 bus_dmamap_unload(sc->sc_dmat, sc->hdr_map); 702 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->hdr_list, 703 IPW_NDATA * sizeof(struct ipw_hdr)); 704 } 705 if (sc->hdr_map != NULL) { 706 bus_dmamem_free(sc->sc_dmat, &sc->hdr_seg, 1); 707 bus_dmamap_destroy(sc->sc_dmat, sc->hdr_map); 708 } 709 710 for (i = 0; i < IPW_NDATA; i++) 711 bus_dmamap_destroy(sc->sc_dmat, sc->tx_sbuf_list[i].map); 712 713 for (i = 0; i < IPW_NRBD; i++) { 714 sbuf = &sc->rx_sbuf_list[i]; 715 if (sbuf->map != NULL) { 716 if (sbuf->m != NULL) { 717 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 718 m_freem(sbuf->m); 719 } 720 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 721 } 722 } 723 724 } 725 726 static int 727 ipw_media_change(struct ifnet *ifp) 728 { 729 int error; 730 731 error = ieee80211_media_change(ifp); 732 if (error != ENETRESET) 733 return error; 734 735 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 736 ipw_init(ifp); 737 738 return 0; 739 } 740 741 /* 742 * The firmware automatically adapts the transmit speed. We report the current 743 * transmit speed here. 744 */ 745 static void 746 ipw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 747 { 748 #define N(a) (sizeof (a) / sizeof (a[0])) 749 struct ipw_softc *sc = ifp->if_softc; 750 struct ieee80211com *ic = &sc->sc_ic; 751 static const struct { 752 uint32_t val; 753 int rate; 754 } rates[] = { 755 { IPW_RATE_DS1, 2 }, 756 { IPW_RATE_DS2, 4 }, 757 { IPW_RATE_DS5, 11 }, 758 { IPW_RATE_DS11, 22 }, 759 }; 760 uint32_t val; 761 int rate, i; 762 763 imr->ifm_status = IFM_AVALID; 764 imr->ifm_active = IFM_IEEE80211; 765 if (ic->ic_state == IEEE80211_S_RUN) 766 imr->ifm_status |= IFM_ACTIVE; 767 768 /* read current transmission rate from adapter */ 769 val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE) & 0xf; 770 771 /* convert ipw rate to 802.11 rate */ 772 for (i = 0; i < N(rates) && rates[i].val != val; i++); 773 rate = (i < N(rates)) ? rates[i].rate : 0; 774 775 imr->ifm_active |= IFM_IEEE80211_11B; 776 imr->ifm_active |= ieee80211_rate2media(ic, rate, IEEE80211_MODE_11B); 777 switch (ic->ic_opmode) { 778 case IEEE80211_M_STA: 779 break; 780 781 case IEEE80211_M_IBSS: 782 imr->ifm_active |= IFM_IEEE80211_ADHOC; 783 break; 784 785 case IEEE80211_M_MONITOR: 786 imr->ifm_active |= IFM_IEEE80211_MONITOR; 787 break; 788 789 case IEEE80211_M_AHDEMO: 790 case IEEE80211_M_HOSTAP: 791 /* should not get there */ 792 break; 793 } 794 #undef N 795 } 796 797 static int 798 ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, 799 int arg) 800 { 801 struct ifnet *ifp = ic->ic_ifp; 802 struct ipw_softc *sc = ifp->if_softc; 803 struct ieee80211_node *ni; 804 uint8_t macaddr[IEEE80211_ADDR_LEN]; 805 uint32_t len; 806 struct ipw_rx_radiotap_header *wr = &sc->sc_rxtap; 807 struct ipw_tx_radiotap_header *wt = &sc->sc_txtap; 808 809 switch (nstate) { 810 case IEEE80211_S_INIT: 811 break; 812 default: 813 KASSERT(ic->ic_curchan != IEEE80211_CHAN_ANYC); 814 KASSERT(ic->ic_curchan != NULL); 815 wt->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 816 wt->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 817 wr->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 818 wr->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 819 break; 820 } 821 822 switch (nstate) { 823 case IEEE80211_S_RUN: 824 DELAY(200); /* firmware needs a short delay here */ 825 826 len = IEEE80211_ADDR_LEN; 827 ipw_read_table2(sc, IPW_INFO_CURRENT_BSSID, macaddr, &len); 828 829 ni = ieee80211_find_node(&ic->ic_scan, macaddr); 830 if (ni == NULL) 831 break; 832 833 ieee80211_ref_node(ni); 834 ieee80211_sta_join(ic, ni); 835 ieee80211_node_authorize(ni); 836 837 if (ic->ic_opmode == IEEE80211_M_STA) 838 ieee80211_notify_node_join(ic, ni, 1); 839 break; 840 841 case IEEE80211_S_INIT: 842 case IEEE80211_S_SCAN: 843 case IEEE80211_S_AUTH: 844 case IEEE80211_S_ASSOC: 845 break; 846 } 847 848 ic->ic_state = nstate; 849 return 0; 850 } 851 852 /* 853 * Read 16 bits at address 'addr' from the serial EEPROM. 854 */ 855 static uint16_t 856 ipw_read_prom_word(struct ipw_softc *sc, uint8_t addr) 857 { 858 uint32_t tmp; 859 uint16_t val; 860 int n; 861 862 /* clock C once before the first command */ 863 IPW_EEPROM_CTL(sc, 0); 864 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 865 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 866 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 867 868 /* write start bit (1) */ 869 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 870 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 871 872 /* write READ opcode (10) */ 873 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 874 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 875 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 876 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 877 878 /* write address A7-A0 */ 879 for (n = 7; n >= 0; n--) { 880 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 881 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D)); 882 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 883 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D) | IPW_EEPROM_C); 884 } 885 886 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 887 888 /* read data Q15-Q0 */ 889 val = 0; 890 for (n = 15; n >= 0; n--) { 891 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 892 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 893 tmp = MEM_READ_4(sc, IPW_MEM_EEPROM_CTL); 894 val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n; 895 } 896 897 IPW_EEPROM_CTL(sc, 0); 898 899 /* clear Chip Select and clock C */ 900 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 901 IPW_EEPROM_CTL(sc, 0); 902 IPW_EEPROM_CTL(sc, IPW_EEPROM_C); 903 904 return le16toh(val); 905 } 906 907 static void 908 ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 909 { 910 911 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof (struct ipw_cmd), 912 BUS_DMASYNC_POSTREAD); 913 914 #ifdef IPW_DEBUG 915 struct ipw_cmd *cmd = mtod(sbuf->m, struct ipw_cmd *); 916 917 DPRINTFN(2, ("cmd ack'ed (%u, %u, %u, %u, %u)\n", le32toh(cmd->type), 918 le32toh(cmd->subtype), le32toh(cmd->seq), le32toh(cmd->len), 919 le32toh(cmd->status))); 920 #endif 921 922 wakeup(&sc->cmd); 923 } 924 925 static void 926 ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 927 { 928 struct ieee80211com *ic = &sc->sc_ic; 929 struct ifnet *ifp = sc->sc_ic.ic_ifp; 930 uint32_t state; 931 int s; 932 933 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof state, 934 BUS_DMASYNC_POSTREAD); 935 936 state = le32toh(*mtod(sbuf->m, uint32_t *)); 937 938 DPRINTFN(2, ("entering state %u\n", state)); 939 940 s = splnet(); 941 942 switch (state) { 943 case IPW_STATE_ASSOCIATED: 944 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 945 break; 946 947 case IPW_STATE_SCANNING: 948 /* don't leave run state on background scan */ 949 if (ic->ic_state != IEEE80211_S_RUN) 950 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 951 952 ic->ic_flags |= IEEE80211_F_SCAN; 953 break; 954 955 case IPW_STATE_SCAN_COMPLETE: 956 ieee80211_notify_scan_done(ic); 957 ic->ic_flags &= ~IEEE80211_F_SCAN; 958 break; 959 960 case IPW_STATE_ASSOCIATION_LOST: 961 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 962 break; 963 964 case IPW_STATE_RADIO_DISABLED: 965 ic->ic_ifp->if_flags &= ~IFF_UP; 966 ipw_stop(ifp, 1); 967 break; 968 } 969 970 splx(s); 971 } 972 973 /* 974 * XXX: Hack to set the current channel to the value advertised in beacons or 975 * probe responses. Only used during AP detection. 976 */ 977 static void 978 ipw_fix_channel(struct ieee80211com *ic, struct mbuf *m) 979 { 980 struct ieee80211_frame *wh; 981 uint8_t subtype; 982 uint8_t *frm, *efrm; 983 984 wh = mtod(m, struct ieee80211_frame *); 985 986 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_MGT) 987 return; 988 989 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 990 991 if (subtype != IEEE80211_FC0_SUBTYPE_BEACON && 992 subtype != IEEE80211_FC0_SUBTYPE_PROBE_RESP) 993 return; 994 995 frm = (uint8_t *)(wh + 1); 996 efrm = mtod(m, uint8_t *) + m->m_len; 997 998 frm += 12; /* skip tstamp, bintval and capinfo fields */ 999 while (frm + 2 < efrm) { 1000 if (*frm == IEEE80211_ELEMID_DSPARMS) { 1001 #if IEEE80211_CHAN_MAX < 255 1002 if (frm[2] <= IEEE80211_CHAN_MAX) 1003 #endif 1004 ic->ic_curchan = &ic->ic_channels[frm[2]]; 1005 } 1006 1007 frm += frm[1] + 2; 1008 } 1009 } 1010 1011 static void 1012 ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 1013 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 1014 { 1015 struct ieee80211com *ic = &sc->sc_ic; 1016 struct ifnet *ifp = &sc->sc_if; 1017 struct mbuf *mnew, *m; 1018 struct ieee80211_frame *wh; 1019 struct ieee80211_node *ni; 1020 int error, s; 1021 1022 DPRINTFN(5, ("received frame len=%u, rssi=%u\n", le32toh(status->len), 1023 status->rssi)); 1024 1025 if (le32toh(status->len) < sizeof (struct ieee80211_frame_min) || 1026 le32toh(status->len) > MCLBYTES) 1027 return; 1028 1029 /* 1030 * Try to allocate a new mbuf for this ring element and load it before 1031 * processing the current mbuf. If the ring element cannot be loaded, 1032 * drop the received packet and reuse the old mbuf. In the unlikely 1033 * case that the old mbuf can't be reloaded either, explicitly panic. 1034 */ 1035 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1036 if (mnew == NULL) { 1037 aprint_error_dev(sc->sc_dev, "could not allocate rx mbuf\n"); 1038 if_statinc(ifp, if_ierrors); 1039 return; 1040 } 1041 1042 MCLGET(mnew, M_DONTWAIT); 1043 if (!(mnew->m_flags & M_EXT)) { 1044 aprint_error_dev(sc->sc_dev, "could not allocate rx mbuf cluster\n"); 1045 m_freem(mnew); 1046 if_statinc(ifp, if_ierrors); 1047 return; 1048 } 1049 1050 mnew->m_pkthdr.len = mnew->m_len = mnew->m_ext.ext_size; 1051 1052 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, le32toh(status->len), 1053 BUS_DMASYNC_POSTREAD); 1054 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1055 1056 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, mnew, 1057 BUS_DMA_READ | BUS_DMA_NOWAIT); 1058 if (error != 0) { 1059 aprint_error_dev(sc->sc_dev, "could not load rx buf DMA map\n"); 1060 m_freem(mnew); 1061 1062 /* try to reload the old mbuf */ 1063 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, 1064 sbuf->m, BUS_DMA_READ | BUS_DMA_NOWAIT); 1065 if (error != 0) { 1066 /* very unlikely that it will fail... */ 1067 panic("%s: unable to remap rx buf", 1068 device_xname(sc->sc_dev)); 1069 } 1070 if_statinc(ifp, if_ierrors); 1071 return; 1072 } 1073 1074 /* 1075 * New mbuf successfully loaded, update Rx ring and continue 1076 * processing. 1077 */ 1078 m = sbuf->m; 1079 sbuf->m = mnew; 1080 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 1081 1082 /* finalize mbuf */ 1083 m_set_rcvif(m, ifp); 1084 m->m_pkthdr.len = m->m_len = le32toh(status->len); 1085 1086 s = splnet(); 1087 1088 if (sc->sc_drvbpf != NULL) { 1089 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 1090 1091 tap->wr_antsignal = status->rssi; 1092 1093 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m, BPF_D_IN); 1094 } 1095 1096 if (ic->ic_state == IEEE80211_S_SCAN) 1097 ipw_fix_channel(ic, m); 1098 1099 wh = mtod(m, struct ieee80211_frame *); 1100 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 1101 1102 /* send the frame to the 802.11 layer */ 1103 ieee80211_input(ic, m, ni, status->rssi, 0); 1104 1105 /* node is no longer needed */ 1106 ieee80211_free_node(ni); 1107 1108 splx(s); 1109 1110 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, 1111 sbuf->map->dm_mapsize, BUS_DMASYNC_PREREAD); 1112 } 1113 1114 static void 1115 ipw_rx_intr(struct ipw_softc *sc) 1116 { 1117 struct ipw_status *status; 1118 struct ipw_soft_bd *sbd; 1119 struct ipw_soft_buf *sbuf; 1120 uint32_t r, i; 1121 1122 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1123 return; 1124 1125 r = CSR_READ_4(sc, IPW_CSR_RX_READ); 1126 1127 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 1128 1129 /* firmware was killed, stop processing received frames */ 1130 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1131 return; 1132 1133 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 1134 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1135 BUS_DMASYNC_POSTREAD); 1136 1137 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 1138 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 1139 BUS_DMASYNC_POSTREAD); 1140 1141 status = &sc->status_list[i]; 1142 sbd = &sc->srbd_list[i]; 1143 sbuf = sbd->priv; 1144 1145 switch (le16toh(status->code) & 0xf) { 1146 case IPW_STATUS_CODE_COMMAND: 1147 ipw_command_intr(sc, sbuf); 1148 break; 1149 1150 case IPW_STATUS_CODE_NEWSTATE: 1151 ipw_newstate_intr(sc, sbuf); 1152 break; 1153 1154 case IPW_STATUS_CODE_DATA_802_3: 1155 case IPW_STATUS_CODE_DATA_802_11: 1156 ipw_data_intr(sc, status, sbd, sbuf); 1157 break; 1158 1159 case IPW_STATUS_CODE_NOTIFICATION: 1160 DPRINTFN(2, ("received notification\n")); 1161 break; 1162 1163 default: 1164 aprint_error_dev(sc->sc_dev, "unknown status code %u\n", 1165 le16toh(status->code)); 1166 } 1167 1168 sbd->bd->flags = 0; 1169 1170 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 1171 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1172 BUS_DMASYNC_PREREAD); 1173 1174 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 1175 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 1176 BUS_DMASYNC_PREREAD); 1177 } 1178 1179 /* Tell the firmware what we have processed */ 1180 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 1181 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 1182 } 1183 1184 static void 1185 ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 1186 { 1187 struct ipw_soft_hdr *shdr; 1188 struct ipw_soft_buf *sbuf; 1189 1190 switch (sbd->type) { 1191 case IPW_SBD_TYPE_COMMAND: 1192 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 1193 0, sizeof(struct ipw_cmd), BUS_DMASYNC_POSTWRITE); 1194 /* bus_dmamap_unload(sc->sc_dmat, sc->cmd_map); */ 1195 break; 1196 1197 case IPW_SBD_TYPE_HEADER: 1198 shdr = sbd->priv; 1199 bus_dmamap_sync(sc->sc_dmat, sc->hdr_map, 1200 shdr->offset, sizeof(struct ipw_hdr), BUS_DMASYNC_POSTWRITE); 1201 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 1202 break; 1203 1204 case IPW_SBD_TYPE_DATA: 1205 sbuf = sbd->priv; 1206 1207 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 1208 0, sbuf->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1209 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1210 m_freem(sbuf->m); 1211 if (sbuf->ni != NULL) 1212 ieee80211_free_node(sbuf->ni); 1213 /* kill watchdog timer */ 1214 sc->sc_tx_timer = 0; 1215 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 1216 break; 1217 } 1218 sbd->type = IPW_SBD_TYPE_NOASSOC; 1219 } 1220 1221 static void 1222 ipw_tx_intr(struct ipw_softc *sc) 1223 { 1224 struct ifnet *ifp = &sc->sc_if; 1225 struct ipw_soft_bd *sbd; 1226 uint32_t r, i; 1227 int s; 1228 1229 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1230 return; 1231 1232 s = splnet(); 1233 1234 r = CSR_READ_4(sc, IPW_CSR_TX_READ); 1235 1236 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) { 1237 sbd = &sc->stbd_list[i]; 1238 1239 if (sbd->type == IPW_SBD_TYPE_DATA) 1240 if_statinc(ifp, if_opackets); 1241 1242 ipw_release_sbd(sc, sbd); 1243 sc->txfree++; 1244 } 1245 1246 /* remember what the firmware has processed */ 1247 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 1248 1249 /* Call start() since some buffer descriptors have been released */ 1250 ifp->if_flags &= ~IFF_OACTIVE; 1251 ipw_start(ifp); /* in softint */ 1252 1253 splx(s); 1254 } 1255 1256 static int 1257 ipw_intr(void *arg) 1258 { 1259 struct ipw_softc *sc = arg; 1260 uint32_t r; 1261 1262 r = CSR_READ_4(sc, IPW_CSR_INTR); 1263 if (r == 0 || r == 0xffffffff) 1264 return 0; 1265 1266 /* Disable interrupts */ 1267 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1268 1269 softint_schedule(sc->sc_soft_ih); 1270 return 1; 1271 } 1272 1273 static void 1274 ipw_softintr(void *arg) 1275 { 1276 struct ipw_softc *sc = arg; 1277 uint32_t r; 1278 int s; 1279 1280 r = CSR_READ_4(sc, IPW_CSR_INTR); 1281 if (r == 0 || r == 0xffffffff) 1282 goto out; 1283 1284 if (r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR)) { 1285 aprint_error_dev(sc->sc_dev, "fatal error\n"); 1286 s = splnet(); 1287 sc->sc_ic.ic_ifp->if_flags &= ~IFF_UP; 1288 ipw_stop(&sc->sc_if, 1); 1289 splx(s); 1290 } 1291 1292 if (r & IPW_INTR_FW_INIT_DONE) { 1293 if (!(r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR))) 1294 wakeup(sc); 1295 } 1296 1297 if (r & IPW_INTR_RX_TRANSFER) 1298 ipw_rx_intr(sc); 1299 1300 if (r & IPW_INTR_TX_TRANSFER) 1301 ipw_tx_intr(sc); 1302 1303 /* Acknowledge all interrupts */ 1304 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 1305 1306 out: 1307 /* Re-enable interrupts */ 1308 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1309 } 1310 1311 /* 1312 * Send a command to the firmware and wait for the acknowledgement. 1313 */ 1314 static int 1315 ipw_cmd(struct ipw_softc *sc, uint32_t type, void *data, uint32_t len) 1316 { 1317 struct ipw_soft_bd *sbd; 1318 1319 sbd = &sc->stbd_list[sc->txcur]; 1320 1321 sc->cmd.type = htole32(type); 1322 sc->cmd.subtype = 0; 1323 sc->cmd.len = htole32(len); 1324 sc->cmd.seq = 0; 1325 1326 (void)memcpy(sc->cmd.data, data, len); 1327 1328 sbd->type = IPW_SBD_TYPE_COMMAND; 1329 sbd->bd->physaddr = htole32(sc->cmd_map->dm_segs[0].ds_addr); 1330 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 1331 sbd->bd->nfrag = 1; 1332 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 1333 IPW_BD_FLAG_TX_LAST_FRAGMENT; 1334 1335 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 0, sizeof (struct ipw_cmd), 1336 BUS_DMASYNC_PREWRITE); 1337 1338 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1339 sc->txcur * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1340 BUS_DMASYNC_PREWRITE); 1341 1342 DPRINTFN(2, ("sending command (%u, %u, %u, %u)\n", type, 0, 0, len)); 1343 1344 /* kick firmware */ 1345 sc->txfree--; 1346 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1347 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1348 1349 /* Wait at most one second for command to complete */ 1350 return tsleep(&sc->cmd, 0, "ipwcmd", hz); 1351 } 1352 1353 static int 1354 ipw_tx_start(struct ifnet *ifp, struct mbuf *m0, struct ieee80211_node *ni) 1355 { 1356 struct ipw_softc *sc = ifp->if_softc; 1357 struct ieee80211com *ic = &sc->sc_ic; 1358 struct ieee80211_frame *wh; 1359 struct ipw_soft_bd *sbd; 1360 struct ipw_soft_hdr *shdr; 1361 struct ipw_soft_buf *sbuf; 1362 struct ieee80211_key *k; 1363 struct mbuf *mnew; 1364 int error, i; 1365 1366 wh = mtod(m0, struct ieee80211_frame *); 1367 1368 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1369 k = ieee80211_crypto_encap(ic, ni, m0); 1370 if (k == NULL) { 1371 m_freem(m0); 1372 return ENOBUFS; 1373 } 1374 1375 /* packet header may have moved, reset our local pointer */ 1376 wh = mtod(m0, struct ieee80211_frame *); 1377 } 1378 1379 if (sc->sc_drvbpf != NULL) { 1380 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 1381 1382 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0, BPF_D_OUT); 1383 } 1384 1385 shdr = TAILQ_FIRST(&sc->sc_free_shdr); 1386 sbuf = TAILQ_FIRST(&sc->sc_free_sbuf); 1387 KASSERT(shdr != NULL && sbuf != NULL); 1388 1389 shdr->hdr->type = htole32(IPW_HDR_TYPE_SEND); 1390 shdr->hdr->subtype = 0; 1391 shdr->hdr->encrypted = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0; 1392 shdr->hdr->encrypt = 0; 1393 shdr->hdr->keyidx = 0; 1394 shdr->hdr->keysz = 0; 1395 shdr->hdr->fragmentsz = 0; 1396 IEEE80211_ADDR_COPY(shdr->hdr->src_addr, wh->i_addr2); 1397 if (ic->ic_opmode == IEEE80211_M_STA) 1398 IEEE80211_ADDR_COPY(shdr->hdr->dst_addr, wh->i_addr3); 1399 else 1400 IEEE80211_ADDR_COPY(shdr->hdr->dst_addr, wh->i_addr1); 1401 1402 /* trim IEEE802.11 header */ 1403 m_adj(m0, sizeof (struct ieee80211_frame)); 1404 1405 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m0, 1406 BUS_DMA_NOWAIT); 1407 if (error != 0 && error != EFBIG) { 1408 aprint_error_dev(sc->sc_dev, "could not map mbuf (error %d)\n", 1409 error); 1410 m_freem(m0); 1411 return error; 1412 } 1413 1414 if (error != 0) { 1415 /* too many fragments, linearize */ 1416 1417 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1418 if (mnew == NULL) { 1419 m_freem(m0); 1420 return ENOMEM; 1421 } 1422 1423 m_copy_pkthdr(mnew, m0); 1424 1425 /* If the data won't fit in the header, get a cluster */ 1426 if (m0->m_pkthdr.len > MHLEN) { 1427 MCLGET(mnew, M_DONTWAIT); 1428 if (!(mnew->m_flags & M_EXT)) { 1429 m_freem(m0); 1430 m_freem(mnew); 1431 return ENOMEM; 1432 } 1433 } 1434 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(mnew, void *)); 1435 m_freem(m0); 1436 mnew->m_len = mnew->m_pkthdr.len; 1437 m0 = mnew; 1438 1439 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m0, 1440 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1441 if (error != 0) { 1442 aprint_error_dev(sc->sc_dev, 1443 "could not map mbuf (error %d)\n", error); 1444 m_freem(m0); 1445 return error; 1446 } 1447 } 1448 1449 TAILQ_REMOVE(&sc->sc_free_sbuf, sbuf, next); 1450 TAILQ_REMOVE(&sc->sc_free_shdr, shdr, next); 1451 1452 sbd = &sc->stbd_list[sc->txcur]; 1453 sbd->type = IPW_SBD_TYPE_HEADER; 1454 sbd->priv = shdr; 1455 sbd->bd->physaddr = htole32(shdr->addr); 1456 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 1457 sbd->bd->nfrag = 1 + sbuf->map->dm_nsegs; 1458 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 1459 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1460 1461 DPRINTFN(5, ("sending tx hdr (%u, %u, %u, %u, )\n", 1462 shdr->hdr->type, shdr->hdr->subtype, shdr->hdr->encrypted, 1463 shdr->hdr->encrypt)); 1464 DPRINTFN(5, ("%s->", ether_sprintf(shdr->hdr->src_addr))); 1465 DPRINTFN(5, ("%s\n", ether_sprintf(shdr->hdr->dst_addr))); 1466 1467 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1468 sc->txcur * sizeof (struct ipw_bd), 1469 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1470 1471 sc->txfree--; 1472 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1473 1474 sbuf->m = m0; 1475 sbuf->ni = ni; 1476 1477 for (i = 0; i < sbuf->map->dm_nsegs; i++) { 1478 sbd = &sc->stbd_list[sc->txcur]; 1479 1480 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[i].ds_addr); 1481 sbd->bd->len = htole32(sbuf->map->dm_segs[i].ds_len); 1482 sbd->bd->nfrag = 0; 1483 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 1484 if (i == sbuf->map->dm_nsegs - 1) { 1485 sbd->type = IPW_SBD_TYPE_DATA; 1486 sbd->priv = sbuf; 1487 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 1488 } else { 1489 sbd->type = IPW_SBD_TYPE_NOASSOC; 1490 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1491 } 1492 1493 DPRINTFN(5, ("sending fragment (%d, %d)\n", i, 1494 (int)sbuf->map->dm_segs[i].ds_len)); 1495 1496 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1497 sc->txcur * sizeof (struct ipw_bd), 1498 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1499 1500 sc->txfree--; 1501 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1502 } 1503 1504 bus_dmamap_sync(sc->sc_dmat, sc->hdr_map, shdr->offset, 1505 sizeof (struct ipw_hdr), BUS_DMASYNC_PREWRITE); 1506 1507 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sbuf->map->dm_mapsize, 1508 BUS_DMASYNC_PREWRITE); 1509 1510 /* Inform firmware about this new packet */ 1511 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1512 1513 return 0; 1514 } 1515 1516 static void 1517 ipw_start(struct ifnet *ifp) 1518 { 1519 struct ipw_softc *sc = ifp->if_softc; 1520 struct ieee80211com *ic = &sc->sc_ic; 1521 struct mbuf *m0; 1522 struct ether_header *eh; 1523 struct ieee80211_node *ni; 1524 1525 if (ic->ic_state != IEEE80211_S_RUN) 1526 return; 1527 1528 for (;;) { 1529 IF_DEQUEUE(&ifp->if_snd, m0); 1530 if (m0 == NULL) 1531 break; 1532 1533 if (sc->txfree < 1 + IPW_MAX_NSEG) { 1534 IF_PREPEND(&ifp->if_snd, m0); 1535 ifp->if_flags |= IFF_OACTIVE; 1536 break; 1537 } 1538 1539 if (m0->m_len < sizeof (struct ether_header) && 1540 (m0 = m_pullup(m0, sizeof (struct ether_header))) == NULL) 1541 continue; 1542 1543 eh = mtod(m0, struct ether_header *); 1544 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1545 if (ni == NULL) { 1546 m_freem(m0); 1547 continue; 1548 } 1549 1550 bpf_mtap(ifp, m0, BPF_D_OUT); 1551 1552 m0 = ieee80211_encap(ic, m0, ni); 1553 if (m0 == NULL) { 1554 ieee80211_free_node(ni); 1555 continue; 1556 } 1557 1558 bpf_mtap3(ic->ic_rawbpf, m0, BPF_D_OUT); 1559 1560 if (ipw_tx_start(ifp, m0, ni) != 0) { 1561 ieee80211_free_node(ni); 1562 if_statinc(ifp, if_oerrors); 1563 break; 1564 } 1565 1566 /* start watchdog timer */ 1567 sc->sc_tx_timer = 5; 1568 ifp->if_timer = 1; 1569 } 1570 } 1571 1572 static void 1573 ipw_watchdog(struct ifnet *ifp) 1574 { 1575 struct ipw_softc *sc = ifp->if_softc; 1576 1577 ifp->if_timer = 0; 1578 1579 if (sc->sc_tx_timer > 0) { 1580 if (--sc->sc_tx_timer == 0) { 1581 aprint_error_dev(sc->sc_dev, "device timeout\n"); 1582 if_statinc(ifp, if_oerrors); 1583 ifp->if_flags &= ~IFF_UP; 1584 ipw_stop(ifp, 1); 1585 return; 1586 } 1587 ifp->if_timer = 1; 1588 } 1589 1590 ieee80211_watchdog(&sc->sc_ic); 1591 } 1592 1593 static int 1594 ipw_get_table1(struct ipw_softc *sc, uint32_t *tbl) 1595 { 1596 uint32_t addr, size, data, i; 1597 int error; 1598 1599 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1600 return ENOTTY; 1601 1602 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, sc->table1_base); 1603 1604 size = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 1605 if ((error = copyout(&size, tbl, sizeof(size))) != 0) 1606 return error; 1607 1608 for (i = 1, ++tbl; i < size; i++, tbl++) { 1609 addr = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 1610 data = MEM_READ_4(sc, addr); 1611 if ((error = copyout(&data, tbl, sizeof(data))) != 0) 1612 return error; 1613 } 1614 return 0; 1615 } 1616 1617 static int 1618 ipw_get_radio(struct ipw_softc *sc, int *ret) 1619 { 1620 uint32_t addr, data; 1621 1622 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1623 return ENOTTY; 1624 1625 addr = ipw_read_table1(sc, IPW_INFO_EEPROM_ADDRESS); 1626 if ((MEM_READ_4(sc, addr + 32) >> 24) & 1) 1627 data = -1; 1628 else if (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED) 1629 data = 0; 1630 else 1631 data = 1; 1632 1633 return copyout(&data, ret, sizeof(data)); 1634 } 1635 1636 static int 1637 ipw_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1638 { 1639 #define IS_RUNNING(ifp) \ 1640 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 1641 1642 struct ipw_softc *sc = ifp->if_softc; 1643 struct ieee80211com *ic = &sc->sc_ic; 1644 struct ifreq *ifr = (struct ifreq *)data; 1645 int s, error = 0; 1646 1647 s = splnet(); 1648 1649 switch (cmd) { 1650 case SIOCSIFFLAGS: 1651 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 1652 break; 1653 if (ifp->if_flags & IFF_UP) { 1654 if (!(ifp->if_flags & IFF_RUNNING)) 1655 ipw_init(ifp); 1656 } else { 1657 if (ifp->if_flags & IFF_RUNNING) 1658 ipw_stop(ifp, 1); 1659 } 1660 break; 1661 1662 case SIOCADDMULTI: 1663 case SIOCDELMULTI: 1664 /* XXX no h/w multicast filter? --dyoung */ 1665 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1666 /* setup multicast filter, etc */ 1667 error = 0; 1668 } 1669 break; 1670 1671 case SIOCGTABLE1: 1672 error = ipw_get_table1(sc, (uint32_t *)ifr->ifr_data); 1673 break; 1674 1675 case SIOCGRADIO: 1676 error = ipw_get_radio(sc, (int *)ifr->ifr_data); 1677 break; 1678 1679 case SIOCSIFMEDIA: 1680 if (ifr->ifr_media & IFM_IEEE80211_ADHOC) 1681 sc->sc_fwname = "ipw2100-1.2-i.fw"; 1682 else if (ifr->ifr_media & IFM_IEEE80211_MONITOR) 1683 sc->sc_fwname = "ipw2100-1.2-p.fw"; 1684 else 1685 sc->sc_fwname = "ipw2100-1.2.fw"; 1686 1687 ipw_free_firmware(sc); 1688 /* FALLTHROUGH */ 1689 default: 1690 error = ieee80211_ioctl(&sc->sc_ic, cmd, data); 1691 if (error != ENETRESET) 1692 break; 1693 1694 if (error == ENETRESET) { 1695 if (IS_RUNNING(ifp) && 1696 (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)) 1697 ipw_init(ifp); 1698 error = 0; 1699 } 1700 1701 } 1702 1703 splx(s); 1704 return error; 1705 #undef IS_RUNNING 1706 } 1707 1708 static uint32_t 1709 ipw_read_table1(struct ipw_softc *sc, uint32_t off) 1710 { 1711 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 1712 } 1713 1714 static void 1715 ipw_write_table1(struct ipw_softc *sc, uint32_t off, uint32_t info) 1716 { 1717 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 1718 } 1719 1720 static int 1721 ipw_read_table2(struct ipw_softc *sc, uint32_t off, void *buf, uint32_t *len) 1722 { 1723 uint32_t addr, info; 1724 uint16_t count, size; 1725 uint32_t total; 1726 1727 /* addr[4] + count[2] + size[2] */ 1728 addr = MEM_READ_4(sc, sc->table2_base + off); 1729 info = MEM_READ_4(sc, sc->table2_base + off + 4); 1730 1731 count = info >> 16; 1732 size = info & 0xffff; 1733 total = count * size; 1734 1735 if (total > *len) { 1736 *len = total; 1737 return EINVAL; 1738 } 1739 1740 *len = total; 1741 ipw_read_mem_1(sc, addr, buf, total); 1742 1743 return 0; 1744 } 1745 1746 static void 1747 ipw_stop_master(struct ipw_softc *sc) 1748 { 1749 int ntries; 1750 1751 /* disable interrupts */ 1752 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1753 1754 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1755 for (ntries = 0; ntries < 50; ntries++) { 1756 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1757 break; 1758 DELAY(10); 1759 } 1760 if (ntries == 50) 1761 aprint_error_dev(sc->sc_dev, "timeout waiting for master\n"); 1762 1763 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1764 IPW_RST_PRINCETON_RESET); 1765 1766 sc->flags &= ~IPW_FLAG_FW_INITED; 1767 } 1768 1769 static int 1770 ipw_reset(struct ipw_softc *sc) 1771 { 1772 int ntries; 1773 1774 ipw_stop_master(sc); 1775 1776 /* move adapter to D0 state */ 1777 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1778 IPW_CTL_INIT); 1779 1780 /* wait for clock stabilization */ 1781 for (ntries = 0; ntries < 1000; ntries++) { 1782 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY) 1783 break; 1784 DELAY(200); 1785 } 1786 if (ntries == 1000) 1787 return EIO; 1788 1789 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1790 IPW_RST_SW_RESET); 1791 1792 DELAY(10); 1793 1794 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1795 IPW_CTL_INIT); 1796 1797 return 0; 1798 } 1799 1800 /* 1801 * Upload the microcode to the device. 1802 */ 1803 static int 1804 ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size) 1805 { 1806 int ntries; 1807 1808 MEM_WRITE_4(sc, 0x3000e0, 0x80000000); 1809 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1810 1811 MEM_WRITE_2(sc, 0x220000, 0x0703); 1812 MEM_WRITE_2(sc, 0x220000, 0x0707); 1813 1814 MEM_WRITE_1(sc, 0x210014, 0x72); 1815 MEM_WRITE_1(sc, 0x210014, 0x72); 1816 1817 MEM_WRITE_1(sc, 0x210000, 0x40); 1818 MEM_WRITE_1(sc, 0x210000, 0x00); 1819 MEM_WRITE_1(sc, 0x210000, 0x40); 1820 1821 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1822 1823 MEM_WRITE_1(sc, 0x210000, 0x00); 1824 MEM_WRITE_1(sc, 0x210000, 0x00); 1825 MEM_WRITE_1(sc, 0x210000, 0x80); 1826 1827 MEM_WRITE_2(sc, 0x220000, 0x0703); 1828 MEM_WRITE_2(sc, 0x220000, 0x0707); 1829 1830 MEM_WRITE_1(sc, 0x210014, 0x72); 1831 MEM_WRITE_1(sc, 0x210014, 0x72); 1832 1833 MEM_WRITE_1(sc, 0x210000, 0x00); 1834 MEM_WRITE_1(sc, 0x210000, 0x80); 1835 1836 for (ntries = 0; ntries < 10; ntries++) { 1837 if (MEM_READ_1(sc, 0x210000) & 1) 1838 break; 1839 DELAY(10); 1840 } 1841 if (ntries == 10) { 1842 aprint_error_dev(sc->sc_dev, "timeout waiting for ucode to initialize\n"); 1843 return EIO; 1844 } 1845 1846 MEM_WRITE_4(sc, 0x3000e0, 0); 1847 1848 return 0; 1849 } 1850 1851 /* set of macros to handle unaligned little endian data in firmware image */ 1852 #define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1853 #define GETLE16(p) ((p)[0] | (p)[1] << 8) 1854 static int 1855 ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size) 1856 { 1857 u_char *p, *end; 1858 uint32_t dst; 1859 uint16_t len; 1860 int error; 1861 1862 p = fw; 1863 end = fw + size; 1864 while (p < end) { 1865 dst = GETLE32(p); p += 4; 1866 len = GETLE16(p); p += 2; 1867 1868 ipw_write_mem_1(sc, dst, p, len); 1869 p += len; 1870 } 1871 1872 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1873 IPW_IO_LED_OFF); 1874 1875 /* enable interrupts */ 1876 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1877 1878 /* kick the firmware */ 1879 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1880 1881 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1882 IPW_CTL_ALLOW_STANDBY); 1883 1884 /* wait at most one second for firmware initialization to complete */ 1885 if ((error = tsleep(sc, 0, "ipwinit", hz)) != 0) { 1886 aprint_error_dev(sc->sc_dev, 1887 "timeout waiting for firmware initialization " 1888 "to complete\n"); 1889 return error; 1890 } 1891 1892 CSR_WRITE_4(sc, IPW_CSR_IO, CSR_READ_4(sc, IPW_CSR_IO) | 1893 IPW_IO_GPIO1_MASK | IPW_IO_GPIO3_MASK); 1894 1895 return 0; 1896 } 1897 1898 /* 1899 * Store firmware into kernel memory so we can download it when we need to, 1900 * e.g when the adapter wakes up from suspend mode. 1901 */ 1902 static int 1903 ipw_cache_firmware(struct ipw_softc *sc) 1904 { 1905 struct ipw_firmware *fw = &sc->fw; 1906 struct ipw_firmware_hdr hdr; 1907 firmware_handle_t fwh; 1908 off_t fwsz, p; 1909 int error; 1910 1911 ipw_free_firmware(sc); 1912 1913 if (ipw_accept_eula == 0) { 1914 aprint_error_dev(sc->sc_dev, 1915 "EULA not accepted; please see the ipw(4) man page.\n"); 1916 return EPERM; 1917 } 1918 1919 if ((error = firmware_open("if_ipw", sc->sc_fwname, &fwh)) != 0) 1920 goto fail0; 1921 1922 fwsz = firmware_get_size(fwh); 1923 1924 if (fwsz < sizeof(hdr)) 1925 goto fail2; 1926 1927 if ((error = firmware_read(fwh, 0, &hdr, sizeof(hdr))) != 0) 1928 goto fail2; 1929 1930 fw->main_size = le32toh(hdr.main_size); 1931 fw->ucode_size = le32toh(hdr.ucode_size); 1932 1933 fw->main = firmware_malloc(fw->main_size); 1934 if (fw->main == NULL) { 1935 error = ENOMEM; 1936 goto fail1; 1937 } 1938 1939 fw->ucode = firmware_malloc(fw->ucode_size); 1940 if (fw->ucode == NULL) { 1941 error = ENOMEM; 1942 goto fail2; 1943 } 1944 1945 p = sizeof(hdr); 1946 if ((error = firmware_read(fwh, p, fw->main, fw->main_size)) != 0) 1947 goto fail3; 1948 1949 p += fw->main_size; 1950 if ((error = firmware_read(fwh, p, fw->ucode, fw->ucode_size)) != 0) 1951 goto fail3; 1952 1953 DPRINTF(("Firmware cached: main %u, ucode %u\n", fw->main_size, 1954 fw->ucode_size)); 1955 1956 sc->flags |= IPW_FLAG_FW_CACHED; 1957 1958 firmware_close(fwh); 1959 1960 return 0; 1961 1962 fail3: firmware_free(fw->ucode, fw->ucode_size); 1963 fail2: firmware_free(fw->main, fw->main_size); 1964 fail1: firmware_close(fwh); 1965 fail0: 1966 return error; 1967 } 1968 1969 static void 1970 ipw_free_firmware(struct ipw_softc *sc) 1971 { 1972 if (!(sc->flags & IPW_FLAG_FW_CACHED)) 1973 return; 1974 1975 firmware_free(sc->fw.main, sc->fw.main_size); 1976 firmware_free(sc->fw.ucode, sc->fw.ucode_size); 1977 1978 sc->flags &= ~IPW_FLAG_FW_CACHED; 1979 } 1980 1981 static int 1982 ipw_config(struct ipw_softc *sc) 1983 { 1984 struct ieee80211com *ic = &sc->sc_ic; 1985 struct ifnet *ifp = &sc->sc_if; 1986 struct ipw_security security; 1987 struct ieee80211_key *k; 1988 struct ipw_wep_key wepkey; 1989 struct ipw_scan_options options; 1990 struct ipw_configuration config; 1991 uint32_t data; 1992 int error, i; 1993 1994 switch (ic->ic_opmode) { 1995 case IEEE80211_M_STA: 1996 case IEEE80211_M_HOSTAP: 1997 data = htole32(IPW_MODE_BSS); 1998 break; 1999 2000 case IEEE80211_M_IBSS: 2001 case IEEE80211_M_AHDEMO: 2002 data = htole32(IPW_MODE_IBSS); 2003 break; 2004 2005 case IEEE80211_M_MONITOR: 2006 data = htole32(IPW_MODE_MONITOR); 2007 break; 2008 } 2009 DPRINTF(("Setting mode to %u\n", le32toh(data))); 2010 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 2011 if (error != 0) 2012 return error; 2013 2014 if (ic->ic_opmode == IEEE80211_M_IBSS || 2015 ic->ic_opmode == IEEE80211_M_MONITOR) { 2016 data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); 2017 DPRINTF(("Setting channel to %u\n", le32toh(data))); 2018 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 2019 if (error != 0) 2020 return error; 2021 } 2022 2023 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2024 DPRINTF(("Enabling adapter\n")); 2025 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 2026 } 2027 2028 DPRINTF(("Setting MAC to %s\n", ether_sprintf(ic->ic_myaddr))); 2029 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 2030 IEEE80211_ADDR_LEN); 2031 if (error != 0) 2032 return error; 2033 2034 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 2035 IPW_CFG_PREAMBLE_AUTO | IPW_CFG_802_1x_ENABLE); 2036 2037 if (ic->ic_opmode == IEEE80211_M_IBSS) 2038 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 2039 if (ifp->if_flags & IFF_PROMISC) 2040 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 2041 config.bss_chan = htole32(0x3fff); /* channels 1-14 */ 2042 config.ibss_chan = htole32(0x7ff); /* channels 1-11 */ 2043 DPRINTF(("Setting adapter configuration 0x%08x\n", config.flags)); 2044 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 2045 if (error != 0) 2046 return error; 2047 2048 data = htole32(0x3); /* 1, 2 */ 2049 DPRINTF(("Setting basic tx rates to 0x%x\n", le32toh(data))); 2050 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 2051 if (error != 0) 2052 return error; 2053 2054 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 2055 DPRINTF(("Setting tx rates to 0x%x\n", le32toh(data))); 2056 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 2057 if (error != 0) 2058 return error; 2059 2060 data = htole32(IPW_POWER_MODE_CAM); 2061 DPRINTF(("Setting power mode to %u\n", le32toh(data))); 2062 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 2063 if (error != 0) 2064 return error; 2065 2066 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2067 data = htole32(32); /* default value */ 2068 DPRINTF(("Setting tx power index to %u\n", le32toh(data))); 2069 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 2070 sizeof data); 2071 if (error != 0) 2072 return error; 2073 } 2074 2075 data = htole32(ic->ic_rtsthreshold); 2076 DPRINTF(("Setting RTS threshold to %u\n", le32toh(data))); 2077 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 2078 if (error != 0) 2079 return error; 2080 2081 data = htole32(ic->ic_fragthreshold); 2082 DPRINTF(("Setting frag threshold to %u\n", le32toh(data))); 2083 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 2084 if (error != 0) 2085 return error; 2086 2087 #ifdef IPW_DEBUG 2088 if (ipw_debug > 0) { 2089 printf("Setting ESSID to "); 2090 ieee80211_print_essid(ic->ic_des_essid, ic->ic_des_esslen); 2091 printf("\n"); 2092 } 2093 #endif 2094 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ic->ic_des_essid, 2095 ic->ic_des_esslen); 2096 if (error != 0) 2097 return error; 2098 2099 /* no mandatory BSSID */ 2100 DPRINTF(("Setting mandatory BSSID to null\n")); 2101 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 2102 if (error != 0) 2103 return error; 2104 2105 if (ic->ic_flags & IEEE80211_F_DESBSSID) { 2106 DPRINTF(("Setting desired BSSID to %s\n", 2107 ether_sprintf(ic->ic_des_bssid))); 2108 error = ipw_cmd(sc, IPW_CMD_SET_DESIRED_BSSID, 2109 ic->ic_des_bssid, IEEE80211_ADDR_LEN); 2110 if (error != 0) 2111 return error; 2112 } 2113 2114 (void)memset(&security, 0, sizeof(security)); 2115 security.authmode = (ic->ic_bss->ni_authmode == IEEE80211_AUTH_SHARED) ? 2116 IPW_AUTH_SHARED : IPW_AUTH_OPEN; 2117 security.ciphers = htole32(IPW_CIPHER_NONE); 2118 DPRINTF(("Setting authmode to %u\n", security.authmode)); 2119 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 2120 sizeof security); 2121 if (error != 0) 2122 return error; 2123 2124 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 2125 k = ic->ic_crypto.cs_nw_keys; 2126 for (i = 0; i < IEEE80211_WEP_NKID; i++, k++) { 2127 if (k->wk_keylen == 0) 2128 continue; 2129 2130 wepkey.idx = i; 2131 wepkey.len = k->wk_keylen; 2132 memset(wepkey.key, 0, sizeof(wepkey.key)); 2133 memcpy(wepkey.key, k->wk_key, k->wk_keylen); 2134 DPRINTF(("Setting wep key index %u len %u\n", 2135 wepkey.idx, wepkey.len)); 2136 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY, &wepkey, 2137 sizeof wepkey); 2138 if (error != 0) 2139 return error; 2140 } 2141 2142 data = htole32(ic->ic_crypto.cs_def_txkey); 2143 DPRINTF(("Setting tx key index to %u\n", le32toh(data))); 2144 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY_INDEX, &data, 2145 sizeof data); 2146 if (error != 0) 2147 return error; 2148 } 2149 2150 data = htole32((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) ? IPW_WEPON : 0); 2151 DPRINTF(("Setting wep flags to 0x%x\n", le32toh(data))); 2152 error = ipw_cmd(sc, IPW_CMD_SET_WEP_FLAGS, &data, sizeof data); 2153 if (error != 0) 2154 return error; 2155 2156 #if 0 2157 struct ipw_wpa_ie ie; 2158 2159 memset(&ie, 0 sizeof(ie)); 2160 ie.len = htole32(sizeof (struct ieee80211_ie_wpa)); 2161 DPRINTF(("Setting wpa ie\n")); 2162 error = ipw_cmd(sc, IPW_CMD_SET_WPA_IE, &ie, sizeof ie); 2163 if (error != 0) 2164 return error; 2165 #endif 2166 2167 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2168 data = htole32(ic->ic_bintval); 2169 DPRINTF(("Setting beacon interval to %u\n", le32toh(data))); 2170 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 2171 sizeof data); 2172 if (error != 0) 2173 return error; 2174 } 2175 2176 options.flags = 0; 2177 options.channels = htole32(0x3fff); /* scan channels 1-14 */ 2178 DPRINTF(("Setting scan options to 0x%x\n", le32toh(options.flags))); 2179 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &options, sizeof options); 2180 if (error != 0) 2181 return error; 2182 2183 /* finally, enable adapter (start scanning for an access point) */ 2184 DPRINTF(("Enabling adapter\n")); 2185 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 2186 } 2187 2188 static int 2189 ipw_init(struct ifnet *ifp) 2190 { 2191 struct ipw_softc *sc = ifp->if_softc; 2192 struct ipw_firmware *fw = &sc->fw; 2193 2194 if (!(sc->flags & IPW_FLAG_FW_CACHED)) { 2195 if (ipw_cache_firmware(sc) != 0) { 2196 aprint_error_dev(sc->sc_dev, 2197 "could not cache the firmware (%s)\n", 2198 sc->sc_fwname); 2199 goto fail; 2200 } 2201 } 2202 2203 ipw_stop(ifp, 0); 2204 2205 if (ipw_reset(sc) != 0) { 2206 aprint_error_dev(sc->sc_dev, "could not reset adapter\n"); 2207 goto fail; 2208 } 2209 2210 if (ipw_load_ucode(sc, fw->ucode, fw->ucode_size) != 0) { 2211 aprint_error_dev(sc->sc_dev, "could not load microcode\n"); 2212 goto fail; 2213 } 2214 2215 ipw_stop_master(sc); 2216 2217 /* 2218 * Setup tx, rx and status rings. 2219 */ 2220 sc->txold = IPW_NTBD - 1; 2221 sc->txcur = 0; 2222 sc->txfree = IPW_NTBD - 2; 2223 sc->rxcur = IPW_NRBD - 1; 2224 2225 CSR_WRITE_4(sc, IPW_CSR_TX_BASE, sc->tbd_map->dm_segs[0].ds_addr); 2226 CSR_WRITE_4(sc, IPW_CSR_TX_SIZE, IPW_NTBD); 2227 CSR_WRITE_4(sc, IPW_CSR_TX_READ, 0); 2228 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 2229 2230 CSR_WRITE_4(sc, IPW_CSR_RX_BASE, sc->rbd_map->dm_segs[0].ds_addr); 2231 CSR_WRITE_4(sc, IPW_CSR_RX_SIZE, IPW_NRBD); 2232 CSR_WRITE_4(sc, IPW_CSR_RX_READ, 0); 2233 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 2234 2235 CSR_WRITE_4(sc, IPW_CSR_STATUS_BASE, sc->status_map->dm_segs[0].ds_addr); 2236 2237 if (ipw_load_firmware(sc, fw->main, fw->main_size) != 0) { 2238 aprint_error_dev(sc->sc_dev, "could not load firmware\n"); 2239 goto fail; 2240 } 2241 2242 sc->flags |= IPW_FLAG_FW_INITED; 2243 2244 /* retrieve information tables base addresses */ 2245 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 2246 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 2247 2248 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 2249 2250 if (ipw_config(sc) != 0) { 2251 aprint_error_dev(sc->sc_dev, "device configuration failed\n"); 2252 goto fail; 2253 } 2254 2255 ifp->if_flags &= ~IFF_OACTIVE; 2256 ifp->if_flags |= IFF_RUNNING; 2257 2258 return 0; 2259 2260 fail: ifp->if_flags &= ~IFF_UP; 2261 ipw_stop(ifp, 0); 2262 2263 return EIO; 2264 } 2265 2266 static void 2267 ipw_stop(struct ifnet *ifp, int disable) 2268 { 2269 struct ipw_softc *sc = ifp->if_softc; 2270 struct ieee80211com *ic = &sc->sc_ic; 2271 int i; 2272 2273 ipw_stop_master(sc); 2274 2275 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 2276 2277 /* 2278 * Release tx buffers. 2279 */ 2280 for (i = 0; i < IPW_NTBD; i++) 2281 ipw_release_sbd(sc, &sc->stbd_list[i]); 2282 2283 sc->sc_tx_timer = 0; 2284 ifp->if_timer = 0; 2285 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2286 2287 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2288 } 2289 2290 static void 2291 ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2292 bus_size_t count) 2293 { 2294 for (; count > 0; offset++, datap++, count--) { 2295 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2296 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 2297 } 2298 } 2299 2300 static void 2301 ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2302 bus_size_t count) 2303 { 2304 for (; count > 0; offset++, datap++, count--) { 2305 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2306 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 2307 } 2308 } 2309 2310 SYSCTL_SETUP(sysctl_hw_ipw_accept_eula_setup, "sysctl hw.ipw.accept_eula") 2311 { 2312 const struct sysctlnode *rnode; 2313 const struct sysctlnode *cnode; 2314 2315 sysctl_createv(NULL, 0, NULL, &rnode, 2316 CTLFLAG_PERMANENT, 2317 CTLTYPE_NODE, "ipw", 2318 NULL, 2319 NULL, 0, 2320 NULL, 0, 2321 CTL_HW, CTL_CREATE, CTL_EOL); 2322 2323 sysctl_createv(NULL, 0, &rnode, &cnode, 2324 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, 2325 CTLTYPE_INT, "accept_eula", 2326 SYSCTL_DESCR("Accept Intel EULA and permit use of ipw(4) firmware"), 2327 NULL, 0, 2328 &ipw_accept_eula, sizeof(ipw_accept_eula), 2329 CTL_CREATE, CTL_EOL); 2330 } 2331
Indexes created Tue Sep 30 17:09:57 GMT 2025