if_ipwreg.h revision 1.2.2.2
1 1.2.2.2 skrll /* $NetBSD: if_ipwreg.h,v 1.2.2.2 2004/08/25 06:58:05 skrll Exp $ */ 2 1.2.2.2 skrll /* Id: if_ipwreg.h,v 1.1.2.1 2004/08/19 16:28:26 damien Exp */ 3 1.2.2.2 skrll 4 1.2.2.2 skrll /*- 5 1.2.2.2 skrll * Copyright (c) 2004 6 1.2.2.2 skrll * Damien Bergamini <damien.bergamini (at) free.fr>. All rights reserved. 7 1.2.2.2 skrll * 8 1.2.2.2 skrll * Redistribution and use in source and binary forms, with or without 9 1.2.2.2 skrll * modification, are permitted provided that the following conditions 10 1.2.2.2 skrll * are met: 11 1.2.2.2 skrll * 1. Redistributions of source code must retain the above copyright 12 1.2.2.2 skrll * notice unmodified, this list of conditions, and the following 13 1.2.2.2 skrll * disclaimer. 14 1.2.2.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 15 1.2.2.2 skrll * notice, this list of conditions and the following disclaimer in the 16 1.2.2.2 skrll * documentation and/or other materials provided with the distribution. 17 1.2.2.2 skrll * 18 1.2.2.2 skrll * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 1.2.2.2 skrll * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 1.2.2.2 skrll * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 1.2.2.2 skrll * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 1.2.2.2 skrll * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 1.2.2.2 skrll * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 1.2.2.2 skrll * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 1.2.2.2 skrll * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 1.2.2.2 skrll * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 1.2.2.2 skrll * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 1.2.2.2 skrll * SUCH DAMAGE. 29 1.2.2.2 skrll */ 30 1.2.2.2 skrll 31 1.2.2.2 skrll #define IPW_NTBD 256 32 1.2.2.2 skrll #define IPW_TBD_SZ (IPW_NTBD * sizeof (struct ipw_bd)) 33 1.2.2.2 skrll #define IPW_NDATA (IPW_NTBD / 2) 34 1.2.2.2 skrll #define IPW_NRBD 256 35 1.2.2.2 skrll #define IPW_RBD_SZ (IPW_NRBD * sizeof (struct ipw_bd)) 36 1.2.2.2 skrll #define IPW_STATUS_SZ (IPW_NRBD * sizeof (struct ipw_status)) 37 1.2.2.2 skrll 38 1.2.2.2 skrll #define IPW_CSR_INTR 0x0008 39 1.2.2.2 skrll #define IPW_CSR_INTR_MASK 0x000c 40 1.2.2.2 skrll #define IPW_CSR_INDIRECT_ADDR 0x0010 41 1.2.2.2 skrll #define IPW_CSR_INDIRECT_DATA 0x0014 42 1.2.2.2 skrll #define IPW_CSR_AUTOINC_ADDR 0x0018 43 1.2.2.2 skrll #define IPW_CSR_AUTOINC_DATA 0x001c 44 1.2.2.2 skrll #define IPW_CSR_RST 0x0020 45 1.2.2.2 skrll #define IPW_CSR_CTL 0x0024 46 1.2.2.2 skrll #define IPW_CSR_IO 0x0030 47 1.2.2.2 skrll #define IPW_CSR_TABLE1_BASE 0x0380 48 1.2.2.2 skrll #define IPW_CSR_TABLE2_BASE 0x0384 49 1.2.2.2 skrll #define IPW_CSR_RX_BD_BASE 0x0240 50 1.2.2.2 skrll #define IPW_CSR_RX_STATUS_BASE 0x0244 51 1.2.2.2 skrll #define IPW_CSR_RX_BD_SIZE 0x0248 52 1.2.2.2 skrll #define IPW_CSR_RX_READ_INDEX 0x02a0 53 1.2.2.2 skrll #define IPW_CSR_RX_WRITE_INDEX 0x0fa0 54 1.2.2.2 skrll #define IPW_CSR_TX_BD_BASE 0x0200 55 1.2.2.2 skrll #define IPW_CSR_TX_BD_SIZE 0x0204 56 1.2.2.2 skrll #define IPW_CSR_TX_READ_INDEX 0x0280 57 1.2.2.2 skrll #define IPW_CSR_TX_WRITE_INDEX 0x0f80 58 1.2.2.2 skrll 59 1.2.2.2 skrll #define IPW_INTR_TX_TRANSFER 0x00000001 60 1.2.2.2 skrll #define IPW_INTR_RX_TRANSFER 0x00000002 61 1.2.2.2 skrll #define IPW_INTR_STATUS_CHANGE 0x00000010 62 1.2.2.2 skrll #define IPW_INTR_COMMAND_DONE 0x00010000 63 1.2.2.2 skrll #define IPW_INTR_FW_INIT_DONE 0x01000000 64 1.2.2.2 skrll #define IPW_INTR_FATAL_ERROR 0x40000000 65 1.2.2.2 skrll #define IPW_INTR_PARITY_ERROR 0x80000000 66 1.2.2.2 skrll 67 1.2.2.2 skrll #define IPW_INTR_MASK \ 68 1.2.2.2 skrll (IPW_INTR_TX_TRANSFER | IPW_INTR_RX_TRANSFER | \ 69 1.2.2.2 skrll IPW_INTR_STATUS_CHANGE | IPW_INTR_COMMAND_DONE | \ 70 1.2.2.2 skrll IPW_INTR_FW_INIT_DONE | IPW_INTR_FATAL_ERROR | \ 71 1.2.2.2 skrll IPW_INTR_PARITY_ERROR) 72 1.2.2.2 skrll 73 1.2.2.2 skrll /* possible flags for register IPW_CSR_RST */ 74 1.2.2.2 skrll #define IPW_RST_PRINCETON_RESET 0x00000001 75 1.2.2.2 skrll #define IPW_RST_SW_RESET 0x00000080 76 1.2.2.2 skrll #define IPW_RST_MASTER_DISABLED 0x00000100 77 1.2.2.2 skrll #define IPW_RST_STOP_MASTER 0x00000200 78 1.2.2.2 skrll 79 1.2.2.2 skrll /* possible flags for register IPW_CSR_CTL */ 80 1.2.2.2 skrll #define IPW_CTL_CLOCK_READY 0x00000001 81 1.2.2.2 skrll #define IPW_CTL_ALLOW_STANDBY 0x00000002 82 1.2.2.2 skrll #define IPW_CTL_INIT_DONE 0x00000004 83 1.2.2.2 skrll 84 1.2.2.2 skrll /* possible flags for register IPW_CSR_IO */ 85 1.2.2.2 skrll #define IPW_IO_GPIO1_ENABLE 0x00000008 86 1.2.2.2 skrll #define IPW_IO_GPIO1_MASK 0x0000000c 87 1.2.2.2 skrll #define IPW_IO_GPIO3_MASK 0x000000c0 88 1.2.2.2 skrll #define IPW_IO_LED_OFF 0x00002000 89 1.2.2.2 skrll #define IPW_IO_RADIO_DISABLED 0x00010000 90 1.2.2.2 skrll 91 1.2.2.2 skrll #define IPW_STATE_ASSOCIATED 0x0004 92 1.2.2.2 skrll #define IPW_STATE_ASSOCIATION_LOST 0x0008 93 1.2.2.2 skrll #define IPW_STATE_SCAN_COMPLETE 0x0020 94 1.2.2.2 skrll #define IPW_STATE_RADIO_DISABLED 0x0100 95 1.2.2.2 skrll #define IPW_STATE_DISABLED 0x0200 96 1.2.2.2 skrll #define IPW_STATE_SCANNING 0x0800 97 1.2.2.2 skrll 98 1.2.2.2 skrll /* table1 offsets */ 99 1.2.2.2 skrll #define IPW_INFO_LOCK 480 100 1.2.2.2 skrll #define IPW_INFO_CARD_DISABLED 628 101 1.2.2.2 skrll #define IPW_INFO_CURRENT_CHANNEL 756 102 1.2.2.2 skrll #define IPW_INFO_CURRENT_TX_RATE 768 103 1.2.2.2 skrll #define IPW_INFO_EEPROM_ADDRESS 816 104 1.2.2.2 skrll 105 1.2.2.2 skrll /* table2 offsets */ 106 1.2.2.2 skrll #define IPW_INFO_ADAPTER_MAC 8 107 1.2.2.2 skrll #define IPW_INFO_CURRENT_SSID 48 108 1.2.2.2 skrll #define IPW_INFO_CURRENT_BSSID 112 109 1.2.2.2 skrll 110 1.2.2.2 skrll /* firmware binary image header */ 111 1.2.2.2 skrll struct ipw_fw_hdr { 112 1.2.2.2 skrll u_int32_t version; 113 1.2.2.2 skrll u_int32_t fw_size; /* firmware size */ 114 1.2.2.2 skrll u_int32_t uc_size; /* microcode size */ 115 1.2.2.2 skrll } __attribute__((__packed__)); 116 1.2.2.2 skrll 117 1.2.2.2 skrll /* buffer descriptor */ 118 1.2.2.2 skrll struct ipw_bd { 119 1.2.2.2 skrll u_int32_t physaddr; 120 1.2.2.2 skrll u_int32_t len; 121 1.2.2.2 skrll u_int8_t flags; 122 1.2.2.2 skrll #define IPW_BD_FLAG_TX_FRAME_802_3 0x00 123 1.2.2.2 skrll #define IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT 0x01 124 1.2.2.2 skrll #define IPW_BD_FLAG_TX_FRAME_COMMAND 0x02 125 1.2.2.2 skrll #define IPW_BD_FLAG_TX_FRAME_802_11 0x04 126 1.2.2.2 skrll #define IPW_BD_FLAG_TX_LAST_FRAGMENT 0x08 127 1.2.2.2 skrll u_int8_t nfrag; /* number of fragments */ 128 1.2.2.2 skrll u_int8_t reserved[6]; 129 1.2.2.2 skrll } __attribute__((__packed__)); 130 1.2.2.2 skrll 131 1.2.2.2 skrll /* status */ 132 1.2.2.2 skrll struct ipw_status { 133 1.2.2.2 skrll u_int32_t len; 134 1.2.2.2 skrll u_int16_t code; 135 1.2.2.2 skrll #define IPW_STATUS_CODE_COMMAND 0 136 1.2.2.2 skrll #define IPW_STATUS_CODE_NEWSTATE 1 137 1.2.2.2 skrll #define IPW_STATUS_CODE_DATA_802_11 2 138 1.2.2.2 skrll #define IPW_STATUS_CODE_DATA_802_3 3 139 1.2.2.2 skrll #define IPW_STATUS_CODE_NOTIFICATION 4 140 1.2.2.2 skrll u_int8_t flags; 141 1.2.2.2 skrll #define IPW_STATUS_FLAG_DECRYPTED 0x01 142 1.2.2.2 skrll #define IPW_STATUS_FLAG_WEP_ENCRYPTED 0x02 143 1.2.2.2 skrll u_int8_t rssi; /* received signal strength indicator */ 144 1.2.2.2 skrll } __attribute__((__packed__)); 145 1.2.2.2 skrll 146 1.2.2.2 skrll /* data header */ 147 1.2.2.2 skrll struct ipw_hdr { 148 1.2.2.2 skrll u_int32_t type; 149 1.2.2.2 skrll #define IPW_HDR_TYPE_SEND 33 150 1.2.2.2 skrll u_int32_t subtype; 151 1.2.2.2 skrll u_int8_t encrypted; 152 1.2.2.2 skrll u_int8_t encrypt; 153 1.2.2.2 skrll u_int8_t keyidx; 154 1.2.2.2 skrll u_int8_t keysz; 155 1.2.2.2 skrll u_int8_t key[IEEE80211_KEYBUF_SIZE]; 156 1.2.2.2 skrll u_int8_t reserved[10]; 157 1.2.2.2 skrll u_int8_t src_addr[IEEE80211_ADDR_LEN]; 158 1.2.2.2 skrll u_int8_t dst_addr[IEEE80211_ADDR_LEN]; 159 1.2.2.2 skrll u_int16_t fragmentsz; 160 1.2.2.2 skrll } __attribute__((__packed__)); 161 1.2.2.2 skrll 162 1.2.2.2 skrll /* command */ 163 1.2.2.2 skrll struct ipw_cmd { 164 1.2.2.2 skrll u_int32_t type; 165 1.2.2.2 skrll #define IPW_CMD_ENABLE 2 166 1.2.2.2 skrll #define IPW_CMD_SET_CONFIGURATION 6 167 1.2.2.2 skrll #define IPW_CMD_SET_ESSID 8 168 1.2.2.2 skrll #define IPW_CMD_SET_MANDATORY_BSSID 9 169 1.2.2.2 skrll #define IPW_CMD_SET_MAC_ADDRESS 11 170 1.2.2.2 skrll #define IPW_CMD_SET_MODE 12 171 1.2.2.2 skrll #define IPW_CMD_SET_CHANNEL 14 172 1.2.2.2 skrll #define IPW_CMD_SET_RTS_THRESHOLD 15 173 1.2.2.2 skrll #define IPW_CMD_SET_FRAG_THRESHOLD 16 174 1.2.2.2 skrll #define IPW_CMD_SET_POWER_MODE 17 175 1.2.2.2 skrll #define IPW_CMD_SET_TX_RATES 18 176 1.2.2.2 skrll #define IPW_CMD_SET_BASIC_TX_RATES 19 177 1.2.2.2 skrll #define IPW_CMD_SET_WEP_KEY 20 178 1.2.2.2 skrll #define IPW_CMD_SET_WEP_KEY_INDEX 25 179 1.2.2.2 skrll #define IPW_CMD_SET_WEP_FLAGS 26 180 1.2.2.2 skrll #define IPW_CMD_ADD_MULTICAST 27 181 1.2.2.2 skrll #define IPW_CMD_SET_BEACON_INTERVAL 29 182 1.2.2.2 skrll #define IPW_CMD_SET_TX_POWER_INDEX 36 183 1.2.2.2 skrll #define IPW_CMD_BROADCAST_SCAN 43 184 1.2.2.2 skrll #define IPW_CMD_DISABLE 44 185 1.2.2.2 skrll #define IPW_CMD_SET_DESIRED_BSSID 45 186 1.2.2.2 skrll #define IPW_CMD_SET_SCAN_OPTIONS 46 187 1.2.2.2 skrll #define IPW_CMD_PREPARE_POWER_DOWN 58 188 1.2.2.2 skrll #define IPW_CMD_DISABLE_PHY 61 189 1.2.2.2 skrll #define IPW_CMD_SET_SECURITY_INFORMATION 67 190 1.2.2.2 skrll u_int32_t subtype; 191 1.2.2.2 skrll u_int32_t seq; 192 1.2.2.2 skrll u_int32_t len; 193 1.2.2.2 skrll u_int8_t data[400]; 194 1.2.2.2 skrll u_int32_t status; 195 1.2.2.2 skrll u_int8_t reserved[68]; 196 1.2.2.2 skrll } __attribute__((__packed__)); 197 1.2.2.2 skrll 198 1.2.2.2 skrll /* possible values for command IPW_CMD_SET_POWER_MODE */ 199 1.2.2.2 skrll #define IPW_POWER_MODE_CAM 0 200 1.2.2.2 skrll #define IPW_POWER_AUTOMATIC 6 201 1.2.2.2 skrll 202 1.2.2.2 skrll /* possible values for command IPW_CMD_SET_MODE */ 203 1.2.2.2 skrll #define IPW_MODE_BSS 0 204 1.2.2.2 skrll #define IPW_MODE_IBSS 1 205 1.2.2.2 skrll #define IPW_MODE_MONITOR 2 206 1.2.2.2 skrll 207 1.2.2.2 skrll /* structure for command IPW_CMD_SET_WEP_KEY */ 208 1.2.2.2 skrll struct ipw_wep_key { 209 1.2.2.2 skrll u_int8_t idx; 210 1.2.2.2 skrll u_int8_t len; 211 1.2.2.2 skrll u_int8_t key[13]; 212 1.2.2.2 skrll } __attribute__((__packed__)); 213 1.2.2.2 skrll 214 1.2.2.2 skrll /* structure for command IPW_CMD_SET_SECURITY_INFORMATION */ 215 1.2.2.2 skrll struct ipw_security { 216 1.2.2.2 skrll u_int32_t ciphers; 217 1.2.2.2 skrll #define IPW_CIPHER_NONE 0x00000001 218 1.2.2.2 skrll #define IPW_CIPHER_WEP40 0x00000002 219 1.2.2.2 skrll #define IPW_CIPHER_WEP104 0x00000020 220 1.2.2.2 skrll u_int16_t version; 221 1.2.2.2 skrll u_int8_t authmode; 222 1.2.2.2 skrll #define IPW_AUTH_OPEN 0 223 1.2.2.2 skrll #define IPW_AUTH_SHARED 1 224 1.2.2.2 skrll u_int8_t replay_counters_number; 225 1.2.2.2 skrll u_int8_t unicast_using_group; 226 1.2.2.2 skrll } __attribute__((__packed__)); 227 1.2.2.2 skrll 228 1.2.2.2 skrll /* structure for command IPW_CMD_SET_SCAN_OPTIONS */ 229 1.2.2.2 skrll struct ipw_scan_options { 230 1.2.2.2 skrll u_int32_t flags; 231 1.2.2.2 skrll #define IPW_SCAN_DO_NOT_ASSOCIATE 0x00000001 232 1.2.2.2 skrll #define IPW_SCAN_PASSIVE 0x00000008 233 1.2.2.2 skrll u_int32_t channels; 234 1.2.2.2 skrll } __attribute__((__packed__)); 235 1.2.2.2 skrll 236 1.2.2.2 skrll /* structure for command IPW_CMD_SET_CONFIGURATION */ 237 1.2.2.2 skrll struct ipw_configuration { 238 1.2.2.2 skrll u_int32_t flags; 239 1.2.2.2 skrll #define IPW_CFG_PROMISCUOUS 0x00000004 240 1.2.2.2 skrll #define IPW_CFG_PREAMBLE_LEN 0x00000010 241 1.2.2.2 skrll #define IPW_CFG_IBSS_AUTO_START 0x00000020 242 1.2.2.2 skrll #define IPW_CFG_802_1x_ENABLE 0x00004000 243 1.2.2.2 skrll #define IPW_CFG_BSS_MASK 0x00008000 244 1.2.2.2 skrll #define IPW_CFG_IBSS_MASK 0x00010000 245 1.2.2.2 skrll u_int32_t channels; 246 1.2.2.2 skrll u_int32_t ibss_chan; 247 1.2.2.2 skrll } __attribute__((__packed__)); 248 1.2.2.2 skrll 249 1.2.2.2 skrll /* 250 1.2.2.2 skrll * control and status registers access macros 251 1.2.2.2 skrll */ 252 1.2.2.2 skrll #define CSR_READ_1(sc, reg) \ 253 1.2.2.2 skrll bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg)) 254 1.2.2.2 skrll 255 1.2.2.2 skrll #define CSR_READ_2(sc, reg) \ 256 1.2.2.2 skrll bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg)) 257 1.2.2.2 skrll 258 1.2.2.2 skrll #define CSR_READ_4(sc, reg) \ 259 1.2.2.2 skrll bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 260 1.2.2.2 skrll 261 1.2.2.2 skrll #define CSR_WRITE_1(sc, reg, val) \ 262 1.2.2.2 skrll bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 263 1.2.2.2 skrll 264 1.2.2.2 skrll #define CSR_WRITE_2(sc, reg, val) \ 265 1.2.2.2 skrll bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 266 1.2.2.2 skrll 267 1.2.2.2 skrll #define CSR_WRITE_4(sc, reg, val) \ 268 1.2.2.2 skrll bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 269 1.2.2.2 skrll 270 1.2.2.2 skrll #define CSR_WRITE_MULTI_1(sc, reg, buf, len) \ 271 1.2.2.2 skrll bus_space_write_multi_1((sc)->sc_st, (sc)->sc_sh, (reg), \ 272 1.2.2.2 skrll (buf), (len)); 273 1.2.2.2 skrll 274 1.2.2.2 skrll /* 275 1.2.2.2 skrll * indirect memory space access macros 276 1.2.2.2 skrll */ 277 1.2.2.2 skrll 278 1.2.2.2 skrll #define MEM_WRITE_1(sc, addr, val) do { \ 279 1.2.2.2 skrll CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \ 280 1.2.2.2 skrll CSR_WRITE_1((sc), IPW_CSR_INDIRECT_DATA, (val)); \ 281 1.2.2.2 skrll } while (/* CONSTCOND */0) 282 1.2.2.2 skrll 283 1.2.2.2 skrll #define MEM_WRITE_2(sc, addr, val) do { \ 284 1.2.2.2 skrll CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \ 285 1.2.2.2 skrll CSR_WRITE_2((sc), IPW_CSR_INDIRECT_DATA, (val)); \ 286 1.2.2.2 skrll } while (/* CONSTCOND */0) 287 1.2.2.2 skrll 288 1.2.2.2 skrll #define MEM_WRITE_4(sc, addr, val) do { \ 289 1.2.2.2 skrll CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \ 290 1.2.2.2 skrll CSR_WRITE_4((sc), IPW_CSR_INDIRECT_DATA, (val)); \ 291 1.2.2.2 skrll } while (/* CONSTCOND */0) 292 1.2.2.2 skrll 293 1.2.2.2 skrll #define MEM_WRITE_MULTI_1(sc, addr, buf, len) do { \ 294 1.2.2.2 skrll CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \ 295 1.2.2.2 skrll CSR_WRITE_MULTI_1((sc), IPW_CSR_INDIRECT_DATA, (buf), (len)); \ 296 1.2.2.2 skrll } while (/* CONSTCOND */0) 297
Indexes created Thu Oct 02 14:10:14 GMT 2025